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1 /*
2 * Copyright 2015 Amazon.com, Inc. or its affiliates.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
34
35 #ifdef CONFIG_RFS_ACCEL
36 #include <linux/cpu_rmap.h>
37 #endif /* CONFIG_RFS_ACCEL */
38 #include <linux/ethtool.h>
39 #include <linux/if_vlan.h>
40 #include <linux/kernel.h>
41 #include <linux/module.h>
42 #include <linux/moduleparam.h>
43 #include <linux/numa.h>
44 #include <linux/pci.h>
45 #include <linux/utsname.h>
46 #include <linux/version.h>
47 #include <linux/vmalloc.h>
48 #include <net/ip.h>
49
50 #include "ena_netdev.h"
51 #include "ena_pci_id_tbl.h"
52
53 static char version[] = DEVICE_NAME " v" DRV_MODULE_VERSION "\n";
54
55 MODULE_AUTHOR("Amazon.com, Inc. or its affiliates");
56 MODULE_DESCRIPTION(DEVICE_NAME);
57 MODULE_LICENSE("GPL");
58 MODULE_VERSION(DRV_MODULE_VERSION);
59
60 /* Time in jiffies before concluding the transmitter is hung. */
61 #define TX_TIMEOUT (5 * HZ)
62
63 #define ENA_NAPI_BUDGET 64
64
65 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | \
66 NETIF_MSG_TX_DONE | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR)
67 static int debug = -1;
68 module_param(debug, int, 0);
69 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
70
71 static struct ena_aenq_handlers aenq_handlers;
72
73 static struct workqueue_struct *ena_wq;
74
75 MODULE_DEVICE_TABLE(pci, ena_pci_tbl);
76
77 static int ena_rss_init_default(struct ena_adapter *adapter);
78
79 static void ena_tx_timeout(struct net_device *dev)
80 {
81 struct ena_adapter *adapter = netdev_priv(dev);
82
83 /* Change the state of the device to trigger reset
84 * Check that we are not in the middle or a trigger already
85 */
86
87 if (test_and_set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
88 return;
89
90 u64_stats_update_begin(&adapter->syncp);
91 adapter->dev_stats.tx_timeout++;
92 u64_stats_update_end(&adapter->syncp);
93
94 netif_err(adapter, tx_err, dev, "Transmit time out\n");
95 }
96
97 static void update_rx_ring_mtu(struct ena_adapter *adapter, int mtu)
98 {
99 int i;
100
101 for (i = 0; i < adapter->num_queues; i++)
102 adapter->rx_ring[i].mtu = mtu;
103 }
104
105 static int ena_change_mtu(struct net_device *dev, int new_mtu)
106 {
107 struct ena_adapter *adapter = netdev_priv(dev);
108 int ret;
109
110 ret = ena_com_set_dev_mtu(adapter->ena_dev, new_mtu);
111 if (!ret) {
112 netif_dbg(adapter, drv, dev, "set MTU to %d\n", new_mtu);
113 update_rx_ring_mtu(adapter, new_mtu);
114 dev->mtu = new_mtu;
115 } else {
116 netif_err(adapter, drv, dev, "Failed to set MTU to %d\n",
117 new_mtu);
118 }
119
120 return ret;
121 }
122
123 static int ena_init_rx_cpu_rmap(struct ena_adapter *adapter)
124 {
125 #ifdef CONFIG_RFS_ACCEL
126 u32 i;
127 int rc;
128
129 adapter->netdev->rx_cpu_rmap = alloc_irq_cpu_rmap(adapter->num_queues);
130 if (!adapter->netdev->rx_cpu_rmap)
131 return -ENOMEM;
132 for (i = 0; i < adapter->num_queues; i++) {
133 int irq_idx = ENA_IO_IRQ_IDX(i);
134
135 rc = irq_cpu_rmap_add(adapter->netdev->rx_cpu_rmap,
136 pci_irq_vector(adapter->pdev, irq_idx));
137 if (rc) {
138 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
139 adapter->netdev->rx_cpu_rmap = NULL;
140 return rc;
141 }
142 }
143 #endif /* CONFIG_RFS_ACCEL */
144 return 0;
145 }
146
147 static void ena_init_io_rings_common(struct ena_adapter *adapter,
148 struct ena_ring *ring, u16 qid)
149 {
150 ring->qid = qid;
151 ring->pdev = adapter->pdev;
152 ring->dev = &adapter->pdev->dev;
153 ring->netdev = adapter->netdev;
154 ring->napi = &adapter->ena_napi[qid].napi;
155 ring->adapter = adapter;
156 ring->ena_dev = adapter->ena_dev;
157 ring->per_napi_packets = 0;
158 ring->per_napi_bytes = 0;
159 ring->cpu = 0;
160 u64_stats_init(&ring->syncp);
161 }
162
163 static void ena_init_io_rings(struct ena_adapter *adapter)
164 {
165 struct ena_com_dev *ena_dev;
166 struct ena_ring *txr, *rxr;
167 int i;
168
169 ena_dev = adapter->ena_dev;
170
171 for (i = 0; i < adapter->num_queues; i++) {
172 txr = &adapter->tx_ring[i];
173 rxr = &adapter->rx_ring[i];
174
175 /* TX/RX common ring state */
176 ena_init_io_rings_common(adapter, txr, i);
177 ena_init_io_rings_common(adapter, rxr, i);
178
179 /* TX specific ring state */
180 txr->ring_size = adapter->tx_ring_size;
181 txr->tx_max_header_size = ena_dev->tx_max_header_size;
182 txr->tx_mem_queue_type = ena_dev->tx_mem_queue_type;
183 txr->sgl_size = adapter->max_tx_sgl_size;
184 txr->smoothed_interval =
185 ena_com_get_nonadaptive_moderation_interval_tx(ena_dev);
186
187 /* RX specific ring state */
188 rxr->ring_size = adapter->rx_ring_size;
189 rxr->rx_copybreak = adapter->rx_copybreak;
190 rxr->sgl_size = adapter->max_rx_sgl_size;
191 rxr->smoothed_interval =
192 ena_com_get_nonadaptive_moderation_interval_rx(ena_dev);
193 }
194 }
195
196 /* ena_setup_tx_resources - allocate I/O Tx resources (Descriptors)
197 * @adapter: network interface device structure
198 * @qid: queue index
199 *
200 * Return 0 on success, negative on failure
201 */
202 static int ena_setup_tx_resources(struct ena_adapter *adapter, int qid)
203 {
204 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
205 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
206 int size, i, node;
207
208 if (tx_ring->tx_buffer_info) {
209 netif_err(adapter, ifup,
210 adapter->netdev, "tx_buffer_info info is not NULL");
211 return -EEXIST;
212 }
213
214 size = sizeof(struct ena_tx_buffer) * tx_ring->ring_size;
215 node = cpu_to_node(ena_irq->cpu);
216
217 tx_ring->tx_buffer_info = vzalloc_node(size, node);
218 if (!tx_ring->tx_buffer_info) {
219 tx_ring->tx_buffer_info = vzalloc(size);
220 if (!tx_ring->tx_buffer_info)
221 return -ENOMEM;
222 }
223
224 size = sizeof(u16) * tx_ring->ring_size;
225 tx_ring->free_tx_ids = vzalloc_node(size, node);
226 if (!tx_ring->free_tx_ids) {
227 tx_ring->free_tx_ids = vzalloc(size);
228 if (!tx_ring->free_tx_ids) {
229 vfree(tx_ring->tx_buffer_info);
230 return -ENOMEM;
231 }
232 }
233
234 /* Req id ring for TX out of order completions */
235 for (i = 0; i < tx_ring->ring_size; i++)
236 tx_ring->free_tx_ids[i] = i;
237
238 /* Reset tx statistics */
239 memset(&tx_ring->tx_stats, 0x0, sizeof(tx_ring->tx_stats));
240
241 tx_ring->next_to_use = 0;
242 tx_ring->next_to_clean = 0;
243 tx_ring->cpu = ena_irq->cpu;
244 return 0;
245 }
246
247 /* ena_free_tx_resources - Free I/O Tx Resources per Queue
248 * @adapter: network interface device structure
249 * @qid: queue index
250 *
251 * Free all transmit software resources
252 */
253 static void ena_free_tx_resources(struct ena_adapter *adapter, int qid)
254 {
255 struct ena_ring *tx_ring = &adapter->tx_ring[qid];
256
257 vfree(tx_ring->tx_buffer_info);
258 tx_ring->tx_buffer_info = NULL;
259
260 vfree(tx_ring->free_tx_ids);
261 tx_ring->free_tx_ids = NULL;
262 }
263
264 /* ena_setup_all_tx_resources - allocate I/O Tx queues resources for All queues
265 * @adapter: private structure
266 *
267 * Return 0 on success, negative on failure
268 */
269 static int ena_setup_all_tx_resources(struct ena_adapter *adapter)
270 {
271 int i, rc = 0;
272
273 for (i = 0; i < adapter->num_queues; i++) {
274 rc = ena_setup_tx_resources(adapter, i);
275 if (rc)
276 goto err_setup_tx;
277 }
278
279 return 0;
280
281 err_setup_tx:
282
283 netif_err(adapter, ifup, adapter->netdev,
284 "Tx queue %d: allocation failed\n", i);
285
286 /* rewind the index freeing the rings as we go */
287 while (i--)
288 ena_free_tx_resources(adapter, i);
289 return rc;
290 }
291
292 /* ena_free_all_io_tx_resources - Free I/O Tx Resources for All Queues
293 * @adapter: board private structure
294 *
295 * Free all transmit software resources
296 */
297 static void ena_free_all_io_tx_resources(struct ena_adapter *adapter)
298 {
299 int i;
300
301 for (i = 0; i < adapter->num_queues; i++)
302 ena_free_tx_resources(adapter, i);
303 }
304
305 /* ena_setup_rx_resources - allocate I/O Rx resources (Descriptors)
306 * @adapter: network interface device structure
307 * @qid: queue index
308 *
309 * Returns 0 on success, negative on failure
310 */
311 static int ena_setup_rx_resources(struct ena_adapter *adapter,
312 u32 qid)
313 {
314 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
315 struct ena_irq *ena_irq = &adapter->irq_tbl[ENA_IO_IRQ_IDX(qid)];
316 int size, node;
317
318 if (rx_ring->rx_buffer_info) {
319 netif_err(adapter, ifup, adapter->netdev,
320 "rx_buffer_info is not NULL");
321 return -EEXIST;
322 }
323
324 /* alloc extra element so in rx path
325 * we can always prefetch rx_info + 1
326 */
327 size = sizeof(struct ena_rx_buffer) * (rx_ring->ring_size + 1);
328 node = cpu_to_node(ena_irq->cpu);
329
330 rx_ring->rx_buffer_info = vzalloc_node(size, node);
331 if (!rx_ring->rx_buffer_info) {
332 rx_ring->rx_buffer_info = vzalloc(size);
333 if (!rx_ring->rx_buffer_info)
334 return -ENOMEM;
335 }
336
337 /* Reset rx statistics */
338 memset(&rx_ring->rx_stats, 0x0, sizeof(rx_ring->rx_stats));
339
340 rx_ring->next_to_clean = 0;
341 rx_ring->next_to_use = 0;
342 rx_ring->cpu = ena_irq->cpu;
343
344 return 0;
345 }
346
347 /* ena_free_rx_resources - Free I/O Rx Resources
348 * @adapter: network interface device structure
349 * @qid: queue index
350 *
351 * Free all receive software resources
352 */
353 static void ena_free_rx_resources(struct ena_adapter *adapter,
354 u32 qid)
355 {
356 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
357
358 vfree(rx_ring->rx_buffer_info);
359 rx_ring->rx_buffer_info = NULL;
360 }
361
362 /* ena_setup_all_rx_resources - allocate I/O Rx queues resources for all queues
363 * @adapter: board private structure
364 *
365 * Return 0 on success, negative on failure
366 */
367 static int ena_setup_all_rx_resources(struct ena_adapter *adapter)
368 {
369 int i, rc = 0;
370
371 for (i = 0; i < adapter->num_queues; i++) {
372 rc = ena_setup_rx_resources(adapter, i);
373 if (rc)
374 goto err_setup_rx;
375 }
376
377 return 0;
378
379 err_setup_rx:
380
381 netif_err(adapter, ifup, adapter->netdev,
382 "Rx queue %d: allocation failed\n", i);
383
384 /* rewind the index freeing the rings as we go */
385 while (i--)
386 ena_free_rx_resources(adapter, i);
387 return rc;
388 }
389
390 /* ena_free_all_io_rx_resources - Free I/O Rx Resources for All Queues
391 * @adapter: board private structure
392 *
393 * Free all receive software resources
394 */
395 static void ena_free_all_io_rx_resources(struct ena_adapter *adapter)
396 {
397 int i;
398
399 for (i = 0; i < adapter->num_queues; i++)
400 ena_free_rx_resources(adapter, i);
401 }
402
403 static inline int ena_alloc_rx_page(struct ena_ring *rx_ring,
404 struct ena_rx_buffer *rx_info, gfp_t gfp)
405 {
406 struct ena_com_buf *ena_buf;
407 struct page *page;
408 dma_addr_t dma;
409
410 /* if previous allocated page is not used */
411 if (unlikely(rx_info->page))
412 return 0;
413
414 page = alloc_page(gfp);
415 if (unlikely(!page)) {
416 u64_stats_update_begin(&rx_ring->syncp);
417 rx_ring->rx_stats.page_alloc_fail++;
418 u64_stats_update_end(&rx_ring->syncp);
419 return -ENOMEM;
420 }
421
422 dma = dma_map_page(rx_ring->dev, page, 0, PAGE_SIZE,
423 DMA_FROM_DEVICE);
424 if (unlikely(dma_mapping_error(rx_ring->dev, dma))) {
425 u64_stats_update_begin(&rx_ring->syncp);
426 rx_ring->rx_stats.dma_mapping_err++;
427 u64_stats_update_end(&rx_ring->syncp);
428
429 __free_page(page);
430 return -EIO;
431 }
432 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
433 "alloc page %p, rx_info %p\n", page, rx_info);
434
435 rx_info->page = page;
436 rx_info->page_offset = 0;
437 ena_buf = &rx_info->ena_buf;
438 ena_buf->paddr = dma;
439 ena_buf->len = PAGE_SIZE;
440
441 return 0;
442 }
443
444 static void ena_free_rx_page(struct ena_ring *rx_ring,
445 struct ena_rx_buffer *rx_info)
446 {
447 struct page *page = rx_info->page;
448 struct ena_com_buf *ena_buf = &rx_info->ena_buf;
449
450 if (unlikely(!page)) {
451 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
452 "Trying to free unallocated buffer\n");
453 return;
454 }
455
456 dma_unmap_page(rx_ring->dev, ena_buf->paddr, PAGE_SIZE,
457 DMA_FROM_DEVICE);
458
459 __free_page(page);
460 rx_info->page = NULL;
461 }
462
463 static int ena_refill_rx_bufs(struct ena_ring *rx_ring, u32 num)
464 {
465 u16 next_to_use;
466 u32 i;
467 int rc;
468
469 next_to_use = rx_ring->next_to_use;
470
471 for (i = 0; i < num; i++) {
472 struct ena_rx_buffer *rx_info =
473 &rx_ring->rx_buffer_info[next_to_use];
474
475 rc = ena_alloc_rx_page(rx_ring, rx_info,
476 __GFP_COLD | GFP_ATOMIC | __GFP_COMP);
477 if (unlikely(rc < 0)) {
478 netif_warn(rx_ring->adapter, rx_err, rx_ring->netdev,
479 "failed to alloc buffer for rx queue %d\n",
480 rx_ring->qid);
481 break;
482 }
483 rc = ena_com_add_single_rx_desc(rx_ring->ena_com_io_sq,
484 &rx_info->ena_buf,
485 next_to_use);
486 if (unlikely(rc)) {
487 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
488 "failed to add buffer for rx queue %d\n",
489 rx_ring->qid);
490 break;
491 }
492 next_to_use = ENA_RX_RING_IDX_NEXT(next_to_use,
493 rx_ring->ring_size);
494 }
495
496 if (unlikely(i < num)) {
497 u64_stats_update_begin(&rx_ring->syncp);
498 rx_ring->rx_stats.refil_partial++;
499 u64_stats_update_end(&rx_ring->syncp);
500 netdev_warn(rx_ring->netdev,
501 "refilled rx qid %d with only %d buffers (from %d)\n",
502 rx_ring->qid, i, num);
503 }
504
505 if (likely(i)) {
506 /* Add memory barrier to make sure the desc were written before
507 * issue a doorbell
508 */
509 wmb();
510 ena_com_write_sq_doorbell(rx_ring->ena_com_io_sq);
511 }
512
513 rx_ring->next_to_use = next_to_use;
514
515 return i;
516 }
517
518 static void ena_free_rx_bufs(struct ena_adapter *adapter,
519 u32 qid)
520 {
521 struct ena_ring *rx_ring = &adapter->rx_ring[qid];
522 u32 i;
523
524 for (i = 0; i < rx_ring->ring_size; i++) {
525 struct ena_rx_buffer *rx_info = &rx_ring->rx_buffer_info[i];
526
527 if (rx_info->page)
528 ena_free_rx_page(rx_ring, rx_info);
529 }
530 }
531
532 /* ena_refill_all_rx_bufs - allocate all queues Rx buffers
533 * @adapter: board private structure
534 *
535 */
536 static void ena_refill_all_rx_bufs(struct ena_adapter *adapter)
537 {
538 struct ena_ring *rx_ring;
539 int i, rc, bufs_num;
540
541 for (i = 0; i < adapter->num_queues; i++) {
542 rx_ring = &adapter->rx_ring[i];
543 bufs_num = rx_ring->ring_size - 1;
544 rc = ena_refill_rx_bufs(rx_ring, bufs_num);
545
546 if (unlikely(rc != bufs_num))
547 netif_warn(rx_ring->adapter, rx_status, rx_ring->netdev,
548 "refilling Queue %d failed. allocated %d buffers from: %d\n",
549 i, rc, bufs_num);
550 }
551 }
552
553 static void ena_free_all_rx_bufs(struct ena_adapter *adapter)
554 {
555 int i;
556
557 for (i = 0; i < adapter->num_queues; i++)
558 ena_free_rx_bufs(adapter, i);
559 }
560
561 /* ena_free_tx_bufs - Free Tx Buffers per Queue
562 * @tx_ring: TX ring for which buffers be freed
563 */
564 static void ena_free_tx_bufs(struct ena_ring *tx_ring)
565 {
566 bool print_once = true;
567 u32 i;
568
569 for (i = 0; i < tx_ring->ring_size; i++) {
570 struct ena_tx_buffer *tx_info = &tx_ring->tx_buffer_info[i];
571 struct ena_com_buf *ena_buf;
572 int nr_frags;
573 int j;
574
575 if (!tx_info->skb)
576 continue;
577
578 if (print_once) {
579 netdev_notice(tx_ring->netdev,
580 "free uncompleted tx skb qid %d idx 0x%x\n",
581 tx_ring->qid, i);
582 print_once = false;
583 } else {
584 netdev_dbg(tx_ring->netdev,
585 "free uncompleted tx skb qid %d idx 0x%x\n",
586 tx_ring->qid, i);
587 }
588
589 ena_buf = tx_info->bufs;
590 dma_unmap_single(tx_ring->dev,
591 ena_buf->paddr,
592 ena_buf->len,
593 DMA_TO_DEVICE);
594
595 /* unmap remaining mapped pages */
596 nr_frags = tx_info->num_of_bufs - 1;
597 for (j = 0; j < nr_frags; j++) {
598 ena_buf++;
599 dma_unmap_page(tx_ring->dev,
600 ena_buf->paddr,
601 ena_buf->len,
602 DMA_TO_DEVICE);
603 }
604
605 dev_kfree_skb_any(tx_info->skb);
606 }
607 netdev_tx_reset_queue(netdev_get_tx_queue(tx_ring->netdev,
608 tx_ring->qid));
609 }
610
611 static void ena_free_all_tx_bufs(struct ena_adapter *adapter)
612 {
613 struct ena_ring *tx_ring;
614 int i;
615
616 for (i = 0; i < adapter->num_queues; i++) {
617 tx_ring = &adapter->tx_ring[i];
618 ena_free_tx_bufs(tx_ring);
619 }
620 }
621
622 static void ena_destroy_all_tx_queues(struct ena_adapter *adapter)
623 {
624 u16 ena_qid;
625 int i;
626
627 for (i = 0; i < adapter->num_queues; i++) {
628 ena_qid = ENA_IO_TXQ_IDX(i);
629 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
630 }
631 }
632
633 static void ena_destroy_all_rx_queues(struct ena_adapter *adapter)
634 {
635 u16 ena_qid;
636 int i;
637
638 for (i = 0; i < adapter->num_queues; i++) {
639 ena_qid = ENA_IO_RXQ_IDX(i);
640 ena_com_destroy_io_queue(adapter->ena_dev, ena_qid);
641 }
642 }
643
644 static void ena_destroy_all_io_queues(struct ena_adapter *adapter)
645 {
646 ena_destroy_all_tx_queues(adapter);
647 ena_destroy_all_rx_queues(adapter);
648 }
649
650 static int validate_tx_req_id(struct ena_ring *tx_ring, u16 req_id)
651 {
652 struct ena_tx_buffer *tx_info = NULL;
653
654 if (likely(req_id < tx_ring->ring_size)) {
655 tx_info = &tx_ring->tx_buffer_info[req_id];
656 if (likely(tx_info->skb))
657 return 0;
658 }
659
660 if (tx_info)
661 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
662 "tx_info doesn't have valid skb\n");
663 else
664 netif_err(tx_ring->adapter, tx_done, tx_ring->netdev,
665 "Invalid req_id: %hu\n", req_id);
666
667 u64_stats_update_begin(&tx_ring->syncp);
668 tx_ring->tx_stats.bad_req_id++;
669 u64_stats_update_end(&tx_ring->syncp);
670
671 /* Trigger device reset */
672 set_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags);
673 return -EFAULT;
674 }
675
676 static int ena_clean_tx_irq(struct ena_ring *tx_ring, u32 budget)
677 {
678 struct netdev_queue *txq;
679 bool above_thresh;
680 u32 tx_bytes = 0;
681 u32 total_done = 0;
682 u16 next_to_clean;
683 u16 req_id;
684 int tx_pkts = 0;
685 int rc;
686
687 next_to_clean = tx_ring->next_to_clean;
688 txq = netdev_get_tx_queue(tx_ring->netdev, tx_ring->qid);
689
690 while (tx_pkts < budget) {
691 struct ena_tx_buffer *tx_info;
692 struct sk_buff *skb;
693 struct ena_com_buf *ena_buf;
694 int i, nr_frags;
695
696 rc = ena_com_tx_comp_req_id_get(tx_ring->ena_com_io_cq,
697 &req_id);
698 if (rc)
699 break;
700
701 rc = validate_tx_req_id(tx_ring, req_id);
702 if (rc)
703 break;
704
705 tx_info = &tx_ring->tx_buffer_info[req_id];
706 skb = tx_info->skb;
707
708 /* prefetch skb_end_pointer() to speedup skb_shinfo(skb) */
709 prefetch(&skb->end);
710
711 tx_info->skb = NULL;
712 tx_info->last_jiffies = 0;
713
714 if (likely(tx_info->num_of_bufs != 0)) {
715 ena_buf = tx_info->bufs;
716
717 dma_unmap_single(tx_ring->dev,
718 dma_unmap_addr(ena_buf, paddr),
719 dma_unmap_len(ena_buf, len),
720 DMA_TO_DEVICE);
721
722 /* unmap remaining mapped pages */
723 nr_frags = tx_info->num_of_bufs - 1;
724 for (i = 0; i < nr_frags; i++) {
725 ena_buf++;
726 dma_unmap_page(tx_ring->dev,
727 dma_unmap_addr(ena_buf, paddr),
728 dma_unmap_len(ena_buf, len),
729 DMA_TO_DEVICE);
730 }
731 }
732
733 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
734 "tx_poll: q %d skb %p completed\n", tx_ring->qid,
735 skb);
736
737 tx_bytes += skb->len;
738 dev_kfree_skb(skb);
739 tx_pkts++;
740 total_done += tx_info->tx_descs;
741
742 tx_ring->free_tx_ids[next_to_clean] = req_id;
743 next_to_clean = ENA_TX_RING_IDX_NEXT(next_to_clean,
744 tx_ring->ring_size);
745 }
746
747 tx_ring->next_to_clean = next_to_clean;
748 ena_com_comp_ack(tx_ring->ena_com_io_sq, total_done);
749 ena_com_update_dev_comp_head(tx_ring->ena_com_io_cq);
750
751 netdev_tx_completed_queue(txq, tx_pkts, tx_bytes);
752
753 netif_dbg(tx_ring->adapter, tx_done, tx_ring->netdev,
754 "tx_poll: q %d done. total pkts: %d\n",
755 tx_ring->qid, tx_pkts);
756
757 /* need to make the rings circular update visible to
758 * ena_start_xmit() before checking for netif_queue_stopped().
759 */
760 smp_mb();
761
762 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
763 ENA_TX_WAKEUP_THRESH;
764 if (unlikely(netif_tx_queue_stopped(txq) && above_thresh)) {
765 __netif_tx_lock(txq, smp_processor_id());
766 above_thresh = ena_com_sq_empty_space(tx_ring->ena_com_io_sq) >
767 ENA_TX_WAKEUP_THRESH;
768 if (netif_tx_queue_stopped(txq) && above_thresh) {
769 netif_tx_wake_queue(txq);
770 u64_stats_update_begin(&tx_ring->syncp);
771 tx_ring->tx_stats.queue_wakeup++;
772 u64_stats_update_end(&tx_ring->syncp);
773 }
774 __netif_tx_unlock(txq);
775 }
776
777 tx_ring->per_napi_bytes += tx_bytes;
778 tx_ring->per_napi_packets += tx_pkts;
779
780 return tx_pkts;
781 }
782
783 static struct sk_buff *ena_rx_skb(struct ena_ring *rx_ring,
784 struct ena_com_rx_buf_info *ena_bufs,
785 u32 descs,
786 u16 *next_to_clean)
787 {
788 struct sk_buff *skb;
789 struct ena_rx_buffer *rx_info =
790 &rx_ring->rx_buffer_info[*next_to_clean];
791 u32 len;
792 u32 buf = 0;
793 void *va;
794
795 len = ena_bufs[0].len;
796 if (unlikely(!rx_info->page)) {
797 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
798 "Page is NULL\n");
799 return NULL;
800 }
801
802 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
803 "rx_info %p page %p\n",
804 rx_info, rx_info->page);
805
806 /* save virt address of first buffer */
807 va = page_address(rx_info->page) + rx_info->page_offset;
808 prefetch(va + NET_IP_ALIGN);
809
810 if (len <= rx_ring->rx_copybreak) {
811 skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
812 rx_ring->rx_copybreak);
813 if (unlikely(!skb)) {
814 u64_stats_update_begin(&rx_ring->syncp);
815 rx_ring->rx_stats.skb_alloc_fail++;
816 u64_stats_update_end(&rx_ring->syncp);
817 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
818 "Failed to allocate skb\n");
819 return NULL;
820 }
821
822 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
823 "rx allocated small packet. len %d. data_len %d\n",
824 skb->len, skb->data_len);
825
826 /* sync this buffer for CPU use */
827 dma_sync_single_for_cpu(rx_ring->dev,
828 dma_unmap_addr(&rx_info->ena_buf, paddr),
829 len,
830 DMA_FROM_DEVICE);
831 skb_copy_to_linear_data(skb, va, len);
832 dma_sync_single_for_device(rx_ring->dev,
833 dma_unmap_addr(&rx_info->ena_buf, paddr),
834 len,
835 DMA_FROM_DEVICE);
836
837 skb_put(skb, len);
838 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
839 *next_to_clean = ENA_RX_RING_IDX_ADD(*next_to_clean, descs,
840 rx_ring->ring_size);
841 return skb;
842 }
843
844 skb = napi_get_frags(rx_ring->napi);
845 if (unlikely(!skb)) {
846 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
847 "Failed allocating skb\n");
848 u64_stats_update_begin(&rx_ring->syncp);
849 rx_ring->rx_stats.skb_alloc_fail++;
850 u64_stats_update_end(&rx_ring->syncp);
851 return NULL;
852 }
853
854 do {
855 dma_unmap_page(rx_ring->dev,
856 dma_unmap_addr(&rx_info->ena_buf, paddr),
857 PAGE_SIZE, DMA_FROM_DEVICE);
858
859 skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_info->page,
860 rx_info->page_offset, len, PAGE_SIZE);
861
862 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
863 "rx skb updated. len %d. data_len %d\n",
864 skb->len, skb->data_len);
865
866 rx_info->page = NULL;
867 *next_to_clean =
868 ENA_RX_RING_IDX_NEXT(*next_to_clean,
869 rx_ring->ring_size);
870 if (likely(--descs == 0))
871 break;
872 rx_info = &rx_ring->rx_buffer_info[*next_to_clean];
873 len = ena_bufs[++buf].len;
874 } while (1);
875
876 return skb;
877 }
878
879 /* ena_rx_checksum - indicate in skb if hw indicated a good cksum
880 * @adapter: structure containing adapter specific data
881 * @ena_rx_ctx: received packet context/metadata
882 * @skb: skb currently being received and modified
883 */
884 static inline void ena_rx_checksum(struct ena_ring *rx_ring,
885 struct ena_com_rx_ctx *ena_rx_ctx,
886 struct sk_buff *skb)
887 {
888 /* Rx csum disabled */
889 if (unlikely(!(rx_ring->netdev->features & NETIF_F_RXCSUM))) {
890 skb->ip_summed = CHECKSUM_NONE;
891 return;
892 }
893
894 /* For fragmented packets the checksum isn't valid */
895 if (ena_rx_ctx->frag) {
896 skb->ip_summed = CHECKSUM_NONE;
897 return;
898 }
899
900 /* if IP and error */
901 if (unlikely((ena_rx_ctx->l3_proto == ENA_ETH_IO_L3_PROTO_IPV4) &&
902 (ena_rx_ctx->l3_csum_err))) {
903 /* ipv4 checksum error */
904 skb->ip_summed = CHECKSUM_NONE;
905 u64_stats_update_begin(&rx_ring->syncp);
906 rx_ring->rx_stats.bad_csum++;
907 u64_stats_update_end(&rx_ring->syncp);
908 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
909 "RX IPv4 header checksum error\n");
910 return;
911 }
912
913 /* if TCP/UDP */
914 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
915 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP))) {
916 if (unlikely(ena_rx_ctx->l4_csum_err)) {
917 /* TCP/UDP checksum error */
918 u64_stats_update_begin(&rx_ring->syncp);
919 rx_ring->rx_stats.bad_csum++;
920 u64_stats_update_end(&rx_ring->syncp);
921 netif_err(rx_ring->adapter, rx_err, rx_ring->netdev,
922 "RX L4 checksum error\n");
923 skb->ip_summed = CHECKSUM_NONE;
924 return;
925 }
926
927 skb->ip_summed = CHECKSUM_UNNECESSARY;
928 }
929 }
930
931 static void ena_set_rx_hash(struct ena_ring *rx_ring,
932 struct ena_com_rx_ctx *ena_rx_ctx,
933 struct sk_buff *skb)
934 {
935 enum pkt_hash_types hash_type;
936
937 if (likely(rx_ring->netdev->features & NETIF_F_RXHASH)) {
938 if (likely((ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_TCP) ||
939 (ena_rx_ctx->l4_proto == ENA_ETH_IO_L4_PROTO_UDP)))
940
941 hash_type = PKT_HASH_TYPE_L4;
942 else
943 hash_type = PKT_HASH_TYPE_NONE;
944
945 /* Override hash type if the packet is fragmented */
946 if (ena_rx_ctx->frag)
947 hash_type = PKT_HASH_TYPE_NONE;
948
949 skb_set_hash(skb, ena_rx_ctx->hash, hash_type);
950 }
951 }
952
953 /* ena_clean_rx_irq - Cleanup RX irq
954 * @rx_ring: RX ring to clean
955 * @napi: napi handler
956 * @budget: how many packets driver is allowed to clean
957 *
958 * Returns the number of cleaned buffers.
959 */
960 static int ena_clean_rx_irq(struct ena_ring *rx_ring, struct napi_struct *napi,
961 u32 budget)
962 {
963 u16 next_to_clean = rx_ring->next_to_clean;
964 u32 res_budget, work_done;
965
966 struct ena_com_rx_ctx ena_rx_ctx;
967 struct ena_adapter *adapter;
968 struct sk_buff *skb;
969 int refill_required;
970 int refill_threshold;
971 int rc = 0;
972 int total_len = 0;
973 int rx_copybreak_pkt = 0;
974
975 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
976 "%s qid %d\n", __func__, rx_ring->qid);
977 res_budget = budget;
978
979 do {
980 ena_rx_ctx.ena_bufs = rx_ring->ena_bufs;
981 ena_rx_ctx.max_bufs = rx_ring->sgl_size;
982 ena_rx_ctx.descs = 0;
983 rc = ena_com_rx_pkt(rx_ring->ena_com_io_cq,
984 rx_ring->ena_com_io_sq,
985 &ena_rx_ctx);
986 if (unlikely(rc))
987 goto error;
988
989 if (unlikely(ena_rx_ctx.descs == 0))
990 break;
991
992 netif_dbg(rx_ring->adapter, rx_status, rx_ring->netdev,
993 "rx_poll: q %d got packet from ena. descs #: %d l3 proto %d l4 proto %d hash: %x\n",
994 rx_ring->qid, ena_rx_ctx.descs, ena_rx_ctx.l3_proto,
995 ena_rx_ctx.l4_proto, ena_rx_ctx.hash);
996
997 /* allocate skb and fill it */
998 skb = ena_rx_skb(rx_ring, rx_ring->ena_bufs, ena_rx_ctx.descs,
999 &next_to_clean);
1000
1001 /* exit if we failed to retrieve a buffer */
1002 if (unlikely(!skb)) {
1003 next_to_clean = ENA_RX_RING_IDX_ADD(next_to_clean,
1004 ena_rx_ctx.descs,
1005 rx_ring->ring_size);
1006 break;
1007 }
1008
1009 ena_rx_checksum(rx_ring, &ena_rx_ctx, skb);
1010
1011 ena_set_rx_hash(rx_ring, &ena_rx_ctx, skb);
1012
1013 skb_record_rx_queue(skb, rx_ring->qid);
1014
1015 if (rx_ring->ena_bufs[0].len <= rx_ring->rx_copybreak) {
1016 total_len += rx_ring->ena_bufs[0].len;
1017 rx_copybreak_pkt++;
1018 napi_gro_receive(napi, skb);
1019 } else {
1020 total_len += skb->len;
1021 napi_gro_frags(napi);
1022 }
1023
1024 res_budget--;
1025 } while (likely(res_budget));
1026
1027 work_done = budget - res_budget;
1028 rx_ring->per_napi_bytes += total_len;
1029 rx_ring->per_napi_packets += work_done;
1030 u64_stats_update_begin(&rx_ring->syncp);
1031 rx_ring->rx_stats.bytes += total_len;
1032 rx_ring->rx_stats.cnt += work_done;
1033 rx_ring->rx_stats.rx_copybreak_pkt += rx_copybreak_pkt;
1034 u64_stats_update_end(&rx_ring->syncp);
1035
1036 rx_ring->next_to_clean = next_to_clean;
1037
1038 refill_required = ena_com_sq_empty_space(rx_ring->ena_com_io_sq);
1039 refill_threshold = rx_ring->ring_size / ENA_RX_REFILL_THRESH_DIVIDER;
1040
1041 /* Optimization, try to batch new rx buffers */
1042 if (refill_required > refill_threshold) {
1043 ena_com_update_dev_comp_head(rx_ring->ena_com_io_cq);
1044 ena_refill_rx_bufs(rx_ring, refill_required);
1045 }
1046
1047 return work_done;
1048
1049 error:
1050 adapter = netdev_priv(rx_ring->netdev);
1051
1052 u64_stats_update_begin(&rx_ring->syncp);
1053 rx_ring->rx_stats.bad_desc_num++;
1054 u64_stats_update_end(&rx_ring->syncp);
1055
1056 /* Too many desc from the device. Trigger reset */
1057 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
1058
1059 return 0;
1060 }
1061
1062 inline void ena_adjust_intr_moderation(struct ena_ring *rx_ring,
1063 struct ena_ring *tx_ring)
1064 {
1065 /* We apply adaptive moderation on Rx path only.
1066 * Tx uses static interrupt moderation.
1067 */
1068 ena_com_calculate_interrupt_delay(rx_ring->ena_dev,
1069 rx_ring->per_napi_packets,
1070 rx_ring->per_napi_bytes,
1071 &rx_ring->smoothed_interval,
1072 &rx_ring->moder_tbl_idx);
1073
1074 /* Reset per napi packets/bytes */
1075 tx_ring->per_napi_packets = 0;
1076 tx_ring->per_napi_bytes = 0;
1077 rx_ring->per_napi_packets = 0;
1078 rx_ring->per_napi_bytes = 0;
1079 }
1080
1081 static inline void ena_unmask_interrupt(struct ena_ring *tx_ring,
1082 struct ena_ring *rx_ring)
1083 {
1084 struct ena_eth_io_intr_reg intr_reg;
1085
1086 /* Update intr register: rx intr delay,
1087 * tx intr delay and interrupt unmask
1088 */
1089 ena_com_update_intr_reg(&intr_reg,
1090 rx_ring->smoothed_interval,
1091 tx_ring->smoothed_interval,
1092 true);
1093
1094 /* It is a shared MSI-X.
1095 * Tx and Rx CQ have pointer to it.
1096 * So we use one of them to reach the intr reg
1097 */
1098 ena_com_unmask_intr(rx_ring->ena_com_io_cq, &intr_reg);
1099 }
1100
1101 static inline void ena_update_ring_numa_node(struct ena_ring *tx_ring,
1102 struct ena_ring *rx_ring)
1103 {
1104 int cpu = get_cpu();
1105 int numa_node;
1106
1107 /* Check only one ring since the 2 rings are running on the same cpu */
1108 if (likely(tx_ring->cpu == cpu))
1109 goto out;
1110
1111 numa_node = cpu_to_node(cpu);
1112 put_cpu();
1113
1114 if (numa_node != NUMA_NO_NODE) {
1115 ena_com_update_numa_node(tx_ring->ena_com_io_cq, numa_node);
1116 ena_com_update_numa_node(rx_ring->ena_com_io_cq, numa_node);
1117 }
1118
1119 tx_ring->cpu = cpu;
1120 rx_ring->cpu = cpu;
1121
1122 return;
1123 out:
1124 put_cpu();
1125 }
1126
1127 static int ena_io_poll(struct napi_struct *napi, int budget)
1128 {
1129 struct ena_napi *ena_napi = container_of(napi, struct ena_napi, napi);
1130 struct ena_ring *tx_ring, *rx_ring;
1131
1132 u32 tx_work_done;
1133 u32 rx_work_done;
1134 int tx_budget;
1135 int napi_comp_call = 0;
1136 int ret;
1137
1138 tx_ring = ena_napi->tx_ring;
1139 rx_ring = ena_napi->rx_ring;
1140
1141 tx_budget = tx_ring->ring_size / ENA_TX_POLL_BUDGET_DIVIDER;
1142
1143 if (!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1144 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags)) {
1145 napi_complete_done(napi, 0);
1146 return 0;
1147 }
1148
1149 tx_work_done = ena_clean_tx_irq(tx_ring, tx_budget);
1150 rx_work_done = ena_clean_rx_irq(rx_ring, napi, budget);
1151
1152 /* If the device is about to reset or down, avoid unmask
1153 * the interrupt and return 0 so NAPI won't reschedule
1154 */
1155 if (unlikely(!test_bit(ENA_FLAG_DEV_UP, &tx_ring->adapter->flags) ||
1156 test_bit(ENA_FLAG_TRIGGER_RESET, &tx_ring->adapter->flags))) {
1157 napi_complete_done(napi, 0);
1158 ret = 0;
1159
1160 } else if ((budget > rx_work_done) && (tx_budget > tx_work_done)) {
1161 napi_comp_call = 1;
1162
1163 /* Update numa and unmask the interrupt only when schedule
1164 * from the interrupt context (vs from sk_busy_loop)
1165 */
1166 if (napi_complete_done(napi, rx_work_done)) {
1167 /* Tx and Rx share the same interrupt vector */
1168 if (ena_com_get_adaptive_moderation_enabled(rx_ring->ena_dev))
1169 ena_adjust_intr_moderation(rx_ring, tx_ring);
1170
1171 ena_unmask_interrupt(tx_ring, rx_ring);
1172 }
1173
1174 ena_update_ring_numa_node(tx_ring, rx_ring);
1175
1176 ret = rx_work_done;
1177 } else {
1178 ret = budget;
1179 }
1180
1181 u64_stats_update_begin(&tx_ring->syncp);
1182 tx_ring->tx_stats.napi_comp += napi_comp_call;
1183 tx_ring->tx_stats.tx_poll++;
1184 u64_stats_update_end(&tx_ring->syncp);
1185
1186 return ret;
1187 }
1188
1189 static irqreturn_t ena_intr_msix_mgmnt(int irq, void *data)
1190 {
1191 struct ena_adapter *adapter = (struct ena_adapter *)data;
1192
1193 ena_com_admin_q_comp_intr_handler(adapter->ena_dev);
1194
1195 /* Don't call the aenq handler before probe is done */
1196 if (likely(test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags)))
1197 ena_com_aenq_intr_handler(adapter->ena_dev, data);
1198
1199 return IRQ_HANDLED;
1200 }
1201
1202 /* ena_intr_msix_io - MSI-X Interrupt Handler for Tx/Rx
1203 * @irq: interrupt number
1204 * @data: pointer to a network interface private napi device structure
1205 */
1206 static irqreturn_t ena_intr_msix_io(int irq, void *data)
1207 {
1208 struct ena_napi *ena_napi = data;
1209
1210 napi_schedule(&ena_napi->napi);
1211
1212 return IRQ_HANDLED;
1213 }
1214
1215 static int ena_enable_msix(struct ena_adapter *adapter, int num_queues)
1216 {
1217 int msix_vecs, rc;
1218
1219 /* Reserved the max msix vectors we might need */
1220 msix_vecs = ENA_MAX_MSIX_VEC(num_queues);
1221
1222 netif_dbg(adapter, probe, adapter->netdev,
1223 "trying to enable MSI-X, vectors %d\n", msix_vecs);
1224
1225 rc = pci_alloc_irq_vectors(adapter->pdev, msix_vecs, msix_vecs,
1226 PCI_IRQ_MSIX);
1227 if (rc < 0) {
1228 netif_err(adapter, probe, adapter->netdev,
1229 "Failed to enable MSI-X, vectors %d rc %d\n",
1230 msix_vecs, rc);
1231 return -ENOSPC;
1232 }
1233
1234 netif_dbg(adapter, probe, adapter->netdev, "enable MSI-X, vectors %d\n",
1235 msix_vecs);
1236
1237 if (msix_vecs >= 1) {
1238 if (ena_init_rx_cpu_rmap(adapter))
1239 netif_warn(adapter, probe, adapter->netdev,
1240 "Failed to map IRQs to CPUs\n");
1241 }
1242
1243 adapter->msix_vecs = msix_vecs;
1244
1245 return 0;
1246 }
1247
1248 static void ena_setup_mgmnt_intr(struct ena_adapter *adapter)
1249 {
1250 u32 cpu;
1251
1252 snprintf(adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].name,
1253 ENA_IRQNAME_SIZE, "ena-mgmnt@pci:%s",
1254 pci_name(adapter->pdev));
1255 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].handler =
1256 ena_intr_msix_mgmnt;
1257 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].data = adapter;
1258 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].vector =
1259 pci_irq_vector(adapter->pdev, ENA_MGMNT_IRQ_IDX);
1260 cpu = cpumask_first(cpu_online_mask);
1261 adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].cpu = cpu;
1262 cpumask_set_cpu(cpu,
1263 &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX].affinity_hint_mask);
1264 }
1265
1266 static void ena_setup_io_intr(struct ena_adapter *adapter)
1267 {
1268 struct net_device *netdev;
1269 int irq_idx, i, cpu;
1270
1271 netdev = adapter->netdev;
1272
1273 for (i = 0; i < adapter->num_queues; i++) {
1274 irq_idx = ENA_IO_IRQ_IDX(i);
1275 cpu = i % num_online_cpus();
1276
1277 snprintf(adapter->irq_tbl[irq_idx].name, ENA_IRQNAME_SIZE,
1278 "%s-Tx-Rx-%d", netdev->name, i);
1279 adapter->irq_tbl[irq_idx].handler = ena_intr_msix_io;
1280 adapter->irq_tbl[irq_idx].data = &adapter->ena_napi[i];
1281 adapter->irq_tbl[irq_idx].vector =
1282 pci_irq_vector(adapter->pdev, irq_idx);
1283 adapter->irq_tbl[irq_idx].cpu = cpu;
1284
1285 cpumask_set_cpu(cpu,
1286 &adapter->irq_tbl[irq_idx].affinity_hint_mask);
1287 }
1288 }
1289
1290 static int ena_request_mgmnt_irq(struct ena_adapter *adapter)
1291 {
1292 unsigned long flags = 0;
1293 struct ena_irq *irq;
1294 int rc;
1295
1296 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1297 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1298 irq->data);
1299 if (rc) {
1300 netif_err(adapter, probe, adapter->netdev,
1301 "failed to request admin irq\n");
1302 return rc;
1303 }
1304
1305 netif_dbg(adapter, probe, adapter->netdev,
1306 "set affinity hint of mgmnt irq.to 0x%lx (irq vector: %d)\n",
1307 irq->affinity_hint_mask.bits[0], irq->vector);
1308
1309 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1310
1311 return rc;
1312 }
1313
1314 static int ena_request_io_irq(struct ena_adapter *adapter)
1315 {
1316 unsigned long flags = 0;
1317 struct ena_irq *irq;
1318 int rc = 0, i, k;
1319
1320 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1321 irq = &adapter->irq_tbl[i];
1322 rc = request_irq(irq->vector, irq->handler, flags, irq->name,
1323 irq->data);
1324 if (rc) {
1325 netif_err(adapter, ifup, adapter->netdev,
1326 "Failed to request I/O IRQ. index %d rc %d\n",
1327 i, rc);
1328 goto err;
1329 }
1330
1331 netif_dbg(adapter, ifup, adapter->netdev,
1332 "set affinity hint of irq. index %d to 0x%lx (irq vector: %d)\n",
1333 i, irq->affinity_hint_mask.bits[0], irq->vector);
1334
1335 irq_set_affinity_hint(irq->vector, &irq->affinity_hint_mask);
1336 }
1337
1338 return rc;
1339
1340 err:
1341 for (k = ENA_IO_IRQ_FIRST_IDX; k < i; k++) {
1342 irq = &adapter->irq_tbl[k];
1343 free_irq(irq->vector, irq->data);
1344 }
1345
1346 return rc;
1347 }
1348
1349 static void ena_free_mgmnt_irq(struct ena_adapter *adapter)
1350 {
1351 struct ena_irq *irq;
1352
1353 irq = &adapter->irq_tbl[ENA_MGMNT_IRQ_IDX];
1354 synchronize_irq(irq->vector);
1355 irq_set_affinity_hint(irq->vector, NULL);
1356 free_irq(irq->vector, irq->data);
1357 }
1358
1359 static void ena_free_io_irq(struct ena_adapter *adapter)
1360 {
1361 struct ena_irq *irq;
1362 int i;
1363
1364 #ifdef CONFIG_RFS_ACCEL
1365 if (adapter->msix_vecs >= 1) {
1366 free_irq_cpu_rmap(adapter->netdev->rx_cpu_rmap);
1367 adapter->netdev->rx_cpu_rmap = NULL;
1368 }
1369 #endif /* CONFIG_RFS_ACCEL */
1370
1371 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++) {
1372 irq = &adapter->irq_tbl[i];
1373 irq_set_affinity_hint(irq->vector, NULL);
1374 free_irq(irq->vector, irq->data);
1375 }
1376 }
1377
1378 static void ena_disable_io_intr_sync(struct ena_adapter *adapter)
1379 {
1380 int i;
1381
1382 if (!netif_running(adapter->netdev))
1383 return;
1384
1385 for (i = ENA_IO_IRQ_FIRST_IDX; i < adapter->msix_vecs; i++)
1386 synchronize_irq(adapter->irq_tbl[i].vector);
1387 }
1388
1389 static void ena_del_napi(struct ena_adapter *adapter)
1390 {
1391 int i;
1392
1393 for (i = 0; i < adapter->num_queues; i++)
1394 netif_napi_del(&adapter->ena_napi[i].napi);
1395 }
1396
1397 static void ena_init_napi(struct ena_adapter *adapter)
1398 {
1399 struct ena_napi *napi;
1400 int i;
1401
1402 for (i = 0; i < adapter->num_queues; i++) {
1403 napi = &adapter->ena_napi[i];
1404
1405 netif_napi_add(adapter->netdev,
1406 &adapter->ena_napi[i].napi,
1407 ena_io_poll,
1408 ENA_NAPI_BUDGET);
1409 napi->rx_ring = &adapter->rx_ring[i];
1410 napi->tx_ring = &adapter->tx_ring[i];
1411 napi->qid = i;
1412 }
1413 }
1414
1415 static void ena_napi_disable_all(struct ena_adapter *adapter)
1416 {
1417 int i;
1418
1419 for (i = 0; i < adapter->num_queues; i++)
1420 napi_disable(&adapter->ena_napi[i].napi);
1421 }
1422
1423 static void ena_napi_enable_all(struct ena_adapter *adapter)
1424 {
1425 int i;
1426
1427 for (i = 0; i < adapter->num_queues; i++)
1428 napi_enable(&adapter->ena_napi[i].napi);
1429 }
1430
1431 static void ena_restore_ethtool_params(struct ena_adapter *adapter)
1432 {
1433 adapter->tx_usecs = 0;
1434 adapter->rx_usecs = 0;
1435 adapter->tx_frames = 1;
1436 adapter->rx_frames = 1;
1437 }
1438
1439 /* Configure the Rx forwarding */
1440 static int ena_rss_configure(struct ena_adapter *adapter)
1441 {
1442 struct ena_com_dev *ena_dev = adapter->ena_dev;
1443 int rc;
1444
1445 /* In case the RSS table wasn't initialized by probe */
1446 if (!ena_dev->rss.tbl_log_size) {
1447 rc = ena_rss_init_default(adapter);
1448 if (rc && (rc != -EPERM)) {
1449 netif_err(adapter, ifup, adapter->netdev,
1450 "Failed to init RSS rc: %d\n", rc);
1451 return rc;
1452 }
1453 }
1454
1455 /* Set indirect table */
1456 rc = ena_com_indirect_table_set(ena_dev);
1457 if (unlikely(rc && rc != -EPERM))
1458 return rc;
1459
1460 /* Configure hash function (if supported) */
1461 rc = ena_com_set_hash_function(ena_dev);
1462 if (unlikely(rc && (rc != -EPERM)))
1463 return rc;
1464
1465 /* Configure hash inputs (if supported) */
1466 rc = ena_com_set_hash_ctrl(ena_dev);
1467 if (unlikely(rc && (rc != -EPERM)))
1468 return rc;
1469
1470 return 0;
1471 }
1472
1473 static int ena_up_complete(struct ena_adapter *adapter)
1474 {
1475 int rc, i;
1476
1477 rc = ena_rss_configure(adapter);
1478 if (rc)
1479 return rc;
1480
1481 ena_init_napi(adapter);
1482
1483 ena_change_mtu(adapter->netdev, adapter->netdev->mtu);
1484
1485 ena_refill_all_rx_bufs(adapter);
1486
1487 /* enable transmits */
1488 netif_tx_start_all_queues(adapter->netdev);
1489
1490 ena_restore_ethtool_params(adapter);
1491
1492 ena_napi_enable_all(adapter);
1493
1494 /* Enable completion queues interrupt */
1495 for (i = 0; i < adapter->num_queues; i++)
1496 ena_unmask_interrupt(&adapter->tx_ring[i],
1497 &adapter->rx_ring[i]);
1498
1499 /* schedule napi in case we had pending packets
1500 * from the last time we disable napi
1501 */
1502 for (i = 0; i < adapter->num_queues; i++)
1503 napi_schedule(&adapter->ena_napi[i].napi);
1504
1505 return 0;
1506 }
1507
1508 static int ena_create_io_tx_queue(struct ena_adapter *adapter, int qid)
1509 {
1510 struct ena_com_create_io_ctx ctx = { 0 };
1511 struct ena_com_dev *ena_dev;
1512 struct ena_ring *tx_ring;
1513 u32 msix_vector;
1514 u16 ena_qid;
1515 int rc;
1516
1517 ena_dev = adapter->ena_dev;
1518
1519 tx_ring = &adapter->tx_ring[qid];
1520 msix_vector = ENA_IO_IRQ_IDX(qid);
1521 ena_qid = ENA_IO_TXQ_IDX(qid);
1522
1523 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_TX;
1524 ctx.qid = ena_qid;
1525 ctx.mem_queue_type = ena_dev->tx_mem_queue_type;
1526 ctx.msix_vector = msix_vector;
1527 ctx.queue_size = adapter->tx_ring_size;
1528 ctx.numa_node = cpu_to_node(tx_ring->cpu);
1529
1530 rc = ena_com_create_io_queue(ena_dev, &ctx);
1531 if (rc) {
1532 netif_err(adapter, ifup, adapter->netdev,
1533 "Failed to create I/O TX queue num %d rc: %d\n",
1534 qid, rc);
1535 return rc;
1536 }
1537
1538 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1539 &tx_ring->ena_com_io_sq,
1540 &tx_ring->ena_com_io_cq);
1541 if (rc) {
1542 netif_err(adapter, ifup, adapter->netdev,
1543 "Failed to get TX queue handlers. TX queue num %d rc: %d\n",
1544 qid, rc);
1545 ena_com_destroy_io_queue(ena_dev, ena_qid);
1546 }
1547
1548 ena_com_update_numa_node(tx_ring->ena_com_io_cq, ctx.numa_node);
1549 return rc;
1550 }
1551
1552 static int ena_create_all_io_tx_queues(struct ena_adapter *adapter)
1553 {
1554 struct ena_com_dev *ena_dev = adapter->ena_dev;
1555 int rc, i;
1556
1557 for (i = 0; i < adapter->num_queues; i++) {
1558 rc = ena_create_io_tx_queue(adapter, i);
1559 if (rc)
1560 goto create_err;
1561 }
1562
1563 return 0;
1564
1565 create_err:
1566 while (i--)
1567 ena_com_destroy_io_queue(ena_dev, ENA_IO_TXQ_IDX(i));
1568
1569 return rc;
1570 }
1571
1572 static int ena_create_io_rx_queue(struct ena_adapter *adapter, int qid)
1573 {
1574 struct ena_com_dev *ena_dev;
1575 struct ena_com_create_io_ctx ctx = { 0 };
1576 struct ena_ring *rx_ring;
1577 u32 msix_vector;
1578 u16 ena_qid;
1579 int rc;
1580
1581 ena_dev = adapter->ena_dev;
1582
1583 rx_ring = &adapter->rx_ring[qid];
1584 msix_vector = ENA_IO_IRQ_IDX(qid);
1585 ena_qid = ENA_IO_RXQ_IDX(qid);
1586
1587 ctx.qid = ena_qid;
1588 ctx.direction = ENA_COM_IO_QUEUE_DIRECTION_RX;
1589 ctx.mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
1590 ctx.msix_vector = msix_vector;
1591 ctx.queue_size = adapter->rx_ring_size;
1592 ctx.numa_node = cpu_to_node(rx_ring->cpu);
1593
1594 rc = ena_com_create_io_queue(ena_dev, &ctx);
1595 if (rc) {
1596 netif_err(adapter, ifup, adapter->netdev,
1597 "Failed to create I/O RX queue num %d rc: %d\n",
1598 qid, rc);
1599 return rc;
1600 }
1601
1602 rc = ena_com_get_io_handlers(ena_dev, ena_qid,
1603 &rx_ring->ena_com_io_sq,
1604 &rx_ring->ena_com_io_cq);
1605 if (rc) {
1606 netif_err(adapter, ifup, adapter->netdev,
1607 "Failed to get RX queue handlers. RX queue num %d rc: %d\n",
1608 qid, rc);
1609 ena_com_destroy_io_queue(ena_dev, ena_qid);
1610 }
1611
1612 ena_com_update_numa_node(rx_ring->ena_com_io_cq, ctx.numa_node);
1613
1614 return rc;
1615 }
1616
1617 static int ena_create_all_io_rx_queues(struct ena_adapter *adapter)
1618 {
1619 struct ena_com_dev *ena_dev = adapter->ena_dev;
1620 int rc, i;
1621
1622 for (i = 0; i < adapter->num_queues; i++) {
1623 rc = ena_create_io_rx_queue(adapter, i);
1624 if (rc)
1625 goto create_err;
1626 }
1627
1628 return 0;
1629
1630 create_err:
1631 while (i--)
1632 ena_com_destroy_io_queue(ena_dev, ENA_IO_RXQ_IDX(i));
1633
1634 return rc;
1635 }
1636
1637 static int ena_up(struct ena_adapter *adapter)
1638 {
1639 int rc;
1640
1641 netdev_dbg(adapter->netdev, "%s\n", __func__);
1642
1643 ena_setup_io_intr(adapter);
1644
1645 rc = ena_request_io_irq(adapter);
1646 if (rc)
1647 goto err_req_irq;
1648
1649 /* allocate transmit descriptors */
1650 rc = ena_setup_all_tx_resources(adapter);
1651 if (rc)
1652 goto err_setup_tx;
1653
1654 /* allocate receive descriptors */
1655 rc = ena_setup_all_rx_resources(adapter);
1656 if (rc)
1657 goto err_setup_rx;
1658
1659 /* Create TX queues */
1660 rc = ena_create_all_io_tx_queues(adapter);
1661 if (rc)
1662 goto err_create_tx_queues;
1663
1664 /* Create RX queues */
1665 rc = ena_create_all_io_rx_queues(adapter);
1666 if (rc)
1667 goto err_create_rx_queues;
1668
1669 rc = ena_up_complete(adapter);
1670 if (rc)
1671 goto err_up;
1672
1673 if (test_bit(ENA_FLAG_LINK_UP, &adapter->flags))
1674 netif_carrier_on(adapter->netdev);
1675
1676 u64_stats_update_begin(&adapter->syncp);
1677 adapter->dev_stats.interface_up++;
1678 u64_stats_update_end(&adapter->syncp);
1679
1680 set_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1681
1682 return rc;
1683
1684 err_up:
1685 ena_destroy_all_rx_queues(adapter);
1686 err_create_rx_queues:
1687 ena_destroy_all_tx_queues(adapter);
1688 err_create_tx_queues:
1689 ena_free_all_io_rx_resources(adapter);
1690 err_setup_rx:
1691 ena_free_all_io_tx_resources(adapter);
1692 err_setup_tx:
1693 ena_free_io_irq(adapter);
1694 err_req_irq:
1695
1696 return rc;
1697 }
1698
1699 static void ena_down(struct ena_adapter *adapter)
1700 {
1701 netif_info(adapter, ifdown, adapter->netdev, "%s\n", __func__);
1702
1703 clear_bit(ENA_FLAG_DEV_UP, &adapter->flags);
1704
1705 u64_stats_update_begin(&adapter->syncp);
1706 adapter->dev_stats.interface_down++;
1707 u64_stats_update_end(&adapter->syncp);
1708
1709 netif_carrier_off(adapter->netdev);
1710 netif_tx_disable(adapter->netdev);
1711
1712 /* After this point the napi handler won't enable the tx queue */
1713 ena_napi_disable_all(adapter);
1714
1715 /* After destroy the queue there won't be any new interrupts */
1716
1717 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags)) {
1718 int rc;
1719
1720 rc = ena_com_dev_reset(adapter->ena_dev);
1721 if (rc)
1722 dev_err(&adapter->pdev->dev, "Device reset failed\n");
1723 }
1724
1725 ena_destroy_all_io_queues(adapter);
1726
1727 ena_disable_io_intr_sync(adapter);
1728 ena_free_io_irq(adapter);
1729 ena_del_napi(adapter);
1730
1731 ena_free_all_tx_bufs(adapter);
1732 ena_free_all_rx_bufs(adapter);
1733 ena_free_all_io_tx_resources(adapter);
1734 ena_free_all_io_rx_resources(adapter);
1735 }
1736
1737 /* ena_open - Called when a network interface is made active
1738 * @netdev: network interface device structure
1739 *
1740 * Returns 0 on success, negative value on failure
1741 *
1742 * The open entry point is called when a network interface is made
1743 * active by the system (IFF_UP). At this point all resources needed
1744 * for transmit and receive operations are allocated, the interrupt
1745 * handler is registered with the OS, the watchdog timer is started,
1746 * and the stack is notified that the interface is ready.
1747 */
1748 static int ena_open(struct net_device *netdev)
1749 {
1750 struct ena_adapter *adapter = netdev_priv(netdev);
1751 int rc;
1752
1753 /* Notify the stack of the actual queue counts. */
1754 rc = netif_set_real_num_tx_queues(netdev, adapter->num_queues);
1755 if (rc) {
1756 netif_err(adapter, ifup, netdev, "Can't set num tx queues\n");
1757 return rc;
1758 }
1759
1760 rc = netif_set_real_num_rx_queues(netdev, adapter->num_queues);
1761 if (rc) {
1762 netif_err(adapter, ifup, netdev, "Can't set num rx queues\n");
1763 return rc;
1764 }
1765
1766 rc = ena_up(adapter);
1767 if (rc)
1768 return rc;
1769
1770 return rc;
1771 }
1772
1773 /* ena_close - Disables a network interface
1774 * @netdev: network interface device structure
1775 *
1776 * Returns 0, this is not allowed to fail
1777 *
1778 * The close entry point is called when an interface is de-activated
1779 * by the OS. The hardware is still under the drivers control, but
1780 * needs to be disabled. A global MAC reset is issued to stop the
1781 * hardware, and all transmit and receive resources are freed.
1782 */
1783 static int ena_close(struct net_device *netdev)
1784 {
1785 struct ena_adapter *adapter = netdev_priv(netdev);
1786
1787 netif_dbg(adapter, ifdown, netdev, "%s\n", __func__);
1788
1789 if (test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
1790 ena_down(adapter);
1791
1792 return 0;
1793 }
1794
1795 static void ena_tx_csum(struct ena_com_tx_ctx *ena_tx_ctx, struct sk_buff *skb)
1796 {
1797 u32 mss = skb_shinfo(skb)->gso_size;
1798 struct ena_com_tx_meta *ena_meta = &ena_tx_ctx->ena_meta;
1799 u8 l4_protocol = 0;
1800
1801 if ((skb->ip_summed == CHECKSUM_PARTIAL) || mss) {
1802 ena_tx_ctx->l4_csum_enable = 1;
1803 if (mss) {
1804 ena_tx_ctx->tso_enable = 1;
1805 ena_meta->l4_hdr_len = tcp_hdr(skb)->doff;
1806 ena_tx_ctx->l4_csum_partial = 0;
1807 } else {
1808 ena_tx_ctx->tso_enable = 0;
1809 ena_meta->l4_hdr_len = 0;
1810 ena_tx_ctx->l4_csum_partial = 1;
1811 }
1812
1813 switch (ip_hdr(skb)->version) {
1814 case IPVERSION:
1815 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV4;
1816 if (ip_hdr(skb)->frag_off & htons(IP_DF))
1817 ena_tx_ctx->df = 1;
1818 if (mss)
1819 ena_tx_ctx->l3_csum_enable = 1;
1820 l4_protocol = ip_hdr(skb)->protocol;
1821 break;
1822 case 6:
1823 ena_tx_ctx->l3_proto = ENA_ETH_IO_L3_PROTO_IPV6;
1824 l4_protocol = ipv6_hdr(skb)->nexthdr;
1825 break;
1826 default:
1827 break;
1828 }
1829
1830 if (l4_protocol == IPPROTO_TCP)
1831 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_TCP;
1832 else
1833 ena_tx_ctx->l4_proto = ENA_ETH_IO_L4_PROTO_UDP;
1834
1835 ena_meta->mss = mss;
1836 ena_meta->l3_hdr_len = skb_network_header_len(skb);
1837 ena_meta->l3_hdr_offset = skb_network_offset(skb);
1838 ena_tx_ctx->meta_valid = 1;
1839
1840 } else {
1841 ena_tx_ctx->meta_valid = 0;
1842 }
1843 }
1844
1845 static int ena_check_and_linearize_skb(struct ena_ring *tx_ring,
1846 struct sk_buff *skb)
1847 {
1848 int num_frags, header_len, rc;
1849
1850 num_frags = skb_shinfo(skb)->nr_frags;
1851 header_len = skb_headlen(skb);
1852
1853 if (num_frags < tx_ring->sgl_size)
1854 return 0;
1855
1856 if ((num_frags == tx_ring->sgl_size) &&
1857 (header_len < tx_ring->tx_max_header_size))
1858 return 0;
1859
1860 u64_stats_update_begin(&tx_ring->syncp);
1861 tx_ring->tx_stats.linearize++;
1862 u64_stats_update_end(&tx_ring->syncp);
1863
1864 rc = skb_linearize(skb);
1865 if (unlikely(rc)) {
1866 u64_stats_update_begin(&tx_ring->syncp);
1867 tx_ring->tx_stats.linearize_failed++;
1868 u64_stats_update_end(&tx_ring->syncp);
1869 }
1870
1871 return rc;
1872 }
1873
1874 /* Called with netif_tx_lock. */
1875 static netdev_tx_t ena_start_xmit(struct sk_buff *skb, struct net_device *dev)
1876 {
1877 struct ena_adapter *adapter = netdev_priv(dev);
1878 struct ena_tx_buffer *tx_info;
1879 struct ena_com_tx_ctx ena_tx_ctx;
1880 struct ena_ring *tx_ring;
1881 struct netdev_queue *txq;
1882 struct ena_com_buf *ena_buf;
1883 void *push_hdr;
1884 u32 len, last_frag;
1885 u16 next_to_use;
1886 u16 req_id;
1887 u16 push_len;
1888 u16 header_len;
1889 dma_addr_t dma;
1890 int qid, rc, nb_hw_desc;
1891 int i = -1;
1892
1893 netif_dbg(adapter, tx_queued, dev, "%s skb %p\n", __func__, skb);
1894 /* Determine which tx ring we will be placed on */
1895 qid = skb_get_queue_mapping(skb);
1896 tx_ring = &adapter->tx_ring[qid];
1897 txq = netdev_get_tx_queue(dev, qid);
1898
1899 rc = ena_check_and_linearize_skb(tx_ring, skb);
1900 if (unlikely(rc))
1901 goto error_drop_packet;
1902
1903 skb_tx_timestamp(skb);
1904 len = skb_headlen(skb);
1905
1906 next_to_use = tx_ring->next_to_use;
1907 req_id = tx_ring->free_tx_ids[next_to_use];
1908 tx_info = &tx_ring->tx_buffer_info[req_id];
1909 tx_info->num_of_bufs = 0;
1910
1911 WARN(tx_info->skb, "SKB isn't NULL req_id %d\n", req_id);
1912 ena_buf = tx_info->bufs;
1913 tx_info->skb = skb;
1914
1915 if (tx_ring->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
1916 /* prepared the push buffer */
1917 push_len = min_t(u32, len, tx_ring->tx_max_header_size);
1918 header_len = push_len;
1919 push_hdr = skb->data;
1920 } else {
1921 push_len = 0;
1922 header_len = min_t(u32, len, tx_ring->tx_max_header_size);
1923 push_hdr = NULL;
1924 }
1925
1926 netif_dbg(adapter, tx_queued, dev,
1927 "skb: %p header_buf->vaddr: %p push_len: %d\n", skb,
1928 push_hdr, push_len);
1929
1930 if (len > push_len) {
1931 dma = dma_map_single(tx_ring->dev, skb->data + push_len,
1932 len - push_len, DMA_TO_DEVICE);
1933 if (dma_mapping_error(tx_ring->dev, dma))
1934 goto error_report_dma_error;
1935
1936 ena_buf->paddr = dma;
1937 ena_buf->len = len - push_len;
1938
1939 ena_buf++;
1940 tx_info->num_of_bufs++;
1941 }
1942
1943 last_frag = skb_shinfo(skb)->nr_frags;
1944
1945 for (i = 0; i < last_frag; i++) {
1946 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1947
1948 len = skb_frag_size(frag);
1949 dma = skb_frag_dma_map(tx_ring->dev, frag, 0, len,
1950 DMA_TO_DEVICE);
1951 if (dma_mapping_error(tx_ring->dev, dma))
1952 goto error_report_dma_error;
1953
1954 ena_buf->paddr = dma;
1955 ena_buf->len = len;
1956 ena_buf++;
1957 }
1958
1959 tx_info->num_of_bufs += last_frag;
1960
1961 memset(&ena_tx_ctx, 0x0, sizeof(struct ena_com_tx_ctx));
1962 ena_tx_ctx.ena_bufs = tx_info->bufs;
1963 ena_tx_ctx.push_header = push_hdr;
1964 ena_tx_ctx.num_bufs = tx_info->num_of_bufs;
1965 ena_tx_ctx.req_id = req_id;
1966 ena_tx_ctx.header_len = header_len;
1967
1968 /* set flags and meta data */
1969 ena_tx_csum(&ena_tx_ctx, skb);
1970
1971 /* prepare the packet's descriptors to dma engine */
1972 rc = ena_com_prepare_tx(tx_ring->ena_com_io_sq, &ena_tx_ctx,
1973 &nb_hw_desc);
1974
1975 if (unlikely(rc)) {
1976 netif_err(adapter, tx_queued, dev,
1977 "failed to prepare tx bufs\n");
1978 u64_stats_update_begin(&tx_ring->syncp);
1979 tx_ring->tx_stats.queue_stop++;
1980 tx_ring->tx_stats.prepare_ctx_err++;
1981 u64_stats_update_end(&tx_ring->syncp);
1982 netif_tx_stop_queue(txq);
1983 goto error_unmap_dma;
1984 }
1985
1986 netdev_tx_sent_queue(txq, skb->len);
1987
1988 u64_stats_update_begin(&tx_ring->syncp);
1989 tx_ring->tx_stats.cnt++;
1990 tx_ring->tx_stats.bytes += skb->len;
1991 u64_stats_update_end(&tx_ring->syncp);
1992
1993 tx_info->tx_descs = nb_hw_desc;
1994 tx_info->last_jiffies = jiffies;
1995
1996 tx_ring->next_to_use = ENA_TX_RING_IDX_NEXT(next_to_use,
1997 tx_ring->ring_size);
1998
1999 /* This WMB is aimed to:
2000 * 1 - perform smp barrier before reading next_to_completion
2001 * 2 - make sure the desc were written before trigger DB
2002 */
2003 wmb();
2004
2005 /* stop the queue when no more space available, the packet can have up
2006 * to sgl_size + 2. one for the meta descriptor and one for header
2007 * (if the header is larger than tx_max_header_size).
2008 */
2009 if (unlikely(ena_com_sq_empty_space(tx_ring->ena_com_io_sq) <
2010 (tx_ring->sgl_size + 2))) {
2011 netif_dbg(adapter, tx_queued, dev, "%s stop queue %d\n",
2012 __func__, qid);
2013
2014 netif_tx_stop_queue(txq);
2015 u64_stats_update_begin(&tx_ring->syncp);
2016 tx_ring->tx_stats.queue_stop++;
2017 u64_stats_update_end(&tx_ring->syncp);
2018
2019 /* There is a rare condition where this function decide to
2020 * stop the queue but meanwhile clean_tx_irq updates
2021 * next_to_completion and terminates.
2022 * The queue will remain stopped forever.
2023 * To solve this issue this function perform rmb, check
2024 * the wakeup condition and wake up the queue if needed.
2025 */
2026 smp_rmb();
2027
2028 if (ena_com_sq_empty_space(tx_ring->ena_com_io_sq)
2029 > ENA_TX_WAKEUP_THRESH) {
2030 netif_tx_wake_queue(txq);
2031 u64_stats_update_begin(&tx_ring->syncp);
2032 tx_ring->tx_stats.queue_wakeup++;
2033 u64_stats_update_end(&tx_ring->syncp);
2034 }
2035 }
2036
2037 if (netif_xmit_stopped(txq) || !skb->xmit_more) {
2038 /* trigger the dma engine */
2039 ena_com_write_sq_doorbell(tx_ring->ena_com_io_sq);
2040 u64_stats_update_begin(&tx_ring->syncp);
2041 tx_ring->tx_stats.doorbells++;
2042 u64_stats_update_end(&tx_ring->syncp);
2043 }
2044
2045 return NETDEV_TX_OK;
2046
2047 error_report_dma_error:
2048 u64_stats_update_begin(&tx_ring->syncp);
2049 tx_ring->tx_stats.dma_mapping_err++;
2050 u64_stats_update_end(&tx_ring->syncp);
2051 netdev_warn(adapter->netdev, "failed to map skb\n");
2052
2053 tx_info->skb = NULL;
2054
2055 error_unmap_dma:
2056 if (i >= 0) {
2057 /* save value of frag that failed */
2058 last_frag = i;
2059
2060 /* start back at beginning and unmap skb */
2061 tx_info->skb = NULL;
2062 ena_buf = tx_info->bufs;
2063 dma_unmap_single(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
2064 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
2065
2066 /* unmap remaining mapped pages */
2067 for (i = 0; i < last_frag; i++) {
2068 ena_buf++;
2069 dma_unmap_page(tx_ring->dev, dma_unmap_addr(ena_buf, paddr),
2070 dma_unmap_len(ena_buf, len), DMA_TO_DEVICE);
2071 }
2072 }
2073
2074 error_drop_packet:
2075
2076 dev_kfree_skb(skb);
2077 return NETDEV_TX_OK;
2078 }
2079
2080 #ifdef CONFIG_NET_POLL_CONTROLLER
2081 static void ena_netpoll(struct net_device *netdev)
2082 {
2083 struct ena_adapter *adapter = netdev_priv(netdev);
2084 int i;
2085
2086 /* Dont schedule NAPI if the driver is in the middle of reset
2087 * or netdev is down.
2088 */
2089
2090 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags) ||
2091 test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2092 return;
2093
2094 for (i = 0; i < adapter->num_queues; i++)
2095 napi_schedule(&adapter->ena_napi[i].napi);
2096 }
2097 #endif /* CONFIG_NET_POLL_CONTROLLER */
2098
2099 static u16 ena_select_queue(struct net_device *dev, struct sk_buff *skb,
2100 void *accel_priv, select_queue_fallback_t fallback)
2101 {
2102 u16 qid;
2103 /* we suspect that this is good for in--kernel network services that
2104 * want to loop incoming skb rx to tx in normal user generated traffic,
2105 * most probably we will not get to this
2106 */
2107 if (skb_rx_queue_recorded(skb))
2108 qid = skb_get_rx_queue(skb);
2109 else
2110 qid = fallback(dev, skb);
2111
2112 return qid;
2113 }
2114
2115 static void ena_config_host_info(struct ena_com_dev *ena_dev)
2116 {
2117 struct ena_admin_host_info *host_info;
2118 int rc;
2119
2120 /* Allocate only the host info */
2121 rc = ena_com_allocate_host_info(ena_dev);
2122 if (rc) {
2123 pr_err("Cannot allocate host info\n");
2124 return;
2125 }
2126
2127 host_info = ena_dev->host_attr.host_info;
2128
2129 host_info->os_type = ENA_ADMIN_OS_LINUX;
2130 host_info->kernel_ver = LINUX_VERSION_CODE;
2131 strncpy(host_info->kernel_ver_str, utsname()->version,
2132 sizeof(host_info->kernel_ver_str) - 1);
2133 host_info->os_dist = 0;
2134 strncpy(host_info->os_dist_str, utsname()->release,
2135 sizeof(host_info->os_dist_str) - 1);
2136 host_info->driver_version =
2137 (DRV_MODULE_VER_MAJOR) |
2138 (DRV_MODULE_VER_MINOR << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) |
2139 (DRV_MODULE_VER_SUBMINOR << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT);
2140
2141 rc = ena_com_set_host_attributes(ena_dev);
2142 if (rc) {
2143 if (rc == -EPERM)
2144 pr_warn("Cannot set host attributes\n");
2145 else
2146 pr_err("Cannot set host attributes\n");
2147
2148 goto err;
2149 }
2150
2151 return;
2152
2153 err:
2154 ena_com_delete_host_info(ena_dev);
2155 }
2156
2157 static void ena_config_debug_area(struct ena_adapter *adapter)
2158 {
2159 u32 debug_area_size;
2160 int rc, ss_count;
2161
2162 ss_count = ena_get_sset_count(adapter->netdev, ETH_SS_STATS);
2163 if (ss_count <= 0) {
2164 netif_err(adapter, drv, adapter->netdev,
2165 "SS count is negative\n");
2166 return;
2167 }
2168
2169 /* allocate 32 bytes for each string and 64bit for the value */
2170 debug_area_size = ss_count * ETH_GSTRING_LEN + sizeof(u64) * ss_count;
2171
2172 rc = ena_com_allocate_debug_area(adapter->ena_dev, debug_area_size);
2173 if (rc) {
2174 pr_err("Cannot allocate debug area\n");
2175 return;
2176 }
2177
2178 rc = ena_com_set_host_attributes(adapter->ena_dev);
2179 if (rc) {
2180 if (rc == -EPERM)
2181 netif_warn(adapter, drv, adapter->netdev,
2182 "Cannot set host attributes\n");
2183 else
2184 netif_err(adapter, drv, adapter->netdev,
2185 "Cannot set host attributes\n");
2186 goto err;
2187 }
2188
2189 return;
2190 err:
2191 ena_com_delete_debug_area(adapter->ena_dev);
2192 }
2193
2194 static struct rtnl_link_stats64 *ena_get_stats64(struct net_device *netdev,
2195 struct rtnl_link_stats64 *stats)
2196 {
2197 struct ena_adapter *adapter = netdev_priv(netdev);
2198 struct ena_ring *rx_ring, *tx_ring;
2199 unsigned int start;
2200 u64 rx_drops;
2201 int i;
2202
2203 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2204 return NULL;
2205
2206 for (i = 0; i < adapter->num_queues; i++) {
2207 u64 bytes, packets;
2208
2209 tx_ring = &adapter->tx_ring[i];
2210
2211 do {
2212 start = u64_stats_fetch_begin_irq(&tx_ring->syncp);
2213 packets = tx_ring->tx_stats.cnt;
2214 bytes = tx_ring->tx_stats.bytes;
2215 } while (u64_stats_fetch_retry_irq(&tx_ring->syncp, start));
2216
2217 stats->tx_packets += packets;
2218 stats->tx_bytes += bytes;
2219
2220 rx_ring = &adapter->rx_ring[i];
2221
2222 do {
2223 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
2224 packets = rx_ring->rx_stats.cnt;
2225 bytes = rx_ring->rx_stats.bytes;
2226 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
2227
2228 stats->rx_packets += packets;
2229 stats->rx_bytes += bytes;
2230 }
2231
2232 do {
2233 start = u64_stats_fetch_begin_irq(&adapter->syncp);
2234 rx_drops = adapter->dev_stats.rx_drops;
2235 } while (u64_stats_fetch_retry_irq(&adapter->syncp, start));
2236
2237 stats->rx_dropped = rx_drops;
2238
2239 stats->multicast = 0;
2240 stats->collisions = 0;
2241
2242 stats->rx_length_errors = 0;
2243 stats->rx_crc_errors = 0;
2244 stats->rx_frame_errors = 0;
2245 stats->rx_fifo_errors = 0;
2246 stats->rx_missed_errors = 0;
2247 stats->tx_window_errors = 0;
2248
2249 stats->rx_errors = 0;
2250 stats->tx_errors = 0;
2251
2252 return stats;
2253 }
2254
2255 static const struct net_device_ops ena_netdev_ops = {
2256 .ndo_open = ena_open,
2257 .ndo_stop = ena_close,
2258 .ndo_start_xmit = ena_start_xmit,
2259 .ndo_select_queue = ena_select_queue,
2260 .ndo_get_stats64 = ena_get_stats64,
2261 .ndo_tx_timeout = ena_tx_timeout,
2262 .ndo_change_mtu = ena_change_mtu,
2263 .ndo_set_mac_address = NULL,
2264 .ndo_validate_addr = eth_validate_addr,
2265 #ifdef CONFIG_NET_POLL_CONTROLLER
2266 .ndo_poll_controller = ena_netpoll,
2267 #endif /* CONFIG_NET_POLL_CONTROLLER */
2268 };
2269
2270 static void ena_device_io_suspend(struct work_struct *work)
2271 {
2272 struct ena_adapter *adapter =
2273 container_of(work, struct ena_adapter, suspend_io_task);
2274 struct net_device *netdev = adapter->netdev;
2275
2276 /* ena_napi_disable_all disables only the IO handling.
2277 * We are still subject to AENQ keep alive watchdog.
2278 */
2279 u64_stats_update_begin(&adapter->syncp);
2280 adapter->dev_stats.io_suspend++;
2281 u64_stats_update_begin(&adapter->syncp);
2282 ena_napi_disable_all(adapter);
2283 netif_tx_lock(netdev);
2284 netif_device_detach(netdev);
2285 netif_tx_unlock(netdev);
2286 }
2287
2288 static void ena_device_io_resume(struct work_struct *work)
2289 {
2290 struct ena_adapter *adapter =
2291 container_of(work, struct ena_adapter, resume_io_task);
2292 struct net_device *netdev = adapter->netdev;
2293
2294 u64_stats_update_begin(&adapter->syncp);
2295 adapter->dev_stats.io_resume++;
2296 u64_stats_update_end(&adapter->syncp);
2297
2298 netif_device_attach(netdev);
2299 ena_napi_enable_all(adapter);
2300 }
2301
2302 static int ena_device_validate_params(struct ena_adapter *adapter,
2303 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2304 {
2305 struct net_device *netdev = adapter->netdev;
2306 int rc;
2307
2308 rc = ether_addr_equal(get_feat_ctx->dev_attr.mac_addr,
2309 adapter->mac_addr);
2310 if (!rc) {
2311 netif_err(adapter, drv, netdev,
2312 "Error, mac address are different\n");
2313 return -EINVAL;
2314 }
2315
2316 if ((get_feat_ctx->max_queues.max_cq_num < adapter->num_queues) ||
2317 (get_feat_ctx->max_queues.max_sq_num < adapter->num_queues)) {
2318 netif_err(adapter, drv, netdev,
2319 "Error, device doesn't support enough queues\n");
2320 return -EINVAL;
2321 }
2322
2323 if (get_feat_ctx->dev_attr.max_mtu < netdev->mtu) {
2324 netif_err(adapter, drv, netdev,
2325 "Error, device max mtu is smaller than netdev MTU\n");
2326 return -EINVAL;
2327 }
2328
2329 return 0;
2330 }
2331
2332 static int ena_device_init(struct ena_com_dev *ena_dev, struct pci_dev *pdev,
2333 struct ena_com_dev_get_features_ctx *get_feat_ctx,
2334 bool *wd_state)
2335 {
2336 struct device *dev = &pdev->dev;
2337 bool readless_supported;
2338 u32 aenq_groups;
2339 int dma_width;
2340 int rc;
2341
2342 rc = ena_com_mmio_reg_read_request_init(ena_dev);
2343 if (rc) {
2344 dev_err(dev, "failed to init mmio read less\n");
2345 return rc;
2346 }
2347
2348 /* The PCIe configuration space revision id indicate if mmio reg
2349 * read is disabled
2350 */
2351 readless_supported = !(pdev->revision & ENA_MMIO_DISABLE_REG_READ);
2352 ena_com_set_mmio_read_mode(ena_dev, readless_supported);
2353
2354 rc = ena_com_dev_reset(ena_dev);
2355 if (rc) {
2356 dev_err(dev, "Can not reset device\n");
2357 goto err_mmio_read_less;
2358 }
2359
2360 rc = ena_com_validate_version(ena_dev);
2361 if (rc) {
2362 dev_err(dev, "device version is too low\n");
2363 goto err_mmio_read_less;
2364 }
2365
2366 dma_width = ena_com_get_dma_width(ena_dev);
2367 if (dma_width < 0) {
2368 dev_err(dev, "Invalid dma width value %d", dma_width);
2369 rc = dma_width;
2370 goto err_mmio_read_less;
2371 }
2372
2373 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2374 if (rc) {
2375 dev_err(dev, "pci_set_dma_mask failed 0x%x\n", rc);
2376 goto err_mmio_read_less;
2377 }
2378
2379 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(dma_width));
2380 if (rc) {
2381 dev_err(dev, "err_pci_set_consistent_dma_mask failed 0x%x\n",
2382 rc);
2383 goto err_mmio_read_less;
2384 }
2385
2386 /* ENA admin level init */
2387 rc = ena_com_admin_init(ena_dev, &aenq_handlers, true);
2388 if (rc) {
2389 dev_err(dev,
2390 "Can not initialize ena admin queue with device\n");
2391 goto err_mmio_read_less;
2392 }
2393
2394 /* To enable the msix interrupts the driver needs to know the number
2395 * of queues. So the driver uses polling mode to retrieve this
2396 * information
2397 */
2398 ena_com_set_admin_polling_mode(ena_dev, true);
2399
2400 ena_config_host_info(ena_dev);
2401
2402 /* Get Device Attributes*/
2403 rc = ena_com_get_dev_attr_feat(ena_dev, get_feat_ctx);
2404 if (rc) {
2405 dev_err(dev, "Cannot get attribute for ena device rc=%d\n", rc);
2406 goto err_admin_init;
2407 }
2408
2409 /* Try to turn all the available aenq groups */
2410 aenq_groups = BIT(ENA_ADMIN_LINK_CHANGE) |
2411 BIT(ENA_ADMIN_FATAL_ERROR) |
2412 BIT(ENA_ADMIN_WARNING) |
2413 BIT(ENA_ADMIN_NOTIFICATION) |
2414 BIT(ENA_ADMIN_KEEP_ALIVE);
2415
2416 aenq_groups &= get_feat_ctx->aenq.supported_groups;
2417
2418 rc = ena_com_set_aenq_config(ena_dev, aenq_groups);
2419 if (rc) {
2420 dev_err(dev, "Cannot configure aenq groups rc= %d\n", rc);
2421 goto err_admin_init;
2422 }
2423
2424 *wd_state = !!(aenq_groups & BIT(ENA_ADMIN_KEEP_ALIVE));
2425
2426 return 0;
2427
2428 err_admin_init:
2429 ena_com_delete_host_info(ena_dev);
2430 ena_com_admin_destroy(ena_dev);
2431 err_mmio_read_less:
2432 ena_com_mmio_reg_read_request_destroy(ena_dev);
2433
2434 return rc;
2435 }
2436
2437 static int ena_enable_msix_and_set_admin_interrupts(struct ena_adapter *adapter,
2438 int io_vectors)
2439 {
2440 struct ena_com_dev *ena_dev = adapter->ena_dev;
2441 struct device *dev = &adapter->pdev->dev;
2442 int rc;
2443
2444 rc = ena_enable_msix(adapter, io_vectors);
2445 if (rc) {
2446 dev_err(dev, "Can not reserve msix vectors\n");
2447 return rc;
2448 }
2449
2450 ena_setup_mgmnt_intr(adapter);
2451
2452 rc = ena_request_mgmnt_irq(adapter);
2453 if (rc) {
2454 dev_err(dev, "Can not setup management interrupts\n");
2455 goto err_disable_msix;
2456 }
2457
2458 ena_com_set_admin_polling_mode(ena_dev, false);
2459
2460 ena_com_admin_aenq_enable(ena_dev);
2461
2462 return 0;
2463
2464 err_disable_msix:
2465 pci_free_irq_vectors(adapter->pdev);
2466 return rc;
2467 }
2468
2469 static void ena_fw_reset_device(struct work_struct *work)
2470 {
2471 struct ena_com_dev_get_features_ctx get_feat_ctx;
2472 struct ena_adapter *adapter =
2473 container_of(work, struct ena_adapter, reset_task);
2474 struct net_device *netdev = adapter->netdev;
2475 struct ena_com_dev *ena_dev = adapter->ena_dev;
2476 struct pci_dev *pdev = adapter->pdev;
2477 bool dev_up, wd_state;
2478 int rc;
2479
2480 if (unlikely(!test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
2481 dev_err(&pdev->dev,
2482 "device reset schedule while reset bit is off\n");
2483 return;
2484 }
2485
2486 netif_carrier_off(netdev);
2487
2488 del_timer_sync(&adapter->timer_service);
2489
2490 rtnl_lock();
2491
2492 dev_up = test_bit(ENA_FLAG_DEV_UP, &adapter->flags);
2493 ena_com_set_admin_running_state(ena_dev, false);
2494
2495 /* After calling ena_close the tx queues and the napi
2496 * are disabled so no one can interfere or touch the
2497 * data structures
2498 */
2499 ena_close(netdev);
2500
2501 ena_free_mgmnt_irq(adapter);
2502
2503 pci_free_irq_vectors(adapter->pdev);
2504
2505 ena_com_abort_admin_commands(ena_dev);
2506
2507 ena_com_wait_for_abort_completion(ena_dev);
2508
2509 ena_com_admin_destroy(ena_dev);
2510
2511 ena_com_mmio_reg_read_request_destroy(ena_dev);
2512
2513 clear_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2514
2515 /* Finish with the destroy part. Start the init part */
2516
2517 rc = ena_device_init(ena_dev, adapter->pdev, &get_feat_ctx, &wd_state);
2518 if (rc) {
2519 dev_err(&pdev->dev, "Can not initialize device\n");
2520 goto err;
2521 }
2522 adapter->wd_state = wd_state;
2523
2524 rc = ena_device_validate_params(adapter, &get_feat_ctx);
2525 if (rc) {
2526 dev_err(&pdev->dev, "Validation of device parameters failed\n");
2527 goto err_device_destroy;
2528 }
2529
2530 rc = ena_enable_msix_and_set_admin_interrupts(adapter,
2531 adapter->num_queues);
2532 if (rc) {
2533 dev_err(&pdev->dev, "Enable MSI-X failed\n");
2534 goto err_device_destroy;
2535 }
2536 /* If the interface was up before the reset bring it up */
2537 if (dev_up) {
2538 rc = ena_up(adapter);
2539 if (rc) {
2540 dev_err(&pdev->dev, "Failed to create I/O queues\n");
2541 goto err_disable_msix;
2542 }
2543 }
2544
2545 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
2546
2547 rtnl_unlock();
2548
2549 dev_err(&pdev->dev, "Device reset completed successfully\n");
2550
2551 return;
2552 err_disable_msix:
2553 ena_free_mgmnt_irq(adapter);
2554 pci_free_irq_vectors(adapter->pdev);
2555 err_device_destroy:
2556 ena_com_admin_destroy(ena_dev);
2557 err:
2558 rtnl_unlock();
2559
2560 clear_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
2561
2562 dev_err(&pdev->dev,
2563 "Reset attempt failed. Can not reset the device\n");
2564 }
2565
2566 static void check_for_missing_tx_completions(struct ena_adapter *adapter)
2567 {
2568 struct ena_tx_buffer *tx_buf;
2569 unsigned long last_jiffies;
2570 struct ena_ring *tx_ring;
2571 int i, j, budget;
2572 u32 missed_tx;
2573
2574 /* Make sure the driver doesn't turn the device in other process */
2575 smp_rmb();
2576
2577 if (!test_bit(ENA_FLAG_DEV_UP, &adapter->flags))
2578 return;
2579
2580 if (test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))
2581 return;
2582
2583 budget = ENA_MONITORED_TX_QUEUES;
2584
2585 for (i = adapter->last_monitored_tx_qid; i < adapter->num_queues; i++) {
2586 tx_ring = &adapter->tx_ring[i];
2587
2588 for (j = 0; j < tx_ring->ring_size; j++) {
2589 tx_buf = &tx_ring->tx_buffer_info[j];
2590 last_jiffies = tx_buf->last_jiffies;
2591 if (unlikely(last_jiffies && time_is_before_jiffies(last_jiffies + TX_TIMEOUT))) {
2592 netif_notice(adapter, tx_err, adapter->netdev,
2593 "Found a Tx that wasn't completed on time, qid %d, index %d.\n",
2594 tx_ring->qid, j);
2595
2596 u64_stats_update_begin(&tx_ring->syncp);
2597 missed_tx = tx_ring->tx_stats.missing_tx_comp++;
2598 u64_stats_update_end(&tx_ring->syncp);
2599
2600 /* Clear last jiffies so the lost buffer won't
2601 * be counted twice.
2602 */
2603 tx_buf->last_jiffies = 0;
2604
2605 if (unlikely(missed_tx > MAX_NUM_OF_TIMEOUTED_PACKETS)) {
2606 netif_err(adapter, tx_err, adapter->netdev,
2607 "The number of lost tx completion is above the threshold (%d > %d). Reset the device\n",
2608 missed_tx, MAX_NUM_OF_TIMEOUTED_PACKETS);
2609 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2610 }
2611 }
2612 }
2613
2614 budget--;
2615 if (!budget)
2616 break;
2617 }
2618
2619 adapter->last_monitored_tx_qid = i % adapter->num_queues;
2620 }
2621
2622 /* Check for keep alive expiration */
2623 static void check_for_missing_keep_alive(struct ena_adapter *adapter)
2624 {
2625 unsigned long keep_alive_expired;
2626
2627 if (!adapter->wd_state)
2628 return;
2629
2630 keep_alive_expired = round_jiffies(adapter->last_keep_alive_jiffies
2631 + ENA_DEVICE_KALIVE_TIMEOUT);
2632 if (unlikely(time_is_before_jiffies(keep_alive_expired))) {
2633 netif_err(adapter, drv, adapter->netdev,
2634 "Keep alive watchdog timeout.\n");
2635 u64_stats_update_begin(&adapter->syncp);
2636 adapter->dev_stats.wd_expired++;
2637 u64_stats_update_end(&adapter->syncp);
2638 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2639 }
2640 }
2641
2642 static void check_for_admin_com_state(struct ena_adapter *adapter)
2643 {
2644 if (unlikely(!ena_com_get_admin_running_state(adapter->ena_dev))) {
2645 netif_err(adapter, drv, adapter->netdev,
2646 "ENA admin queue is not in running state!\n");
2647 u64_stats_update_begin(&adapter->syncp);
2648 adapter->dev_stats.admin_q_pause++;
2649 u64_stats_update_end(&adapter->syncp);
2650 set_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags);
2651 }
2652 }
2653
2654 static void ena_update_host_info(struct ena_admin_host_info *host_info,
2655 struct net_device *netdev)
2656 {
2657 host_info->supported_network_features[0] =
2658 netdev->features & GENMASK_ULL(31, 0);
2659 host_info->supported_network_features[1] =
2660 (netdev->features & GENMASK_ULL(63, 32)) >> 32;
2661 }
2662
2663 static void ena_timer_service(unsigned long data)
2664 {
2665 struct ena_adapter *adapter = (struct ena_adapter *)data;
2666 u8 *debug_area = adapter->ena_dev->host_attr.debug_area_virt_addr;
2667 struct ena_admin_host_info *host_info =
2668 adapter->ena_dev->host_attr.host_info;
2669
2670 check_for_missing_keep_alive(adapter);
2671
2672 check_for_admin_com_state(adapter);
2673
2674 check_for_missing_tx_completions(adapter);
2675
2676 if (debug_area)
2677 ena_dump_stats_to_buf(adapter, debug_area);
2678
2679 if (host_info)
2680 ena_update_host_info(host_info, adapter->netdev);
2681
2682 if (unlikely(test_bit(ENA_FLAG_TRIGGER_RESET, &adapter->flags))) {
2683 netif_err(adapter, drv, adapter->netdev,
2684 "Trigger reset is on\n");
2685 ena_dump_stats_to_dmesg(adapter);
2686 queue_work(ena_wq, &adapter->reset_task);
2687 return;
2688 }
2689
2690 /* Reset the timer */
2691 mod_timer(&adapter->timer_service, jiffies + HZ);
2692 }
2693
2694 static int ena_calc_io_queue_num(struct pci_dev *pdev,
2695 struct ena_com_dev *ena_dev,
2696 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2697 {
2698 int io_sq_num, io_queue_num;
2699
2700 /* In case of LLQ use the llq number in the get feature cmd */
2701 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2702 io_sq_num = get_feat_ctx->max_queues.max_llq_num;
2703
2704 if (io_sq_num == 0) {
2705 dev_err(&pdev->dev,
2706 "Trying to use LLQ but llq_num is 0. Fall back into regular queues\n");
2707
2708 ena_dev->tx_mem_queue_type =
2709 ENA_ADMIN_PLACEMENT_POLICY_HOST;
2710 io_sq_num = get_feat_ctx->max_queues.max_sq_num;
2711 }
2712 } else {
2713 io_sq_num = get_feat_ctx->max_queues.max_sq_num;
2714 }
2715
2716 io_queue_num = min_t(int, num_online_cpus(), ENA_MAX_NUM_IO_QUEUES);
2717 io_queue_num = min_t(int, io_queue_num, io_sq_num);
2718 io_queue_num = min_t(int, io_queue_num,
2719 get_feat_ctx->max_queues.max_cq_num);
2720 /* 1 IRQ for for mgmnt and 1 IRQs for each IO direction */
2721 io_queue_num = min_t(int, io_queue_num, pci_msix_vec_count(pdev) - 1);
2722 if (unlikely(!io_queue_num)) {
2723 dev_err(&pdev->dev, "The device doesn't have io queues\n");
2724 return -EFAULT;
2725 }
2726
2727 return io_queue_num;
2728 }
2729
2730 static void ena_set_push_mode(struct pci_dev *pdev, struct ena_com_dev *ena_dev,
2731 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2732 {
2733 bool has_mem_bar;
2734
2735 has_mem_bar = pci_select_bars(pdev, IORESOURCE_MEM) & BIT(ENA_MEM_BAR);
2736
2737 /* Enable push mode if device supports LLQ */
2738 if (has_mem_bar && (get_feat_ctx->max_queues.max_llq_num > 0))
2739 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_DEV;
2740 else
2741 ena_dev->tx_mem_queue_type = ENA_ADMIN_PLACEMENT_POLICY_HOST;
2742 }
2743
2744 static void ena_set_dev_offloads(struct ena_com_dev_get_features_ctx *feat,
2745 struct net_device *netdev)
2746 {
2747 netdev_features_t dev_features = 0;
2748
2749 /* Set offload features */
2750 if (feat->offload.tx &
2751 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK)
2752 dev_features |= NETIF_F_IP_CSUM;
2753
2754 if (feat->offload.tx &
2755 ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK)
2756 dev_features |= NETIF_F_IPV6_CSUM;
2757
2758 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK)
2759 dev_features |= NETIF_F_TSO;
2760
2761 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK)
2762 dev_features |= NETIF_F_TSO6;
2763
2764 if (feat->offload.tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK)
2765 dev_features |= NETIF_F_TSO_ECN;
2766
2767 if (feat->offload.rx_supported &
2768 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK)
2769 dev_features |= NETIF_F_RXCSUM;
2770
2771 if (feat->offload.rx_supported &
2772 ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK)
2773 dev_features |= NETIF_F_RXCSUM;
2774
2775 netdev->features =
2776 dev_features |
2777 NETIF_F_SG |
2778 NETIF_F_RXHASH |
2779 NETIF_F_HIGHDMA;
2780
2781 netdev->hw_features |= netdev->features;
2782 netdev->vlan_features |= netdev->features;
2783 }
2784
2785 static void ena_set_conf_feat_params(struct ena_adapter *adapter,
2786 struct ena_com_dev_get_features_ctx *feat)
2787 {
2788 struct net_device *netdev = adapter->netdev;
2789
2790 /* Copy mac address */
2791 if (!is_valid_ether_addr(feat->dev_attr.mac_addr)) {
2792 eth_hw_addr_random(netdev);
2793 ether_addr_copy(adapter->mac_addr, netdev->dev_addr);
2794 } else {
2795 ether_addr_copy(adapter->mac_addr, feat->dev_attr.mac_addr);
2796 ether_addr_copy(netdev->dev_addr, adapter->mac_addr);
2797 }
2798
2799 /* Set offload features */
2800 ena_set_dev_offloads(feat, netdev);
2801
2802 adapter->max_mtu = feat->dev_attr.max_mtu;
2803 netdev->max_mtu = adapter->max_mtu;
2804 netdev->min_mtu = ENA_MIN_MTU;
2805 }
2806
2807 static int ena_rss_init_default(struct ena_adapter *adapter)
2808 {
2809 struct ena_com_dev *ena_dev = adapter->ena_dev;
2810 struct device *dev = &adapter->pdev->dev;
2811 int rc, i;
2812 u32 val;
2813
2814 rc = ena_com_rss_init(ena_dev, ENA_RX_RSS_TABLE_LOG_SIZE);
2815 if (unlikely(rc)) {
2816 dev_err(dev, "Cannot init indirect table\n");
2817 goto err_rss_init;
2818 }
2819
2820 for (i = 0; i < ENA_RX_RSS_TABLE_SIZE; i++) {
2821 val = ethtool_rxfh_indir_default(i, adapter->num_queues);
2822 rc = ena_com_indirect_table_fill_entry(ena_dev, i,
2823 ENA_IO_RXQ_IDX(val));
2824 if (unlikely(rc && (rc != -EPERM))) {
2825 dev_err(dev, "Cannot fill indirect table\n");
2826 goto err_fill_indir;
2827 }
2828 }
2829
2830 rc = ena_com_fill_hash_function(ena_dev, ENA_ADMIN_CRC32, NULL,
2831 ENA_HASH_KEY_SIZE, 0xFFFFFFFF);
2832 if (unlikely(rc && (rc != -EPERM))) {
2833 dev_err(dev, "Cannot fill hash function\n");
2834 goto err_fill_indir;
2835 }
2836
2837 rc = ena_com_set_default_hash_ctrl(ena_dev);
2838 if (unlikely(rc && (rc != -EPERM))) {
2839 dev_err(dev, "Cannot fill hash control\n");
2840 goto err_fill_indir;
2841 }
2842
2843 return 0;
2844
2845 err_fill_indir:
2846 ena_com_rss_destroy(ena_dev);
2847 err_rss_init:
2848
2849 return rc;
2850 }
2851
2852 static void ena_release_bars(struct ena_com_dev *ena_dev, struct pci_dev *pdev)
2853 {
2854 int release_bars;
2855
2856 release_bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
2857 pci_release_selected_regions(pdev, release_bars);
2858 }
2859
2860 static int ena_calc_queue_size(struct pci_dev *pdev,
2861 struct ena_com_dev *ena_dev,
2862 u16 *max_tx_sgl_size,
2863 u16 *max_rx_sgl_size,
2864 struct ena_com_dev_get_features_ctx *get_feat_ctx)
2865 {
2866 u32 queue_size = ENA_DEFAULT_RING_SIZE;
2867
2868 queue_size = min_t(u32, queue_size,
2869 get_feat_ctx->max_queues.max_cq_depth);
2870 queue_size = min_t(u32, queue_size,
2871 get_feat_ctx->max_queues.max_sq_depth);
2872
2873 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV)
2874 queue_size = min_t(u32, queue_size,
2875 get_feat_ctx->max_queues.max_llq_depth);
2876
2877 queue_size = rounddown_pow_of_two(queue_size);
2878
2879 if (unlikely(!queue_size)) {
2880 dev_err(&pdev->dev, "Invalid queue size\n");
2881 return -EFAULT;
2882 }
2883
2884 *max_tx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
2885 get_feat_ctx->max_queues.max_packet_tx_descs);
2886 *max_rx_sgl_size = min_t(u16, ENA_PKT_MAX_BUFS,
2887 get_feat_ctx->max_queues.max_packet_rx_descs);
2888
2889 return queue_size;
2890 }
2891
2892 /* ena_probe - Device Initialization Routine
2893 * @pdev: PCI device information struct
2894 * @ent: entry in ena_pci_tbl
2895 *
2896 * Returns 0 on success, negative on failure
2897 *
2898 * ena_probe initializes an adapter identified by a pci_dev structure.
2899 * The OS initialization, configuring of the adapter private structure,
2900 * and a hardware reset occur.
2901 */
2902 static int ena_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2903 {
2904 struct ena_com_dev_get_features_ctx get_feat_ctx;
2905 static int version_printed;
2906 struct net_device *netdev;
2907 struct ena_adapter *adapter;
2908 struct ena_com_dev *ena_dev = NULL;
2909 static int adapters_found;
2910 int io_queue_num, bars, rc;
2911 int queue_size;
2912 u16 tx_sgl_size = 0;
2913 u16 rx_sgl_size = 0;
2914 bool wd_state;
2915
2916 dev_dbg(&pdev->dev, "%s\n", __func__);
2917
2918 if (version_printed++ == 0)
2919 dev_info(&pdev->dev, "%s", version);
2920
2921 rc = pci_enable_device_mem(pdev);
2922 if (rc) {
2923 dev_err(&pdev->dev, "pci_enable_device_mem() failed!\n");
2924 return rc;
2925 }
2926
2927 pci_set_master(pdev);
2928
2929 ena_dev = vzalloc(sizeof(*ena_dev));
2930 if (!ena_dev) {
2931 rc = -ENOMEM;
2932 goto err_disable_device;
2933 }
2934
2935 bars = pci_select_bars(pdev, IORESOURCE_MEM) & ENA_BAR_MASK;
2936 rc = pci_request_selected_regions(pdev, bars, DRV_MODULE_NAME);
2937 if (rc) {
2938 dev_err(&pdev->dev, "pci_request_selected_regions failed %d\n",
2939 rc);
2940 goto err_free_ena_dev;
2941 }
2942
2943 ena_dev->reg_bar = ioremap(pci_resource_start(pdev, ENA_REG_BAR),
2944 pci_resource_len(pdev, ENA_REG_BAR));
2945 if (!ena_dev->reg_bar) {
2946 dev_err(&pdev->dev, "failed to remap regs bar\n");
2947 rc = -EFAULT;
2948 goto err_free_region;
2949 }
2950
2951 ena_dev->dmadev = &pdev->dev;
2952
2953 rc = ena_device_init(ena_dev, pdev, &get_feat_ctx, &wd_state);
2954 if (rc) {
2955 dev_err(&pdev->dev, "ena device init failed\n");
2956 if (rc == -ETIME)
2957 rc = -EPROBE_DEFER;
2958 goto err_free_region;
2959 }
2960
2961 ena_set_push_mode(pdev, ena_dev, &get_feat_ctx);
2962
2963 if (ena_dev->tx_mem_queue_type == ENA_ADMIN_PLACEMENT_POLICY_DEV) {
2964 ena_dev->mem_bar = ioremap_wc(pci_resource_start(pdev, ENA_MEM_BAR),
2965 pci_resource_len(pdev, ENA_MEM_BAR));
2966 if (!ena_dev->mem_bar) {
2967 rc = -EFAULT;
2968 goto err_device_destroy;
2969 }
2970 }
2971
2972 /* initial Tx interrupt delay, Assumes 1 usec granularity.
2973 * Updated during device initialization with the real granularity
2974 */
2975 ena_dev->intr_moder_tx_interval = ENA_INTR_INITIAL_TX_INTERVAL_USECS;
2976 io_queue_num = ena_calc_io_queue_num(pdev, ena_dev, &get_feat_ctx);
2977 queue_size = ena_calc_queue_size(pdev, ena_dev, &tx_sgl_size,
2978 &rx_sgl_size, &get_feat_ctx);
2979 if ((queue_size <= 0) || (io_queue_num <= 0)) {
2980 rc = -EFAULT;
2981 goto err_device_destroy;
2982 }
2983
2984 dev_info(&pdev->dev, "creating %d io queues. queue size: %d\n",
2985 io_queue_num, queue_size);
2986
2987 /* dev zeroed in init_etherdev */
2988 netdev = alloc_etherdev_mq(sizeof(struct ena_adapter), io_queue_num);
2989 if (!netdev) {
2990 dev_err(&pdev->dev, "alloc_etherdev_mq failed\n");
2991 rc = -ENOMEM;
2992 goto err_device_destroy;
2993 }
2994
2995 SET_NETDEV_DEV(netdev, &pdev->dev);
2996
2997 adapter = netdev_priv(netdev);
2998 pci_set_drvdata(pdev, adapter);
2999
3000 adapter->ena_dev = ena_dev;
3001 adapter->netdev = netdev;
3002 adapter->pdev = pdev;
3003
3004 ena_set_conf_feat_params(adapter, &get_feat_ctx);
3005
3006 adapter->msg_enable = netif_msg_init(debug, DEFAULT_MSG_ENABLE);
3007
3008 adapter->tx_ring_size = queue_size;
3009 adapter->rx_ring_size = queue_size;
3010
3011 adapter->max_tx_sgl_size = tx_sgl_size;
3012 adapter->max_rx_sgl_size = rx_sgl_size;
3013
3014 adapter->num_queues = io_queue_num;
3015 adapter->last_monitored_tx_qid = 0;
3016
3017 adapter->rx_copybreak = ENA_DEFAULT_RX_COPYBREAK;
3018 adapter->wd_state = wd_state;
3019
3020 snprintf(adapter->name, ENA_NAME_MAX_LEN, "ena_%d", adapters_found);
3021
3022 rc = ena_com_init_interrupt_moderation(adapter->ena_dev);
3023 if (rc) {
3024 dev_err(&pdev->dev,
3025 "Failed to query interrupt moderation feature\n");
3026 goto err_netdev_destroy;
3027 }
3028 ena_init_io_rings(adapter);
3029
3030 netdev->netdev_ops = &ena_netdev_ops;
3031 netdev->watchdog_timeo = TX_TIMEOUT;
3032 ena_set_ethtool_ops(netdev);
3033
3034 netdev->priv_flags |= IFF_UNICAST_FLT;
3035
3036 u64_stats_init(&adapter->syncp);
3037
3038 rc = ena_enable_msix_and_set_admin_interrupts(adapter, io_queue_num);
3039 if (rc) {
3040 dev_err(&pdev->dev,
3041 "Failed to enable and set the admin interrupts\n");
3042 goto err_worker_destroy;
3043 }
3044 rc = ena_rss_init_default(adapter);
3045 if (rc && (rc != -EPERM)) {
3046 dev_err(&pdev->dev, "Cannot init RSS rc: %d\n", rc);
3047 goto err_free_msix;
3048 }
3049
3050 ena_config_debug_area(adapter);
3051
3052 memcpy(adapter->netdev->perm_addr, adapter->mac_addr, netdev->addr_len);
3053
3054 netif_carrier_off(netdev);
3055
3056 rc = register_netdev(netdev);
3057 if (rc) {
3058 dev_err(&pdev->dev, "Cannot register net device\n");
3059 goto err_rss;
3060 }
3061
3062 INIT_WORK(&adapter->suspend_io_task, ena_device_io_suspend);
3063 INIT_WORK(&adapter->resume_io_task, ena_device_io_resume);
3064 INIT_WORK(&adapter->reset_task, ena_fw_reset_device);
3065
3066 adapter->last_keep_alive_jiffies = jiffies;
3067
3068 setup_timer(&adapter->timer_service, ena_timer_service,
3069 (unsigned long)adapter);
3070 mod_timer(&adapter->timer_service, round_jiffies(jiffies + HZ));
3071
3072 dev_info(&pdev->dev, "%s found at mem %lx, mac addr %pM Queues %d\n",
3073 DEVICE_NAME, (long)pci_resource_start(pdev, 0),
3074 netdev->dev_addr, io_queue_num);
3075
3076 set_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags);
3077
3078 adapters_found++;
3079
3080 return 0;
3081
3082 err_rss:
3083 ena_com_delete_debug_area(ena_dev);
3084 ena_com_rss_destroy(ena_dev);
3085 err_free_msix:
3086 ena_com_dev_reset(ena_dev);
3087 ena_free_mgmnt_irq(adapter);
3088 pci_free_irq_vectors(adapter->pdev);
3089 err_worker_destroy:
3090 ena_com_destroy_interrupt_moderation(ena_dev);
3091 del_timer(&adapter->timer_service);
3092 cancel_work_sync(&adapter->suspend_io_task);
3093 cancel_work_sync(&adapter->resume_io_task);
3094 err_netdev_destroy:
3095 free_netdev(netdev);
3096 err_device_destroy:
3097 ena_com_delete_host_info(ena_dev);
3098 ena_com_admin_destroy(ena_dev);
3099 err_free_region:
3100 ena_release_bars(ena_dev, pdev);
3101 err_free_ena_dev:
3102 vfree(ena_dev);
3103 err_disable_device:
3104 pci_disable_device(pdev);
3105 return rc;
3106 }
3107
3108 /*****************************************************************************/
3109 static int ena_sriov_configure(struct pci_dev *dev, int numvfs)
3110 {
3111 int rc;
3112
3113 if (numvfs > 0) {
3114 rc = pci_enable_sriov(dev, numvfs);
3115 if (rc != 0) {
3116 dev_err(&dev->dev,
3117 "pci_enable_sriov failed to enable: %d vfs with the error: %d\n",
3118 numvfs, rc);
3119 return rc;
3120 }
3121
3122 return numvfs;
3123 }
3124
3125 if (numvfs == 0) {
3126 pci_disable_sriov(dev);
3127 return 0;
3128 }
3129
3130 return -EINVAL;
3131 }
3132
3133 /*****************************************************************************/
3134 /*****************************************************************************/
3135
3136 /* ena_remove - Device Removal Routine
3137 * @pdev: PCI device information struct
3138 *
3139 * ena_remove is called by the PCI subsystem to alert the driver
3140 * that it should release a PCI device.
3141 */
3142 static void ena_remove(struct pci_dev *pdev)
3143 {
3144 struct ena_adapter *adapter = pci_get_drvdata(pdev);
3145 struct ena_com_dev *ena_dev;
3146 struct net_device *netdev;
3147
3148 ena_dev = adapter->ena_dev;
3149 netdev = adapter->netdev;
3150
3151 #ifdef CONFIG_RFS_ACCEL
3152 if ((adapter->msix_vecs >= 1) && (netdev->rx_cpu_rmap)) {
3153 free_irq_cpu_rmap(netdev->rx_cpu_rmap);
3154 netdev->rx_cpu_rmap = NULL;
3155 }
3156 #endif /* CONFIG_RFS_ACCEL */
3157
3158 unregister_netdev(netdev);
3159 del_timer_sync(&adapter->timer_service);
3160
3161 cancel_work_sync(&adapter->reset_task);
3162
3163 cancel_work_sync(&adapter->suspend_io_task);
3164
3165 cancel_work_sync(&adapter->resume_io_task);
3166
3167 /* Reset the device only if the device is running. */
3168 if (test_bit(ENA_FLAG_DEVICE_RUNNING, &adapter->flags))
3169 ena_com_dev_reset(ena_dev);
3170
3171 ena_free_mgmnt_irq(adapter);
3172
3173 pci_free_irq_vectors(adapter->pdev);
3174
3175 free_netdev(netdev);
3176
3177 ena_com_mmio_reg_read_request_destroy(ena_dev);
3178
3179 ena_com_abort_admin_commands(ena_dev);
3180
3181 ena_com_wait_for_abort_completion(ena_dev);
3182
3183 ena_com_admin_destroy(ena_dev);
3184
3185 ena_com_rss_destroy(ena_dev);
3186
3187 ena_com_delete_debug_area(ena_dev);
3188
3189 ena_com_delete_host_info(ena_dev);
3190
3191 ena_release_bars(ena_dev, pdev);
3192
3193 pci_disable_device(pdev);
3194
3195 ena_com_destroy_interrupt_moderation(ena_dev);
3196
3197 vfree(ena_dev);
3198 }
3199
3200 static struct pci_driver ena_pci_driver = {
3201 .name = DRV_MODULE_NAME,
3202 .id_table = ena_pci_tbl,
3203 .probe = ena_probe,
3204 .remove = ena_remove,
3205 .sriov_configure = ena_sriov_configure,
3206 };
3207
3208 static int __init ena_init(void)
3209 {
3210 pr_info("%s", version);
3211
3212 ena_wq = create_singlethread_workqueue(DRV_MODULE_NAME);
3213 if (!ena_wq) {
3214 pr_err("Failed to create workqueue\n");
3215 return -ENOMEM;
3216 }
3217
3218 return pci_register_driver(&ena_pci_driver);
3219 }
3220
3221 static void __exit ena_cleanup(void)
3222 {
3223 pci_unregister_driver(&ena_pci_driver);
3224
3225 if (ena_wq) {
3226 destroy_workqueue(ena_wq);
3227 ena_wq = NULL;
3228 }
3229 }
3230
3231 /******************************************************************************
3232 ******************************** AENQ Handlers *******************************
3233 *****************************************************************************/
3234 /* ena_update_on_link_change:
3235 * Notify the network interface about the change in link status
3236 */
3237 static void ena_update_on_link_change(void *adapter_data,
3238 struct ena_admin_aenq_entry *aenq_e)
3239 {
3240 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3241 struct ena_admin_aenq_link_change_desc *aenq_desc =
3242 (struct ena_admin_aenq_link_change_desc *)aenq_e;
3243 int status = aenq_desc->flags &
3244 ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
3245
3246 if (status) {
3247 netdev_dbg(adapter->netdev, "%s\n", __func__);
3248 set_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3249 netif_carrier_on(adapter->netdev);
3250 } else {
3251 clear_bit(ENA_FLAG_LINK_UP, &adapter->flags);
3252 netif_carrier_off(adapter->netdev);
3253 }
3254 }
3255
3256 static void ena_keep_alive_wd(void *adapter_data,
3257 struct ena_admin_aenq_entry *aenq_e)
3258 {
3259 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3260
3261 adapter->last_keep_alive_jiffies = jiffies;
3262 }
3263
3264 static void ena_notification(void *adapter_data,
3265 struct ena_admin_aenq_entry *aenq_e)
3266 {
3267 struct ena_adapter *adapter = (struct ena_adapter *)adapter_data;
3268
3269 WARN(aenq_e->aenq_common_desc.group != ENA_ADMIN_NOTIFICATION,
3270 "Invalid group(%x) expected %x\n",
3271 aenq_e->aenq_common_desc.group,
3272 ENA_ADMIN_NOTIFICATION);
3273
3274 switch (aenq_e->aenq_common_desc.syndrom) {
3275 case ENA_ADMIN_SUSPEND:
3276 /* Suspend just the IO queues.
3277 * We deliberately don't suspend admin so the timer and
3278 * the keep_alive events should remain.
3279 */
3280 queue_work(ena_wq, &adapter->suspend_io_task);
3281 break;
3282 case ENA_ADMIN_RESUME:
3283 queue_work(ena_wq, &adapter->resume_io_task);
3284 break;
3285 default:
3286 netif_err(adapter, drv, adapter->netdev,
3287 "Invalid aenq notification link state %d\n",
3288 aenq_e->aenq_common_desc.syndrom);
3289 }
3290 }
3291
3292 /* This handler will called for unknown event group or unimplemented handlers*/
3293 static void unimplemented_aenq_handler(void *data,
3294 struct ena_admin_aenq_entry *aenq_e)
3295 {
3296 struct ena_adapter *adapter = (struct ena_adapter *)data;
3297
3298 netif_err(adapter, drv, adapter->netdev,
3299 "Unknown event was received or event with unimplemented handler\n");
3300 }
3301
3302 static struct ena_aenq_handlers aenq_handlers = {
3303 .handlers = {
3304 [ENA_ADMIN_LINK_CHANGE] = ena_update_on_link_change,
3305 [ENA_ADMIN_NOTIFICATION] = ena_notification,
3306 [ENA_ADMIN_KEEP_ALIVE] = ena_keep_alive_wd,
3307 },
3308 .unimplemented_handler = unimplemented_aenq_handler
3309 };
3310
3311 module_init(ena_init);
3312 module_exit(ena_cleanup);