2 * NVM Express device driver
3 * Copyright (c) 2011-2014, Intel Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 #include <linux/aer.h>
16 #include <linux/bitops.h>
17 #include <linux/blkdev.h>
18 #include <linux/blk-mq.h>
19 #include <linux/blk-mq-pci.h>
20 #include <linux/cpu.h>
21 #include <linux/delay.h>
22 #include <linux/dmi.h>
23 #include <linux/errno.h>
25 #include <linux/genhd.h>
26 #include <linux/hdreg.h>
27 #include <linux/idr.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
31 #include <linux/kdev_t.h>
32 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/mutex.h>
37 #include <linux/pci.h>
38 #include <linux/poison.h>
39 #include <linux/ptrace.h>
40 #include <linux/sched.h>
41 #include <linux/slab.h>
42 #include <linux/t10-pi.h>
43 #include <linux/timer.h>
44 #include <linux/types.h>
45 #include <linux/io-64-nonatomic-lo-hi.h>
46 #include <asm/unaligned.h>
50 #define NVME_Q_DEPTH 1024
51 #define NVME_AQ_DEPTH 256
52 #define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
53 #define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
55 /* Google Vendor ID is not in include/linux/pci_ids.h */
56 #define PCI_VENDOR_ID_GOOGLE 0x1AE0
59 * We handle AEN commands ourselves and don't even let the
60 * block layer know about them.
62 #define NVME_AQ_BLKMQ_DEPTH (NVME_AQ_DEPTH - NVME_NR_AERS)
64 static int use_threaded_interrupts
;
65 module_param(use_threaded_interrupts
, int, 0);
67 static bool use_cmb_sqes
= true;
68 module_param(use_cmb_sqes
, bool, 0644);
69 MODULE_PARM_DESC(use_cmb_sqes
, "use controller's memory buffer for I/O SQes");
71 static struct workqueue_struct
*nvme_workq
;
76 static int nvme_reset(struct nvme_dev
*dev
);
77 static void nvme_process_cq(struct nvme_queue
*nvmeq
);
78 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
);
81 * Represents an NVM Express device. Each nvme_dev is a PCI function.
84 struct nvme_queue
**queues
;
85 struct blk_mq_tag_set tagset
;
86 struct blk_mq_tag_set admin_tagset
;
89 struct dma_pool
*prp_page_pool
;
90 struct dma_pool
*prp_small_pool
;
92 unsigned online_queues
;
97 struct work_struct reset_work
;
98 struct work_struct remove_work
;
99 struct timer_list watchdog_timer
;
100 struct mutex shutdown_lock
;
103 dma_addr_t cmb_dma_addr
;
107 struct nvme_ctrl ctrl
;
108 struct completion ioq_wait
;
109 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
117 static inline struct nvme_dev
*to_nvme_dev(struct nvme_ctrl
*ctrl
)
119 return container_of(ctrl
, struct nvme_dev
, ctrl
);
123 * An NVM Express queue. Each device has at least two (one for admin
124 * commands and one for I/O commands).
127 struct device
*q_dmadev
;
128 struct nvme_dev
*dev
;
129 char irqname
[24]; /* nvme4294967295-65535\0 */
131 struct nvme_command
*sq_cmds
;
132 struct nvme_command __iomem
*sq_cmds_io
;
133 volatile struct nvme_completion
*cqes
;
134 struct blk_mq_tags
**tags
;
135 dma_addr_t sq_dma_addr
;
136 dma_addr_t cq_dma_addr
;
145 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
146 u32
*sq_doorbell_addr
;
147 u32
*sq_eventidx_addr
;
148 u32
*cq_doorbell_addr
;
149 u32
*cq_eventidx_addr
;
154 * The nvme_iod describes the data in an I/O, including the list of PRP
155 * entries. You can't see it in this data structure because C doesn't let
156 * me express that. Use nvme_init_iod to ensure there's enough space
157 * allocated to store the PRP list.
160 struct nvme_request req
;
161 struct nvme_queue
*nvmeq
;
163 int npages
; /* In the PRP list. 0 means small pool in use */
164 int nents
; /* Used in scatterlist */
165 int length
; /* Of data, in bytes */
166 dma_addr_t first_dma
;
167 struct scatterlist meta_sg
; /* metadata requires single contiguous buffer */
168 struct scatterlist
*sg
;
169 struct scatterlist inline_sg
[0];
173 * Check we didin't inadvertently grow the command struct
175 static inline void _nvme_check_size(void)
177 BUILD_BUG_ON(sizeof(struct nvme_rw_command
) != 64);
178 BUILD_BUG_ON(sizeof(struct nvme_create_cq
) != 64);
179 BUILD_BUG_ON(sizeof(struct nvme_create_sq
) != 64);
180 BUILD_BUG_ON(sizeof(struct nvme_delete_queue
) != 64);
181 BUILD_BUG_ON(sizeof(struct nvme_features
) != 64);
182 BUILD_BUG_ON(sizeof(struct nvme_format_cmd
) != 64);
183 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd
) != 64);
184 BUILD_BUG_ON(sizeof(struct nvme_command
) != 64);
185 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl
) != 4096);
186 BUILD_BUG_ON(sizeof(struct nvme_id_ns
) != 4096);
187 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type
) != 64);
188 BUILD_BUG_ON(sizeof(struct nvme_smart_log
) != 512);
189 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
190 BUILD_BUG_ON(sizeof(struct nvme_doorbell_memory
) != 64);
195 * Max size of iod being embedded in the request payload
197 #define NVME_INT_PAGES 2
198 #define NVME_INT_BYTES(dev) (NVME_INT_PAGES * (dev)->ctrl.page_size)
201 * Will slightly overestimate the number of pages needed. This is OK
202 * as it only leads to a small amount of wasted memory for the lifetime of
205 static int nvme_npages(unsigned size
, struct nvme_dev
*dev
)
207 unsigned nprps
= DIV_ROUND_UP(size
+ dev
->ctrl
.page_size
,
208 dev
->ctrl
.page_size
);
209 return DIV_ROUND_UP(8 * nprps
, PAGE_SIZE
- 8);
212 static unsigned int nvme_iod_alloc_size(struct nvme_dev
*dev
,
213 unsigned int size
, unsigned int nseg
)
215 return sizeof(__le64
*) * nvme_npages(size
, dev
) +
216 sizeof(struct scatterlist
) * nseg
;
219 static unsigned int nvme_cmd_size(struct nvme_dev
*dev
)
221 return sizeof(struct nvme_iod
) +
222 nvme_iod_alloc_size(dev
, NVME_INT_BYTES(dev
), NVME_INT_PAGES
);
225 static int nvmeq_irq(struct nvme_queue
*nvmeq
)
227 return pci_irq_vector(to_pci_dev(nvmeq
->dev
->dev
), nvmeq
->cq_vector
);
230 static int nvme_admin_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
231 unsigned int hctx_idx
)
233 struct nvme_dev
*dev
= data
;
234 struct nvme_queue
*nvmeq
= dev
->queues
[0];
236 WARN_ON(hctx_idx
!= 0);
237 WARN_ON(dev
->admin_tagset
.tags
[0] != hctx
->tags
);
238 WARN_ON(nvmeq
->tags
);
240 hctx
->driver_data
= nvmeq
;
241 nvmeq
->tags
= &dev
->admin_tagset
.tags
[0];
245 static void nvme_admin_exit_hctx(struct blk_mq_hw_ctx
*hctx
, unsigned int hctx_idx
)
247 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
252 static int nvme_admin_init_request(void *data
, struct request
*req
,
253 unsigned int hctx_idx
, unsigned int rq_idx
,
254 unsigned int numa_node
)
256 struct nvme_dev
*dev
= data
;
257 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
258 struct nvme_queue
*nvmeq
= dev
->queues
[0];
265 static int nvme_init_hctx(struct blk_mq_hw_ctx
*hctx
, void *data
,
266 unsigned int hctx_idx
)
268 struct nvme_dev
*dev
= data
;
269 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
272 nvmeq
->tags
= &dev
->tagset
.tags
[hctx_idx
];
274 WARN_ON(dev
->tagset
.tags
[hctx_idx
] != hctx
->tags
);
275 hctx
->driver_data
= nvmeq
;
279 static int nvme_init_request(void *data
, struct request
*req
,
280 unsigned int hctx_idx
, unsigned int rq_idx
,
281 unsigned int numa_node
)
283 struct nvme_dev
*dev
= data
;
284 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
285 struct nvme_queue
*nvmeq
= dev
->queues
[hctx_idx
+ 1];
292 static int nvme_pci_map_queues(struct blk_mq_tag_set
*set
)
294 struct nvme_dev
*dev
= set
->driver_data
;
296 return blk_mq_pci_map_queues(set
, to_pci_dev(dev
->dev
));
299 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
300 static int nvme_vendor_memory_size(struct nvme_dev
*dev
)
302 return ((num_possible_cpus() + 1) * 8 * dev
->db_stride
);
305 static int nvme_set_doorbell_memory(struct nvme_dev
*dev
)
307 struct nvme_command c
;
309 memset(&c
, 0, sizeof(c
));
310 c
.doorbell_memory
.opcode
= nvme_admin_doorbell_memory
;
311 c
.doorbell_memory
.prp1
= cpu_to_le64(dev
->doorbell
);
312 c
.doorbell_memory
.prp2
= cpu_to_le64(dev
->eventidx
);
314 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
317 static inline int nvme_ext_need_event(u16 event_idx
, u16 new_idx
, u16 old
)
319 /* Borrowed from vring_need_event */
320 return (u16
)(new_idx
- event_idx
- 1) < (u16
)(new_idx
- old
);
323 static void nvme_ext_write_doorbell(u16 value
, u32 __iomem
* q_db
,
324 u32
* db_addr
, volatile u32
* event_idx
)
330 old_value
= *db_addr
;
334 if (!nvme_ext_need_event(*event_idx
, value
, old_value
))
345 * __nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
346 * @nvmeq: The queue to use
347 * @cmd: The command to send
349 * Safe to use from interrupt context
351 static void __nvme_submit_cmd(struct nvme_queue
*nvmeq
,
352 struct nvme_command
*cmd
)
354 u16 tail
= nvmeq
->sq_tail
;
356 if (nvmeq
->sq_cmds_io
)
357 memcpy_toio(&nvmeq
->sq_cmds_io
[tail
], cmd
, sizeof(*cmd
));
359 memcpy(&nvmeq
->sq_cmds
[tail
], cmd
, sizeof(*cmd
));
361 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
362 if (nvmeq
->sq_doorbell_addr
)
366 if (++tail
== nvmeq
->q_depth
)
368 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
369 nvme_ext_write_doorbell(tail
, nvmeq
->q_db
,
370 nvmeq
->sq_doorbell_addr
, nvmeq
->sq_eventidx_addr
);
372 writel(tail
, nvmeq
->q_db
);
374 nvmeq
->sq_tail
= tail
;
377 static __le64
**iod_list(struct request
*req
)
379 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
380 return (__le64
**)(iod
->sg
+ blk_rq_nr_phys_segments(req
));
383 static int nvme_init_iod(struct request
*rq
, struct nvme_dev
*dev
)
385 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(rq
);
386 int nseg
= blk_rq_nr_phys_segments(rq
);
387 unsigned int size
= blk_rq_payload_bytes(rq
);
389 if (nseg
> NVME_INT_PAGES
|| size
> NVME_INT_BYTES(dev
)) {
390 iod
->sg
= kmalloc(nvme_iod_alloc_size(dev
, size
, nseg
), GFP_ATOMIC
);
392 return BLK_MQ_RQ_QUEUE_BUSY
;
394 iod
->sg
= iod
->inline_sg
;
402 if (!(rq
->rq_flags
& RQF_DONTPREP
)) {
404 rq
->rq_flags
|= RQF_DONTPREP
;
406 return BLK_MQ_RQ_QUEUE_OK
;
409 static void nvme_free_iod(struct nvme_dev
*dev
, struct request
*req
)
411 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
412 const int last_prp
= dev
->ctrl
.page_size
/ 8 - 1;
414 __le64
**list
= iod_list(req
);
415 dma_addr_t prp_dma
= iod
->first_dma
;
417 if (iod
->npages
== 0)
418 dma_pool_free(dev
->prp_small_pool
, list
[0], prp_dma
);
419 for (i
= 0; i
< iod
->npages
; i
++) {
420 __le64
*prp_list
= list
[i
];
421 dma_addr_t next_prp_dma
= le64_to_cpu(prp_list
[last_prp
]);
422 dma_pool_free(dev
->prp_page_pool
, prp_list
, prp_dma
);
423 prp_dma
= next_prp_dma
;
426 if (iod
->sg
!= iod
->inline_sg
)
430 #ifdef CONFIG_BLK_DEV_INTEGRITY
431 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
433 if (be32_to_cpu(pi
->ref_tag
) == v
)
434 pi
->ref_tag
= cpu_to_be32(p
);
437 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
439 if (be32_to_cpu(pi
->ref_tag
) == p
)
440 pi
->ref_tag
= cpu_to_be32(v
);
444 * nvme_dif_remap - remaps ref tags to bip seed and physical lba
446 * The virtual start sector is the one that was originally submitted by the
447 * block layer. Due to partitioning, MD/DM cloning, etc. the actual physical
448 * start sector may be different. Remap protection information to match the
449 * physical LBA on writes, and back to the original seed on reads.
451 * Type 0 and 3 do not have a ref tag, so no remapping required.
453 static void nvme_dif_remap(struct request
*req
,
454 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
456 struct nvme_ns
*ns
= req
->rq_disk
->private_data
;
457 struct bio_integrity_payload
*bip
;
458 struct t10_pi_tuple
*pi
;
460 u32 i
, nlb
, ts
, phys
, virt
;
462 if (!ns
->pi_type
|| ns
->pi_type
== NVME_NS_DPS_PI_TYPE3
)
465 bip
= bio_integrity(req
->bio
);
469 pmap
= kmap_atomic(bip
->bip_vec
->bv_page
) + bip
->bip_vec
->bv_offset
;
472 virt
= bip_get_seed(bip
);
473 phys
= nvme_block_nr(ns
, blk_rq_pos(req
));
474 nlb
= (blk_rq_bytes(req
) >> ns
->lba_shift
);
475 ts
= ns
->disk
->queue
->integrity
.tuple_size
;
477 for (i
= 0; i
< nlb
; i
++, virt
++, phys
++) {
478 pi
= (struct t10_pi_tuple
*)p
;
479 dif_swap(phys
, virt
, pi
);
484 #else /* CONFIG_BLK_DEV_INTEGRITY */
485 static void nvme_dif_remap(struct request
*req
,
486 void (*dif_swap
)(u32 p
, u32 v
, struct t10_pi_tuple
*pi
))
489 static void nvme_dif_prep(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
492 static void nvme_dif_complete(u32 p
, u32 v
, struct t10_pi_tuple
*pi
)
497 static bool nvme_setup_prps(struct nvme_dev
*dev
, struct request
*req
)
499 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
500 struct dma_pool
*pool
;
501 int length
= blk_rq_payload_bytes(req
);
502 struct scatterlist
*sg
= iod
->sg
;
503 int dma_len
= sg_dma_len(sg
);
504 u64 dma_addr
= sg_dma_address(sg
);
505 u32 page_size
= dev
->ctrl
.page_size
;
506 int offset
= dma_addr
& (page_size
- 1);
508 __le64
**list
= iod_list(req
);
512 length
-= (page_size
- offset
);
516 dma_len
-= (page_size
- offset
);
518 dma_addr
+= (page_size
- offset
);
521 dma_addr
= sg_dma_address(sg
);
522 dma_len
= sg_dma_len(sg
);
525 if (length
<= page_size
) {
526 iod
->first_dma
= dma_addr
;
530 nprps
= DIV_ROUND_UP(length
, page_size
);
531 if (nprps
<= (256 / 8)) {
532 pool
= dev
->prp_small_pool
;
535 pool
= dev
->prp_page_pool
;
539 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
541 iod
->first_dma
= dma_addr
;
546 iod
->first_dma
= prp_dma
;
549 if (i
== page_size
>> 3) {
550 __le64
*old_prp_list
= prp_list
;
551 prp_list
= dma_pool_alloc(pool
, GFP_ATOMIC
, &prp_dma
);
554 list
[iod
->npages
++] = prp_list
;
555 prp_list
[0] = old_prp_list
[i
- 1];
556 old_prp_list
[i
- 1] = cpu_to_le64(prp_dma
);
559 prp_list
[i
++] = cpu_to_le64(dma_addr
);
560 dma_len
-= page_size
;
561 dma_addr
+= page_size
;
569 dma_addr
= sg_dma_address(sg
);
570 dma_len
= sg_dma_len(sg
);
576 static int nvme_map_data(struct nvme_dev
*dev
, struct request
*req
,
577 struct nvme_command
*cmnd
)
579 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
580 struct request_queue
*q
= req
->q
;
581 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
582 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
583 int ret
= BLK_MQ_RQ_QUEUE_ERROR
;
585 sg_init_table(iod
->sg
, blk_rq_nr_phys_segments(req
));
586 iod
->nents
= blk_rq_map_sg(q
, req
, iod
->sg
);
590 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
591 if (!dma_map_sg_attrs(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
,
595 if (!nvme_setup_prps(dev
, req
))
598 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
599 if (blk_integrity_rq(req
)) {
600 if (blk_rq_count_integrity_sg(q
, req
->bio
) != 1)
603 sg_init_table(&iod
->meta_sg
, 1);
604 if (blk_rq_map_integrity_sg(q
, req
->bio
, &iod
->meta_sg
) != 1)
607 if (rq_data_dir(req
))
608 nvme_dif_remap(req
, nvme_dif_prep
);
610 if (!dma_map_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
))
614 cmnd
->rw
.dptr
.prp1
= cpu_to_le64(sg_dma_address(iod
->sg
));
615 cmnd
->rw
.dptr
.prp2
= cpu_to_le64(iod
->first_dma
);
616 if (blk_integrity_rq(req
))
617 cmnd
->rw
.metadata
= cpu_to_le64(sg_dma_address(&iod
->meta_sg
));
618 return BLK_MQ_RQ_QUEUE_OK
;
621 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
626 static void nvme_unmap_data(struct nvme_dev
*dev
, struct request
*req
)
628 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
629 enum dma_data_direction dma_dir
= rq_data_dir(req
) ?
630 DMA_TO_DEVICE
: DMA_FROM_DEVICE
;
633 dma_unmap_sg(dev
->dev
, iod
->sg
, iod
->nents
, dma_dir
);
634 if (blk_integrity_rq(req
)) {
635 if (!rq_data_dir(req
))
636 nvme_dif_remap(req
, nvme_dif_complete
);
637 dma_unmap_sg(dev
->dev
, &iod
->meta_sg
, 1, dma_dir
);
641 nvme_cleanup_cmd(req
);
642 nvme_free_iod(dev
, req
);
646 * NOTE: ns is NULL when called on the admin queue.
648 static int nvme_queue_rq(struct blk_mq_hw_ctx
*hctx
,
649 const struct blk_mq_queue_data
*bd
)
651 struct nvme_ns
*ns
= hctx
->queue
->queuedata
;
652 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
653 struct nvme_dev
*dev
= nvmeq
->dev
;
654 struct request
*req
= bd
->rq
;
655 struct nvme_command cmnd
;
656 int ret
= BLK_MQ_RQ_QUEUE_OK
;
659 * If formated with metadata, require the block layer provide a buffer
660 * unless this namespace is formated such that the metadata can be
661 * stripped/generated by the controller with PRACT=1.
663 if (ns
&& ns
->ms
&& !blk_integrity_rq(req
)) {
664 if (!(ns
->pi_type
&& ns
->ms
== 8) &&
665 req
->cmd_type
!= REQ_TYPE_DRV_PRIV
) {
666 blk_mq_end_request(req
, -EFAULT
);
667 return BLK_MQ_RQ_QUEUE_OK
;
671 ret
= nvme_setup_cmd(ns
, req
, &cmnd
);
672 if (ret
!= BLK_MQ_RQ_QUEUE_OK
)
675 ret
= nvme_init_iod(req
, dev
);
676 if (ret
!= BLK_MQ_RQ_QUEUE_OK
)
679 if (blk_rq_nr_phys_segments(req
))
680 ret
= nvme_map_data(dev
, req
, &cmnd
);
682 if (ret
!= BLK_MQ_RQ_QUEUE_OK
)
683 goto out_cleanup_iod
;
685 blk_mq_start_request(req
);
687 spin_lock_irq(&nvmeq
->q_lock
);
688 if (unlikely(nvmeq
->cq_vector
< 0)) {
689 if (ns
&& !test_bit(NVME_NS_DEAD
, &ns
->flags
))
690 ret
= BLK_MQ_RQ_QUEUE_BUSY
;
692 ret
= BLK_MQ_RQ_QUEUE_ERROR
;
693 spin_unlock_irq(&nvmeq
->q_lock
);
694 goto out_cleanup_iod
;
696 __nvme_submit_cmd(nvmeq
, &cmnd
);
697 nvme_process_cq(nvmeq
);
698 spin_unlock_irq(&nvmeq
->q_lock
);
699 return BLK_MQ_RQ_QUEUE_OK
;
701 nvme_free_iod(dev
, req
);
703 nvme_cleanup_cmd(req
);
707 static void nvme_complete_rq(struct request
*req
)
709 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
710 struct nvme_dev
*dev
= iod
->nvmeq
->dev
;
713 nvme_unmap_data(dev
, req
);
715 if (unlikely(req
->errors
)) {
716 if (nvme_req_needs_retry(req
, req
->errors
)) {
718 nvme_requeue_req(req
);
722 if (req
->cmd_type
== REQ_TYPE_DRV_PRIV
)
725 error
= nvme_error_status(req
->errors
);
728 if (unlikely(iod
->aborted
)) {
729 dev_warn(dev
->ctrl
.device
,
730 "completing aborted command with status: %04x\n",
734 blk_mq_end_request(req
, error
);
737 /* We read the CQE phase first to check if the rest of the entry is valid */
738 static inline bool nvme_cqe_valid(struct nvme_queue
*nvmeq
, u16 head
,
741 return (le16_to_cpu(nvmeq
->cqes
[head
].status
) & 1) == phase
;
744 static void __nvme_process_cq(struct nvme_queue
*nvmeq
, unsigned int *tag
)
748 head
= nvmeq
->cq_head
;
749 phase
= nvmeq
->cq_phase
;
751 while (nvme_cqe_valid(nvmeq
, head
, phase
)) {
752 struct nvme_completion cqe
= nvmeq
->cqes
[head
];
755 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
756 if (to_pci_dev(nvmeq
->dev
->dev
)->vendor
== PCI_VENDOR_ID_GOOGLE
)
759 if (++head
== nvmeq
->q_depth
) {
764 if (tag
&& *tag
== cqe
.command_id
)
767 if (unlikely(cqe
.command_id
>= nvmeq
->q_depth
)) {
768 dev_warn(nvmeq
->dev
->ctrl
.device
,
769 "invalid id %d completed on queue %d\n",
770 cqe
.command_id
, le16_to_cpu(cqe
.sq_id
));
775 * AEN requests are special as they don't time out and can
776 * survive any kind of queue freeze and often don't respond to
777 * aborts. We don't even bother to allocate a struct request
778 * for them but rather special case them here.
780 if (unlikely(nvmeq
->qid
== 0 &&
781 cqe
.command_id
>= NVME_AQ_BLKMQ_DEPTH
)) {
782 nvme_complete_async_event(&nvmeq
->dev
->ctrl
,
783 cqe
.status
, &cqe
.result
);
787 req
= blk_mq_tag_to_rq(*nvmeq
->tags
, cqe
.command_id
);
788 nvme_req(req
)->result
= cqe
.result
;
789 blk_mq_complete_request(req
, le16_to_cpu(cqe
.status
) >> 1);
792 if (head
== nvmeq
->cq_head
&& phase
== nvmeq
->cq_phase
)
795 if (likely(nvmeq
->cq_vector
>= 0))
796 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
797 nvme_ext_write_doorbell(head
,
798 nvmeq
->q_db
+ nvmeq
->dev
->db_stride
,
799 nvmeq
->cq_doorbell_addr
,
800 nvmeq
->cq_eventidx_addr
);
802 writel(head
, nvmeq
->q_db
+ nvmeq
->dev
->db_stride
);
804 nvmeq
->cq_head
= head
;
805 nvmeq
->cq_phase
= phase
;
810 static void nvme_process_cq(struct nvme_queue
*nvmeq
)
812 __nvme_process_cq(nvmeq
, NULL
);
815 static irqreturn_t
nvme_irq(int irq
, void *data
)
818 struct nvme_queue
*nvmeq
= data
;
819 spin_lock(&nvmeq
->q_lock
);
820 nvme_process_cq(nvmeq
);
821 result
= nvmeq
->cqe_seen
? IRQ_HANDLED
: IRQ_NONE
;
823 spin_unlock(&nvmeq
->q_lock
);
827 static irqreturn_t
nvme_irq_check(int irq
, void *data
)
829 struct nvme_queue
*nvmeq
= data
;
830 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
))
831 return IRQ_WAKE_THREAD
;
835 static int nvme_poll(struct blk_mq_hw_ctx
*hctx
, unsigned int tag
)
837 struct nvme_queue
*nvmeq
= hctx
->driver_data
;
839 if (nvme_cqe_valid(nvmeq
, nvmeq
->cq_head
, nvmeq
->cq_phase
)) {
840 spin_lock_irq(&nvmeq
->q_lock
);
841 __nvme_process_cq(nvmeq
, &tag
);
842 spin_unlock_irq(&nvmeq
->q_lock
);
851 static void nvme_pci_submit_async_event(struct nvme_ctrl
*ctrl
, int aer_idx
)
853 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
854 struct nvme_queue
*nvmeq
= dev
->queues
[0];
855 struct nvme_command c
;
857 memset(&c
, 0, sizeof(c
));
858 c
.common
.opcode
= nvme_admin_async_event
;
859 c
.common
.command_id
= NVME_AQ_BLKMQ_DEPTH
+ aer_idx
;
861 spin_lock_irq(&nvmeq
->q_lock
);
862 __nvme_submit_cmd(nvmeq
, &c
);
863 spin_unlock_irq(&nvmeq
->q_lock
);
866 static int adapter_delete_queue(struct nvme_dev
*dev
, u8 opcode
, u16 id
)
868 struct nvme_command c
;
870 memset(&c
, 0, sizeof(c
));
871 c
.delete_queue
.opcode
= opcode
;
872 c
.delete_queue
.qid
= cpu_to_le16(id
);
874 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
877 static int adapter_alloc_cq(struct nvme_dev
*dev
, u16 qid
,
878 struct nvme_queue
*nvmeq
)
880 struct nvme_command c
;
881 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_CQ_IRQ_ENABLED
;
884 * Note: we (ab)use the fact the the prp fields survive if no data
885 * is attached to the request.
887 memset(&c
, 0, sizeof(c
));
888 c
.create_cq
.opcode
= nvme_admin_create_cq
;
889 c
.create_cq
.prp1
= cpu_to_le64(nvmeq
->cq_dma_addr
);
890 c
.create_cq
.cqid
= cpu_to_le16(qid
);
891 c
.create_cq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
892 c
.create_cq
.cq_flags
= cpu_to_le16(flags
);
893 c
.create_cq
.irq_vector
= cpu_to_le16(nvmeq
->cq_vector
);
895 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
898 static int adapter_alloc_sq(struct nvme_dev
*dev
, u16 qid
,
899 struct nvme_queue
*nvmeq
)
901 struct nvme_command c
;
902 int flags
= NVME_QUEUE_PHYS_CONTIG
| NVME_SQ_PRIO_MEDIUM
;
905 * Note: we (ab)use the fact the the prp fields survive if no data
906 * is attached to the request.
908 memset(&c
, 0, sizeof(c
));
909 c
.create_sq
.opcode
= nvme_admin_create_sq
;
910 c
.create_sq
.prp1
= cpu_to_le64(nvmeq
->sq_dma_addr
);
911 c
.create_sq
.sqid
= cpu_to_le16(qid
);
912 c
.create_sq
.qsize
= cpu_to_le16(nvmeq
->q_depth
- 1);
913 c
.create_sq
.sq_flags
= cpu_to_le16(flags
);
914 c
.create_sq
.cqid
= cpu_to_le16(qid
);
916 return nvme_submit_sync_cmd(dev
->ctrl
.admin_q
, &c
, NULL
, 0);
919 static int adapter_delete_cq(struct nvme_dev
*dev
, u16 cqid
)
921 return adapter_delete_queue(dev
, nvme_admin_delete_cq
, cqid
);
924 static int adapter_delete_sq(struct nvme_dev
*dev
, u16 sqid
)
926 return adapter_delete_queue(dev
, nvme_admin_delete_sq
, sqid
);
929 static void abort_endio(struct request
*req
, int error
)
931 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
932 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
933 u16 status
= req
->errors
;
935 dev_warn(nvmeq
->dev
->ctrl
.device
, "Abort status: 0x%x", status
);
936 atomic_inc(&nvmeq
->dev
->ctrl
.abort_limit
);
937 blk_mq_free_request(req
);
940 static enum blk_eh_timer_return
nvme_timeout(struct request
*req
, bool reserved
)
942 struct nvme_iod
*iod
= blk_mq_rq_to_pdu(req
);
943 struct nvme_queue
*nvmeq
= iod
->nvmeq
;
944 struct nvme_dev
*dev
= nvmeq
->dev
;
945 struct request
*abort_req
;
946 struct nvme_command cmd
;
949 * Shutdown immediately if controller times out while starting. The
950 * reset work will see the pci device disabled when it gets the forced
951 * cancellation error. All outstanding requests are completed on
952 * shutdown, so we return BLK_EH_HANDLED.
954 if (dev
->ctrl
.state
== NVME_CTRL_RESETTING
) {
955 dev_warn(dev
->ctrl
.device
,
956 "I/O %d QID %d timeout, disable controller\n",
957 req
->tag
, nvmeq
->qid
);
958 nvme_dev_disable(dev
, false);
959 req
->errors
= NVME_SC_CANCELLED
;
960 return BLK_EH_HANDLED
;
964 * Shutdown the controller immediately and schedule a reset if the
965 * command was already aborted once before and still hasn't been
966 * returned to the driver, or if this is the admin queue.
968 if (!nvmeq
->qid
|| iod
->aborted
) {
969 dev_warn(dev
->ctrl
.device
,
970 "I/O %d QID %d timeout, reset controller\n",
971 req
->tag
, nvmeq
->qid
);
972 nvme_dev_disable(dev
, false);
976 * Mark the request as handled, since the inline shutdown
977 * forces all outstanding requests to complete.
979 req
->errors
= NVME_SC_CANCELLED
;
980 return BLK_EH_HANDLED
;
985 if (atomic_dec_return(&dev
->ctrl
.abort_limit
) < 0) {
986 atomic_inc(&dev
->ctrl
.abort_limit
);
987 return BLK_EH_RESET_TIMER
;
990 memset(&cmd
, 0, sizeof(cmd
));
991 cmd
.abort
.opcode
= nvme_admin_abort_cmd
;
992 cmd
.abort
.cid
= req
->tag
;
993 cmd
.abort
.sqid
= cpu_to_le16(nvmeq
->qid
);
995 dev_warn(nvmeq
->dev
->ctrl
.device
,
996 "I/O %d QID %d timeout, aborting\n",
997 req
->tag
, nvmeq
->qid
);
999 abort_req
= nvme_alloc_request(dev
->ctrl
.admin_q
, &cmd
,
1000 BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1001 if (IS_ERR(abort_req
)) {
1002 atomic_inc(&dev
->ctrl
.abort_limit
);
1003 return BLK_EH_RESET_TIMER
;
1006 abort_req
->timeout
= ADMIN_TIMEOUT
;
1007 abort_req
->end_io_data
= NULL
;
1008 blk_execute_rq_nowait(abort_req
->q
, NULL
, abort_req
, 0, abort_endio
);
1011 * The aborted req will be completed on receiving the abort req.
1012 * We enable the timer again. If hit twice, it'll cause a device reset,
1013 * as the device then is in a faulty state.
1015 return BLK_EH_RESET_TIMER
;
1018 static void nvme_free_queue(struct nvme_queue
*nvmeq
)
1020 dma_free_coherent(nvmeq
->q_dmadev
, CQ_SIZE(nvmeq
->q_depth
),
1021 (void *)nvmeq
->cqes
, nvmeq
->cq_dma_addr
);
1023 dma_free_coherent(nvmeq
->q_dmadev
, SQ_SIZE(nvmeq
->q_depth
),
1024 nvmeq
->sq_cmds
, nvmeq
->sq_dma_addr
);
1028 static void nvme_free_queues(struct nvme_dev
*dev
, int lowest
)
1032 for (i
= dev
->queue_count
- 1; i
>= lowest
; i
--) {
1033 struct nvme_queue
*nvmeq
= dev
->queues
[i
];
1035 dev
->queues
[i
] = NULL
;
1036 nvme_free_queue(nvmeq
);
1041 * nvme_suspend_queue - put queue into suspended state
1042 * @nvmeq - queue to suspend
1044 static int nvme_suspend_queue(struct nvme_queue
*nvmeq
)
1048 spin_lock_irq(&nvmeq
->q_lock
);
1049 if (nvmeq
->cq_vector
== -1) {
1050 spin_unlock_irq(&nvmeq
->q_lock
);
1053 vector
= nvmeq_irq(nvmeq
);
1054 nvmeq
->dev
->online_queues
--;
1055 nvmeq
->cq_vector
= -1;
1056 spin_unlock_irq(&nvmeq
->q_lock
);
1058 if (!nvmeq
->qid
&& nvmeq
->dev
->ctrl
.admin_q
)
1059 blk_mq_stop_hw_queues(nvmeq
->dev
->ctrl
.admin_q
);
1061 free_irq(vector
, nvmeq
);
1066 static void nvme_disable_admin_queue(struct nvme_dev
*dev
, bool shutdown
)
1068 struct nvme_queue
*nvmeq
= dev
->queues
[0];
1072 if (nvme_suspend_queue(nvmeq
))
1076 nvme_shutdown_ctrl(&dev
->ctrl
);
1078 nvme_disable_ctrl(&dev
->ctrl
, lo_hi_readq(
1079 dev
->bar
+ NVME_REG_CAP
));
1081 spin_lock_irq(&nvmeq
->q_lock
);
1082 nvme_process_cq(nvmeq
);
1083 spin_unlock_irq(&nvmeq
->q_lock
);
1086 static int nvme_cmb_qdepth(struct nvme_dev
*dev
, int nr_io_queues
,
1089 int q_depth
= dev
->q_depth
;
1090 unsigned q_size_aligned
= roundup(q_depth
* entry_size
,
1091 dev
->ctrl
.page_size
);
1093 if (q_size_aligned
* nr_io_queues
> dev
->cmb_size
) {
1094 u64 mem_per_q
= div_u64(dev
->cmb_size
, nr_io_queues
);
1095 mem_per_q
= round_down(mem_per_q
, dev
->ctrl
.page_size
);
1096 q_depth
= div_u64(mem_per_q
, entry_size
);
1099 * Ensure the reduced q_depth is above some threshold where it
1100 * would be better to map queues in system memory with the
1110 static int nvme_alloc_sq_cmds(struct nvme_dev
*dev
, struct nvme_queue
*nvmeq
,
1113 if (qid
&& dev
->cmb
&& use_cmb_sqes
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1114 unsigned offset
= (qid
- 1) * roundup(SQ_SIZE(depth
),
1115 dev
->ctrl
.page_size
);
1116 nvmeq
->sq_dma_addr
= dev
->cmb_dma_addr
+ offset
;
1117 nvmeq
->sq_cmds_io
= dev
->cmb
+ offset
;
1119 nvmeq
->sq_cmds
= dma_alloc_coherent(dev
->dev
, SQ_SIZE(depth
),
1120 &nvmeq
->sq_dma_addr
, GFP_KERNEL
);
1121 if (!nvmeq
->sq_cmds
)
1128 static struct nvme_queue
*nvme_alloc_queue(struct nvme_dev
*dev
, int qid
,
1131 struct nvme_queue
*nvmeq
= kzalloc(sizeof(*nvmeq
), GFP_KERNEL
);
1135 nvmeq
->cqes
= dma_zalloc_coherent(dev
->dev
, CQ_SIZE(depth
),
1136 &nvmeq
->cq_dma_addr
, GFP_KERNEL
);
1140 if (nvme_alloc_sq_cmds(dev
, nvmeq
, qid
, depth
))
1143 nvmeq
->q_dmadev
= dev
->dev
;
1145 snprintf(nvmeq
->irqname
, sizeof(nvmeq
->irqname
), "nvme%dq%d",
1146 dev
->ctrl
.instance
, qid
);
1147 spin_lock_init(&nvmeq
->q_lock
);
1149 nvmeq
->cq_phase
= 1;
1150 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1151 nvmeq
->q_depth
= depth
;
1153 nvmeq
->cq_vector
= -1;
1154 dev
->queues
[qid
] = nvmeq
;
1157 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
1158 if (dev
->db_mem
&& dev
->ei_mem
&& qid
!= 0) {
1159 nvmeq
->sq_doorbell_addr
= &dev
->db_mem
[qid
* 2 * dev
->db_stride
];
1160 nvmeq
->cq_doorbell_addr
=
1161 &dev
->db_mem
[(qid
* 2 + 1) * dev
->db_stride
];
1162 nvmeq
->sq_eventidx_addr
= &dev
->ei_mem
[qid
* 2 * dev
->db_stride
];
1163 nvmeq
->cq_eventidx_addr
=
1164 &dev
->ei_mem
[(qid
* 2 + 1) * dev
->db_stride
];
1171 dma_free_coherent(dev
->dev
, CQ_SIZE(depth
), (void *)nvmeq
->cqes
,
1172 nvmeq
->cq_dma_addr
);
1178 static int queue_request_irq(struct nvme_queue
*nvmeq
)
1180 if (use_threaded_interrupts
)
1181 return request_threaded_irq(nvmeq_irq(nvmeq
), nvme_irq_check
,
1182 nvme_irq
, IRQF_SHARED
, nvmeq
->irqname
, nvmeq
);
1184 return request_irq(nvmeq_irq(nvmeq
), nvme_irq
, IRQF_SHARED
,
1185 nvmeq
->irqname
, nvmeq
);
1188 static void nvme_init_queue(struct nvme_queue
*nvmeq
, u16 qid
)
1190 struct nvme_dev
*dev
= nvmeq
->dev
;
1192 spin_lock_irq(&nvmeq
->q_lock
);
1195 nvmeq
->cq_phase
= 1;
1196 nvmeq
->q_db
= &dev
->dbs
[qid
* 2 * dev
->db_stride
];
1197 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
1198 if (to_pci_dev(dev
->dev
)->vendor
== PCI_VENDOR_ID_GOOGLE
&& qid
!= 0) {
1199 nvmeq
->sq_doorbell_addr
= &dev
->db_mem
[qid
* 2 * dev
->db_stride
];
1200 nvmeq
->cq_doorbell_addr
=
1201 &dev
->db_mem
[(qid
* 2 + 1) * dev
->db_stride
];
1202 nvmeq
->sq_eventidx_addr
= &dev
->ei_mem
[qid
* 2 * dev
->db_stride
];
1203 nvmeq
->cq_eventidx_addr
=
1204 &dev
->ei_mem
[(qid
* 2 + 1) * dev
->db_stride
];
1207 memset((void *)nvmeq
->cqes
, 0, CQ_SIZE(nvmeq
->q_depth
));
1208 dev
->online_queues
++;
1209 spin_unlock_irq(&nvmeq
->q_lock
);
1212 static int nvme_create_queue(struct nvme_queue
*nvmeq
, int qid
)
1214 struct nvme_dev
*dev
= nvmeq
->dev
;
1217 nvmeq
->cq_vector
= qid
- 1;
1218 result
= adapter_alloc_cq(dev
, qid
, nvmeq
);
1222 result
= adapter_alloc_sq(dev
, qid
, nvmeq
);
1226 result
= queue_request_irq(nvmeq
);
1230 nvme_init_queue(nvmeq
, qid
);
1234 adapter_delete_sq(dev
, qid
);
1236 adapter_delete_cq(dev
, qid
);
1240 static struct blk_mq_ops nvme_mq_admin_ops
= {
1241 .queue_rq
= nvme_queue_rq
,
1242 .complete
= nvme_complete_rq
,
1243 .init_hctx
= nvme_admin_init_hctx
,
1244 .exit_hctx
= nvme_admin_exit_hctx
,
1245 .init_request
= nvme_admin_init_request
,
1246 .timeout
= nvme_timeout
,
1249 static struct blk_mq_ops nvme_mq_ops
= {
1250 .queue_rq
= nvme_queue_rq
,
1251 .complete
= nvme_complete_rq
,
1252 .init_hctx
= nvme_init_hctx
,
1253 .init_request
= nvme_init_request
,
1254 .map_queues
= nvme_pci_map_queues
,
1255 .timeout
= nvme_timeout
,
1259 static void nvme_dev_remove_admin(struct nvme_dev
*dev
)
1261 if (dev
->ctrl
.admin_q
&& !blk_queue_dying(dev
->ctrl
.admin_q
)) {
1263 * If the controller was reset during removal, it's possible
1264 * user requests may be waiting on a stopped queue. Start the
1265 * queue to flush these to completion.
1267 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1268 blk_cleanup_queue(dev
->ctrl
.admin_q
);
1269 blk_mq_free_tag_set(&dev
->admin_tagset
);
1273 static int nvme_alloc_admin_tags(struct nvme_dev
*dev
)
1275 if (!dev
->ctrl
.admin_q
) {
1276 dev
->admin_tagset
.ops
= &nvme_mq_admin_ops
;
1277 dev
->admin_tagset
.nr_hw_queues
= 1;
1280 * Subtract one to leave an empty queue entry for 'Full Queue'
1281 * condition. See NVM-Express 1.2 specification, section 4.1.2.
1283 dev
->admin_tagset
.queue_depth
= NVME_AQ_BLKMQ_DEPTH
- 1;
1284 dev
->admin_tagset
.timeout
= ADMIN_TIMEOUT
;
1285 dev
->admin_tagset
.numa_node
= dev_to_node(dev
->dev
);
1286 dev
->admin_tagset
.cmd_size
= nvme_cmd_size(dev
);
1287 dev
->admin_tagset
.driver_data
= dev
;
1289 if (blk_mq_alloc_tag_set(&dev
->admin_tagset
))
1292 dev
->ctrl
.admin_q
= blk_mq_init_queue(&dev
->admin_tagset
);
1293 if (IS_ERR(dev
->ctrl
.admin_q
)) {
1294 blk_mq_free_tag_set(&dev
->admin_tagset
);
1297 if (!blk_get_queue(dev
->ctrl
.admin_q
)) {
1298 nvme_dev_remove_admin(dev
);
1299 dev
->ctrl
.admin_q
= NULL
;
1303 blk_mq_start_stopped_hw_queues(dev
->ctrl
.admin_q
, true);
1308 static int nvme_configure_admin_queue(struct nvme_dev
*dev
)
1312 u64 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1313 struct nvme_queue
*nvmeq
;
1315 dev
->subsystem
= readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 1, 0) ?
1316 NVME_CAP_NSSRC(cap
) : 0;
1318 if (dev
->subsystem
&&
1319 (readl(dev
->bar
+ NVME_REG_CSTS
) & NVME_CSTS_NSSRO
))
1320 writel(NVME_CSTS_NSSRO
, dev
->bar
+ NVME_REG_CSTS
);
1322 result
= nvme_disable_ctrl(&dev
->ctrl
, cap
);
1326 nvmeq
= dev
->queues
[0];
1328 nvmeq
= nvme_alloc_queue(dev
, 0, NVME_AQ_DEPTH
);
1333 aqa
= nvmeq
->q_depth
- 1;
1336 writel(aqa
, dev
->bar
+ NVME_REG_AQA
);
1337 lo_hi_writeq(nvmeq
->sq_dma_addr
, dev
->bar
+ NVME_REG_ASQ
);
1338 lo_hi_writeq(nvmeq
->cq_dma_addr
, dev
->bar
+ NVME_REG_ACQ
);
1340 result
= nvme_enable_ctrl(&dev
->ctrl
, cap
);
1344 nvmeq
->cq_vector
= 0;
1345 result
= queue_request_irq(nvmeq
);
1347 nvmeq
->cq_vector
= -1;
1354 static bool nvme_should_reset(struct nvme_dev
*dev
, u32 csts
)
1357 /* If true, indicates loss of adapter communication, possibly by a
1358 * NVMe Subsystem reset.
1360 bool nssro
= dev
->subsystem
&& (csts
& NVME_CSTS_NSSRO
);
1362 /* If there is a reset ongoing, we shouldn't reset again. */
1363 if (work_busy(&dev
->reset_work
))
1366 /* We shouldn't reset unless the controller is on fatal error state
1367 * _or_ if we lost the communication with it.
1369 if (!(csts
& NVME_CSTS_CFS
) && !nssro
)
1372 /* If PCI error recovery process is happening, we cannot reset or
1373 * the recovery mechanism will surely fail.
1375 if (pci_channel_offline(to_pci_dev(dev
->dev
)))
1381 static void nvme_warn_reset(struct nvme_dev
*dev
, u32 csts
)
1383 /* Read a config register to help see what died. */
1387 result
= pci_read_config_word(to_pci_dev(dev
->dev
), PCI_STATUS
,
1389 if (result
== PCIBIOS_SUCCESSFUL
)
1391 "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1395 "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1399 static void nvme_watchdog_timer(unsigned long data
)
1401 struct nvme_dev
*dev
= (struct nvme_dev
*)data
;
1402 u32 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1404 /* Skip controllers under certain specific conditions. */
1405 if (nvme_should_reset(dev
, csts
)) {
1406 if (!nvme_reset(dev
))
1407 nvme_warn_reset(dev
, csts
);
1411 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1414 static int nvme_create_io_queues(struct nvme_dev
*dev
)
1419 for (i
= dev
->queue_count
; i
<= dev
->max_qid
; i
++) {
1420 if (!nvme_alloc_queue(dev
, i
, dev
->q_depth
)) {
1426 max
= min(dev
->max_qid
, dev
->queue_count
- 1);
1427 for (i
= dev
->online_queues
; i
<= max
; i
++) {
1428 ret
= nvme_create_queue(dev
->queues
[i
], i
);
1434 * Ignore failing Create SQ/CQ commands, we can continue with less
1435 * than the desired aount of queues, and even a controller without
1436 * I/O queues an still be used to issue admin commands. This might
1437 * be useful to upgrade a buggy firmware for example.
1439 return ret
>= 0 ? 0 : ret
;
1442 static ssize_t
nvme_cmb_show(struct device
*dev
,
1443 struct device_attribute
*attr
,
1446 struct nvme_dev
*ndev
= to_nvme_dev(dev_get_drvdata(dev
));
1448 return scnprintf(buf
, PAGE_SIZE
, "cmbloc : x%08x\ncmbsz : x%08x\n",
1449 ndev
->cmbloc
, ndev
->cmbsz
);
1451 static DEVICE_ATTR(cmb
, S_IRUGO
, nvme_cmb_show
, NULL
);
1453 static void __iomem
*nvme_map_cmb(struct nvme_dev
*dev
)
1455 u64 szu
, size
, offset
;
1456 resource_size_t bar_size
;
1457 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1459 dma_addr_t dma_addr
;
1461 dev
->cmbsz
= readl(dev
->bar
+ NVME_REG_CMBSZ
);
1462 if (!(NVME_CMB_SZ(dev
->cmbsz
)))
1464 dev
->cmbloc
= readl(dev
->bar
+ NVME_REG_CMBLOC
);
1469 szu
= (u64
)1 << (12 + 4 * NVME_CMB_SZU(dev
->cmbsz
));
1470 size
= szu
* NVME_CMB_SZ(dev
->cmbsz
);
1471 offset
= szu
* NVME_CMB_OFST(dev
->cmbloc
);
1472 bar_size
= pci_resource_len(pdev
, NVME_CMB_BIR(dev
->cmbloc
));
1474 if (offset
> bar_size
)
1478 * Controllers may support a CMB size larger than their BAR,
1479 * for example, due to being behind a bridge. Reduce the CMB to
1480 * the reported size of the BAR
1482 if (size
> bar_size
- offset
)
1483 size
= bar_size
- offset
;
1485 dma_addr
= pci_resource_start(pdev
, NVME_CMB_BIR(dev
->cmbloc
)) + offset
;
1486 cmb
= ioremap_wc(dma_addr
, size
);
1490 dev
->cmb_dma_addr
= dma_addr
;
1491 dev
->cmb_size
= size
;
1495 static inline void nvme_release_cmb(struct nvme_dev
*dev
)
1503 static size_t db_bar_size(struct nvme_dev
*dev
, unsigned nr_io_queues
)
1505 return 4096 + ((nr_io_queues
+ 1) * 8 * dev
->db_stride
);
1508 static int nvme_setup_io_queues(struct nvme_dev
*dev
)
1510 struct nvme_queue
*adminq
= dev
->queues
[0];
1511 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1512 int result
, nr_io_queues
, size
;
1514 nr_io_queues
= num_online_cpus();
1515 result
= nvme_set_queue_count(&dev
->ctrl
, &nr_io_queues
);
1519 if (nr_io_queues
== 0)
1522 if (dev
->cmb
&& NVME_CMB_SQS(dev
->cmbsz
)) {
1523 result
= nvme_cmb_qdepth(dev
, nr_io_queues
,
1524 sizeof(struct nvme_command
));
1526 dev
->q_depth
= result
;
1528 nvme_release_cmb(dev
);
1531 size
= db_bar_size(dev
, nr_io_queues
);
1535 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), size
);
1538 if (!--nr_io_queues
)
1540 size
= db_bar_size(dev
, nr_io_queues
);
1542 dev
->dbs
= dev
->bar
+ 4096;
1543 adminq
->q_db
= dev
->dbs
;
1546 /* Deregister the admin queue's interrupt */
1547 free_irq(pci_irq_vector(pdev
, 0), adminq
);
1550 * If we enable msix early due to not intx, disable it again before
1551 * setting up the full range we need.
1553 pci_free_irq_vectors(pdev
);
1554 nr_io_queues
= pci_alloc_irq_vectors(pdev
, 1, nr_io_queues
,
1555 PCI_IRQ_ALL_TYPES
| PCI_IRQ_AFFINITY
);
1556 if (nr_io_queues
<= 0)
1558 dev
->max_qid
= nr_io_queues
;
1561 * Should investigate if there's a performance win from allocating
1562 * more queues than interrupt vectors; it might allow the submission
1563 * path to scale better, even if the receive path is limited by the
1564 * number of interrupts.
1567 result
= queue_request_irq(adminq
);
1569 adminq
->cq_vector
= -1;
1572 return nvme_create_io_queues(dev
);
1575 static void nvme_del_queue_end(struct request
*req
, int error
)
1577 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1579 blk_mq_free_request(req
);
1580 complete(&nvmeq
->dev
->ioq_wait
);
1583 static void nvme_del_cq_end(struct request
*req
, int error
)
1585 struct nvme_queue
*nvmeq
= req
->end_io_data
;
1588 unsigned long flags
;
1591 * We might be called with the AQ q_lock held
1592 * and the I/O queue q_lock should always
1593 * nest inside the AQ one.
1595 spin_lock_irqsave_nested(&nvmeq
->q_lock
, flags
,
1596 SINGLE_DEPTH_NESTING
);
1597 nvme_process_cq(nvmeq
);
1598 spin_unlock_irqrestore(&nvmeq
->q_lock
, flags
);
1601 nvme_del_queue_end(req
, error
);
1604 static int nvme_delete_queue(struct nvme_queue
*nvmeq
, u8 opcode
)
1606 struct request_queue
*q
= nvmeq
->dev
->ctrl
.admin_q
;
1607 struct request
*req
;
1608 struct nvme_command cmd
;
1610 memset(&cmd
, 0, sizeof(cmd
));
1611 cmd
.delete_queue
.opcode
= opcode
;
1612 cmd
.delete_queue
.qid
= cpu_to_le16(nvmeq
->qid
);
1614 req
= nvme_alloc_request(q
, &cmd
, BLK_MQ_REQ_NOWAIT
, NVME_QID_ANY
);
1616 return PTR_ERR(req
);
1618 req
->timeout
= ADMIN_TIMEOUT
;
1619 req
->end_io_data
= nvmeq
;
1621 blk_execute_rq_nowait(q
, NULL
, req
, false,
1622 opcode
== nvme_admin_delete_cq
?
1623 nvme_del_cq_end
: nvme_del_queue_end
);
1627 static void nvme_disable_io_queues(struct nvme_dev
*dev
, int queues
)
1630 unsigned long timeout
;
1631 u8 opcode
= nvme_admin_delete_sq
;
1633 for (pass
= 0; pass
< 2; pass
++) {
1634 int sent
= 0, i
= queues
;
1636 reinit_completion(&dev
->ioq_wait
);
1638 timeout
= ADMIN_TIMEOUT
;
1639 for (; i
> 0; i
--, sent
++)
1640 if (nvme_delete_queue(dev
->queues
[i
], opcode
))
1644 timeout
= wait_for_completion_io_timeout(&dev
->ioq_wait
, timeout
);
1650 opcode
= nvme_admin_delete_cq
;
1655 * Return: error value if an error occurred setting up the queues or calling
1656 * Identify Device. 0 if these succeeded, even if adding some of the
1657 * namespaces failed. At the moment, these failures are silent. TBD which
1658 * failures should be reported.
1660 static int nvme_dev_add(struct nvme_dev
*dev
)
1662 if (!dev
->ctrl
.tagset
) {
1663 dev
->tagset
.ops
= &nvme_mq_ops
;
1664 dev
->tagset
.nr_hw_queues
= dev
->online_queues
- 1;
1665 dev
->tagset
.timeout
= NVME_IO_TIMEOUT
;
1666 dev
->tagset
.numa_node
= dev_to_node(dev
->dev
);
1667 dev
->tagset
.queue_depth
=
1668 min_t(int, dev
->q_depth
, BLK_MQ_MAX_DEPTH
) - 1;
1669 dev
->tagset
.cmd_size
= nvme_cmd_size(dev
);
1670 dev
->tagset
.flags
= BLK_MQ_F_SHOULD_MERGE
;
1671 dev
->tagset
.driver_data
= dev
;
1673 if (blk_mq_alloc_tag_set(&dev
->tagset
))
1675 dev
->ctrl
.tagset
= &dev
->tagset
;
1677 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
1678 if (to_pci_dev(dev
->dev
)->vendor
== PCI_VENDOR_ID_GOOGLE
) {
1679 int res
= nvme_set_doorbell_memory(dev
);
1681 // Free memory and continue on.
1682 dma_free_coherent(dev
->dev
, 8192, dev
->db_mem
, dev
->doorbell
);
1683 dma_free_coherent(dev
->dev
, 8192, dev
->ei_mem
, dev
->doorbell
);
1690 blk_mq_update_nr_hw_queues(&dev
->tagset
, dev
->online_queues
- 1);
1692 /* Free previously allocated queues that are no longer usable */
1693 nvme_free_queues(dev
, dev
->online_queues
);
1699 static int nvme_pci_enable(struct nvme_dev
*dev
)
1702 int result
= -ENOMEM
;
1703 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1705 if (pci_enable_device_mem(pdev
))
1708 pci_set_master(pdev
);
1710 if (dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(64)) &&
1711 dma_set_mask_and_coherent(dev
->dev
, DMA_BIT_MASK(32)))
1714 if (readl(dev
->bar
+ NVME_REG_CSTS
) == -1) {
1720 * Some devices and/or platforms don't advertise or work with INTx
1721 * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
1722 * adjust this later.
1724 result
= pci_alloc_irq_vectors(pdev
, 1, 1, PCI_IRQ_ALL_TYPES
);
1728 cap
= lo_hi_readq(dev
->bar
+ NVME_REG_CAP
);
1730 dev
->q_depth
= min_t(int, NVME_CAP_MQES(cap
) + 1, NVME_Q_DEPTH
);
1731 dev
->db_stride
= 1 << NVME_CAP_STRIDE(cap
);
1732 dev
->dbs
= dev
->bar
+ 4096;
1735 * Temporary fix for the Apple controller found in the MacBook8,1 and
1736 * some MacBook7,1 to avoid controller resets and data loss.
1738 if (pdev
->vendor
== PCI_VENDOR_ID_APPLE
&& pdev
->device
== 0x2001) {
1740 dev_warn(dev
->dev
, "detected Apple NVMe controller, set "
1741 "queue depth=%u to work around controller resets\n",
1746 * CMBs can currently only exist on >=1.2 PCIe devices. We only
1747 * populate sysfs if a CMB is implemented. Note that we add the
1748 * CMB attribute to the nvme_ctrl kobj which removes the need to remove
1749 * it on exit. Since nvme_dev_attrs_group has no name we can pass
1750 * NULL as final argument to sysfs_add_file_to_group.
1753 if (readl(dev
->bar
+ NVME_REG_VS
) >= NVME_VS(1, 2, 0)) {
1754 dev
->cmb
= nvme_map_cmb(dev
);
1757 if (sysfs_add_file_to_group(&dev
->ctrl
.device
->kobj
,
1758 &dev_attr_cmb
.attr
, NULL
))
1760 "failed to add sysfs attribute for CMB\n");
1764 pci_enable_pcie_error_reporting(pdev
);
1765 pci_save_state(pdev
);
1767 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
1768 if (pdev
->vendor
== PCI_VENDOR_ID_GOOGLE
) {
1769 int mem_size
= nvme_vendor_memory_size(dev
);
1770 dev
->db_mem
= dma_alloc_coherent(&pdev
->dev
, mem_size
, &dev
->doorbell
, GFP_KERNEL
);
1775 dev
->ei_mem
= dma_alloc_coherent(&pdev
->dev
, mem_size
, &dev
->eventidx
, GFP_KERNEL
);
1785 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
1787 dma_free_coherent(&pdev
->dev
, nvme_vendor_memory_size(dev
), dev
->db_mem
, dev
->doorbell
);
1792 pci_disable_device(pdev
);
1796 static void nvme_dev_unmap(struct nvme_dev
*dev
)
1800 pci_release_mem_regions(to_pci_dev(dev
->dev
));
1803 static void nvme_pci_disable(struct nvme_dev
*dev
)
1805 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1806 #ifdef CONFIG_NVME_VENDOR_EXT_GOOGLE
1807 int mem_size
= nvme_vendor_memory_size(dev
);
1810 dma_free_coherent(&pdev
->dev
, mem_size
, dev
->db_mem
, dev
->doorbell
);
1812 dma_free_coherent(&pdev
->dev
, mem_size
, dev
->ei_mem
, dev
->eventidx
);
1815 pci_free_irq_vectors(pdev
);
1817 if (pci_is_enabled(pdev
)) {
1818 pci_disable_pcie_error_reporting(pdev
);
1819 pci_disable_device(pdev
);
1823 static void nvme_dev_disable(struct nvme_dev
*dev
, bool shutdown
)
1828 del_timer_sync(&dev
->watchdog_timer
);
1830 mutex_lock(&dev
->shutdown_lock
);
1831 if (pci_is_enabled(to_pci_dev(dev
->dev
))) {
1832 nvme_stop_queues(&dev
->ctrl
);
1833 csts
= readl(dev
->bar
+ NVME_REG_CSTS
);
1836 queues
= dev
->online_queues
- 1;
1837 for (i
= dev
->queue_count
- 1; i
> 0; i
--)
1838 nvme_suspend_queue(dev
->queues
[i
]);
1840 if (csts
& NVME_CSTS_CFS
|| !(csts
& NVME_CSTS_RDY
)) {
1841 /* A device might become IO incapable very soon during
1842 * probe, before the admin queue is configured. Thus,
1843 * queue_count can be 0 here.
1845 if (dev
->queue_count
)
1846 nvme_suspend_queue(dev
->queues
[0]);
1848 nvme_disable_io_queues(dev
, queues
);
1849 nvme_disable_admin_queue(dev
, shutdown
);
1851 nvme_pci_disable(dev
);
1853 blk_mq_tagset_busy_iter(&dev
->tagset
, nvme_cancel_request
, &dev
->ctrl
);
1854 blk_mq_tagset_busy_iter(&dev
->admin_tagset
, nvme_cancel_request
, &dev
->ctrl
);
1855 mutex_unlock(&dev
->shutdown_lock
);
1858 static int nvme_setup_prp_pools(struct nvme_dev
*dev
)
1860 dev
->prp_page_pool
= dma_pool_create("prp list page", dev
->dev
,
1861 PAGE_SIZE
, PAGE_SIZE
, 0);
1862 if (!dev
->prp_page_pool
)
1865 /* Optimisation for I/Os between 4k and 128k */
1866 dev
->prp_small_pool
= dma_pool_create("prp list 256", dev
->dev
,
1868 if (!dev
->prp_small_pool
) {
1869 dma_pool_destroy(dev
->prp_page_pool
);
1875 static void nvme_release_prp_pools(struct nvme_dev
*dev
)
1877 dma_pool_destroy(dev
->prp_page_pool
);
1878 dma_pool_destroy(dev
->prp_small_pool
);
1881 static void nvme_pci_free_ctrl(struct nvme_ctrl
*ctrl
)
1883 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
1885 put_device(dev
->dev
);
1886 if (dev
->tagset
.tags
)
1887 blk_mq_free_tag_set(&dev
->tagset
);
1888 if (dev
->ctrl
.admin_q
)
1889 blk_put_queue(dev
->ctrl
.admin_q
);
1894 static void nvme_remove_dead_ctrl(struct nvme_dev
*dev
, int status
)
1896 dev_warn(dev
->ctrl
.device
, "Removing after probe failure status: %d\n", status
);
1898 kref_get(&dev
->ctrl
.kref
);
1899 nvme_dev_disable(dev
, false);
1900 if (!schedule_work(&dev
->remove_work
))
1901 nvme_put_ctrl(&dev
->ctrl
);
1904 static void nvme_reset_work(struct work_struct
*work
)
1906 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, reset_work
);
1907 int result
= -ENODEV
;
1909 if (WARN_ON(dev
->ctrl
.state
== NVME_CTRL_RESETTING
))
1913 * If we're called to reset a live controller first shut it down before
1916 if (dev
->ctrl
.ctrl_config
& NVME_CC_ENABLE
)
1917 nvme_dev_disable(dev
, false);
1919 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_RESETTING
))
1922 result
= nvme_pci_enable(dev
);
1926 result
= nvme_configure_admin_queue(dev
);
1930 nvme_init_queue(dev
->queues
[0], 0);
1931 result
= nvme_alloc_admin_tags(dev
);
1935 result
= nvme_init_identify(&dev
->ctrl
);
1939 result
= nvme_setup_io_queues(dev
);
1944 * A controller that can not execute IO typically requires user
1945 * intervention to correct. For such degraded controllers, the driver
1946 * should not submit commands the user did not request, so skip
1947 * registering for asynchronous event notification on this condition.
1949 if (dev
->online_queues
> 1)
1950 nvme_queue_async_events(&dev
->ctrl
);
1952 mod_timer(&dev
->watchdog_timer
, round_jiffies(jiffies
+ HZ
));
1955 * Keep the controller around but remove all namespaces if we don't have
1956 * any working I/O queue.
1958 if (dev
->online_queues
< 2) {
1959 dev_warn(dev
->ctrl
.device
, "IO queues not created\n");
1960 nvme_kill_queues(&dev
->ctrl
);
1961 nvme_remove_namespaces(&dev
->ctrl
);
1963 nvme_start_queues(&dev
->ctrl
);
1967 if (!nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_LIVE
)) {
1968 dev_warn(dev
->ctrl
.device
, "failed to mark controller live\n");
1972 if (dev
->online_queues
> 1)
1973 nvme_queue_scan(&dev
->ctrl
);
1977 nvme_remove_dead_ctrl(dev
, result
);
1980 static void nvme_remove_dead_ctrl_work(struct work_struct
*work
)
1982 struct nvme_dev
*dev
= container_of(work
, struct nvme_dev
, remove_work
);
1983 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
1985 nvme_kill_queues(&dev
->ctrl
);
1986 if (pci_get_drvdata(pdev
))
1987 device_release_driver(&pdev
->dev
);
1988 nvme_put_ctrl(&dev
->ctrl
);
1991 static int nvme_reset(struct nvme_dev
*dev
)
1993 if (!dev
->ctrl
.admin_q
|| blk_queue_dying(dev
->ctrl
.admin_q
))
1995 if (work_busy(&dev
->reset_work
))
1997 if (!queue_work(nvme_workq
, &dev
->reset_work
))
2002 static int nvme_pci_reg_read32(struct nvme_ctrl
*ctrl
, u32 off
, u32
*val
)
2004 *val
= readl(to_nvme_dev(ctrl
)->bar
+ off
);
2008 static int nvme_pci_reg_write32(struct nvme_ctrl
*ctrl
, u32 off
, u32 val
)
2010 writel(val
, to_nvme_dev(ctrl
)->bar
+ off
);
2014 static int nvme_pci_reg_read64(struct nvme_ctrl
*ctrl
, u32 off
, u64
*val
)
2016 *val
= readq(to_nvme_dev(ctrl
)->bar
+ off
);
2020 static int nvme_pci_reset_ctrl(struct nvme_ctrl
*ctrl
)
2022 struct nvme_dev
*dev
= to_nvme_dev(ctrl
);
2023 int ret
= nvme_reset(dev
);
2026 flush_work(&dev
->reset_work
);
2030 static const struct nvme_ctrl_ops nvme_pci_ctrl_ops
= {
2032 .module
= THIS_MODULE
,
2033 .reg_read32
= nvme_pci_reg_read32
,
2034 .reg_write32
= nvme_pci_reg_write32
,
2035 .reg_read64
= nvme_pci_reg_read64
,
2036 .reset_ctrl
= nvme_pci_reset_ctrl
,
2037 .free_ctrl
= nvme_pci_free_ctrl
,
2038 .submit_async_event
= nvme_pci_submit_async_event
,
2041 static int nvme_dev_map(struct nvme_dev
*dev
)
2043 struct pci_dev
*pdev
= to_pci_dev(dev
->dev
);
2045 if (pci_request_mem_regions(pdev
, "nvme"))
2048 dev
->bar
= ioremap(pci_resource_start(pdev
, 0), 8192);
2054 pci_release_mem_regions(pdev
);
2058 static unsigned long check_dell_samsung_bug(struct pci_dev
*pdev
)
2060 if (pdev
->vendor
== 0x144d && pdev
->device
== 0xa802) {
2062 * Several Samsung devices seem to drop off the PCIe bus
2063 * randomly when APST is on and uses the deepest sleep state.
2064 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2065 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2066 * 950 PRO 256GB", but it seems to be restricted to two Dell
2069 if (dmi_match(DMI_SYS_VENDOR
, "Dell Inc.") &&
2070 (dmi_match(DMI_PRODUCT_NAME
, "XPS 15 9550") ||
2071 dmi_match(DMI_PRODUCT_NAME
, "Precision 5510")))
2072 return NVME_QUIRK_NO_DEEPEST_PS
;
2078 static int nvme_probe(struct pci_dev
*pdev
, const struct pci_device_id
*id
)
2080 int node
, result
= -ENOMEM
;
2081 struct nvme_dev
*dev
;
2082 unsigned long quirks
= id
->driver_data
;
2084 node
= dev_to_node(&pdev
->dev
);
2085 if (node
== NUMA_NO_NODE
)
2086 set_dev_node(&pdev
->dev
, first_memory_node
);
2088 dev
= kzalloc_node(sizeof(*dev
), GFP_KERNEL
, node
);
2091 dev
->queues
= kzalloc_node((num_possible_cpus() + 1) * sizeof(void *),
2096 dev
->dev
= get_device(&pdev
->dev
);
2097 pci_set_drvdata(pdev
, dev
);
2099 result
= nvme_dev_map(dev
);
2103 INIT_WORK(&dev
->reset_work
, nvme_reset_work
);
2104 INIT_WORK(&dev
->remove_work
, nvme_remove_dead_ctrl_work
);
2105 setup_timer(&dev
->watchdog_timer
, nvme_watchdog_timer
,
2106 (unsigned long)dev
);
2107 mutex_init(&dev
->shutdown_lock
);
2108 init_completion(&dev
->ioq_wait
);
2110 result
= nvme_setup_prp_pools(dev
);
2114 quirks
|= check_dell_samsung_bug(pdev
);
2116 result
= nvme_init_ctrl(&dev
->ctrl
, &pdev
->dev
, &nvme_pci_ctrl_ops
,
2121 dev_info(dev
->ctrl
.device
, "pci function %s\n", dev_name(&pdev
->dev
));
2123 queue_work(nvme_workq
, &dev
->reset_work
);
2127 nvme_release_prp_pools(dev
);
2129 put_device(dev
->dev
);
2130 nvme_dev_unmap(dev
);
2137 static void nvme_reset_notify(struct pci_dev
*pdev
, bool prepare
)
2139 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2142 nvme_dev_disable(dev
, false);
2147 static void nvme_shutdown(struct pci_dev
*pdev
)
2149 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2150 nvme_dev_disable(dev
, true);
2154 * The driver's remove may be called on a device in a partially initialized
2155 * state. This function must not have any dependencies on the device state in
2158 static void nvme_remove(struct pci_dev
*pdev
)
2160 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2162 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DELETING
);
2164 pci_set_drvdata(pdev
, NULL
);
2166 if (!pci_device_is_present(pdev
)) {
2167 nvme_change_ctrl_state(&dev
->ctrl
, NVME_CTRL_DEAD
);
2168 nvme_dev_disable(dev
, false);
2171 flush_work(&dev
->reset_work
);
2172 nvme_uninit_ctrl(&dev
->ctrl
);
2173 nvme_dev_disable(dev
, true);
2174 nvme_dev_remove_admin(dev
);
2175 nvme_free_queues(dev
, 0);
2176 nvme_release_cmb(dev
);
2177 nvme_release_prp_pools(dev
);
2178 nvme_dev_unmap(dev
);
2179 nvme_put_ctrl(&dev
->ctrl
);
2182 static int nvme_pci_sriov_configure(struct pci_dev
*pdev
, int numvfs
)
2187 if (pci_vfs_assigned(pdev
)) {
2188 dev_warn(&pdev
->dev
,
2189 "Cannot disable SR-IOV VFs while assigned\n");
2192 pci_disable_sriov(pdev
);
2196 ret
= pci_enable_sriov(pdev
, numvfs
);
2197 return ret
? ret
: numvfs
;
2200 #ifdef CONFIG_PM_SLEEP
2201 static int nvme_suspend(struct device
*dev
)
2203 struct pci_dev
*pdev
= to_pci_dev(dev
);
2204 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2206 nvme_dev_disable(ndev
, true);
2210 static int nvme_resume(struct device
*dev
)
2212 struct pci_dev
*pdev
= to_pci_dev(dev
);
2213 struct nvme_dev
*ndev
= pci_get_drvdata(pdev
);
2220 static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops
, nvme_suspend
, nvme_resume
);
2222 static pci_ers_result_t
nvme_error_detected(struct pci_dev
*pdev
,
2223 pci_channel_state_t state
)
2225 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2228 * A frozen channel requires a reset. When detected, this method will
2229 * shutdown the controller to quiesce. The controller will be restarted
2230 * after the slot reset through driver's slot_reset callback.
2233 case pci_channel_io_normal
:
2234 return PCI_ERS_RESULT_CAN_RECOVER
;
2235 case pci_channel_io_frozen
:
2236 dev_warn(dev
->ctrl
.device
,
2237 "frozen state error detected, reset controller\n");
2238 nvme_dev_disable(dev
, false);
2239 return PCI_ERS_RESULT_NEED_RESET
;
2240 case pci_channel_io_perm_failure
:
2241 dev_warn(dev
->ctrl
.device
,
2242 "failure state error detected, request disconnect\n");
2243 return PCI_ERS_RESULT_DISCONNECT
;
2245 return PCI_ERS_RESULT_NEED_RESET
;
2248 static pci_ers_result_t
nvme_slot_reset(struct pci_dev
*pdev
)
2250 struct nvme_dev
*dev
= pci_get_drvdata(pdev
);
2252 dev_info(dev
->ctrl
.device
, "restart after slot reset\n");
2253 pci_restore_state(pdev
);
2255 return PCI_ERS_RESULT_RECOVERED
;
2258 static void nvme_error_resume(struct pci_dev
*pdev
)
2260 pci_cleanup_aer_uncorrect_error_status(pdev
);
2263 static const struct pci_error_handlers nvme_err_handler
= {
2264 .error_detected
= nvme_error_detected
,
2265 .slot_reset
= nvme_slot_reset
,
2266 .resume
= nvme_error_resume
,
2267 .reset_notify
= nvme_reset_notify
,
2270 static const struct pci_device_id nvme_id_table
[] = {
2271 { PCI_VDEVICE(INTEL
, 0x0953),
2272 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2273 NVME_QUIRK_DISCARD_ZEROES
, },
2274 { PCI_VDEVICE(INTEL
, 0x0a53),
2275 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2276 NVME_QUIRK_DISCARD_ZEROES
, },
2277 { PCI_VDEVICE(INTEL
, 0x0a54),
2278 .driver_data
= NVME_QUIRK_STRIPE_SIZE
|
2279 NVME_QUIRK_DISCARD_ZEROES
, },
2280 { PCI_VDEVICE(INTEL
, 0xf1a5), /* Intel 600P/P3100 */
2281 .driver_data
= NVME_QUIRK_NO_DEEPEST_PS
},
2282 { PCI_VDEVICE(INTEL
, 0x5845), /* Qemu emulated controller */
2283 .driver_data
= NVME_QUIRK_IDENTIFY_CNS
, },
2284 { PCI_DEVICE(0x1c58, 0x0003), /* HGST adapter */
2285 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2286 { PCI_DEVICE(0x1c5f, 0x0540), /* Memblaze Pblaze4 adapter */
2287 .driver_data
= NVME_QUIRK_DELAY_BEFORE_CHK_RDY
, },
2288 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS
, 0xffffff) },
2289 { PCI_DEVICE(PCI_VENDOR_ID_APPLE
, 0x2001) },
2292 MODULE_DEVICE_TABLE(pci
, nvme_id_table
);
2294 static struct pci_driver nvme_driver
= {
2296 .id_table
= nvme_id_table
,
2297 .probe
= nvme_probe
,
2298 .remove
= nvme_remove
,
2299 .shutdown
= nvme_shutdown
,
2301 .pm
= &nvme_dev_pm_ops
,
2303 .sriov_configure
= nvme_pci_sriov_configure
,
2304 .err_handler
= &nvme_err_handler
,
2307 static int __init
nvme_init(void)
2311 nvme_workq
= alloc_workqueue("nvme", WQ_UNBOUND
| WQ_MEM_RECLAIM
, 0);
2315 result
= pci_register_driver(&nvme_driver
);
2317 destroy_workqueue(nvme_workq
);
2321 static void __exit
nvme_exit(void)
2323 pci_unregister_driver(&nvme_driver
);
2324 destroy_workqueue(nvme_workq
);
2328 MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2329 MODULE_LICENSE("GPL");
2330 MODULE_VERSION("1.0");
2331 module_init(nvme_init
);
2332 module_exit(nvme_exit
);