2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
5 * Copyright 2008 Openmoko, Inc.
6 * Copyright 2008 Simtec Electronics
7 * Ben Dooks <ben@simtec.co.uk>
8 * http://armlinux.simtec.co.uk/
10 * S3C USB2.0 High-speed / OtG driver
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/spinlock.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/mutex.h>
24 #include <linux/seq_file.h>
25 #include <linux/delay.h>
27 #include <linux/slab.h>
28 #include <linux/of_platform.h>
30 #include <linux/usb/ch9.h>
31 #include <linux/usb/gadget.h>
32 #include <linux/usb/phy.h>
37 /* conversion functions */
38 static inline struct dwc2_hsotg_req
*our_req(struct usb_request
*req
)
40 return container_of(req
, struct dwc2_hsotg_req
, req
);
43 static inline struct dwc2_hsotg_ep
*our_ep(struct usb_ep
*ep
)
45 return container_of(ep
, struct dwc2_hsotg_ep
, ep
);
48 static inline struct dwc2_hsotg
*to_hsotg(struct usb_gadget
*gadget
)
50 return container_of(gadget
, struct dwc2_hsotg
, gadget
);
53 static inline void __orr32(void __iomem
*ptr
, u32 val
)
55 dwc2_writel(dwc2_readl(ptr
) | val
, ptr
);
58 static inline void __bic32(void __iomem
*ptr
, u32 val
)
60 dwc2_writel(dwc2_readl(ptr
) & ~val
, ptr
);
63 static inline struct dwc2_hsotg_ep
*index_to_ep(struct dwc2_hsotg
*hsotg
,
64 u32 ep_index
, u32 dir_in
)
67 return hsotg
->eps_in
[ep_index
];
69 return hsotg
->eps_out
[ep_index
];
72 /* forward declaration of functions */
73 static void dwc2_hsotg_dump(struct dwc2_hsotg
*hsotg
);
76 * using_dma - return the DMA status of the driver.
77 * @hsotg: The driver state.
79 * Return true if we're using DMA.
81 * Currently, we have the DMA support code worked into everywhere
82 * that needs it, but the AMBA DMA implementation in the hardware can
83 * only DMA from 32bit aligned addresses. This means that gadgets such
84 * as the CDC Ethernet cannot work as they often pass packets which are
87 * Unfortunately the choice to use DMA or not is global to the controller
88 * and seems to be only settable when the controller is being put through
89 * a core reset. This means we either need to fix the gadgets to take
90 * account of DMA alignment, or add bounce buffers (yuerk).
92 * g_using_dma is set depending on dts flag.
94 static inline bool using_dma(struct dwc2_hsotg
*hsotg
)
96 return hsotg
->g_using_dma
;
100 * dwc2_gadget_incr_frame_num - Increments the targeted frame number.
101 * @hs_ep: The endpoint
102 * @increment: The value to increment by
104 * This function will also check if the frame number overruns DSTS_SOFFN_LIMIT.
105 * If an overrun occurs it will wrap the value and set the frame_overrun flag.
107 static inline void dwc2_gadget_incr_frame_num(struct dwc2_hsotg_ep
*hs_ep
)
109 hs_ep
->target_frame
+= hs_ep
->interval
;
110 if (hs_ep
->target_frame
> DSTS_SOFFN_LIMIT
) {
111 hs_ep
->frame_overrun
= 1;
112 hs_ep
->target_frame
&= DSTS_SOFFN_LIMIT
;
114 hs_ep
->frame_overrun
= 0;
119 * dwc2_hsotg_en_gsint - enable one or more of the general interrupt
120 * @hsotg: The device state
121 * @ints: A bitmask of the interrupts to enable
123 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
125 u32 gsintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
128 new_gsintmsk
= gsintmsk
| ints
;
130 if (new_gsintmsk
!= gsintmsk
) {
131 dev_dbg(hsotg
->dev
, "gsintmsk now 0x%08x\n", new_gsintmsk
);
132 dwc2_writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
137 * dwc2_hsotg_disable_gsint - disable one or more of the general interrupt
138 * @hsotg: The device state
139 * @ints: A bitmask of the interrupts to enable
141 static void dwc2_hsotg_disable_gsint(struct dwc2_hsotg
*hsotg
, u32 ints
)
143 u32 gsintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
146 new_gsintmsk
= gsintmsk
& ~ints
;
148 if (new_gsintmsk
!= gsintmsk
)
149 dwc2_writel(new_gsintmsk
, hsotg
->regs
+ GINTMSK
);
153 * dwc2_hsotg_ctrl_epint - enable/disable an endpoint irq
154 * @hsotg: The device state
155 * @ep: The endpoint index
156 * @dir_in: True if direction is in.
157 * @en: The enable value, true to enable
159 * Set or clear the mask for an individual endpoint's interrupt
162 static void dwc2_hsotg_ctrl_epint(struct dwc2_hsotg
*hsotg
,
163 unsigned int ep
, unsigned int dir_in
,
173 local_irq_save(flags
);
174 daint
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
179 dwc2_writel(daint
, hsotg
->regs
+ DAINTMSK
);
180 local_irq_restore(flags
);
184 * dwc2_hsotg_init_fifo - initialise non-periodic FIFOs
185 * @hsotg: The device instance.
187 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg
*hsotg
)
194 /* Reset fifo map if not correctly cleared during previous session */
195 WARN_ON(hsotg
->fifo_map
);
198 /* set RX/NPTX FIFO sizes */
199 dwc2_writel(hsotg
->g_rx_fifo_sz
, hsotg
->regs
+ GRXFSIZ
);
200 dwc2_writel((hsotg
->g_rx_fifo_sz
<< FIFOSIZE_STARTADDR_SHIFT
) |
201 (hsotg
->g_np_g_tx_fifo_sz
<< FIFOSIZE_DEPTH_SHIFT
),
202 hsotg
->regs
+ GNPTXFSIZ
);
205 * arange all the rest of the TX FIFOs, as some versions of this
206 * block have overlapping default addresses. This also ensures
207 * that if the settings have been changed, then they are set to
211 /* start at the end of the GNPTXFSIZ, rounded up */
212 addr
= hsotg
->g_rx_fifo_sz
+ hsotg
->g_np_g_tx_fifo_sz
;
215 * Configure fifos sizes from provided configuration and assign
216 * them to endpoints dynamically according to maxpacket size value of
219 for (ep
= 1; ep
< MAX_EPS_CHANNELS
; ep
++) {
220 if (!hsotg
->g_tx_fifo_sz
[ep
])
223 val
|= hsotg
->g_tx_fifo_sz
[ep
] << FIFOSIZE_DEPTH_SHIFT
;
224 WARN_ONCE(addr
+ hsotg
->g_tx_fifo_sz
[ep
] > hsotg
->fifo_mem
,
225 "insufficient fifo memory");
226 addr
+= hsotg
->g_tx_fifo_sz
[ep
];
228 dwc2_writel(val
, hsotg
->regs
+ DPTXFSIZN(ep
));
232 * according to p428 of the design guide, we need to ensure that
233 * all fifos are flushed before continuing
236 dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH
|
237 GRSTCTL_RXFFLSH
, hsotg
->regs
+ GRSTCTL
);
239 /* wait until the fifos are both flushed */
242 val
= dwc2_readl(hsotg
->regs
+ GRSTCTL
);
244 if ((val
& (GRSTCTL_TXFFLSH
| GRSTCTL_RXFFLSH
)) == 0)
247 if (--timeout
== 0) {
249 "%s: timeout flushing fifos (GRSTCTL=%08x)\n",
257 dev_dbg(hsotg
->dev
, "FIFOs reset, timeout at %d\n", timeout
);
261 * @ep: USB endpoint to allocate request for.
262 * @flags: Allocation flags
264 * Allocate a new USB request structure appropriate for the specified endpoint
266 static struct usb_request
*dwc2_hsotg_ep_alloc_request(struct usb_ep
*ep
,
269 struct dwc2_hsotg_req
*req
;
271 req
= kzalloc(sizeof(struct dwc2_hsotg_req
), flags
);
275 INIT_LIST_HEAD(&req
->queue
);
281 * is_ep_periodic - return true if the endpoint is in periodic mode.
282 * @hs_ep: The endpoint to query.
284 * Returns true if the endpoint is in periodic mode, meaning it is being
285 * used for an Interrupt or ISO transfer.
287 static inline int is_ep_periodic(struct dwc2_hsotg_ep
*hs_ep
)
289 return hs_ep
->periodic
;
293 * dwc2_hsotg_unmap_dma - unmap the DMA memory being used for the request
294 * @hsotg: The device state.
295 * @hs_ep: The endpoint for the request
296 * @hs_req: The request being processed.
298 * This is the reverse of dwc2_hsotg_map_dma(), called for the completion
299 * of a request to ensure the buffer is ready for access by the caller.
301 static void dwc2_hsotg_unmap_dma(struct dwc2_hsotg
*hsotg
,
302 struct dwc2_hsotg_ep
*hs_ep
,
303 struct dwc2_hsotg_req
*hs_req
)
305 struct usb_request
*req
= &hs_req
->req
;
307 /* ignore this if we're not moving any data */
308 if (hs_req
->req
.length
== 0)
311 usb_gadget_unmap_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
315 * dwc2_hsotg_write_fifo - write packet Data to the TxFIFO
316 * @hsotg: The controller state.
317 * @hs_ep: The endpoint we're going to write for.
318 * @hs_req: The request to write data for.
320 * This is called when the TxFIFO has some space in it to hold a new
321 * transmission and we have something to give it. The actual setup of
322 * the data size is done elsewhere, so all we have to do is to actually
325 * The return value is zero if there is more space (or nothing was done)
326 * otherwise -ENOSPC is returned if the FIFO space was used up.
328 * This routine is only needed for PIO
330 static int dwc2_hsotg_write_fifo(struct dwc2_hsotg
*hsotg
,
331 struct dwc2_hsotg_ep
*hs_ep
,
332 struct dwc2_hsotg_req
*hs_req
)
334 bool periodic
= is_ep_periodic(hs_ep
);
335 u32 gnptxsts
= dwc2_readl(hsotg
->regs
+ GNPTXSTS
);
336 int buf_pos
= hs_req
->req
.actual
;
337 int to_write
= hs_ep
->size_loaded
;
343 to_write
-= (buf_pos
- hs_ep
->last_load
);
345 /* if there's nothing to write, get out early */
349 if (periodic
&& !hsotg
->dedicated_fifos
) {
350 u32 epsize
= dwc2_readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
355 * work out how much data was loaded so we can calculate
356 * how much data is left in the fifo.
359 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
362 * if shared fifo, we cannot write anything until the
363 * previous data has been completely sent.
365 if (hs_ep
->fifo_load
!= 0) {
366 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
370 dev_dbg(hsotg
->dev
, "%s: left=%d, load=%d, fifo=%d, size %d\n",
372 hs_ep
->size_loaded
, hs_ep
->fifo_load
, hs_ep
->fifo_size
);
374 /* how much of the data has moved */
375 size_done
= hs_ep
->size_loaded
- size_left
;
377 /* how much data is left in the fifo */
378 can_write
= hs_ep
->fifo_load
- size_done
;
379 dev_dbg(hsotg
->dev
, "%s: => can_write1=%d\n",
380 __func__
, can_write
);
382 can_write
= hs_ep
->fifo_size
- can_write
;
383 dev_dbg(hsotg
->dev
, "%s: => can_write2=%d\n",
384 __func__
, can_write
);
386 if (can_write
<= 0) {
387 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_PTXFEMP
);
390 } else if (hsotg
->dedicated_fifos
&& hs_ep
->index
!= 0) {
391 can_write
= dwc2_readl(hsotg
->regs
+
392 DTXFSTS(hs_ep
->fifo_index
));
397 if (GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(gnptxsts
) == 0) {
399 "%s: no queue slots available (0x%08x)\n",
402 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_NPTXFEMP
);
406 can_write
= GNPTXSTS_NP_TXF_SPC_AVAIL_GET(gnptxsts
);
407 can_write
*= 4; /* fifo size is in 32bit quantities. */
410 max_transfer
= hs_ep
->ep
.maxpacket
* hs_ep
->mc
;
412 dev_dbg(hsotg
->dev
, "%s: GNPTXSTS=%08x, can=%d, to=%d, max_transfer %d\n",
413 __func__
, gnptxsts
, can_write
, to_write
, max_transfer
);
416 * limit to 512 bytes of data, it seems at least on the non-periodic
417 * FIFO, requests of >512 cause the endpoint to get stuck with a
418 * fragment of the end of the transfer in it.
420 if (can_write
> 512 && !periodic
)
424 * limit the write to one max-packet size worth of data, but allow
425 * the transfer to return that it did not run out of fifo space
428 if (to_write
> max_transfer
) {
429 to_write
= max_transfer
;
431 /* it's needed only when we do not use dedicated fifos */
432 if (!hsotg
->dedicated_fifos
)
433 dwc2_hsotg_en_gsint(hsotg
,
434 periodic
? GINTSTS_PTXFEMP
:
438 /* see if we can write data */
440 if (to_write
> can_write
) {
441 to_write
= can_write
;
442 pkt_round
= to_write
% max_transfer
;
445 * Round the write down to an
446 * exact number of packets.
448 * Note, we do not currently check to see if we can ever
449 * write a full packet or not to the FIFO.
453 to_write
-= pkt_round
;
456 * enable correct FIFO interrupt to alert us when there
460 /* it's needed only when we do not use dedicated fifos */
461 if (!hsotg
->dedicated_fifos
)
462 dwc2_hsotg_en_gsint(hsotg
,
463 periodic
? GINTSTS_PTXFEMP
:
467 dev_dbg(hsotg
->dev
, "write %d/%d, can_write %d, done %d\n",
468 to_write
, hs_req
->req
.length
, can_write
, buf_pos
);
473 hs_req
->req
.actual
= buf_pos
+ to_write
;
474 hs_ep
->total_data
+= to_write
;
477 hs_ep
->fifo_load
+= to_write
;
479 to_write
= DIV_ROUND_UP(to_write
, 4);
480 data
= hs_req
->req
.buf
+ buf_pos
;
482 iowrite32_rep(hsotg
->regs
+ EPFIFO(hs_ep
->index
), data
, to_write
);
484 return (to_write
>= can_write
) ? -ENOSPC
: 0;
488 * get_ep_limit - get the maximum data legnth for this endpoint
489 * @hs_ep: The endpoint
491 * Return the maximum data that can be queued in one go on a given endpoint
492 * so that transfers that are too long can be split.
494 static unsigned get_ep_limit(struct dwc2_hsotg_ep
*hs_ep
)
496 int index
= hs_ep
->index
;
501 maxsize
= DXEPTSIZ_XFERSIZE_LIMIT
+ 1;
502 maxpkt
= DXEPTSIZ_PKTCNT_LIMIT
+ 1;
506 maxpkt
= DIEPTSIZ0_PKTCNT_LIMIT
+ 1;
511 /* we made the constant loading easier above by using +1 */
516 * constrain by packet count if maxpkts*pktsize is greater
517 * than the length register size.
520 if ((maxpkt
* hs_ep
->ep
.maxpacket
) < maxsize
)
521 maxsize
= maxpkt
* hs_ep
->ep
.maxpacket
;
527 * dwc2_hsotg_read_frameno - read current frame number
528 * @hsotg: The device instance
530 * Return the current frame number
532 static u32
dwc2_hsotg_read_frameno(struct dwc2_hsotg
*hsotg
)
536 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
537 dsts
&= DSTS_SOFFN_MASK
;
538 dsts
>>= DSTS_SOFFN_SHIFT
;
544 * dwc2_hsotg_start_req - start a USB request from an endpoint's queue
545 * @hsotg: The controller state.
546 * @hs_ep: The endpoint to process a request for
547 * @hs_req: The request to start.
548 * @continuing: True if we are doing more for the current request.
550 * Start the given request running by setting the endpoint registers
551 * appropriately, and writing any data to the FIFOs.
553 static void dwc2_hsotg_start_req(struct dwc2_hsotg
*hsotg
,
554 struct dwc2_hsotg_ep
*hs_ep
,
555 struct dwc2_hsotg_req
*hs_req
,
558 struct usb_request
*ureq
= &hs_req
->req
;
559 int index
= hs_ep
->index
;
560 int dir_in
= hs_ep
->dir_in
;
570 if (hs_ep
->req
&& !continuing
) {
571 dev_err(hsotg
->dev
, "%s: active request\n", __func__
);
574 } else if (hs_ep
->req
!= hs_req
&& continuing
) {
576 "%s: continue different req\n", __func__
);
582 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
583 epsize_reg
= dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
585 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x, ep %d, dir %s\n",
586 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
), index
,
587 hs_ep
->dir_in
? "in" : "out");
589 /* If endpoint is stalled, we will restart request later */
590 ctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
592 if (index
&& ctrl
& DXEPCTL_STALL
) {
593 dev_warn(hsotg
->dev
, "%s: ep%d is stalled\n", __func__
, index
);
597 length
= ureq
->length
- ureq
->actual
;
598 dev_dbg(hsotg
->dev
, "ureq->length:%d ureq->actual:%d\n",
599 ureq
->length
, ureq
->actual
);
601 maxreq
= get_ep_limit(hs_ep
);
602 if (length
> maxreq
) {
603 int round
= maxreq
% hs_ep
->ep
.maxpacket
;
605 dev_dbg(hsotg
->dev
, "%s: length %d, max-req %d, r %d\n",
606 __func__
, length
, maxreq
, round
);
608 /* round down to multiple of packets */
616 packets
= DIV_ROUND_UP(length
, hs_ep
->ep
.maxpacket
);
618 packets
= 1; /* send one packet if length is zero. */
620 if (hs_ep
->isochronous
&& length
> (hs_ep
->mc
* hs_ep
->ep
.maxpacket
)) {
621 dev_err(hsotg
->dev
, "req length > maxpacket*mc\n");
625 if (dir_in
&& index
!= 0)
626 if (hs_ep
->isochronous
)
627 epsize
= DXEPTSIZ_MC(packets
);
629 epsize
= DXEPTSIZ_MC(1);
634 * zero length packet should be programmed on its own and should not
635 * be counted in DIEPTSIZ.PktCnt with other packets.
637 if (dir_in
&& ureq
->zero
&& !continuing
) {
638 /* Test if zlp is actually required. */
639 if ((ureq
->length
>= hs_ep
->ep
.maxpacket
) &&
640 !(ureq
->length
% hs_ep
->ep
.maxpacket
))
644 epsize
|= DXEPTSIZ_PKTCNT(packets
);
645 epsize
|= DXEPTSIZ_XFERSIZE(length
);
647 dev_dbg(hsotg
->dev
, "%s: %d@%d/%d, 0x%08x => 0x%08x\n",
648 __func__
, packets
, length
, ureq
->length
, epsize
, epsize_reg
);
650 /* store the request as the current one we're doing */
653 /* write size / packets */
654 dwc2_writel(epsize
, hsotg
->regs
+ epsize_reg
);
656 if (using_dma(hsotg
) && !continuing
) {
657 unsigned int dma_reg
;
660 * write DMA address to control register, buffer already
661 * synced by dwc2_hsotg_ep_queue().
664 dma_reg
= dir_in
? DIEPDMA(index
) : DOEPDMA(index
);
665 dwc2_writel(ureq
->dma
, hsotg
->regs
+ dma_reg
);
667 dev_dbg(hsotg
->dev
, "%s: %pad => 0x%08x\n",
668 __func__
, &ureq
->dma
, dma_reg
);
671 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1) {
672 hs_ep
->target_frame
= dwc2_hsotg_read_frameno(hsotg
);
673 dwc2_gadget_incr_frame_num(hs_ep
);
675 if (hs_ep
->target_frame
& 0x1)
676 ctrl
|= DXEPCTL_SETODDFR
;
678 ctrl
|= DXEPCTL_SETEVENFR
;
681 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
683 dev_dbg(hsotg
->dev
, "ep0 state:%d\n", hsotg
->ep0_state
);
685 /* For Setup request do not clear NAK */
686 if (!(index
== 0 && hsotg
->ep0_state
== DWC2_EP0_SETUP
))
687 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
689 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
690 dwc2_writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
693 * set these, it seems that DMA support increments past the end
694 * of the packet buffer so we need to calculate the length from
697 hs_ep
->size_loaded
= length
;
698 hs_ep
->last_load
= ureq
->actual
;
700 if (dir_in
&& !using_dma(hsotg
)) {
701 /* set these anyway, we may need them for non-periodic in */
702 hs_ep
->fifo_load
= 0;
704 dwc2_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
708 * Note, trying to clear the NAK here causes problems with transmit
709 * on the S3C6400 ending up with the TXFIFO becoming full.
712 /* check ep is enabled */
713 if (!(dwc2_readl(hsotg
->regs
+ epctrl_reg
) & DXEPCTL_EPENA
))
715 "ep%d: failed to become enabled (DXEPCTL=0x%08x)?\n",
716 index
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
718 dev_dbg(hsotg
->dev
, "%s: DXEPCTL=0x%08x\n",
719 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
721 /* enable ep interrupts */
722 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 1);
726 * dwc2_hsotg_map_dma - map the DMA memory being used for the request
727 * @hsotg: The device state.
728 * @hs_ep: The endpoint the request is on.
729 * @req: The request being processed.
731 * We've been asked to queue a request, so ensure that the memory buffer
732 * is correctly setup for DMA. If we've been passed an extant DMA address
733 * then ensure the buffer has been synced to memory. If our buffer has no
734 * DMA memory, then we map the memory and mark our request to allow us to
735 * cleanup on completion.
737 static int dwc2_hsotg_map_dma(struct dwc2_hsotg
*hsotg
,
738 struct dwc2_hsotg_ep
*hs_ep
,
739 struct usb_request
*req
)
741 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
744 /* if the length is zero, ignore the DMA data */
745 if (hs_req
->req
.length
== 0)
748 ret
= usb_gadget_map_request(&hsotg
->gadget
, req
, hs_ep
->dir_in
);
755 dev_err(hsotg
->dev
, "%s: failed to map buffer %p, %d bytes\n",
756 __func__
, req
->buf
, req
->length
);
761 static int dwc2_hsotg_handle_unaligned_buf_start(struct dwc2_hsotg
*hsotg
,
762 struct dwc2_hsotg_ep
*hs_ep
, struct dwc2_hsotg_req
*hs_req
)
764 void *req_buf
= hs_req
->req
.buf
;
766 /* If dma is not being used or buffer is aligned */
767 if (!using_dma(hsotg
) || !((long)req_buf
& 3))
770 WARN_ON(hs_req
->saved_req_buf
);
772 dev_dbg(hsotg
->dev
, "%s: %s: buf=%p length=%d\n", __func__
,
773 hs_ep
->ep
.name
, req_buf
, hs_req
->req
.length
);
775 hs_req
->req
.buf
= kmalloc(hs_req
->req
.length
, GFP_ATOMIC
);
776 if (!hs_req
->req
.buf
) {
777 hs_req
->req
.buf
= req_buf
;
779 "%s: unable to allocate memory for bounce buffer\n",
784 /* Save actual buffer */
785 hs_req
->saved_req_buf
= req_buf
;
788 memcpy(hs_req
->req
.buf
, req_buf
, hs_req
->req
.length
);
792 static void dwc2_hsotg_handle_unaligned_buf_complete(struct dwc2_hsotg
*hsotg
,
793 struct dwc2_hsotg_ep
*hs_ep
, struct dwc2_hsotg_req
*hs_req
)
795 /* If dma is not being used or buffer was aligned */
796 if (!using_dma(hsotg
) || !hs_req
->saved_req_buf
)
799 dev_dbg(hsotg
->dev
, "%s: %s: status=%d actual-length=%d\n", __func__
,
800 hs_ep
->ep
.name
, hs_req
->req
.status
, hs_req
->req
.actual
);
802 /* Copy data from bounce buffer on successful out transfer */
803 if (!hs_ep
->dir_in
&& !hs_req
->req
.status
)
804 memcpy(hs_req
->saved_req_buf
, hs_req
->req
.buf
,
807 /* Free bounce buffer */
808 kfree(hs_req
->req
.buf
);
810 hs_req
->req
.buf
= hs_req
->saved_req_buf
;
811 hs_req
->saved_req_buf
= NULL
;
815 * dwc2_gadget_target_frame_elapsed - Checks target frame
816 * @hs_ep: The driver endpoint to check
818 * Returns 1 if targeted frame elapsed. If returned 1 then we need to drop
819 * corresponding transfer.
821 static bool dwc2_gadget_target_frame_elapsed(struct dwc2_hsotg_ep
*hs_ep
)
823 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
824 u32 target_frame
= hs_ep
->target_frame
;
825 u32 current_frame
= dwc2_hsotg_read_frameno(hsotg
);
826 bool frame_overrun
= hs_ep
->frame_overrun
;
828 if (!frame_overrun
&& current_frame
>= target_frame
)
831 if (frame_overrun
&& current_frame
>= target_frame
&&
832 ((current_frame
- target_frame
) < DSTS_SOFFN_LIMIT
/ 2))
838 static int dwc2_hsotg_ep_queue(struct usb_ep
*ep
, struct usb_request
*req
,
841 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
842 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
843 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
847 dev_dbg(hs
->dev
, "%s: req %p: %d@%p, noi=%d, zero=%d, snok=%d\n",
848 ep
->name
, req
, req
->length
, req
->buf
, req
->no_interrupt
,
849 req
->zero
, req
->short_not_ok
);
851 /* Prevent new request submission when controller is suspended */
852 if (hs
->lx_state
== DWC2_L2
) {
853 dev_dbg(hs
->dev
, "%s: don't submit request while suspended\n",
858 /* initialise status of the request */
859 INIT_LIST_HEAD(&hs_req
->queue
);
861 req
->status
= -EINPROGRESS
;
863 ret
= dwc2_hsotg_handle_unaligned_buf_start(hs
, hs_ep
, hs_req
);
867 /* if we're using DMA, sync the buffers as necessary */
869 ret
= dwc2_hsotg_map_dma(hs
, hs_ep
, req
);
874 first
= list_empty(&hs_ep
->queue
);
875 list_add_tail(&hs_req
->queue
, &hs_ep
->queue
);
878 if (!hs_ep
->isochronous
) {
879 dwc2_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
883 while (dwc2_gadget_target_frame_elapsed(hs_ep
))
884 dwc2_gadget_incr_frame_num(hs_ep
);
886 if (hs_ep
->target_frame
!= TARGET_FRAME_INITIAL
)
887 dwc2_hsotg_start_req(hs
, hs_ep
, hs_req
, false);
892 static int dwc2_hsotg_ep_queue_lock(struct usb_ep
*ep
, struct usb_request
*req
,
895 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
896 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
897 unsigned long flags
= 0;
900 spin_lock_irqsave(&hs
->lock
, flags
);
901 ret
= dwc2_hsotg_ep_queue(ep
, req
, gfp_flags
);
902 spin_unlock_irqrestore(&hs
->lock
, flags
);
907 static void dwc2_hsotg_ep_free_request(struct usb_ep
*ep
,
908 struct usb_request
*req
)
910 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
916 * dwc2_hsotg_complete_oursetup - setup completion callback
917 * @ep: The endpoint the request was on.
918 * @req: The request completed.
920 * Called on completion of any requests the driver itself
921 * submitted that need cleaning up.
923 static void dwc2_hsotg_complete_oursetup(struct usb_ep
*ep
,
924 struct usb_request
*req
)
926 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
927 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
929 dev_dbg(hsotg
->dev
, "%s: ep %p, req %p\n", __func__
, ep
, req
);
931 dwc2_hsotg_ep_free_request(ep
, req
);
935 * ep_from_windex - convert control wIndex value to endpoint
936 * @hsotg: The driver state.
937 * @windex: The control request wIndex field (in host order).
939 * Convert the given wIndex into a pointer to an driver endpoint
940 * structure, or return NULL if it is not a valid endpoint.
942 static struct dwc2_hsotg_ep
*ep_from_windex(struct dwc2_hsotg
*hsotg
,
945 struct dwc2_hsotg_ep
*ep
;
946 int dir
= (windex
& USB_DIR_IN
) ? 1 : 0;
947 int idx
= windex
& 0x7F;
952 if (idx
> hsotg
->num_of_eps
)
955 ep
= index_to_ep(hsotg
, idx
, dir
);
957 if (idx
&& ep
->dir_in
!= dir
)
964 * dwc2_hsotg_set_test_mode - Enable usb Test Modes
965 * @hsotg: The driver state.
966 * @testmode: requested usb test mode
967 * Enable usb Test Mode requested by the Host.
969 int dwc2_hsotg_set_test_mode(struct dwc2_hsotg
*hsotg
, int testmode
)
971 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
973 dctl
&= ~DCTL_TSTCTL_MASK
;
980 dctl
|= testmode
<< DCTL_TSTCTL_SHIFT
;
985 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
990 * dwc2_hsotg_send_reply - send reply to control request
991 * @hsotg: The device state
993 * @buff: Buffer for request
994 * @length: Length of reply.
996 * Create a request and queue it on the given endpoint. This is useful as
997 * an internal method of sending replies to certain control requests, etc.
999 static int dwc2_hsotg_send_reply(struct dwc2_hsotg
*hsotg
,
1000 struct dwc2_hsotg_ep
*ep
,
1004 struct usb_request
*req
;
1007 dev_dbg(hsotg
->dev
, "%s: buff %p, len %d\n", __func__
, buff
, length
);
1009 req
= dwc2_hsotg_ep_alloc_request(&ep
->ep
, GFP_ATOMIC
);
1010 hsotg
->ep0_reply
= req
;
1012 dev_warn(hsotg
->dev
, "%s: cannot alloc req\n", __func__
);
1016 req
->buf
= hsotg
->ep0_buff
;
1017 req
->length
= length
;
1019 * zero flag is for sending zlp in DATA IN stage. It has no impact on
1023 req
->complete
= dwc2_hsotg_complete_oursetup
;
1026 memcpy(req
->buf
, buff
, length
);
1028 ret
= dwc2_hsotg_ep_queue(&ep
->ep
, req
, GFP_ATOMIC
);
1030 dev_warn(hsotg
->dev
, "%s: cannot queue req\n", __func__
);
1038 * dwc2_hsotg_process_req_status - process request GET_STATUS
1039 * @hsotg: The device state
1040 * @ctrl: USB control request
1042 static int dwc2_hsotg_process_req_status(struct dwc2_hsotg
*hsotg
,
1043 struct usb_ctrlrequest
*ctrl
)
1045 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1046 struct dwc2_hsotg_ep
*ep
;
1050 dev_dbg(hsotg
->dev
, "%s: USB_REQ_GET_STATUS\n", __func__
);
1053 dev_warn(hsotg
->dev
, "%s: direction out?\n", __func__
);
1057 switch (ctrl
->bRequestType
& USB_RECIP_MASK
) {
1058 case USB_RECIP_DEVICE
:
1059 reply
= cpu_to_le16(0); /* bit 0 => self powered,
1060 * bit 1 => remote wakeup */
1063 case USB_RECIP_INTERFACE
:
1064 /* currently, the data result should be zero */
1065 reply
= cpu_to_le16(0);
1068 case USB_RECIP_ENDPOINT
:
1069 ep
= ep_from_windex(hsotg
, le16_to_cpu(ctrl
->wIndex
));
1073 reply
= cpu_to_le16(ep
->halted
? 1 : 0);
1080 if (le16_to_cpu(ctrl
->wLength
) != 2)
1083 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, &reply
, 2);
1085 dev_err(hsotg
->dev
, "%s: failed to send reply\n", __func__
);
1092 static int dwc2_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
, bool now
);
1095 * get_ep_head - return the first request on the endpoint
1096 * @hs_ep: The controller endpoint to get
1098 * Get the first request on the endpoint.
1100 static struct dwc2_hsotg_req
*get_ep_head(struct dwc2_hsotg_ep
*hs_ep
)
1102 if (list_empty(&hs_ep
->queue
))
1105 return list_first_entry(&hs_ep
->queue
, struct dwc2_hsotg_req
, queue
);
1109 * dwc2_gadget_start_next_request - Starts next request from ep queue
1110 * @hs_ep: Endpoint structure
1112 * If queue is empty and EP is ISOC-OUT - unmasks OUTTKNEPDIS which is masked
1113 * in its handler. Hence we need to unmask it here to be able to do
1114 * resynchronization.
1116 static void dwc2_gadget_start_next_request(struct dwc2_hsotg_ep
*hs_ep
)
1119 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1120 int dir_in
= hs_ep
->dir_in
;
1121 struct dwc2_hsotg_req
*hs_req
;
1122 u32 epmsk_reg
= dir_in
? DIEPMSK
: DOEPMSK
;
1124 if (!list_empty(&hs_ep
->queue
)) {
1125 hs_req
= get_ep_head(hs_ep
);
1126 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, false);
1129 if (!hs_ep
->isochronous
)
1133 dev_dbg(hsotg
->dev
, "%s: No more ISOC-IN requests\n",
1136 dev_dbg(hsotg
->dev
, "%s: No more ISOC-OUT requests\n",
1138 mask
= dwc2_readl(hsotg
->regs
+ epmsk_reg
);
1139 mask
|= DOEPMSK_OUTTKNEPDISMSK
;
1140 dwc2_writel(mask
, hsotg
->regs
+ epmsk_reg
);
1145 * dwc2_hsotg_process_req_feature - process request {SET,CLEAR}_FEATURE
1146 * @hsotg: The device state
1147 * @ctrl: USB control request
1149 static int dwc2_hsotg_process_req_feature(struct dwc2_hsotg
*hsotg
,
1150 struct usb_ctrlrequest
*ctrl
)
1152 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1153 struct dwc2_hsotg_req
*hs_req
;
1154 bool set
= (ctrl
->bRequest
== USB_REQ_SET_FEATURE
);
1155 struct dwc2_hsotg_ep
*ep
;
1162 dev_dbg(hsotg
->dev
, "%s: %s_FEATURE\n",
1163 __func__
, set
? "SET" : "CLEAR");
1165 wValue
= le16_to_cpu(ctrl
->wValue
);
1166 wIndex
= le16_to_cpu(ctrl
->wIndex
);
1167 recip
= ctrl
->bRequestType
& USB_RECIP_MASK
;
1170 case USB_RECIP_DEVICE
:
1172 case USB_DEVICE_TEST_MODE
:
1173 if ((wIndex
& 0xff) != 0)
1178 hsotg
->test_mode
= wIndex
>> 8;
1179 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1182 "%s: failed to send reply\n", __func__
);
1191 case USB_RECIP_ENDPOINT
:
1192 ep
= ep_from_windex(hsotg
, wIndex
);
1194 dev_dbg(hsotg
->dev
, "%s: no endpoint for 0x%04x\n",
1200 case USB_ENDPOINT_HALT
:
1201 halted
= ep
->halted
;
1203 dwc2_hsotg_ep_sethalt(&ep
->ep
, set
, true);
1205 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1208 "%s: failed to send reply\n", __func__
);
1213 * we have to complete all requests for ep if it was
1214 * halted, and the halt was cleared by CLEAR_FEATURE
1217 if (!set
&& halted
) {
1219 * If we have request in progress,
1225 list_del_init(&hs_req
->queue
);
1226 if (hs_req
->req
.complete
) {
1227 spin_unlock(&hsotg
->lock
);
1228 usb_gadget_giveback_request(
1229 &ep
->ep
, &hs_req
->req
);
1230 spin_lock(&hsotg
->lock
);
1234 /* If we have pending request, then start it */
1236 dwc2_gadget_start_next_request(ep
);
1252 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
);
1255 * dwc2_hsotg_stall_ep0 - stall ep0
1256 * @hsotg: The device state
1258 * Set stall for ep0 as response for setup request.
1260 static void dwc2_hsotg_stall_ep0(struct dwc2_hsotg
*hsotg
)
1262 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1266 dev_dbg(hsotg
->dev
, "ep0 stall (dir=%d)\n", ep0
->dir_in
);
1267 reg
= (ep0
->dir_in
) ? DIEPCTL0
: DOEPCTL0
;
1270 * DxEPCTL_Stall will be cleared by EP once it has
1271 * taken effect, so no need to clear later.
1274 ctrl
= dwc2_readl(hsotg
->regs
+ reg
);
1275 ctrl
|= DXEPCTL_STALL
;
1276 ctrl
|= DXEPCTL_CNAK
;
1277 dwc2_writel(ctrl
, hsotg
->regs
+ reg
);
1280 "written DXEPCTL=0x%08x to %08x (DXEPCTL=0x%08x)\n",
1281 ctrl
, reg
, dwc2_readl(hsotg
->regs
+ reg
));
1284 * complete won't be called, so we enqueue
1285 * setup request here
1287 dwc2_hsotg_enqueue_setup(hsotg
);
1291 * dwc2_hsotg_process_control - process a control request
1292 * @hsotg: The device state
1293 * @ctrl: The control request received
1295 * The controller has received the SETUP phase of a control request, and
1296 * needs to work out what to do next (and whether to pass it on to the
1299 static void dwc2_hsotg_process_control(struct dwc2_hsotg
*hsotg
,
1300 struct usb_ctrlrequest
*ctrl
)
1302 struct dwc2_hsotg_ep
*ep0
= hsotg
->eps_out
[0];
1307 "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n",
1308 ctrl
->bRequestType
, ctrl
->bRequest
, ctrl
->wValue
,
1309 ctrl
->wIndex
, ctrl
->wLength
);
1311 if (ctrl
->wLength
== 0) {
1313 hsotg
->ep0_state
= DWC2_EP0_STATUS_IN
;
1314 } else if (ctrl
->bRequestType
& USB_DIR_IN
) {
1316 hsotg
->ep0_state
= DWC2_EP0_DATA_IN
;
1319 hsotg
->ep0_state
= DWC2_EP0_DATA_OUT
;
1322 if ((ctrl
->bRequestType
& USB_TYPE_MASK
) == USB_TYPE_STANDARD
) {
1323 switch (ctrl
->bRequest
) {
1324 case USB_REQ_SET_ADDRESS
:
1325 hsotg
->connected
= 1;
1326 dcfg
= dwc2_readl(hsotg
->regs
+ DCFG
);
1327 dcfg
&= ~DCFG_DEVADDR_MASK
;
1328 dcfg
|= (le16_to_cpu(ctrl
->wValue
) <<
1329 DCFG_DEVADDR_SHIFT
) & DCFG_DEVADDR_MASK
;
1330 dwc2_writel(dcfg
, hsotg
->regs
+ DCFG
);
1332 dev_info(hsotg
->dev
, "new address %d\n", ctrl
->wValue
);
1334 ret
= dwc2_hsotg_send_reply(hsotg
, ep0
, NULL
, 0);
1337 case USB_REQ_GET_STATUS
:
1338 ret
= dwc2_hsotg_process_req_status(hsotg
, ctrl
);
1341 case USB_REQ_CLEAR_FEATURE
:
1342 case USB_REQ_SET_FEATURE
:
1343 ret
= dwc2_hsotg_process_req_feature(hsotg
, ctrl
);
1348 /* as a fallback, try delivering it to the driver to deal with */
1350 if (ret
== 0 && hsotg
->driver
) {
1351 spin_unlock(&hsotg
->lock
);
1352 ret
= hsotg
->driver
->setup(&hsotg
->gadget
, ctrl
);
1353 spin_lock(&hsotg
->lock
);
1355 dev_dbg(hsotg
->dev
, "driver->setup() ret %d\n", ret
);
1359 * the request is either unhandlable, or is not formatted correctly
1360 * so respond with a STALL for the status stage to indicate failure.
1364 dwc2_hsotg_stall_ep0(hsotg
);
1368 * dwc2_hsotg_complete_setup - completion of a setup transfer
1369 * @ep: The endpoint the request was on.
1370 * @req: The request completed.
1372 * Called on completion of any requests the driver itself submitted for
1375 static void dwc2_hsotg_complete_setup(struct usb_ep
*ep
,
1376 struct usb_request
*req
)
1378 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
1379 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
1381 if (req
->status
< 0) {
1382 dev_dbg(hsotg
->dev
, "%s: failed %d\n", __func__
, req
->status
);
1386 spin_lock(&hsotg
->lock
);
1387 if (req
->actual
== 0)
1388 dwc2_hsotg_enqueue_setup(hsotg
);
1390 dwc2_hsotg_process_control(hsotg
, req
->buf
);
1391 spin_unlock(&hsotg
->lock
);
1395 * dwc2_hsotg_enqueue_setup - start a request for EP0 packets
1396 * @hsotg: The device state.
1398 * Enqueue a request on EP0 if necessary to received any SETUP packets
1399 * received from the host.
1401 static void dwc2_hsotg_enqueue_setup(struct dwc2_hsotg
*hsotg
)
1403 struct usb_request
*req
= hsotg
->ctrl_req
;
1404 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
1407 dev_dbg(hsotg
->dev
, "%s: queueing setup request\n", __func__
);
1411 req
->buf
= hsotg
->ctrl_buff
;
1412 req
->complete
= dwc2_hsotg_complete_setup
;
1414 if (!list_empty(&hs_req
->queue
)) {
1415 dev_dbg(hsotg
->dev
, "%s already queued???\n", __func__
);
1419 hsotg
->eps_out
[0]->dir_in
= 0;
1420 hsotg
->eps_out
[0]->send_zlp
= 0;
1421 hsotg
->ep0_state
= DWC2_EP0_SETUP
;
1423 ret
= dwc2_hsotg_ep_queue(&hsotg
->eps_out
[0]->ep
, req
, GFP_ATOMIC
);
1425 dev_err(hsotg
->dev
, "%s: failed queue (%d)\n", __func__
, ret
);
1427 * Don't think there's much we can do other than watch the
1433 static void dwc2_hsotg_program_zlp(struct dwc2_hsotg
*hsotg
,
1434 struct dwc2_hsotg_ep
*hs_ep
)
1437 u8 index
= hs_ep
->index
;
1438 u32 epctl_reg
= hs_ep
->dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
1439 u32 epsiz_reg
= hs_ep
->dir_in
? DIEPTSIZ(index
) : DOEPTSIZ(index
);
1442 dev_dbg(hsotg
->dev
, "Sending zero-length packet on ep%d\n",
1445 dev_dbg(hsotg
->dev
, "Receiving zero-length packet on ep%d\n",
1448 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
1449 DXEPTSIZ_XFERSIZE(0), hsotg
->regs
+
1452 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
1453 ctrl
|= DXEPCTL_CNAK
; /* clear NAK set by core */
1454 ctrl
|= DXEPCTL_EPENA
; /* ensure ep enabled */
1455 ctrl
|= DXEPCTL_USBACTEP
;
1456 dwc2_writel(ctrl
, hsotg
->regs
+ epctl_reg
);
1460 * dwc2_hsotg_complete_request - complete a request given to us
1461 * @hsotg: The device state.
1462 * @hs_ep: The endpoint the request was on.
1463 * @hs_req: The request to complete.
1464 * @result: The result code (0 => Ok, otherwise errno)
1466 * The given request has finished, so call the necessary completion
1467 * if it has one and then look to see if we can start a new request
1470 * Note, expects the ep to already be locked as appropriate.
1472 static void dwc2_hsotg_complete_request(struct dwc2_hsotg
*hsotg
,
1473 struct dwc2_hsotg_ep
*hs_ep
,
1474 struct dwc2_hsotg_req
*hs_req
,
1479 dev_dbg(hsotg
->dev
, "%s: nothing to complete?\n", __func__
);
1483 dev_dbg(hsotg
->dev
, "complete: ep %p %s, req %p, %d => %p\n",
1484 hs_ep
, hs_ep
->ep
.name
, hs_req
, result
, hs_req
->req
.complete
);
1487 * only replace the status if we've not already set an error
1488 * from a previous transaction
1491 if (hs_req
->req
.status
== -EINPROGRESS
)
1492 hs_req
->req
.status
= result
;
1494 if (using_dma(hsotg
))
1495 dwc2_hsotg_unmap_dma(hsotg
, hs_ep
, hs_req
);
1497 dwc2_hsotg_handle_unaligned_buf_complete(hsotg
, hs_ep
, hs_req
);
1500 list_del_init(&hs_req
->queue
);
1503 * call the complete request with the locks off, just in case the
1504 * request tries to queue more work for this endpoint.
1507 if (hs_req
->req
.complete
) {
1508 spin_unlock(&hsotg
->lock
);
1509 usb_gadget_giveback_request(&hs_ep
->ep
, &hs_req
->req
);
1510 spin_lock(&hsotg
->lock
);
1514 * Look to see if there is anything else to do. Note, the completion
1515 * of the previous request may have caused a new request to be started
1516 * so be careful when doing this.
1519 if (!hs_ep
->req
&& result
>= 0) {
1520 dwc2_gadget_start_next_request(hs_ep
);
1525 * dwc2_hsotg_rx_data - receive data from the FIFO for an endpoint
1526 * @hsotg: The device state.
1527 * @ep_idx: The endpoint index for the data
1528 * @size: The size of data in the fifo, in bytes
1530 * The FIFO status shows there is data to read from the FIFO for a given
1531 * endpoint, so sort out whether we need to read the data into a request
1532 * that has been made for that endpoint.
1534 static void dwc2_hsotg_rx_data(struct dwc2_hsotg
*hsotg
, int ep_idx
, int size
)
1536 struct dwc2_hsotg_ep
*hs_ep
= hsotg
->eps_out
[ep_idx
];
1537 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
1538 void __iomem
*fifo
= hsotg
->regs
+ EPFIFO(ep_idx
);
1545 u32 epctl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(ep_idx
));
1549 "%s: FIFO %d bytes on ep%d but no req (DXEPCTl=0x%08x)\n",
1550 __func__
, size
, ep_idx
, epctl
);
1552 /* dump the data from the FIFO, we've nothing we can do */
1553 for (ptr
= 0; ptr
< size
; ptr
+= 4)
1554 (void)dwc2_readl(fifo
);
1560 read_ptr
= hs_req
->req
.actual
;
1561 max_req
= hs_req
->req
.length
- read_ptr
;
1563 dev_dbg(hsotg
->dev
, "%s: read %d/%d, done %d/%d\n",
1564 __func__
, to_read
, max_req
, read_ptr
, hs_req
->req
.length
);
1566 if (to_read
> max_req
) {
1568 * more data appeared than we where willing
1569 * to deal with in this request.
1572 /* currently we don't deal this */
1576 hs_ep
->total_data
+= to_read
;
1577 hs_req
->req
.actual
+= to_read
;
1578 to_read
= DIV_ROUND_UP(to_read
, 4);
1581 * note, we might over-write the buffer end by 3 bytes depending on
1582 * alignment of the data.
1584 ioread32_rep(fifo
, hs_req
->req
.buf
+ read_ptr
, to_read
);
1588 * dwc2_hsotg_ep0_zlp - send/receive zero-length packet on control endpoint
1589 * @hsotg: The device instance
1590 * @dir_in: If IN zlp
1592 * Generate a zero-length IN packet request for terminating a SETUP
1595 * Note, since we don't write any data to the TxFIFO, then it is
1596 * currently believed that we do not need to wait for any space in
1599 static void dwc2_hsotg_ep0_zlp(struct dwc2_hsotg
*hsotg
, bool dir_in
)
1601 /* eps_out[0] is used in both directions */
1602 hsotg
->eps_out
[0]->dir_in
= dir_in
;
1603 hsotg
->ep0_state
= dir_in
? DWC2_EP0_STATUS_IN
: DWC2_EP0_STATUS_OUT
;
1605 dwc2_hsotg_program_zlp(hsotg
, hsotg
->eps_out
[0]);
1608 static void dwc2_hsotg_change_ep_iso_parity(struct dwc2_hsotg
*hsotg
,
1613 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
1614 if (ctrl
& DXEPCTL_EOFRNUM
)
1615 ctrl
|= DXEPCTL_SETEVENFR
;
1617 ctrl
|= DXEPCTL_SETODDFR
;
1618 dwc2_writel(ctrl
, hsotg
->regs
+ epctl_reg
);
1622 * dwc2_hsotg_handle_outdone - handle receiving OutDone/SetupDone from RXFIFO
1623 * @hsotg: The device instance
1624 * @epnum: The endpoint received from
1626 * The RXFIFO has delivered an OutDone event, which means that the data
1627 * transfer for an OUT endpoint has been completed, either by a short
1628 * packet or by the finish of a transfer.
1630 static void dwc2_hsotg_handle_outdone(struct dwc2_hsotg
*hsotg
, int epnum
)
1632 u32 epsize
= dwc2_readl(hsotg
->regs
+ DOEPTSIZ(epnum
));
1633 struct dwc2_hsotg_ep
*hs_ep
= hsotg
->eps_out
[epnum
];
1634 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
1635 struct usb_request
*req
= &hs_req
->req
;
1636 unsigned size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
1640 dev_dbg(hsotg
->dev
, "%s: no request active\n", __func__
);
1644 if (epnum
== 0 && hsotg
->ep0_state
== DWC2_EP0_STATUS_OUT
) {
1645 dev_dbg(hsotg
->dev
, "zlp packet received\n");
1646 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1647 dwc2_hsotg_enqueue_setup(hsotg
);
1651 if (using_dma(hsotg
)) {
1655 * Calculate the size of the transfer by checking how much
1656 * is left in the endpoint size register and then working it
1657 * out from the amount we loaded for the transfer.
1659 * We need to do this as DMA pointers are always 32bit aligned
1660 * so may overshoot/undershoot the transfer.
1663 size_done
= hs_ep
->size_loaded
- size_left
;
1664 size_done
+= hs_ep
->last_load
;
1666 req
->actual
= size_done
;
1669 /* if there is more request to do, schedule new transfer */
1670 if (req
->actual
< req
->length
&& size_left
== 0) {
1671 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
1675 if (req
->actual
< req
->length
&& req
->short_not_ok
) {
1676 dev_dbg(hsotg
->dev
, "%s: got %d/%d (short not ok) => error\n",
1677 __func__
, req
->actual
, req
->length
);
1680 * todo - what should we return here? there's no one else
1681 * even bothering to check the status.
1685 if (epnum
== 0 && hsotg
->ep0_state
== DWC2_EP0_DATA_OUT
) {
1686 /* Move to STATUS IN */
1687 dwc2_hsotg_ep0_zlp(hsotg
, true);
1692 * Slave mode OUT transfers do not go through XferComplete so
1693 * adjust the ISOC parity here.
1695 if (!using_dma(hsotg
)) {
1696 if (hs_ep
->isochronous
&& hs_ep
->interval
== 1)
1697 dwc2_hsotg_change_ep_iso_parity(hsotg
, DOEPCTL(epnum
));
1698 else if (hs_ep
->isochronous
&& hs_ep
->interval
> 1)
1699 dwc2_gadget_incr_frame_num(hs_ep
);
1702 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, result
);
1706 * dwc2_hsotg_handle_rx - RX FIFO has data
1707 * @hsotg: The device instance
1709 * The IRQ handler has detected that the RX FIFO has some data in it
1710 * that requires processing, so find out what is in there and do the
1713 * The RXFIFO is a true FIFO, the packets coming out are still in packet
1714 * chunks, so if you have x packets received on an endpoint you'll get x
1715 * FIFO events delivered, each with a packet's worth of data in it.
1717 * When using DMA, we should not be processing events from the RXFIFO
1718 * as the actual data should be sent to the memory directly and we turn
1719 * on the completion interrupts to get notifications of transfer completion.
1721 static void dwc2_hsotg_handle_rx(struct dwc2_hsotg
*hsotg
)
1723 u32 grxstsr
= dwc2_readl(hsotg
->regs
+ GRXSTSP
);
1724 u32 epnum
, status
, size
;
1726 WARN_ON(using_dma(hsotg
));
1728 epnum
= grxstsr
& GRXSTS_EPNUM_MASK
;
1729 status
= grxstsr
& GRXSTS_PKTSTS_MASK
;
1731 size
= grxstsr
& GRXSTS_BYTECNT_MASK
;
1732 size
>>= GRXSTS_BYTECNT_SHIFT
;
1734 dev_dbg(hsotg
->dev
, "%s: GRXSTSP=0x%08x (%d@%d)\n",
1735 __func__
, grxstsr
, size
, epnum
);
1737 switch ((status
& GRXSTS_PKTSTS_MASK
) >> GRXSTS_PKTSTS_SHIFT
) {
1738 case GRXSTS_PKTSTS_GLOBALOUTNAK
:
1739 dev_dbg(hsotg
->dev
, "GLOBALOUTNAK\n");
1742 case GRXSTS_PKTSTS_OUTDONE
:
1743 dev_dbg(hsotg
->dev
, "OutDone (Frame=0x%08x)\n",
1744 dwc2_hsotg_read_frameno(hsotg
));
1746 if (!using_dma(hsotg
))
1747 dwc2_hsotg_handle_outdone(hsotg
, epnum
);
1750 case GRXSTS_PKTSTS_SETUPDONE
:
1752 "SetupDone (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1753 dwc2_hsotg_read_frameno(hsotg
),
1754 dwc2_readl(hsotg
->regs
+ DOEPCTL(0)));
1756 * Call dwc2_hsotg_handle_outdone here if it was not called from
1757 * GRXSTS_PKTSTS_OUTDONE. That is, if the core didn't
1758 * generate GRXSTS_PKTSTS_OUTDONE for setup packet.
1760 if (hsotg
->ep0_state
== DWC2_EP0_SETUP
)
1761 dwc2_hsotg_handle_outdone(hsotg
, epnum
);
1764 case GRXSTS_PKTSTS_OUTRX
:
1765 dwc2_hsotg_rx_data(hsotg
, epnum
, size
);
1768 case GRXSTS_PKTSTS_SETUPRX
:
1770 "SetupRX (Frame=0x%08x, DOPEPCTL=0x%08x)\n",
1771 dwc2_hsotg_read_frameno(hsotg
),
1772 dwc2_readl(hsotg
->regs
+ DOEPCTL(0)));
1774 WARN_ON(hsotg
->ep0_state
!= DWC2_EP0_SETUP
);
1776 dwc2_hsotg_rx_data(hsotg
, epnum
, size
);
1780 dev_warn(hsotg
->dev
, "%s: unknown status %08x\n",
1783 dwc2_hsotg_dump(hsotg
);
1789 * dwc2_hsotg_ep0_mps - turn max packet size into register setting
1790 * @mps: The maximum packet size in bytes.
1792 static u32
dwc2_hsotg_ep0_mps(unsigned int mps
)
1796 return D0EPCTL_MPS_64
;
1798 return D0EPCTL_MPS_32
;
1800 return D0EPCTL_MPS_16
;
1802 return D0EPCTL_MPS_8
;
1805 /* bad max packet size, warn and return invalid result */
1811 * dwc2_hsotg_set_ep_maxpacket - set endpoint's max-packet field
1812 * @hsotg: The driver state.
1813 * @ep: The index number of the endpoint
1814 * @mps: The maximum packet size in bytes
1816 * Configure the maximum packet size for the given endpoint, updating
1817 * the hardware control registers to reflect this.
1819 static void dwc2_hsotg_set_ep_maxpacket(struct dwc2_hsotg
*hsotg
,
1820 unsigned int ep
, unsigned int mps
, unsigned int dir_in
)
1822 struct dwc2_hsotg_ep
*hs_ep
;
1823 void __iomem
*regs
= hsotg
->regs
;
1828 hs_ep
= index_to_ep(hsotg
, ep
, dir_in
);
1833 /* EP0 is a special case */
1834 mpsval
= dwc2_hsotg_ep0_mps(mps
);
1837 hs_ep
->ep
.maxpacket
= mps
;
1840 mpsval
= mps
& DXEPCTL_MPS_MASK
;
1843 mcval
= ((mps
>> 11) & 0x3) + 1;
1847 hs_ep
->ep
.maxpacket
= mpsval
;
1851 reg
= dwc2_readl(regs
+ DIEPCTL(ep
));
1852 reg
&= ~DXEPCTL_MPS_MASK
;
1854 dwc2_writel(reg
, regs
+ DIEPCTL(ep
));
1856 reg
= dwc2_readl(regs
+ DOEPCTL(ep
));
1857 reg
&= ~DXEPCTL_MPS_MASK
;
1859 dwc2_writel(reg
, regs
+ DOEPCTL(ep
));
1865 dev_err(hsotg
->dev
, "ep%d: bad mps of %d\n", ep
, mps
);
1869 * dwc2_hsotg_txfifo_flush - flush Tx FIFO
1870 * @hsotg: The driver state
1871 * @idx: The index for the endpoint (0..15)
1873 static void dwc2_hsotg_txfifo_flush(struct dwc2_hsotg
*hsotg
, unsigned int idx
)
1878 dwc2_writel(GRSTCTL_TXFNUM(idx
) | GRSTCTL_TXFFLSH
,
1879 hsotg
->regs
+ GRSTCTL
);
1881 /* wait until the fifo is flushed */
1885 val
= dwc2_readl(hsotg
->regs
+ GRSTCTL
);
1887 if ((val
& (GRSTCTL_TXFFLSH
)) == 0)
1890 if (--timeout
== 0) {
1892 "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
1902 * dwc2_hsotg_trytx - check to see if anything needs transmitting
1903 * @hsotg: The driver state
1904 * @hs_ep: The driver endpoint to check.
1906 * Check to see if there is a request that has data to send, and if so
1907 * make an attempt to write data into the FIFO.
1909 static int dwc2_hsotg_trytx(struct dwc2_hsotg
*hsotg
,
1910 struct dwc2_hsotg_ep
*hs_ep
)
1912 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
1914 if (!hs_ep
->dir_in
|| !hs_req
) {
1916 * if request is not enqueued, we disable interrupts
1917 * for endpoints, excepting ep0
1919 if (hs_ep
->index
!= 0)
1920 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
,
1925 if (hs_req
->req
.actual
< hs_req
->req
.length
) {
1926 dev_dbg(hsotg
->dev
, "trying to write more for ep%d\n",
1928 return dwc2_hsotg_write_fifo(hsotg
, hs_ep
, hs_req
);
1935 * dwc2_hsotg_complete_in - complete IN transfer
1936 * @hsotg: The device state.
1937 * @hs_ep: The endpoint that has just completed.
1939 * An IN transfer has been completed, update the transfer's state and then
1940 * call the relevant completion routines.
1942 static void dwc2_hsotg_complete_in(struct dwc2_hsotg
*hsotg
,
1943 struct dwc2_hsotg_ep
*hs_ep
)
1945 struct dwc2_hsotg_req
*hs_req
= hs_ep
->req
;
1946 u32 epsize
= dwc2_readl(hsotg
->regs
+ DIEPTSIZ(hs_ep
->index
));
1947 int size_left
, size_done
;
1950 dev_dbg(hsotg
->dev
, "XferCompl but no req\n");
1954 /* Finish ZLP handling for IN EP0 transactions */
1955 if (hs_ep
->index
== 0 && hsotg
->ep0_state
== DWC2_EP0_STATUS_IN
) {
1956 dev_dbg(hsotg
->dev
, "zlp packet sent\n");
1957 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
1958 if (hsotg
->test_mode
) {
1961 ret
= dwc2_hsotg_set_test_mode(hsotg
, hsotg
->test_mode
);
1963 dev_dbg(hsotg
->dev
, "Invalid Test #%d\n",
1965 dwc2_hsotg_stall_ep0(hsotg
);
1969 dwc2_hsotg_enqueue_setup(hsotg
);
1974 * Calculate the size of the transfer by checking how much is left
1975 * in the endpoint size register and then working it out from
1976 * the amount we loaded for the transfer.
1978 * We do this even for DMA, as the transfer may have incremented
1979 * past the end of the buffer (DMA transfers are always 32bit
1983 size_left
= DXEPTSIZ_XFERSIZE_GET(epsize
);
1985 size_done
= hs_ep
->size_loaded
- size_left
;
1986 size_done
+= hs_ep
->last_load
;
1988 if (hs_req
->req
.actual
!= size_done
)
1989 dev_dbg(hsotg
->dev
, "%s: adjusting size done %d => %d\n",
1990 __func__
, hs_req
->req
.actual
, size_done
);
1992 hs_req
->req
.actual
= size_done
;
1993 dev_dbg(hsotg
->dev
, "req->length:%d req->actual:%d req->zero:%d\n",
1994 hs_req
->req
.length
, hs_req
->req
.actual
, hs_req
->req
.zero
);
1996 if (!size_left
&& hs_req
->req
.actual
< hs_req
->req
.length
) {
1997 dev_dbg(hsotg
->dev
, "%s trying more for req...\n", __func__
);
1998 dwc2_hsotg_start_req(hsotg
, hs_ep
, hs_req
, true);
2002 /* Zlp for all endpoints, for ep0 only in DATA IN stage */
2003 if (hs_ep
->send_zlp
) {
2004 dwc2_hsotg_program_zlp(hsotg
, hs_ep
);
2005 hs_ep
->send_zlp
= 0;
2006 /* transfer will be completed on next complete interrupt */
2010 if (hs_ep
->index
== 0 && hsotg
->ep0_state
== DWC2_EP0_DATA_IN
) {
2011 /* Move to STATUS OUT */
2012 dwc2_hsotg_ep0_zlp(hsotg
, false);
2016 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
, 0);
2020 * dwc2_gadget_read_ep_interrupts - reads interrupts for given ep
2021 * @hsotg: The device state.
2022 * @idx: Index of ep.
2023 * @dir_in: Endpoint direction 1-in 0-out.
2025 * Reads for endpoint with given index and direction, by masking
2026 * epint_reg with coresponding mask.
2028 static u32
dwc2_gadget_read_ep_interrupts(struct dwc2_hsotg
*hsotg
,
2029 unsigned int idx
, int dir_in
)
2031 u32 epmsk_reg
= dir_in
? DIEPMSK
: DOEPMSK
;
2032 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
2037 mask
= dwc2_readl(hsotg
->regs
+ epmsk_reg
);
2038 diepempmsk
= dwc2_readl(hsotg
->regs
+ DIEPEMPMSK
);
2039 mask
|= ((diepempmsk
>> idx
) & 0x1) ? DIEPMSK_TXFIFOEMPTY
: 0;
2040 mask
|= DXEPINT_SETUP_RCVD
;
2042 ints
= dwc2_readl(hsotg
->regs
+ epint_reg
);
2048 * dwc2_gadget_handle_ep_disabled - handle DXEPINT_EPDISBLD
2049 * @hs_ep: The endpoint on which interrupt is asserted.
2051 * This interrupt indicates that the endpoint has been disabled per the
2052 * application's request.
2054 * For IN endpoints flushes txfifo, in case of BULK clears DCTL_CGNPINNAK,
2055 * in case of ISOC completes current request.
2057 * For ISOC-OUT endpoints completes expired requests. If there is remaining
2058 * request starts it.
2060 static void dwc2_gadget_handle_ep_disabled(struct dwc2_hsotg_ep
*hs_ep
)
2062 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2063 struct dwc2_hsotg_req
*hs_req
;
2064 unsigned char idx
= hs_ep
->index
;
2065 int dir_in
= hs_ep
->dir_in
;
2066 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
2067 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
2069 dev_dbg(hsotg
->dev
, "%s: EPDisbld\n", __func__
);
2072 int epctl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
2074 dwc2_hsotg_txfifo_flush(hsotg
, hs_ep
->fifo_index
);
2076 if (hs_ep
->isochronous
) {
2077 dwc2_hsotg_complete_in(hsotg
, hs_ep
);
2081 if ((epctl
& DXEPCTL_STALL
) && (epctl
& DXEPCTL_EPTYPE_BULK
)) {
2082 int dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
2084 dctl
|= DCTL_CGNPINNAK
;
2085 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
2090 if (dctl
& DCTL_GOUTNAKSTS
) {
2091 dctl
|= DCTL_CGOUTNAK
;
2092 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);
2095 if (!hs_ep
->isochronous
)
2098 if (list_empty(&hs_ep
->queue
)) {
2099 dev_dbg(hsotg
->dev
, "%s: complete_ep 0x%p, ep->queue empty!\n",
2105 hs_req
= get_ep_head(hs_ep
);
2107 dwc2_hsotg_complete_request(hsotg
, hs_ep
, hs_req
,
2109 dwc2_gadget_incr_frame_num(hs_ep
);
2110 } while (dwc2_gadget_target_frame_elapsed(hs_ep
));
2112 dwc2_gadget_start_next_request(hs_ep
);
2116 * dwc2_gadget_handle_out_token_ep_disabled - handle DXEPINT_OUTTKNEPDIS
2117 * @hs_ep: The endpoint on which interrupt is asserted.
2119 * This is starting point for ISOC-OUT transfer, synchronization done with
2120 * first out token received from host while corresponding EP is disabled.
2122 * Device does not know initial frame in which out token will come. For this
2123 * HW generates OUTTKNEPDIS - out token is received while EP is disabled. Upon
2124 * getting this interrupt SW starts calculation for next transfer frame.
2126 static void dwc2_gadget_handle_out_token_ep_disabled(struct dwc2_hsotg_ep
*ep
)
2128 struct dwc2_hsotg
*hsotg
= ep
->parent
;
2129 int dir_in
= ep
->dir_in
;
2132 if (dir_in
|| !ep
->isochronous
)
2135 dwc2_hsotg_complete_request(hsotg
, ep
, get_ep_head(ep
), -ENODATA
);
2137 if (ep
->interval
> 1 &&
2138 ep
->target_frame
== TARGET_FRAME_INITIAL
) {
2142 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
2143 ep
->target_frame
= dwc2_hsotg_read_frameno(hsotg
);
2144 dwc2_gadget_incr_frame_num(ep
);
2146 ctrl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(ep
->index
));
2147 if (ep
->target_frame
& 0x1)
2148 ctrl
|= DXEPCTL_SETODDFR
;
2150 ctrl
|= DXEPCTL_SETEVENFR
;
2152 dwc2_writel(ctrl
, hsotg
->regs
+ DOEPCTL(ep
->index
));
2155 dwc2_gadget_start_next_request(ep
);
2156 doepmsk
= dwc2_readl(hsotg
->regs
+ DOEPMSK
);
2157 doepmsk
&= ~DOEPMSK_OUTTKNEPDISMSK
;
2158 dwc2_writel(doepmsk
, hsotg
->regs
+ DOEPMSK
);
2162 * dwc2_gadget_handle_nak - handle NAK interrupt
2163 * @hs_ep: The endpoint on which interrupt is asserted.
2165 * This is starting point for ISOC-IN transfer, synchronization done with
2166 * first IN token received from host while corresponding EP is disabled.
2168 * Device does not know when first one token will arrive from host. On first
2169 * token arrival HW generates 2 interrupts: 'in token received while FIFO empty'
2170 * and 'NAK'. NAK interrupt for ISOC-IN means that token has arrived and ZLP was
2171 * sent in response to that as there was no data in FIFO. SW is basing on this
2172 * interrupt to obtain frame in which token has come and then based on the
2173 * interval calculates next frame for transfer.
2175 static void dwc2_gadget_handle_nak(struct dwc2_hsotg_ep
*hs_ep
)
2177 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2178 int dir_in
= hs_ep
->dir_in
;
2180 if (!dir_in
|| !hs_ep
->isochronous
)
2183 if (hs_ep
->target_frame
== TARGET_FRAME_INITIAL
) {
2184 hs_ep
->target_frame
= dwc2_hsotg_read_frameno(hsotg
);
2185 if (hs_ep
->interval
> 1) {
2186 u32 ctrl
= dwc2_readl(hsotg
->regs
+
2187 DIEPCTL(hs_ep
->index
));
2188 if (hs_ep
->target_frame
& 0x1)
2189 ctrl
|= DXEPCTL_SETODDFR
;
2191 ctrl
|= DXEPCTL_SETEVENFR
;
2193 dwc2_writel(ctrl
, hsotg
->regs
+ DIEPCTL(hs_ep
->index
));
2196 dwc2_hsotg_complete_request(hsotg
, hs_ep
,
2197 get_ep_head(hs_ep
), 0);
2200 dwc2_gadget_incr_frame_num(hs_ep
);
2204 * dwc2_hsotg_epint - handle an in/out endpoint interrupt
2205 * @hsotg: The driver state
2206 * @idx: The index for the endpoint (0..15)
2207 * @dir_in: Set if this is an IN endpoint
2209 * Process and clear any interrupt pending for an individual endpoint
2211 static void dwc2_hsotg_epint(struct dwc2_hsotg
*hsotg
, unsigned int idx
,
2214 struct dwc2_hsotg_ep
*hs_ep
= index_to_ep(hsotg
, idx
, dir_in
);
2215 u32 epint_reg
= dir_in
? DIEPINT(idx
) : DOEPINT(idx
);
2216 u32 epctl_reg
= dir_in
? DIEPCTL(idx
) : DOEPCTL(idx
);
2217 u32 epsiz_reg
= dir_in
? DIEPTSIZ(idx
) : DOEPTSIZ(idx
);
2221 ints
= dwc2_gadget_read_ep_interrupts(hsotg
, idx
, dir_in
);
2222 ctrl
= dwc2_readl(hsotg
->regs
+ epctl_reg
);
2224 /* Clear endpoint interrupts */
2225 dwc2_writel(ints
, hsotg
->regs
+ epint_reg
);
2228 dev_err(hsotg
->dev
, "%s:Interrupt for unconfigured ep%d(%s)\n",
2229 __func__
, idx
, dir_in
? "in" : "out");
2233 dev_dbg(hsotg
->dev
, "%s: ep%d(%s) DxEPINT=0x%08x\n",
2234 __func__
, idx
, dir_in
? "in" : "out", ints
);
2236 /* Don't process XferCompl interrupt if it is a setup packet */
2237 if (idx
== 0 && (ints
& (DXEPINT_SETUP
| DXEPINT_SETUP_RCVD
)))
2238 ints
&= ~DXEPINT_XFERCOMPL
;
2240 if (ints
& DXEPINT_STSPHSERCVD
)
2241 dev_dbg(hsotg
->dev
, "%s: StsPhseRcvd asserted\n", __func__
);
2243 if (ints
& DXEPINT_XFERCOMPL
) {
2245 "%s: XferCompl: DxEPCTL=0x%08x, DXEPTSIZ=%08x\n",
2246 __func__
, dwc2_readl(hsotg
->regs
+ epctl_reg
),
2247 dwc2_readl(hsotg
->regs
+ epsiz_reg
));
2250 * we get OutDone from the FIFO, so we only need to look
2251 * at completing IN requests here
2254 if (hs_ep
->isochronous
&& hs_ep
->interval
> 1)
2255 dwc2_gadget_incr_frame_num(hs_ep
);
2257 dwc2_hsotg_complete_in(hsotg
, hs_ep
);
2258 if (ints
& DXEPINT_NAKINTRPT
)
2259 ints
&= ~DXEPINT_NAKINTRPT
;
2261 if (idx
== 0 && !hs_ep
->req
)
2262 dwc2_hsotg_enqueue_setup(hsotg
);
2263 } else if (using_dma(hsotg
)) {
2265 * We're using DMA, we need to fire an OutDone here
2266 * as we ignore the RXFIFO.
2268 if (hs_ep
->isochronous
&& hs_ep
->interval
> 1)
2269 dwc2_gadget_incr_frame_num(hs_ep
);
2271 dwc2_hsotg_handle_outdone(hsotg
, idx
);
2275 if (ints
& DXEPINT_EPDISBLD
)
2276 dwc2_gadget_handle_ep_disabled(hs_ep
);
2278 if (ints
& DXEPINT_OUTTKNEPDIS
)
2279 dwc2_gadget_handle_out_token_ep_disabled(hs_ep
);
2281 if (ints
& DXEPINT_NAKINTRPT
)
2282 dwc2_gadget_handle_nak(hs_ep
);
2284 if (ints
& DXEPINT_AHBERR
)
2285 dev_dbg(hsotg
->dev
, "%s: AHBErr\n", __func__
);
2287 if (ints
& DXEPINT_SETUP
) { /* Setup or Timeout */
2288 dev_dbg(hsotg
->dev
, "%s: Setup/Timeout\n", __func__
);
2290 if (using_dma(hsotg
) && idx
== 0) {
2292 * this is the notification we've received a
2293 * setup packet. In non-DMA mode we'd get this
2294 * from the RXFIFO, instead we need to process
2301 dwc2_hsotg_handle_outdone(hsotg
, 0);
2305 if (ints
& DXEPINT_BACK2BACKSETUP
)
2306 dev_dbg(hsotg
->dev
, "%s: B2BSetup/INEPNakEff\n", __func__
);
2308 if (dir_in
&& !hs_ep
->isochronous
) {
2309 /* not sure if this is important, but we'll clear it anyway */
2310 if (ints
& DXEPINT_INTKNTXFEMP
) {
2311 dev_dbg(hsotg
->dev
, "%s: ep%d: INTknTXFEmpMsk\n",
2315 /* this probably means something bad is happening */
2316 if (ints
& DXEPINT_INTKNEPMIS
) {
2317 dev_warn(hsotg
->dev
, "%s: ep%d: INTknEP\n",
2321 /* FIFO has space or is empty (see GAHBCFG) */
2322 if (hsotg
->dedicated_fifos
&&
2323 ints
& DXEPINT_TXFEMP
) {
2324 dev_dbg(hsotg
->dev
, "%s: ep%d: TxFIFOEmpty\n",
2326 if (!using_dma(hsotg
))
2327 dwc2_hsotg_trytx(hsotg
, hs_ep
);
2333 * dwc2_hsotg_irq_enumdone - Handle EnumDone interrupt (enumeration done)
2334 * @hsotg: The device state.
2336 * Handle updating the device settings after the enumeration phase has
2339 static void dwc2_hsotg_irq_enumdone(struct dwc2_hsotg
*hsotg
)
2341 u32 dsts
= dwc2_readl(hsotg
->regs
+ DSTS
);
2342 int ep0_mps
= 0, ep_mps
= 8;
2345 * This should signal the finish of the enumeration phase
2346 * of the USB handshaking, so we should now know what rate
2350 dev_dbg(hsotg
->dev
, "EnumDone (DSTS=0x%08x)\n", dsts
);
2353 * note, since we're limited by the size of transfer on EP0, and
2354 * it seems IN transfers must be a even number of packets we do
2355 * not advertise a 64byte MPS on EP0.
2358 /* catch both EnumSpd_FS and EnumSpd_FS48 */
2359 switch ((dsts
& DSTS_ENUMSPD_MASK
) >> DSTS_ENUMSPD_SHIFT
) {
2360 case DSTS_ENUMSPD_FS
:
2361 case DSTS_ENUMSPD_FS48
:
2362 hsotg
->gadget
.speed
= USB_SPEED_FULL
;
2363 ep0_mps
= EP0_MPS_LIMIT
;
2367 case DSTS_ENUMSPD_HS
:
2368 hsotg
->gadget
.speed
= USB_SPEED_HIGH
;
2369 ep0_mps
= EP0_MPS_LIMIT
;
2373 case DSTS_ENUMSPD_LS
:
2374 hsotg
->gadget
.speed
= USB_SPEED_LOW
;
2376 * note, we don't actually support LS in this driver at the
2377 * moment, and the documentation seems to imply that it isn't
2378 * supported by the PHYs on some of the devices.
2382 dev_info(hsotg
->dev
, "new device is %s\n",
2383 usb_speed_string(hsotg
->gadget
.speed
));
2386 * we should now know the maximum packet size for an
2387 * endpoint, so set the endpoints to a default value.
2392 /* Initialize ep0 for both in and out directions */
2393 dwc2_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
, 1);
2394 dwc2_hsotg_set_ep_maxpacket(hsotg
, 0, ep0_mps
, 0);
2395 for (i
= 1; i
< hsotg
->num_of_eps
; i
++) {
2396 if (hsotg
->eps_in
[i
])
2397 dwc2_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
, 1);
2398 if (hsotg
->eps_out
[i
])
2399 dwc2_hsotg_set_ep_maxpacket(hsotg
, i
, ep_mps
, 0);
2403 /* ensure after enumeration our EP0 is active */
2405 dwc2_hsotg_enqueue_setup(hsotg
);
2407 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2408 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
2409 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
2413 * kill_all_requests - remove all requests from the endpoint's queue
2414 * @hsotg: The device state.
2415 * @ep: The endpoint the requests may be on.
2416 * @result: The result code to use.
2418 * Go through the requests on the given endpoint and mark them
2419 * completed with the given result code.
2421 static void kill_all_requests(struct dwc2_hsotg
*hsotg
,
2422 struct dwc2_hsotg_ep
*ep
,
2425 struct dwc2_hsotg_req
*req
, *treq
;
2430 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
)
2431 dwc2_hsotg_complete_request(hsotg
, ep
, req
,
2434 if (!hsotg
->dedicated_fifos
)
2436 size
= (dwc2_readl(hsotg
->regs
+ DTXFSTS(ep
->fifo_index
)) & 0xffff) * 4;
2437 if (size
< ep
->fifo_size
)
2438 dwc2_hsotg_txfifo_flush(hsotg
, ep
->fifo_index
);
2442 * dwc2_hsotg_disconnect - disconnect service
2443 * @hsotg: The device state.
2445 * The device has been disconnected. Remove all current
2446 * transactions and signal the gadget driver that this
2449 void dwc2_hsotg_disconnect(struct dwc2_hsotg
*hsotg
)
2453 if (!hsotg
->connected
)
2456 hsotg
->connected
= 0;
2457 hsotg
->test_mode
= 0;
2459 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++) {
2460 if (hsotg
->eps_in
[ep
])
2461 kill_all_requests(hsotg
, hsotg
->eps_in
[ep
],
2463 if (hsotg
->eps_out
[ep
])
2464 kill_all_requests(hsotg
, hsotg
->eps_out
[ep
],
2468 call_gadget(hsotg
, disconnect
);
2469 hsotg
->lx_state
= DWC2_L3
;
2473 * dwc2_hsotg_irq_fifoempty - TX FIFO empty interrupt handler
2474 * @hsotg: The device state:
2475 * @periodic: True if this is a periodic FIFO interrupt
2477 static void dwc2_hsotg_irq_fifoempty(struct dwc2_hsotg
*hsotg
, bool periodic
)
2479 struct dwc2_hsotg_ep
*ep
;
2482 /* look through for any more data to transmit */
2483 for (epno
= 0; epno
< hsotg
->num_of_eps
; epno
++) {
2484 ep
= index_to_ep(hsotg
, epno
, 1);
2492 if ((periodic
&& !ep
->periodic
) ||
2493 (!periodic
&& ep
->periodic
))
2496 ret
= dwc2_hsotg_trytx(hsotg
, ep
);
2502 /* IRQ flags which will trigger a retry around the IRQ loop */
2503 #define IRQ_RETRY_MASK (GINTSTS_NPTXFEMP | \
2508 * dwc2_hsotg_core_init - issue softreset to the core
2509 * @hsotg: The device state
2511 * Issue a soft reset to the core, and await the core finishing it.
2513 void dwc2_hsotg_core_init_disconnected(struct dwc2_hsotg
*hsotg
,
2520 /* Kill any ep0 requests as controller will be reinitialized */
2521 kill_all_requests(hsotg
, hsotg
->eps_out
[0], -ECONNRESET
);
2524 if (dwc2_core_reset(hsotg
))
2528 * we must now enable ep0 ready for host detection and then
2529 * set configuration.
2532 /* keep other bits untouched (so e.g. forced modes are not lost) */
2533 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
2534 usbcfg
&= ~(GUSBCFG_TOUTCAL_MASK
| GUSBCFG_PHYIF16
| GUSBCFG_SRPCAP
|
2537 /* set the PLL on, remove the HNP/SRP and set the PHY */
2538 val
= (hsotg
->phyif
== GUSBCFG_PHYIF8
) ? 9 : 5;
2539 usbcfg
|= hsotg
->phyif
| GUSBCFG_TOUTCAL(7) |
2540 (val
<< GUSBCFG_USBTRDTIM_SHIFT
);
2541 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
2543 dwc2_hsotg_init_fifo(hsotg
);
2546 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2548 dwc2_writel(DCFG_EPMISCNT(1) | DCFG_DEVSPD_HS
, hsotg
->regs
+ DCFG
);
2550 /* Clear any pending OTG interrupts */
2551 dwc2_writel(0xffffffff, hsotg
->regs
+ GOTGINT
);
2553 /* Clear any pending interrupts */
2554 dwc2_writel(0xffffffff, hsotg
->regs
+ GINTSTS
);
2555 intmsk
= GINTSTS_ERLYSUSP
| GINTSTS_SESSREQINT
|
2556 GINTSTS_GOUTNAKEFF
| GINTSTS_GINNAKEFF
|
2557 GINTSTS_USBRST
| GINTSTS_RESETDET
|
2558 GINTSTS_ENUMDONE
| GINTSTS_OTGINT
|
2559 GINTSTS_USBSUSP
| GINTSTS_WKUPINT
|
2560 GINTSTS_INCOMPL_SOIN
| GINTSTS_INCOMPL_SOOUT
;
2562 if (hsotg
->core_params
->external_id_pin_ctl
<= 0)
2563 intmsk
|= GINTSTS_CONIDSTSCHNG
;
2565 dwc2_writel(intmsk
, hsotg
->regs
+ GINTMSK
);
2567 if (using_dma(hsotg
))
2568 dwc2_writel(GAHBCFG_GLBL_INTR_EN
| GAHBCFG_DMA_EN
|
2569 (GAHBCFG_HBSTLEN_INCR4
<< GAHBCFG_HBSTLEN_SHIFT
),
2570 hsotg
->regs
+ GAHBCFG
);
2572 dwc2_writel(((hsotg
->dedicated_fifos
) ?
2573 (GAHBCFG_NP_TXF_EMP_LVL
|
2574 GAHBCFG_P_TXF_EMP_LVL
) : 0) |
2575 GAHBCFG_GLBL_INTR_EN
, hsotg
->regs
+ GAHBCFG
);
2578 * If INTknTXFEmpMsk is enabled, it's important to disable ep interrupts
2579 * when we have no data to transfer. Otherwise we get being flooded by
2583 dwc2_writel(((hsotg
->dedicated_fifos
&& !using_dma(hsotg
)) ?
2584 DIEPMSK_TXFIFOEMPTY
| DIEPMSK_INTKNTXFEMPMSK
: 0) |
2585 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
|
2586 DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
,
2587 hsotg
->regs
+ DIEPMSK
);
2590 * don't need XferCompl, we get that from RXFIFO in slave mode. In
2591 * DMA mode we may need this.
2593 dwc2_writel((using_dma(hsotg
) ? (DIEPMSK_XFERCOMPLMSK
) : 0) |
2594 DOEPMSK_EPDISBLDMSK
| DOEPMSK_AHBERRMSK
|
2595 DOEPMSK_SETUPMSK
| DOEPMSK_STSPHSERCVDMSK
,
2596 hsotg
->regs
+ DOEPMSK
);
2598 dwc2_writel(0, hsotg
->regs
+ DAINTMSK
);
2600 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2601 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
2602 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
2604 /* enable in and out endpoint interrupts */
2605 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_OEPINT
| GINTSTS_IEPINT
);
2608 * Enable the RXFIFO when in slave mode, as this is how we collect
2609 * the data. In DMA mode, we get events from the FIFO but also
2610 * things we cannot process, so do not use it.
2612 if (!using_dma(hsotg
))
2613 dwc2_hsotg_en_gsint(hsotg
, GINTSTS_RXFLVL
);
2615 /* Enable interrupts for EP0 in and out */
2616 dwc2_hsotg_ctrl_epint(hsotg
, 0, 0, 1);
2617 dwc2_hsotg_ctrl_epint(hsotg
, 0, 1, 1);
2619 if (!is_usb_reset
) {
2620 __orr32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
2621 udelay(10); /* see openiboot */
2622 __bic32(hsotg
->regs
+ DCTL
, DCTL_PWRONPRGDONE
);
2625 dev_dbg(hsotg
->dev
, "DCTL=0x%08x\n", dwc2_readl(hsotg
->regs
+ DCTL
));
2628 * DxEPCTL_USBActEp says RO in manual, but seems to be set by
2629 * writing to the EPCTL register..
2632 /* set to read 1 8byte packet */
2633 dwc2_writel(DXEPTSIZ_MC(1) | DXEPTSIZ_PKTCNT(1) |
2634 DXEPTSIZ_XFERSIZE(8), hsotg
->regs
+ DOEPTSIZ0
);
2636 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg
->eps_out
[0]->ep
.maxpacket
) |
2637 DXEPCTL_CNAK
| DXEPCTL_EPENA
|
2639 hsotg
->regs
+ DOEPCTL0
);
2641 /* enable, but don't activate EP0in */
2642 dwc2_writel(dwc2_hsotg_ep0_mps(hsotg
->eps_out
[0]->ep
.maxpacket
) |
2643 DXEPCTL_USBACTEP
, hsotg
->regs
+ DIEPCTL0
);
2645 dwc2_hsotg_enqueue_setup(hsotg
);
2647 dev_dbg(hsotg
->dev
, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
2648 dwc2_readl(hsotg
->regs
+ DIEPCTL0
),
2649 dwc2_readl(hsotg
->regs
+ DOEPCTL0
));
2651 /* clear global NAKs */
2652 val
= DCTL_CGOUTNAK
| DCTL_CGNPINNAK
;
2654 val
|= DCTL_SFTDISCON
;
2655 __orr32(hsotg
->regs
+ DCTL
, val
);
2657 /* must be at-least 3ms to allow bus to see disconnect */
2660 hsotg
->lx_state
= DWC2_L0
;
2663 static void dwc2_hsotg_core_disconnect(struct dwc2_hsotg
*hsotg
)
2665 /* set the soft-disconnect bit */
2666 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2669 void dwc2_hsotg_core_connect(struct dwc2_hsotg
*hsotg
)
2671 /* remove the soft-disconnect and let's go */
2672 __bic32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
2676 * dwc2_gadget_handle_incomplete_isoc_in - handle incomplete ISO IN Interrupt.
2677 * @hsotg: The device state:
2679 * This interrupt indicates one of the following conditions occurred while
2680 * transmitting an ISOC transaction.
2681 * - Corrupted IN Token for ISOC EP.
2682 * - Packet not complete in FIFO.
2684 * The following actions will be taken:
2685 * - Determine the EP
2686 * - Disable EP; when 'Endpoint Disabled' interrupt is received Flush FIFO
2688 static void dwc2_gadget_handle_incomplete_isoc_in(struct dwc2_hsotg
*hsotg
)
2690 struct dwc2_hsotg_ep
*hs_ep
;
2694 dev_dbg(hsotg
->dev
, "Incomplete isoc in interrupt received:\n");
2696 for (idx
= 1; idx
<= hsotg
->num_of_eps
; idx
++) {
2697 hs_ep
= hsotg
->eps_in
[idx
];
2698 epctrl
= dwc2_readl(hsotg
->regs
+ DIEPCTL(idx
));
2699 if ((epctrl
& DXEPCTL_EPENA
) && hs_ep
->isochronous
&&
2700 dwc2_gadget_target_frame_elapsed(hs_ep
)) {
2701 epctrl
|= DXEPCTL_SNAK
;
2702 epctrl
|= DXEPCTL_EPDIS
;
2703 dwc2_writel(epctrl
, hsotg
->regs
+ DIEPCTL(idx
));
2707 /* Clear interrupt */
2708 dwc2_writel(GINTSTS_INCOMPL_SOIN
, hsotg
->regs
+ GINTSTS
);
2712 * dwc2_gadget_handle_incomplete_isoc_out - handle incomplete ISO OUT Interrupt
2713 * @hsotg: The device state:
2715 * This interrupt indicates one of the following conditions occurred while
2716 * transmitting an ISOC transaction.
2717 * - Corrupted OUT Token for ISOC EP.
2718 * - Packet not complete in FIFO.
2720 * The following actions will be taken:
2721 * - Determine the EP
2722 * - Set DCTL_SGOUTNAK and unmask GOUTNAKEFF if target frame elapsed.
2724 static void dwc2_gadget_handle_incomplete_isoc_out(struct dwc2_hsotg
*hsotg
)
2729 struct dwc2_hsotg_ep
*hs_ep
;
2732 dev_dbg(hsotg
->dev
, "%s: GINTSTS_INCOMPL_SOOUT\n", __func__
);
2734 for (idx
= 1; idx
<= hsotg
->num_of_eps
; idx
++) {
2735 hs_ep
= hsotg
->eps_out
[idx
];
2736 epctrl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(idx
));
2737 if ((epctrl
& DXEPCTL_EPENA
) && hs_ep
->isochronous
&&
2738 dwc2_gadget_target_frame_elapsed(hs_ep
)) {
2739 /* Unmask GOUTNAKEFF interrupt */
2740 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
2741 gintmsk
|= GINTSTS_GOUTNAKEFF
;
2742 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
2744 gintsts
= dwc2_readl(hsotg
->regs
+ GINTSTS
);
2745 if (!(gintsts
& GINTSTS_GOUTNAKEFF
))
2746 __orr32(hsotg
->regs
+ DCTL
, DCTL_SGOUTNAK
);
2750 /* Clear interrupt */
2751 dwc2_writel(GINTSTS_INCOMPL_SOOUT
, hsotg
->regs
+ GINTSTS
);
2755 * dwc2_hsotg_irq - handle device interrupt
2756 * @irq: The IRQ number triggered
2757 * @pw: The pw value when registered the handler.
2759 static irqreturn_t
dwc2_hsotg_irq(int irq
, void *pw
)
2761 struct dwc2_hsotg
*hsotg
= pw
;
2762 int retry_count
= 8;
2766 if (!dwc2_is_device_mode(hsotg
))
2769 spin_lock(&hsotg
->lock
);
2771 gintsts
= dwc2_readl(hsotg
->regs
+ GINTSTS
);
2772 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
2774 dev_dbg(hsotg
->dev
, "%s: %08x %08x (%08x) retry %d\n",
2775 __func__
, gintsts
, gintsts
& gintmsk
, gintmsk
, retry_count
);
2779 if (gintsts
& GINTSTS_RESETDET
) {
2780 dev_dbg(hsotg
->dev
, "%s: USBRstDet\n", __func__
);
2782 dwc2_writel(GINTSTS_RESETDET
, hsotg
->regs
+ GINTSTS
);
2784 /* This event must be used only if controller is suspended */
2785 if (hsotg
->lx_state
== DWC2_L2
) {
2786 dwc2_exit_hibernation(hsotg
, true);
2787 hsotg
->lx_state
= DWC2_L0
;
2791 if (gintsts
& (GINTSTS_USBRST
| GINTSTS_RESETDET
)) {
2793 u32 usb_status
= dwc2_readl(hsotg
->regs
+ GOTGCTL
);
2794 u32 connected
= hsotg
->connected
;
2796 dev_dbg(hsotg
->dev
, "%s: USBRst\n", __func__
);
2797 dev_dbg(hsotg
->dev
, "GNPTXSTS=%08x\n",
2798 dwc2_readl(hsotg
->regs
+ GNPTXSTS
));
2800 dwc2_writel(GINTSTS_USBRST
, hsotg
->regs
+ GINTSTS
);
2802 /* Report disconnection if it is not already done. */
2803 dwc2_hsotg_disconnect(hsotg
);
2805 if (usb_status
& GOTGCTL_BSESVLD
&& connected
)
2806 dwc2_hsotg_core_init_disconnected(hsotg
, true);
2809 if (gintsts
& GINTSTS_ENUMDONE
) {
2810 dwc2_writel(GINTSTS_ENUMDONE
, hsotg
->regs
+ GINTSTS
);
2812 dwc2_hsotg_irq_enumdone(hsotg
);
2815 if (gintsts
& (GINTSTS_OEPINT
| GINTSTS_IEPINT
)) {
2816 u32 daint
= dwc2_readl(hsotg
->regs
+ DAINT
);
2817 u32 daintmsk
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
2818 u32 daint_out
, daint_in
;
2822 daint_out
= daint
>> DAINT_OUTEP_SHIFT
;
2823 daint_in
= daint
& ~(daint_out
<< DAINT_OUTEP_SHIFT
);
2825 dev_dbg(hsotg
->dev
, "%s: daint=%08x\n", __func__
, daint
);
2827 for (ep
= 0; ep
< hsotg
->num_of_eps
&& daint_out
;
2828 ep
++, daint_out
>>= 1) {
2830 dwc2_hsotg_epint(hsotg
, ep
, 0);
2833 for (ep
= 0; ep
< hsotg
->num_of_eps
&& daint_in
;
2834 ep
++, daint_in
>>= 1) {
2836 dwc2_hsotg_epint(hsotg
, ep
, 1);
2840 /* check both FIFOs */
2842 if (gintsts
& GINTSTS_NPTXFEMP
) {
2843 dev_dbg(hsotg
->dev
, "NPTxFEmp\n");
2846 * Disable the interrupt to stop it happening again
2847 * unless one of these endpoint routines decides that
2848 * it needs re-enabling
2851 dwc2_hsotg_disable_gsint(hsotg
, GINTSTS_NPTXFEMP
);
2852 dwc2_hsotg_irq_fifoempty(hsotg
, false);
2855 if (gintsts
& GINTSTS_PTXFEMP
) {
2856 dev_dbg(hsotg
->dev
, "PTxFEmp\n");
2858 /* See note in GINTSTS_NPTxFEmp */
2860 dwc2_hsotg_disable_gsint(hsotg
, GINTSTS_PTXFEMP
);
2861 dwc2_hsotg_irq_fifoempty(hsotg
, true);
2864 if (gintsts
& GINTSTS_RXFLVL
) {
2866 * note, since GINTSTS_RxFLvl doubles as FIFO-not-empty,
2867 * we need to retry dwc2_hsotg_handle_rx if this is still
2871 dwc2_hsotg_handle_rx(hsotg
);
2874 if (gintsts
& GINTSTS_ERLYSUSP
) {
2875 dev_dbg(hsotg
->dev
, "GINTSTS_ErlySusp\n");
2876 dwc2_writel(GINTSTS_ERLYSUSP
, hsotg
->regs
+ GINTSTS
);
2880 * these next two seem to crop-up occasionally causing the core
2881 * to shutdown the USB transfer, so try clearing them and logging
2885 if (gintsts
& GINTSTS_GOUTNAKEFF
) {
2889 struct dwc2_hsotg_ep
*hs_ep
;
2891 /* Mask this interrupt */
2892 gintmsk
= dwc2_readl(hsotg
->regs
+ GINTMSK
);
2893 gintmsk
&= ~GINTSTS_GOUTNAKEFF
;
2894 dwc2_writel(gintmsk
, hsotg
->regs
+ GINTMSK
);
2896 dev_dbg(hsotg
->dev
, "GOUTNakEff triggered\n");
2897 for (idx
= 1; idx
<= hsotg
->num_of_eps
; idx
++) {
2898 hs_ep
= hsotg
->eps_out
[idx
];
2899 epctrl
= dwc2_readl(hsotg
->regs
+ DOEPCTL(idx
));
2901 if ((epctrl
& DXEPCTL_EPENA
) && hs_ep
->isochronous
) {
2902 epctrl
|= DXEPCTL_SNAK
;
2903 epctrl
|= DXEPCTL_EPDIS
;
2904 dwc2_writel(epctrl
, hsotg
->regs
+ DOEPCTL(idx
));
2908 /* This interrupt bit is cleared in DXEPINT_EPDISBLD handler */
2911 if (gintsts
& GINTSTS_GINNAKEFF
) {
2912 dev_info(hsotg
->dev
, "GINNakEff triggered\n");
2914 __orr32(hsotg
->regs
+ DCTL
, DCTL_CGNPINNAK
);
2916 dwc2_hsotg_dump(hsotg
);
2919 if (gintsts
& GINTSTS_INCOMPL_SOIN
)
2920 dwc2_gadget_handle_incomplete_isoc_in(hsotg
);
2922 if (gintsts
& GINTSTS_INCOMPL_SOOUT
)
2923 dwc2_gadget_handle_incomplete_isoc_out(hsotg
);
2926 * if we've had fifo events, we should try and go around the
2927 * loop again to see if there's any point in returning yet.
2930 if (gintsts
& IRQ_RETRY_MASK
&& --retry_count
> 0)
2933 spin_unlock(&hsotg
->lock
);
2939 * dwc2_hsotg_ep_enable - enable the given endpoint
2940 * @ep: The USB endpint to configure
2941 * @desc: The USB endpoint descriptor to configure with.
2943 * This is called from the USB gadget code's usb_ep_enable().
2945 static int dwc2_hsotg_ep_enable(struct usb_ep
*ep
,
2946 const struct usb_endpoint_descriptor
*desc
)
2948 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
2949 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
2950 unsigned long flags
;
2951 unsigned int index
= hs_ep
->index
;
2956 unsigned int dir_in
;
2957 unsigned int i
, val
, size
;
2961 "%s: ep %s: a 0x%02x, attr 0x%02x, mps 0x%04x, intr %d\n",
2962 __func__
, ep
->name
, desc
->bEndpointAddress
, desc
->bmAttributes
,
2963 desc
->wMaxPacketSize
, desc
->bInterval
);
2965 /* not to be called for EP0 */
2967 dev_err(hsotg
->dev
, "%s: called for EP 0\n", __func__
);
2971 dir_in
= (desc
->bEndpointAddress
& USB_ENDPOINT_DIR_MASK
) ? 1 : 0;
2972 if (dir_in
!= hs_ep
->dir_in
) {
2973 dev_err(hsotg
->dev
, "%s: direction mismatch!\n", __func__
);
2977 mps
= usb_endpoint_maxp(desc
);
2979 /* note, we handle this here instead of dwc2_hsotg_set_ep_maxpacket */
2981 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
2982 epctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
2984 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x from 0x%08x\n",
2985 __func__
, epctrl
, epctrl_reg
);
2987 spin_lock_irqsave(&hsotg
->lock
, flags
);
2989 epctrl
&= ~(DXEPCTL_EPTYPE_MASK
| DXEPCTL_MPS_MASK
);
2990 epctrl
|= DXEPCTL_MPS(mps
);
2993 * mark the endpoint as active, otherwise the core may ignore
2994 * transactions entirely for this endpoint
2996 epctrl
|= DXEPCTL_USBACTEP
;
2998 /* update the endpoint state */
2999 dwc2_hsotg_set_ep_maxpacket(hsotg
, hs_ep
->index
, mps
, dir_in
);
3001 /* default, set to non-periodic */
3002 hs_ep
->isochronous
= 0;
3003 hs_ep
->periodic
= 0;
3005 hs_ep
->interval
= desc
->bInterval
;
3007 switch (desc
->bmAttributes
& USB_ENDPOINT_XFERTYPE_MASK
) {
3008 case USB_ENDPOINT_XFER_ISOC
:
3009 epctrl
|= DXEPCTL_EPTYPE_ISO
;
3010 epctrl
|= DXEPCTL_SETEVENFR
;
3011 hs_ep
->isochronous
= 1;
3012 hs_ep
->interval
= 1 << (desc
->bInterval
- 1);
3013 hs_ep
->target_frame
= TARGET_FRAME_INITIAL
;
3015 hs_ep
->periodic
= 1;
3016 mask
= dwc2_readl(hsotg
->regs
+ DIEPMSK
);
3017 mask
|= DIEPMSK_NAKMSK
;
3018 dwc2_writel(mask
, hsotg
->regs
+ DIEPMSK
);
3020 mask
= dwc2_readl(hsotg
->regs
+ DOEPMSK
);
3021 mask
|= DOEPMSK_OUTTKNEPDISMSK
;
3022 dwc2_writel(mask
, hsotg
->regs
+ DOEPMSK
);
3026 case USB_ENDPOINT_XFER_BULK
:
3027 epctrl
|= DXEPCTL_EPTYPE_BULK
;
3030 case USB_ENDPOINT_XFER_INT
:
3032 hs_ep
->periodic
= 1;
3034 if (hsotg
->gadget
.speed
== USB_SPEED_HIGH
)
3035 hs_ep
->interval
= 1 << (desc
->bInterval
- 1);
3037 epctrl
|= DXEPCTL_EPTYPE_INTERRUPT
;
3040 case USB_ENDPOINT_XFER_CONTROL
:
3041 epctrl
|= DXEPCTL_EPTYPE_CONTROL
;
3046 * if the hardware has dedicated fifos, we must give each IN EP
3047 * a unique tx-fifo even if it is non-periodic.
3049 if (dir_in
&& hsotg
->dedicated_fifos
) {
3051 u32 fifo_size
= UINT_MAX
;
3052 size
= hs_ep
->ep
.maxpacket
*hs_ep
->mc
;
3053 for (i
= 1; i
< hsotg
->num_of_eps
; ++i
) {
3054 if (hsotg
->fifo_map
& (1<<i
))
3056 val
= dwc2_readl(hsotg
->regs
+ DPTXFSIZN(i
));
3057 val
= (val
>> FIFOSIZE_DEPTH_SHIFT
)*4;
3060 /* Search for smallest acceptable fifo */
3061 if (val
< fifo_size
) {
3068 "%s: No suitable fifo found\n", __func__
);
3072 hsotg
->fifo_map
|= 1 << fifo_index
;
3073 epctrl
|= DXEPCTL_TXFNUM(fifo_index
);
3074 hs_ep
->fifo_index
= fifo_index
;
3075 hs_ep
->fifo_size
= fifo_size
;
3078 /* for non control endpoints, set PID to D0 */
3079 if (index
&& !hs_ep
->isochronous
)
3080 epctrl
|= DXEPCTL_SETD0PID
;
3082 dev_dbg(hsotg
->dev
, "%s: write DxEPCTL=0x%08x\n",
3085 dwc2_writel(epctrl
, hsotg
->regs
+ epctrl_reg
);
3086 dev_dbg(hsotg
->dev
, "%s: read DxEPCTL=0x%08x\n",
3087 __func__
, dwc2_readl(hsotg
->regs
+ epctrl_reg
));
3089 /* enable the endpoint interrupt */
3090 dwc2_hsotg_ctrl_epint(hsotg
, index
, dir_in
, 1);
3093 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3098 * dwc2_hsotg_ep_disable - disable given endpoint
3099 * @ep: The endpoint to disable.
3101 static int dwc2_hsotg_ep_disable(struct usb_ep
*ep
)
3103 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
3104 struct dwc2_hsotg
*hsotg
= hs_ep
->parent
;
3105 int dir_in
= hs_ep
->dir_in
;
3106 int index
= hs_ep
->index
;
3107 unsigned long flags
;
3111 dev_dbg(hsotg
->dev
, "%s(ep %p)\n", __func__
, ep
);
3113 if (ep
== &hsotg
->eps_out
[0]->ep
) {
3114 dev_err(hsotg
->dev
, "%s: called for ep0\n", __func__
);
3118 epctrl_reg
= dir_in
? DIEPCTL(index
) : DOEPCTL(index
);
3120 spin_lock_irqsave(&hsotg
->lock
, flags
);
3122 ctrl
= dwc2_readl(hsotg
->regs
+ epctrl_reg
);
3123 ctrl
&= ~DXEPCTL_EPENA
;
3124 ctrl
&= ~DXEPCTL_USBACTEP
;
3125 ctrl
|= DXEPCTL_SNAK
;
3127 dev_dbg(hsotg
->dev
, "%s: DxEPCTL=0x%08x\n", __func__
, ctrl
);
3128 dwc2_writel(ctrl
, hsotg
->regs
+ epctrl_reg
);
3130 /* disable endpoint interrupts */
3131 dwc2_hsotg_ctrl_epint(hsotg
, hs_ep
->index
, hs_ep
->dir_in
, 0);
3133 /* terminate all requests with shutdown */
3134 kill_all_requests(hsotg
, hs_ep
, -ESHUTDOWN
);
3136 hsotg
->fifo_map
&= ~(1 << hs_ep
->fifo_index
);
3137 hs_ep
->fifo_index
= 0;
3138 hs_ep
->fifo_size
= 0;
3140 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3145 * on_list - check request is on the given endpoint
3146 * @ep: The endpoint to check.
3147 * @test: The request to test if it is on the endpoint.
3149 static bool on_list(struct dwc2_hsotg_ep
*ep
, struct dwc2_hsotg_req
*test
)
3151 struct dwc2_hsotg_req
*req
, *treq
;
3153 list_for_each_entry_safe(req
, treq
, &ep
->queue
, queue
) {
3161 static int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg
*hs_otg
, u32 reg
,
3162 u32 bit
, u32 timeout
)
3166 for (i
= 0; i
< timeout
; i
++) {
3167 if (dwc2_readl(hs_otg
->regs
+ reg
) & bit
)
3175 static void dwc2_hsotg_ep_stop_xfr(struct dwc2_hsotg
*hsotg
,
3176 struct dwc2_hsotg_ep
*hs_ep
)
3181 epctrl_reg
= hs_ep
->dir_in
? DIEPCTL(hs_ep
->index
) :
3182 DOEPCTL(hs_ep
->index
);
3183 epint_reg
= hs_ep
->dir_in
? DIEPINT(hs_ep
->index
) :
3184 DOEPINT(hs_ep
->index
);
3186 dev_dbg(hsotg
->dev
, "%s: stopping transfer on %s\n", __func__
,
3188 if (hs_ep
->dir_in
) {
3189 __orr32(hsotg
->regs
+ epctrl_reg
, DXEPCTL_SNAK
);
3190 /* Wait for Nak effect */
3191 if (dwc2_hsotg_wait_bit_set(hsotg
, epint_reg
,
3192 DXEPINT_INEPNAKEFF
, 100))
3193 dev_warn(hsotg
->dev
,
3194 "%s: timeout DIEPINT.NAKEFF\n", __func__
);
3196 if (!(dwc2_readl(hsotg
->regs
+ GINTSTS
) & GINTSTS_GOUTNAKEFF
))
3197 __orr32(hsotg
->regs
+ DCTL
, DCTL_SGOUTNAK
);
3199 /* Wait for global nak to take effect */
3200 if (dwc2_hsotg_wait_bit_set(hsotg
, GINTSTS
,
3201 GINTSTS_GOUTNAKEFF
, 100))
3202 dev_warn(hsotg
->dev
,
3203 "%s: timeout GINTSTS.GOUTNAKEFF\n", __func__
);
3207 __orr32(hsotg
->regs
+ epctrl_reg
, DXEPCTL_EPDIS
| DXEPCTL_SNAK
);
3209 /* Wait for ep to be disabled */
3210 if (dwc2_hsotg_wait_bit_set(hsotg
, epint_reg
, DXEPINT_EPDISBLD
, 100))
3211 dev_warn(hsotg
->dev
,
3212 "%s: timeout DOEPCTL.EPDisable\n", __func__
);
3214 if (hs_ep
->dir_in
) {
3215 if (hsotg
->dedicated_fifos
) {
3216 dwc2_writel(GRSTCTL_TXFNUM(hs_ep
->fifo_index
) |
3217 GRSTCTL_TXFFLSH
, hsotg
->regs
+ GRSTCTL
);
3218 /* Wait for fifo flush */
3219 if (dwc2_hsotg_wait_bit_set(hsotg
, GRSTCTL
,
3220 GRSTCTL_TXFFLSH
, 100))
3221 dev_warn(hsotg
->dev
,
3222 "%s: timeout flushing fifos\n",
3225 /* TODO: Flush shared tx fifo */
3227 /* Remove global NAKs */
3228 __bic32(hsotg
->regs
+ DCTL
, DCTL_SGOUTNAK
);
3233 * dwc2_hsotg_ep_dequeue - dequeue given endpoint
3234 * @ep: The endpoint to dequeue.
3235 * @req: The request to be removed from a queue.
3237 static int dwc2_hsotg_ep_dequeue(struct usb_ep
*ep
, struct usb_request
*req
)
3239 struct dwc2_hsotg_req
*hs_req
= our_req(req
);
3240 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
3241 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
3242 unsigned long flags
;
3244 dev_dbg(hs
->dev
, "ep_dequeue(%p,%p)\n", ep
, req
);
3246 spin_lock_irqsave(&hs
->lock
, flags
);
3248 if (!on_list(hs_ep
, hs_req
)) {
3249 spin_unlock_irqrestore(&hs
->lock
, flags
);
3253 /* Dequeue already started request */
3254 if (req
== &hs_ep
->req
->req
)
3255 dwc2_hsotg_ep_stop_xfr(hs
, hs_ep
);
3257 dwc2_hsotg_complete_request(hs
, hs_ep
, hs_req
, -ECONNRESET
);
3258 spin_unlock_irqrestore(&hs
->lock
, flags
);
3264 * dwc2_hsotg_ep_sethalt - set halt on a given endpoint
3265 * @ep: The endpoint to set halt.
3266 * @value: Set or unset the halt.
3267 * @now: If true, stall the endpoint now. Otherwise return -EAGAIN if
3268 * the endpoint is busy processing requests.
3270 * We need to stall the endpoint immediately if request comes from set_feature
3271 * protocol command handler.
3273 static int dwc2_hsotg_ep_sethalt(struct usb_ep
*ep
, int value
, bool now
)
3275 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
3276 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
3277 int index
= hs_ep
->index
;
3282 dev_info(hs
->dev
, "%s(ep %p %s, %d)\n", __func__
, ep
, ep
->name
, value
);
3286 dwc2_hsotg_stall_ep0(hs
);
3289 "%s: can't clear halt on ep0\n", __func__
);
3293 if (hs_ep
->isochronous
) {
3294 dev_err(hs
->dev
, "%s is Isochronous Endpoint\n", ep
->name
);
3298 if (!now
&& value
&& !list_empty(&hs_ep
->queue
)) {
3299 dev_dbg(hs
->dev
, "%s request is pending, cannot halt\n",
3304 if (hs_ep
->dir_in
) {
3305 epreg
= DIEPCTL(index
);
3306 epctl
= dwc2_readl(hs
->regs
+ epreg
);
3309 epctl
|= DXEPCTL_STALL
| DXEPCTL_SNAK
;
3310 if (epctl
& DXEPCTL_EPENA
)
3311 epctl
|= DXEPCTL_EPDIS
;
3313 epctl
&= ~DXEPCTL_STALL
;
3314 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
3315 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
3316 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
3317 epctl
|= DXEPCTL_SETD0PID
;
3319 dwc2_writel(epctl
, hs
->regs
+ epreg
);
3322 epreg
= DOEPCTL(index
);
3323 epctl
= dwc2_readl(hs
->regs
+ epreg
);
3326 epctl
|= DXEPCTL_STALL
;
3328 epctl
&= ~DXEPCTL_STALL
;
3329 xfertype
= epctl
& DXEPCTL_EPTYPE_MASK
;
3330 if (xfertype
== DXEPCTL_EPTYPE_BULK
||
3331 xfertype
== DXEPCTL_EPTYPE_INTERRUPT
)
3332 epctl
|= DXEPCTL_SETD0PID
;
3334 dwc2_writel(epctl
, hs
->regs
+ epreg
);
3337 hs_ep
->halted
= value
;
3343 * dwc2_hsotg_ep_sethalt_lock - set halt on a given endpoint with lock held
3344 * @ep: The endpoint to set halt.
3345 * @value: Set or unset the halt.
3347 static int dwc2_hsotg_ep_sethalt_lock(struct usb_ep
*ep
, int value
)
3349 struct dwc2_hsotg_ep
*hs_ep
= our_ep(ep
);
3350 struct dwc2_hsotg
*hs
= hs_ep
->parent
;
3351 unsigned long flags
= 0;
3354 spin_lock_irqsave(&hs
->lock
, flags
);
3355 ret
= dwc2_hsotg_ep_sethalt(ep
, value
, false);
3356 spin_unlock_irqrestore(&hs
->lock
, flags
);
3361 static struct usb_ep_ops dwc2_hsotg_ep_ops
= {
3362 .enable
= dwc2_hsotg_ep_enable
,
3363 .disable
= dwc2_hsotg_ep_disable
,
3364 .alloc_request
= dwc2_hsotg_ep_alloc_request
,
3365 .free_request
= dwc2_hsotg_ep_free_request
,
3366 .queue
= dwc2_hsotg_ep_queue_lock
,
3367 .dequeue
= dwc2_hsotg_ep_dequeue
,
3368 .set_halt
= dwc2_hsotg_ep_sethalt_lock
,
3369 /* note, don't believe we have any call for the fifo routines */
3373 * dwc2_hsotg_init - initalize the usb core
3374 * @hsotg: The driver state
3376 static void dwc2_hsotg_init(struct dwc2_hsotg
*hsotg
)
3380 /* unmask subset of endpoint interrupts */
3382 dwc2_writel(DIEPMSK_TIMEOUTMSK
| DIEPMSK_AHBERRMSK
|
3383 DIEPMSK_EPDISBLDMSK
| DIEPMSK_XFERCOMPLMSK
,
3384 hsotg
->regs
+ DIEPMSK
);
3386 dwc2_writel(DOEPMSK_SETUPMSK
| DOEPMSK_AHBERRMSK
|
3387 DOEPMSK_EPDISBLDMSK
| DOEPMSK_XFERCOMPLMSK
,
3388 hsotg
->regs
+ DOEPMSK
);
3390 dwc2_writel(0, hsotg
->regs
+ DAINTMSK
);
3392 /* Be in disconnected state until gadget is registered */
3393 __orr32(hsotg
->regs
+ DCTL
, DCTL_SFTDISCON
);
3397 dev_dbg(hsotg
->dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3398 dwc2_readl(hsotg
->regs
+ GRXFSIZ
),
3399 dwc2_readl(hsotg
->regs
+ GNPTXFSIZ
));
3401 dwc2_hsotg_init_fifo(hsotg
);
3403 /* keep other bits untouched (so e.g. forced modes are not lost) */
3404 usbcfg
= dwc2_readl(hsotg
->regs
+ GUSBCFG
);
3405 usbcfg
&= ~(GUSBCFG_TOUTCAL_MASK
| GUSBCFG_PHYIF16
| GUSBCFG_SRPCAP
|
3408 /* set the PLL on, remove the HNP/SRP and set the PHY */
3409 trdtim
= (hsotg
->phyif
== GUSBCFG_PHYIF8
) ? 9 : 5;
3410 usbcfg
|= hsotg
->phyif
| GUSBCFG_TOUTCAL(7) |
3411 (trdtim
<< GUSBCFG_USBTRDTIM_SHIFT
);
3412 dwc2_writel(usbcfg
, hsotg
->regs
+ GUSBCFG
);
3414 if (using_dma(hsotg
))
3415 __orr32(hsotg
->regs
+ GAHBCFG
, GAHBCFG_DMA_EN
);
3419 * dwc2_hsotg_udc_start - prepare the udc for work
3420 * @gadget: The usb gadget state
3421 * @driver: The usb gadget driver
3423 * Perform initialization to prepare udc device and driver
3426 static int dwc2_hsotg_udc_start(struct usb_gadget
*gadget
,
3427 struct usb_gadget_driver
*driver
)
3429 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
3430 unsigned long flags
;
3434 pr_err("%s: called with no device\n", __func__
);
3439 dev_err(hsotg
->dev
, "%s: no driver\n", __func__
);
3443 if (driver
->max_speed
< USB_SPEED_FULL
)
3444 dev_err(hsotg
->dev
, "%s: bad speed\n", __func__
);
3446 if (!driver
->setup
) {
3447 dev_err(hsotg
->dev
, "%s: missing entry points\n", __func__
);
3451 WARN_ON(hsotg
->driver
);
3453 driver
->driver
.bus
= NULL
;
3454 hsotg
->driver
= driver
;
3455 hsotg
->gadget
.dev
.of_node
= hsotg
->dev
->of_node
;
3456 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3458 if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
) {
3459 ret
= dwc2_lowlevel_hw_enable(hsotg
);
3464 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
3465 otg_set_peripheral(hsotg
->uphy
->otg
, &hsotg
->gadget
);
3467 spin_lock_irqsave(&hsotg
->lock
, flags
);
3468 if (dwc2_hw_is_device(hsotg
)) {
3469 dwc2_hsotg_init(hsotg
);
3470 dwc2_hsotg_core_init_disconnected(hsotg
, false);
3474 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3476 dev_info(hsotg
->dev
, "bound driver %s\n", driver
->driver
.name
);
3481 hsotg
->driver
= NULL
;
3486 * dwc2_hsotg_udc_stop - stop the udc
3487 * @gadget: The usb gadget state
3488 * @driver: The usb gadget driver
3490 * Stop udc hw block and stay tunned for future transmissions
3492 static int dwc2_hsotg_udc_stop(struct usb_gadget
*gadget
)
3494 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
3495 unsigned long flags
= 0;
3501 /* all endpoints should be shutdown */
3502 for (ep
= 1; ep
< hsotg
->num_of_eps
; ep
++) {
3503 if (hsotg
->eps_in
[ep
])
3504 dwc2_hsotg_ep_disable(&hsotg
->eps_in
[ep
]->ep
);
3505 if (hsotg
->eps_out
[ep
])
3506 dwc2_hsotg_ep_disable(&hsotg
->eps_out
[ep
]->ep
);
3509 spin_lock_irqsave(&hsotg
->lock
, flags
);
3511 hsotg
->driver
= NULL
;
3512 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3515 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3517 if (!IS_ERR_OR_NULL(hsotg
->uphy
))
3518 otg_set_peripheral(hsotg
->uphy
->otg
, NULL
);
3520 if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
)
3521 dwc2_lowlevel_hw_disable(hsotg
);
3527 * dwc2_hsotg_gadget_getframe - read the frame number
3528 * @gadget: The usb gadget state
3530 * Read the {micro} frame number
3532 static int dwc2_hsotg_gadget_getframe(struct usb_gadget
*gadget
)
3534 return dwc2_hsotg_read_frameno(to_hsotg(gadget
));
3538 * dwc2_hsotg_pullup - connect/disconnect the USB PHY
3539 * @gadget: The usb gadget state
3540 * @is_on: Current state of the USB PHY
3542 * Connect/Disconnect the USB PHY pullup
3544 static int dwc2_hsotg_pullup(struct usb_gadget
*gadget
, int is_on
)
3546 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
3547 unsigned long flags
= 0;
3549 dev_dbg(hsotg
->dev
, "%s: is_on: %d op_state: %d\n", __func__
, is_on
,
3552 /* Don't modify pullup state while in host mode */
3553 if (hsotg
->op_state
!= OTG_STATE_B_PERIPHERAL
) {
3554 hsotg
->enabled
= is_on
;
3558 spin_lock_irqsave(&hsotg
->lock
, flags
);
3561 dwc2_hsotg_core_init_disconnected(hsotg
, false);
3562 dwc2_hsotg_core_connect(hsotg
);
3564 dwc2_hsotg_core_disconnect(hsotg
);
3565 dwc2_hsotg_disconnect(hsotg
);
3569 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3570 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3575 static int dwc2_hsotg_vbus_session(struct usb_gadget
*gadget
, int is_active
)
3577 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
3578 unsigned long flags
;
3580 dev_dbg(hsotg
->dev
, "%s: is_active: %d\n", __func__
, is_active
);
3581 spin_lock_irqsave(&hsotg
->lock
, flags
);
3584 * If controller is hibernated, it must exit from hibernation
3585 * before being initialized / de-initialized
3587 if (hsotg
->lx_state
== DWC2_L2
)
3588 dwc2_exit_hibernation(hsotg
, false);
3591 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
3593 dwc2_hsotg_core_init_disconnected(hsotg
, false);
3595 dwc2_hsotg_core_connect(hsotg
);
3597 dwc2_hsotg_core_disconnect(hsotg
);
3598 dwc2_hsotg_disconnect(hsotg
);
3601 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3606 * dwc2_hsotg_vbus_draw - report bMaxPower field
3607 * @gadget: The usb gadget state
3608 * @mA: Amount of current
3610 * Report how much power the device may consume to the phy.
3612 static int dwc2_hsotg_vbus_draw(struct usb_gadget
*gadget
, unsigned mA
)
3614 struct dwc2_hsotg
*hsotg
= to_hsotg(gadget
);
3616 if (IS_ERR_OR_NULL(hsotg
->uphy
))
3618 return usb_phy_set_power(hsotg
->uphy
, mA
);
3621 static const struct usb_gadget_ops dwc2_hsotg_gadget_ops
= {
3622 .get_frame
= dwc2_hsotg_gadget_getframe
,
3623 .udc_start
= dwc2_hsotg_udc_start
,
3624 .udc_stop
= dwc2_hsotg_udc_stop
,
3625 .pullup
= dwc2_hsotg_pullup
,
3626 .vbus_session
= dwc2_hsotg_vbus_session
,
3627 .vbus_draw
= dwc2_hsotg_vbus_draw
,
3631 * dwc2_hsotg_initep - initialise a single endpoint
3632 * @hsotg: The device state.
3633 * @hs_ep: The endpoint to be initialised.
3634 * @epnum: The endpoint number
3636 * Initialise the given endpoint (as part of the probe and device state
3637 * creation) to give to the gadget driver. Setup the endpoint name, any
3638 * direction information and other state that may be required.
3640 static void dwc2_hsotg_initep(struct dwc2_hsotg
*hsotg
,
3641 struct dwc2_hsotg_ep
*hs_ep
,
3654 hs_ep
->dir_in
= dir_in
;
3655 hs_ep
->index
= epnum
;
3657 snprintf(hs_ep
->name
, sizeof(hs_ep
->name
), "ep%d%s", epnum
, dir
);
3659 INIT_LIST_HEAD(&hs_ep
->queue
);
3660 INIT_LIST_HEAD(&hs_ep
->ep
.ep_list
);
3662 /* add to the list of endpoints known by the gadget driver */
3664 list_add_tail(&hs_ep
->ep
.ep_list
, &hsotg
->gadget
.ep_list
);
3666 hs_ep
->parent
= hsotg
;
3667 hs_ep
->ep
.name
= hs_ep
->name
;
3668 usb_ep_set_maxpacket_limit(&hs_ep
->ep
, epnum
? 1024 : EP0_MPS_LIMIT
);
3669 hs_ep
->ep
.ops
= &dwc2_hsotg_ep_ops
;
3672 hs_ep
->ep
.caps
.type_control
= true;
3674 hs_ep
->ep
.caps
.type_iso
= true;
3675 hs_ep
->ep
.caps
.type_bulk
= true;
3676 hs_ep
->ep
.caps
.type_int
= true;
3680 hs_ep
->ep
.caps
.dir_in
= true;
3682 hs_ep
->ep
.caps
.dir_out
= true;
3685 * if we're using dma, we need to set the next-endpoint pointer
3686 * to be something valid.
3689 if (using_dma(hsotg
)) {
3690 u32 next
= DXEPCTL_NEXTEP((epnum
+ 1) % 15);
3692 dwc2_writel(next
, hsotg
->regs
+ DIEPCTL(epnum
));
3694 dwc2_writel(next
, hsotg
->regs
+ DOEPCTL(epnum
));
3699 * dwc2_hsotg_hw_cfg - read HW configuration registers
3700 * @param: The device state
3702 * Read the USB core HW configuration registers
3704 static int dwc2_hsotg_hw_cfg(struct dwc2_hsotg
*hsotg
)
3710 /* check hardware configuration */
3712 hsotg
->num_of_eps
= hsotg
->hw_params
.num_dev_ep
;
3715 hsotg
->num_of_eps
++;
3717 hsotg
->eps_in
[0] = devm_kzalloc(hsotg
->dev
, sizeof(struct dwc2_hsotg_ep
),
3719 if (!hsotg
->eps_in
[0])
3721 /* Same dwc2_hsotg_ep is used in both directions for ep0 */
3722 hsotg
->eps_out
[0] = hsotg
->eps_in
[0];
3724 cfg
= hsotg
->hw_params
.dev_ep_dirs
;
3725 for (i
= 1, cfg
>>= 2; i
< hsotg
->num_of_eps
; i
++, cfg
>>= 2) {
3727 /* Direction in or both */
3728 if (!(ep_type
& 2)) {
3729 hsotg
->eps_in
[i
] = devm_kzalloc(hsotg
->dev
,
3730 sizeof(struct dwc2_hsotg_ep
), GFP_KERNEL
);
3731 if (!hsotg
->eps_in
[i
])
3734 /* Direction out or both */
3735 if (!(ep_type
& 1)) {
3736 hsotg
->eps_out
[i
] = devm_kzalloc(hsotg
->dev
,
3737 sizeof(struct dwc2_hsotg_ep
), GFP_KERNEL
);
3738 if (!hsotg
->eps_out
[i
])
3743 hsotg
->fifo_mem
= hsotg
->hw_params
.total_fifo_size
;
3744 hsotg
->dedicated_fifos
= hsotg
->hw_params
.en_multiple_tx_fifo
;
3746 dev_info(hsotg
->dev
, "EPs: %d, %s fifos, %d entries in SPRAM\n",
3748 hsotg
->dedicated_fifos
? "dedicated" : "shared",
3754 * dwc2_hsotg_dump - dump state of the udc
3755 * @param: The device state
3757 static void dwc2_hsotg_dump(struct dwc2_hsotg
*hsotg
)
3760 struct device
*dev
= hsotg
->dev
;
3761 void __iomem
*regs
= hsotg
->regs
;
3765 dev_info(dev
, "DCFG=0x%08x, DCTL=0x%08x, DIEPMSK=%08x\n",
3766 dwc2_readl(regs
+ DCFG
), dwc2_readl(regs
+ DCTL
),
3767 dwc2_readl(regs
+ DIEPMSK
));
3769 dev_info(dev
, "GAHBCFG=0x%08x, GHWCFG1=0x%08x\n",
3770 dwc2_readl(regs
+ GAHBCFG
), dwc2_readl(regs
+ GHWCFG1
));
3772 dev_info(dev
, "GRXFSIZ=0x%08x, GNPTXFSIZ=0x%08x\n",
3773 dwc2_readl(regs
+ GRXFSIZ
), dwc2_readl(regs
+ GNPTXFSIZ
));
3775 /* show periodic fifo settings */
3777 for (idx
= 1; idx
< hsotg
->num_of_eps
; idx
++) {
3778 val
= dwc2_readl(regs
+ DPTXFSIZN(idx
));
3779 dev_info(dev
, "DPTx[%d] FSize=%d, StAddr=0x%08x\n", idx
,
3780 val
>> FIFOSIZE_DEPTH_SHIFT
,
3781 val
& FIFOSIZE_STARTADDR_MASK
);
3784 for (idx
= 0; idx
< hsotg
->num_of_eps
; idx
++) {
3786 "ep%d-in: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n", idx
,
3787 dwc2_readl(regs
+ DIEPCTL(idx
)),
3788 dwc2_readl(regs
+ DIEPTSIZ(idx
)),
3789 dwc2_readl(regs
+ DIEPDMA(idx
)));
3791 val
= dwc2_readl(regs
+ DOEPCTL(idx
));
3793 "ep%d-out: EPCTL=0x%08x, SIZ=0x%08x, DMA=0x%08x\n",
3794 idx
, dwc2_readl(regs
+ DOEPCTL(idx
)),
3795 dwc2_readl(regs
+ DOEPTSIZ(idx
)),
3796 dwc2_readl(regs
+ DOEPDMA(idx
)));
3800 dev_info(dev
, "DVBUSDIS=0x%08x, DVBUSPULSE=%08x\n",
3801 dwc2_readl(regs
+ DVBUSDIS
), dwc2_readl(regs
+ DVBUSPULSE
));
3806 static void dwc2_hsotg_of_probe(struct dwc2_hsotg
*hsotg
)
3808 struct device_node
*np
= hsotg
->dev
->of_node
;
3812 /* Enable dma if requested in device tree */
3813 hsotg
->g_using_dma
= of_property_read_bool(np
, "g-use-dma");
3816 * Register TX periodic fifo size per endpoint.
3817 * EP0 is excluded since it has no fifo configuration.
3819 if (!of_find_property(np
, "g-tx-fifo-size", &len
))
3824 /* Read tx fifo sizes other than ep0 */
3825 if (of_property_read_u32_array(np
, "g-tx-fifo-size",
3826 &hsotg
->g_tx_fifo_sz
[1], len
))
3832 /* Make remaining TX fifos unavailable */
3833 if (len
< MAX_EPS_CHANNELS
) {
3834 for (i
= len
; i
< MAX_EPS_CHANNELS
; i
++)
3835 hsotg
->g_tx_fifo_sz
[i
] = 0;
3839 /* Register RX fifo size */
3840 of_property_read_u32(np
, "g-rx-fifo-size", &hsotg
->g_rx_fifo_sz
);
3842 /* Register NPTX fifo size */
3843 of_property_read_u32(np
, "g-np-tx-fifo-size",
3844 &hsotg
->g_np_g_tx_fifo_sz
);
3847 static inline void dwc2_hsotg_of_probe(struct dwc2_hsotg
*hsotg
) { }
3851 * dwc2_gadget_init - init function for gadget
3852 * @dwc2: The data structure for the DWC2 driver.
3853 * @irq: The IRQ number for the controller.
3855 int dwc2_gadget_init(struct dwc2_hsotg
*hsotg
, int irq
)
3857 struct device
*dev
= hsotg
->dev
;
3861 u32 p_tx_fifo
[] = DWC2_G_P_LEGACY_TX_FIFO_SIZE
;
3863 /* Initialize to legacy fifo configuration values */
3864 hsotg
->g_rx_fifo_sz
= 2048;
3865 hsotg
->g_np_g_tx_fifo_sz
= 1024;
3866 memcpy(&hsotg
->g_tx_fifo_sz
[1], p_tx_fifo
, sizeof(p_tx_fifo
));
3867 /* Device tree specific probe */
3868 dwc2_hsotg_of_probe(hsotg
);
3870 /* Check against largest possible value. */
3871 if (hsotg
->g_np_g_tx_fifo_sz
>
3872 hsotg
->hw_params
.dev_nperio_tx_fifo_size
) {
3873 dev_warn(dev
, "Specified GNPTXFDEP=%d > %d\n",
3874 hsotg
->g_np_g_tx_fifo_sz
,
3875 hsotg
->hw_params
.dev_nperio_tx_fifo_size
);
3876 hsotg
->g_np_g_tx_fifo_sz
=
3877 hsotg
->hw_params
.dev_nperio_tx_fifo_size
;
3880 /* Dump fifo information */
3881 dev_dbg(dev
, "NonPeriodic TXFIFO size: %d\n",
3882 hsotg
->g_np_g_tx_fifo_sz
);
3883 dev_dbg(dev
, "RXFIFO size: %d\n", hsotg
->g_rx_fifo_sz
);
3884 for (i
= 0; i
< MAX_EPS_CHANNELS
; i
++)
3885 dev_dbg(dev
, "Periodic TXFIFO%2d size: %d\n", i
,
3886 hsotg
->g_tx_fifo_sz
[i
]);
3888 hsotg
->gadget
.max_speed
= USB_SPEED_HIGH
;
3889 hsotg
->gadget
.ops
= &dwc2_hsotg_gadget_ops
;
3890 hsotg
->gadget
.name
= dev_name(dev
);
3891 if (hsotg
->dr_mode
== USB_DR_MODE_OTG
)
3892 hsotg
->gadget
.is_otg
= 1;
3893 else if (hsotg
->dr_mode
== USB_DR_MODE_PERIPHERAL
)
3894 hsotg
->op_state
= OTG_STATE_B_PERIPHERAL
;
3896 ret
= dwc2_hsotg_hw_cfg(hsotg
);
3898 dev_err(hsotg
->dev
, "Hardware configuration failed: %d\n", ret
);
3902 hsotg
->ctrl_buff
= devm_kzalloc(hsotg
->dev
,
3903 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
3904 if (!hsotg
->ctrl_buff
)
3907 hsotg
->ep0_buff
= devm_kzalloc(hsotg
->dev
,
3908 DWC2_CTRL_BUFF_SIZE
, GFP_KERNEL
);
3909 if (!hsotg
->ep0_buff
)
3912 ret
= devm_request_irq(hsotg
->dev
, irq
, dwc2_hsotg_irq
, IRQF_SHARED
,
3913 dev_name(hsotg
->dev
), hsotg
);
3915 dev_err(dev
, "cannot claim IRQ for gadget\n");
3919 /* hsotg->num_of_eps holds number of EPs other than ep0 */
3921 if (hsotg
->num_of_eps
== 0) {
3922 dev_err(dev
, "wrong number of EPs (zero)\n");
3926 /* setup endpoint information */
3928 INIT_LIST_HEAD(&hsotg
->gadget
.ep_list
);
3929 hsotg
->gadget
.ep0
= &hsotg
->eps_out
[0]->ep
;
3931 /* allocate EP0 request */
3933 hsotg
->ctrl_req
= dwc2_hsotg_ep_alloc_request(&hsotg
->eps_out
[0]->ep
,
3935 if (!hsotg
->ctrl_req
) {
3936 dev_err(dev
, "failed to allocate ctrl req\n");
3940 /* initialise the endpoints now the core has been initialised */
3941 for (epnum
= 0; epnum
< hsotg
->num_of_eps
; epnum
++) {
3942 if (hsotg
->eps_in
[epnum
])
3943 dwc2_hsotg_initep(hsotg
, hsotg
->eps_in
[epnum
],
3945 if (hsotg
->eps_out
[epnum
])
3946 dwc2_hsotg_initep(hsotg
, hsotg
->eps_out
[epnum
],
3950 ret
= usb_add_gadget_udc(dev
, &hsotg
->gadget
);
3954 dwc2_hsotg_dump(hsotg
);
3960 * dwc2_hsotg_remove - remove function for hsotg driver
3961 * @pdev: The platform information for the driver
3963 int dwc2_hsotg_remove(struct dwc2_hsotg
*hsotg
)
3965 usb_del_gadget_udc(&hsotg
->gadget
);
3970 int dwc2_hsotg_suspend(struct dwc2_hsotg
*hsotg
)
3972 unsigned long flags
;
3974 if (hsotg
->lx_state
!= DWC2_L0
)
3977 if (hsotg
->driver
) {
3980 dev_info(hsotg
->dev
, "suspending usb gadget %s\n",
3981 hsotg
->driver
->driver
.name
);
3983 spin_lock_irqsave(&hsotg
->lock
, flags
);
3985 dwc2_hsotg_core_disconnect(hsotg
);
3986 dwc2_hsotg_disconnect(hsotg
);
3987 hsotg
->gadget
.speed
= USB_SPEED_UNKNOWN
;
3988 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
3990 for (ep
= 0; ep
< hsotg
->num_of_eps
; ep
++) {
3991 if (hsotg
->eps_in
[ep
])
3992 dwc2_hsotg_ep_disable(&hsotg
->eps_in
[ep
]->ep
);
3993 if (hsotg
->eps_out
[ep
])
3994 dwc2_hsotg_ep_disable(&hsotg
->eps_out
[ep
]->ep
);
4001 int dwc2_hsotg_resume(struct dwc2_hsotg
*hsotg
)
4003 unsigned long flags
;
4005 if (hsotg
->lx_state
== DWC2_L2
)
4008 if (hsotg
->driver
) {
4009 dev_info(hsotg
->dev
, "resuming usb gadget %s\n",
4010 hsotg
->driver
->driver
.name
);
4012 spin_lock_irqsave(&hsotg
->lock
, flags
);
4013 dwc2_hsotg_core_init_disconnected(hsotg
, false);
4015 dwc2_hsotg_core_connect(hsotg
);
4016 spin_unlock_irqrestore(&hsotg
->lock
, flags
);
4023 * dwc2_backup_device_registers() - Backup controller device registers.
4024 * When suspending usb bus, registers needs to be backuped
4025 * if controller power is disabled once suspended.
4027 * @hsotg: Programming view of the DWC_otg controller
4029 int dwc2_backup_device_registers(struct dwc2_hsotg
*hsotg
)
4031 struct dwc2_dregs_backup
*dr
;
4034 dev_dbg(hsotg
->dev
, "%s\n", __func__
);
4036 /* Backup dev regs */
4037 dr
= &hsotg
->dr_backup
;
4039 dr
->dcfg
= dwc2_readl(hsotg
->regs
+ DCFG
);
4040 dr
->dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
4041 dr
->daintmsk
= dwc2_readl(hsotg
->regs
+ DAINTMSK
);
4042 dr
->diepmsk
= dwc2_readl(hsotg
->regs
+ DIEPMSK
);
4043 dr
->doepmsk
= dwc2_readl(hsotg
->regs
+ DOEPMSK
);
4045 for (i
= 0; i
< hsotg
->num_of_eps
; i
++) {
4047 dr
->diepctl
[i
] = dwc2_readl(hsotg
->regs
+ DIEPCTL(i
));
4049 /* Ensure DATA PID is correctly configured */
4050 if (dr
->diepctl
[i
] & DXEPCTL_DPID
)
4051 dr
->diepctl
[i
] |= DXEPCTL_SETD1PID
;
4053 dr
->diepctl
[i
] |= DXEPCTL_SETD0PID
;
4055 dr
->dieptsiz
[i
] = dwc2_readl(hsotg
->regs
+ DIEPTSIZ(i
));
4056 dr
->diepdma
[i
] = dwc2_readl(hsotg
->regs
+ DIEPDMA(i
));
4058 /* Backup OUT EPs */
4059 dr
->doepctl
[i
] = dwc2_readl(hsotg
->regs
+ DOEPCTL(i
));
4061 /* Ensure DATA PID is correctly configured */
4062 if (dr
->doepctl
[i
] & DXEPCTL_DPID
)
4063 dr
->doepctl
[i
] |= DXEPCTL_SETD1PID
;
4065 dr
->doepctl
[i
] |= DXEPCTL_SETD0PID
;
4067 dr
->doeptsiz
[i
] = dwc2_readl(hsotg
->regs
+ DOEPTSIZ(i
));
4068 dr
->doepdma
[i
] = dwc2_readl(hsotg
->regs
+ DOEPDMA(i
));
4075 * dwc2_restore_device_registers() - Restore controller device registers.
4076 * When resuming usb bus, device registers needs to be restored
4077 * if controller power were disabled.
4079 * @hsotg: Programming view of the DWC_otg controller
4081 int dwc2_restore_device_registers(struct dwc2_hsotg
*hsotg
)
4083 struct dwc2_dregs_backup
*dr
;
4087 dev_dbg(hsotg
->dev
, "%s\n", __func__
);
4089 /* Restore dev regs */
4090 dr
= &hsotg
->dr_backup
;
4092 dev_err(hsotg
->dev
, "%s: no device registers to restore\n",
4098 dwc2_writel(dr
->dcfg
, hsotg
->regs
+ DCFG
);
4099 dwc2_writel(dr
->dctl
, hsotg
->regs
+ DCTL
);
4100 dwc2_writel(dr
->daintmsk
, hsotg
->regs
+ DAINTMSK
);
4101 dwc2_writel(dr
->diepmsk
, hsotg
->regs
+ DIEPMSK
);
4102 dwc2_writel(dr
->doepmsk
, hsotg
->regs
+ DOEPMSK
);
4104 for (i
= 0; i
< hsotg
->num_of_eps
; i
++) {
4105 /* Restore IN EPs */
4106 dwc2_writel(dr
->diepctl
[i
], hsotg
->regs
+ DIEPCTL(i
));
4107 dwc2_writel(dr
->dieptsiz
[i
], hsotg
->regs
+ DIEPTSIZ(i
));
4108 dwc2_writel(dr
->diepdma
[i
], hsotg
->regs
+ DIEPDMA(i
));
4110 /* Restore OUT EPs */
4111 dwc2_writel(dr
->doepctl
[i
], hsotg
->regs
+ DOEPCTL(i
));
4112 dwc2_writel(dr
->doeptsiz
[i
], hsotg
->regs
+ DOEPTSIZ(i
));
4113 dwc2_writel(dr
->doepdma
[i
], hsotg
->regs
+ DOEPDMA(i
));
4116 /* Set the Power-On Programming done bit */
4117 dctl
= dwc2_readl(hsotg
->regs
+ DCTL
);
4118 dctl
|= DCTL_PWRONPRGDONE
;
4119 dwc2_writel(dctl
, hsotg
->regs
+ DCTL
);