KVM: arm64: vgic-v3: Add misc Group-0 handlers

[mirror_ubuntu-zesty-kernel.git] / virt / kvm / arm / hyp / vgic-v3-sr.c

diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c
index 1af7f94a525592a12b88421d157bf21b8389d891..86824e99ecb8d4aeae4af4107096fd6591e64900 100644 (file)
--- a/virt/kvm/arm/hyp/vgic-v3-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v3-sr.c
@@ -294,6 +294,9 @@ void __hyp_text __vgic_v3_save_state(struct kvm_vcpu *vcpu)
 
                vcpu->arch.vgic_cpu.live_lrs = 0;
        } else {
+               if (static_branch_unlikely(&vgic_v3_cpuif_trap))
+                       write_gicreg(0, ICH_HCR_EL2);
+
                cpu_if->vgic_misr  = 0;
                cpu_if->vgic_eisr  = 0;
                cpu_if->vgic_elrsr = 0xffff;
@@ -378,6 +381,14 @@ void __hyp_text __vgic_v3_restore_state(struct kvm_vcpu *vcpu)
 
                        __gic_v3_set_lr(cpu_if->vgic_lr[i], i);
                }
+       } else {
+               /*
+                * If we need to trap system registers, we must write
+                * ICH_HCR_EL2 anyway, even if no interrupts are being
+                * injected,
+                */
+               if (static_branch_unlikely(&vgic_v3_cpuif_trap))
+                       write_gicreg(cpu_if->vgic_hcr, ICH_HCR_EL2);
        }
 
        /*
@@ -727,11 +738,28 @@ static void __hyp_text __vgic_v3_write_eoir(struct kvm_vcpu *vcpu, u32 vmcr, int
        __vgic_v3_clear_active_lr(lr, lr_val);
 }
 
+static void __hyp_text __vgic_v3_read_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
+{
+       vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG0_MASK));
+}
+
 static void __hyp_text __vgic_v3_read_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 {
        vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG1_MASK));
 }
 
+static void __hyp_text __vgic_v3_write_igrpen0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
+{
+       u64 val = vcpu_get_reg(vcpu, rt);
+
+       if (val & 1)
+               vmcr |= ICH_VMCR_ENG0_MASK;
+       else
+               vmcr &= ~ICH_VMCR_ENG0_MASK;
+
+       __vgic_v3_write_vmcr(vmcr);
+}
+
 static void __hyp_text __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 {
        u64 val = vcpu_get_reg(vcpu, rt);
@@ -744,11 +772,33 @@ static void __hyp_text __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr,
        __vgic_v3_write_vmcr(vmcr);
 }
 
+static void __hyp_text __vgic_v3_read_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
+{
+       vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr0(vmcr));
+}
+
 static void __hyp_text __vgic_v3_read_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 {
        vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr1(vmcr));
 }
 
+static void __hyp_text __vgic_v3_write_bpr0(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
+{
+       u64 val = vcpu_get_reg(vcpu, rt);
+       u8 bpr_min = __vgic_v3_bpr_min() - 1;
+
+       /* Enforce BPR limiting */
+       if (val < bpr_min)
+               val = bpr_min;
+
+       val <<= ICH_VMCR_BPR0_SHIFT;
+       val &= ICH_VMCR_BPR0_MASK;
+       vmcr &= ~ICH_VMCR_BPR0_MASK;
+       vmcr |= val;
+
+       __vgic_v3_write_vmcr(vmcr);
+}
+
 static void __hyp_text __vgic_v3_write_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 {
        u64 val = vcpu_get_reg(vcpu, rt);
@@ -769,6 +819,96 @@ static void __hyp_text __vgic_v3_write_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int
        __vgic_v3_write_vmcr(vmcr);
 }
 
+static void __hyp_text __vgic_v3_read_apxrn(struct kvm_vcpu *vcpu, int rt, int n)
+{
+       u32 val;
+
+       if (!__vgic_v3_get_group(vcpu))
+               val = __vgic_v3_read_ap0rn(n);
+       else
+               val = __vgic_v3_read_ap1rn(n);
+
+       vcpu_set_reg(vcpu, rt, val);
+}
+
+static void __hyp_text __vgic_v3_write_apxrn(struct kvm_vcpu *vcpu, int rt, int n)
+{
+       u32 val = vcpu_get_reg(vcpu, rt);
+
+       if (!__vgic_v3_get_group(vcpu))
+               __vgic_v3_write_ap0rn(val, n);
+       else
+               __vgic_v3_write_ap1rn(val, n);
+}
+
+static void __hyp_text __vgic_v3_read_apxr0(struct kvm_vcpu *vcpu,
+                                           u32 vmcr, int rt)
+{
+       __vgic_v3_read_apxrn(vcpu, rt, 0);
+}
+
+static void __hyp_text __vgic_v3_read_apxr1(struct kvm_vcpu *vcpu,
+                                           u32 vmcr, int rt)
+{
+       __vgic_v3_read_apxrn(vcpu, rt, 1);
+}
+
+static void __hyp_text __vgic_v3_read_apxr2(struct kvm_vcpu *vcpu,
+                                           u32 vmcr, int rt)
+{
+       __vgic_v3_read_apxrn(vcpu, rt, 2);
+}
+
+static void __hyp_text __vgic_v3_read_apxr3(struct kvm_vcpu *vcpu,
+                                           u32 vmcr, int rt)
+{
+       __vgic_v3_read_apxrn(vcpu, rt, 3);
+}
+
+static void __hyp_text __vgic_v3_write_apxr0(struct kvm_vcpu *vcpu,
+                                            u32 vmcr, int rt)
+{
+       __vgic_v3_write_apxrn(vcpu, rt, 0);
+}
+
+static void __hyp_text __vgic_v3_write_apxr1(struct kvm_vcpu *vcpu,
+                                            u32 vmcr, int rt)
+{
+       __vgic_v3_write_apxrn(vcpu, rt, 1);
+}
+
+static void __hyp_text __vgic_v3_write_apxr2(struct kvm_vcpu *vcpu,
+                                            u32 vmcr, int rt)
+{
+       __vgic_v3_write_apxrn(vcpu, rt, 2);
+}
+
+static void __hyp_text __vgic_v3_write_apxr3(struct kvm_vcpu *vcpu,
+                                            u32 vmcr, int rt)
+{
+       __vgic_v3_write_apxrn(vcpu, rt, 3);
+}
+
+static void __hyp_text __vgic_v3_read_hppir(struct kvm_vcpu *vcpu,
+                                           u32 vmcr, int rt)
+{
+       u64 lr_val;
+       int lr, lr_grp, grp;
+
+       grp = __vgic_v3_get_group(vcpu);
+
+       lr = __vgic_v3_highest_priority_lr(vcpu, vmcr, &lr_val);
+       if (lr == -1)
+               goto spurious;
+
+       lr_grp = !!(lr_val & ICH_LR_GROUP);
+       if (lr_grp != grp)
+               lr_val = ICC_IAR1_EL1_SPURIOUS;
+
+spurious:
+       vcpu_set_reg(vcpu, rt, lr_val & ICH_LR_VIRTUAL_ID_MASK);
+}
+
 int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
 {
        int rt;
@@ -791,9 +931,11 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
        is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
 
        switch (sysreg) {
+       case ICC_IAR0_EL1:
        case ICC_IAR1_EL1:
                fn = __vgic_v3_read_iar;
                break;
+       case ICC_EOIR0_EL1:
        case ICC_EOIR1_EL1:
                fn = __vgic_v3_write_eoir;
                break;
@@ -809,6 +951,50 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
                else
                        fn = __vgic_v3_write_bpr1;
                break;
+       case ICC_AP0Rn_EL1(0):
+       case ICC_AP1Rn_EL1(0):
+               if (is_read)
+                       fn = __vgic_v3_read_apxr0;
+               else
+                       fn = __vgic_v3_write_apxr0;
+               break;
+       case ICC_AP0Rn_EL1(1):
+       case ICC_AP1Rn_EL1(1):
+               if (is_read)
+                       fn = __vgic_v3_read_apxr1;
+               else
+                       fn = __vgic_v3_write_apxr1;
+               break;
+       case ICC_AP0Rn_EL1(2):
+       case ICC_AP1Rn_EL1(2):
+               if (is_read)
+                       fn = __vgic_v3_read_apxr2;
+               else
+                       fn = __vgic_v3_write_apxr2;
+               break;
+       case ICC_AP0Rn_EL1(3):
+       case ICC_AP1Rn_EL1(3):
+               if (is_read)
+                       fn = __vgic_v3_read_apxr3;
+               else
+                       fn = __vgic_v3_write_apxr3;
+               break;
+       case ICC_HPPIR0_EL1:
+       case ICC_HPPIR1_EL1:
+               fn = __vgic_v3_read_hppir;
+               break;
+       case ICC_GRPEN0_EL1:
+               if (is_read)
+                       fn = __vgic_v3_read_igrpen0;
+               else
+                       fn = __vgic_v3_write_igrpen0;
+               break;
+       case ICC_BPR0_EL1:
+               if (is_read)
+                       fn = __vgic_v3_read_bpr0;
+               else
+                       fn = __vgic_v3_write_bpr0;
+               break;
        default:
                return 0;
        }