net: hns: Modify GMAC init TX threshold value

BugLink: https://bugs.launchpad.net/bugs/1696031
This patch reduces GMAC TX threshold value to avoid gmac
hang-up with speed 100M/duplex half.

Signed-off-by: lipeng <lipeng321@huawei.com>
Signed-off-by: JinchuanTian <tianjinchuan1@huawei.com>
Reviewed-by: Yisen Zhuang <yisen.zhuang@huawei.com>
Signed-off-by: Salil Mehta <salil.mehta@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 87ff7e1f460d709100cf5203738d62629ab6949b)
Signed-off-by: dann frazier <dann.frazier@canonical.com>
Acked-by: Stefan Bader <stefan.bader@canonical.com>
Acked-by: Seth Forshee <seth.forshee@canonical.com>
Signed-off-by: Stefan Bader <stefan.bader@canonical.com>

diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c
index 3382441fe7b51e84bb5e815ffc1e4fa192b09a91..a8dbe001725f9137e3a997ba109b8db6a04c4360 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_gmac.c
@@ -325,6 +325,12 @@ static void hns_gmac_init(void *mac_drv)
        hns_gmac_tx_loop_pkt_dis(mac_drv);
        if (drv->mac_cb->mac_type == HNAE_PORT_DEBUG)
                hns_gmac_set_uc_match(mac_drv, 0);
+
+       /* reduce gmac tx water line to avoid gmac hang-up
+        * in speed 100M and duplex half.
+        */
+       dsaf_set_dev_field(drv, GMAC_TX_WATER_LINE_REG, GMAC_TX_WATER_LINE_MASK,
+                          GMAC_TX_WATER_LINE_SHIFT, 8);
 }
 
 void hns_gmac_update_stats(void *mac_drv)

diff --git a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h
index 8fa18fc17cd2e25f2e3458e608abe6f5a96b60d9..4b8af68af02e869a5585a75684e1056a40b73798 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h
+++ b/drivers/net/ethernet/hisilicon/hns/hns_dsaf_reg.h
@@ -466,6 +466,7 @@
 
 #define GMAC_DUPLEX_TYPE_REG                   0x0008UL
 #define GMAC_FD_FC_TYPE_REG                    0x000CUL
+#define GMAC_TX_WATER_LINE_REG                 0x0010UL
 #define GMAC_FC_TX_TIMER_REG                   0x001CUL
 #define GMAC_FD_FC_ADDR_LOW_REG                        0x0020UL
 #define GMAC_FD_FC_ADDR_HIGH_REG               0x0024UL
@@ -912,6 +913,9 @@
 
 #define GMAC_DUPLEX_TYPE_B 0
 
+#define GMAC_TX_WATER_LINE_MASK                ((1UL << 8) - 1)
+#define GMAC_TX_WATER_LINE_SHIFT       0
+
 #define GMAC_FC_TX_TIMER_S 0
 #define GMAC_FC_TX_TIMER_M 0xffff