Commit
488f9bc8e3def93e0baef53cee2026c2cb0d8956 slightly increased the
reported rate of PLLD, so the clk driver decided that PLLD/3/8 was now
higher than our requested pixel clock rate and rejected it in favor of
PLLD/4/8, which then ran the pixel clock way out of spec.
By bumping the requested clock rate just slightly, we get back to
PLLD/3/8 like we wanted and the panel displays content again.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Tim Gardner <tim.gardner@canonical.com>
#define HBP 46
#define HFP ((PIXEL_CLOCK / (VTOTAL * VREFRESH)) - (HACT + HSW + HBP))
- .clock = PIXEL_CLOCK / 1000,
+ /* Round up the pixel clock a bit (10khz), so that the
+ * "don't run things faster than the requested clock
+ * rate" rule of the clk driver doesn't reject the
+ * divide-by-3 mode due to rounding error.
+ */
+ .clock = PIXEL_CLOCK / 1000 + 10,
.hdisplay = HACT,
.hsync_start = HACT + HFP,
.hsync_end = HACT + HFP + HSW,