patches/kernel/0012-x86-cpu-Fix-AMD-erratum-1485-on-Zen4-based-CPUs.patch

   1 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
   2 From: "Borislav Petkov (AMD)" <bp@alien8.de>
   3 Date: Sat, 7 Oct 2023 12:57:02 +0200
   4 Subject: [PATCH] x86/cpu: Fix AMD erratum #1485 on Zen4-based CPUs
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Fix erratum #1485 on Zen4 parts where running with STIBP disabled can
  10 cause an #UD exception. The performance impact of the fix is negligible.
  11
  12 Reported-by: René Rebe <rene@exactcode.de>
  13 Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de>
  14 Tested-by: René Rebe <rene@exactcode.de>
  15 Cc: <stable@kernel.org>
  16 Link: https://lore.kernel.org/r/D99589F4-BC5D-430B-87B2-72C20370CF57@exactcode.com
  17 Signed-off-by: Thomas Lamprecht <t.lamprecht@proxmox.com>
  18 ---
  19  arch/x86/include/asm/msr-index.h | 9 +++++++--
  20  arch/x86/kernel/cpu/amd.c        | 8 ++++++++
  21  2 files changed, 15 insertions(+), 2 deletions(-)
  22
  23 diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
  24 index 1d111350197f..b37abb55e948 100644
  25 --- a/arch/x86/include/asm/msr-index.h
  26 +++ b/arch/x86/include/asm/msr-index.h
  27 @@ -637,12 +637,17 @@
  28  /* AMD Last Branch Record MSRs */
  29  #define MSR_AMD64_LBR_SELECT                   0xc000010e
  30
  31 -/* Fam 17h MSRs */
  32 -#define MSR_F17H_IRPERF                        0xc00000e9
  33 +/* Zen4 */
  34 +#define MSR_ZEN4_BP_CFG                        0xc001102e
  35 +#define MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT 5
  36
  37 +/* Zen 2 */
  38  #define MSR_ZEN2_SPECTRAL_CHICKEN      0xc00110e3
  39  #define MSR_ZEN2_SPECTRAL_CHICKEN_BIT  BIT_ULL(1)
  40
  41 +/* Fam 17h MSRs */
  42 +#define MSR_F17H_IRPERF                        0xc00000e9
  43 +
  44  /* Fam 16h MSRs */
  45  #define MSR_F16H_L2I_PERF_CTL          0xc0010230
  46  #define MSR_F16H_L2I_PERF_CTR          0xc0010231
  47 diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
  48 index 7eca6a8abbb1..981bc23665a3 100644
  49 --- a/arch/x86/kernel/cpu/amd.c
  50 +++ b/arch/x86/kernel/cpu/amd.c
  51 @@ -80,6 +80,10 @@ static const int amd_div0[] =
  52         AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x17, 0x00, 0x0, 0x2f, 0xf),
  53                            AMD_MODEL_RANGE(0x17, 0x50, 0x0, 0x5f, 0xf));
  54
  55 +static const int amd_erratum_1485[] =
  56 +       AMD_LEGACY_ERRATUM(AMD_MODEL_RANGE(0x19, 0x10, 0x0, 0x1f, 0xf),
  57 +                          AMD_MODEL_RANGE(0x19, 0x60, 0x0, 0xaf, 0xf));
  58 +
  59  static bool cpu_has_amd_erratum(struct cpuinfo_x86 *cpu, const int *erratum)
  60  {
  61         int osvw_id = *erratum++;
  62 @@ -1140,6 +1144,10 @@ static void init_amd(struct cpuinfo_x86 *c)
  63                 pr_notice_once("AMD Zen1 DIV0 bug detected. Disable SMT for full protection.\n");
  64                 setup_force_cpu_bug(X86_BUG_DIV0);
  65         }
  66 +
  67 +       if (!cpu_has(c, X86_FEATURE_HYPERVISOR) &&
  68 +            cpu_has_amd_erratum(c, amd_erratum_1485))
  69 +               msr_set_bit(MSR_ZEN4_BP_CFG, MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT);
  70  }
  71
  72  #ifdef CONFIG_X86_32