patches/kernel/0121-x86-cpufeature-Add-User-Mode-Instruction-Prevention-.patch

   1 From c2c378764103c12f96d1e913c8a2ffe3af3b1360 Mon Sep 17 00:00:00 2001
   2 From: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
   3 Date: Sun, 5 Nov 2017 18:27:51 -0800
   4 Subject: [PATCH 121/241] x86/cpufeature: Add User-Mode Instruction Prevention
   5  definitions
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 CVE-2017-5754
  11
  12 [ Note, this is a Git cherry-pick of the following commit: (limited to the cpufeatures.h file)
  13
  14     3522c2a6a4f3 ("x86/cpufeature: Add User-Mode Instruction Prevention definitions")
  15
  16   ... for easier x86 PTI code testing and back-porting. ]
  17
  18 User-Mode Instruction Prevention is a security feature present in new
  19 Intel processors that, when set, prevents the execution of a subset of
  20 instructions if such instructions are executed in user mode (CPL > 0).
  21 Attempting to execute such instructions causes a general protection
  22 exception.
  23
  24 The subset of instructions comprises:
  25
  26  * SGDT - Store Global Descriptor Table
  27  * SIDT - Store Interrupt Descriptor Table
  28  * SLDT - Store Local Descriptor Table
  29  * SMSW - Store Machine Status Word
  30  * STR  - Store Task Register
  31
  32 This feature is also added to the list of disabled-features to allow
  33 a cleaner handling of build-time configuration.
  34
  35 Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
  36 Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
  37 Reviewed-by: Borislav Petkov <bp@suse.de>
  38 Cc: Andrew Morton <akpm@linux-foundation.org>
  39 Cc: Andy Lutomirski <luto@kernel.org>
  40 Cc: Borislav Petkov <bp@alien8.de>
  41 Cc: Brian Gerst <brgerst@gmail.com>
  42 Cc: Chen Yucong <slaoub@gmail.com>
  43 Cc: Chris Metcalf <cmetcalf@mellanox.com>
  44 Cc: Dave Hansen <dave.hansen@linux.intel.com>
  45 Cc: Denys Vlasenko <dvlasenk@redhat.com>
  46 Cc: Fenghua Yu <fenghua.yu@intel.com>
  47 Cc: H. Peter Anvin <hpa@zytor.com>
  48 Cc: Huang Rui <ray.huang@amd.com>
  49 Cc: Jiri Slaby <jslaby@suse.cz>
  50 Cc: Jonathan Corbet <corbet@lwn.net>
  51 Cc: Josh Poimboeuf <jpoimboe@redhat.com>
  52 Cc: Linus Torvalds <torvalds@linux-foundation.org>
  53 Cc: Masami Hiramatsu <mhiramat@kernel.org>
  54 Cc: Michael S. Tsirkin <mst@redhat.com>
  55 Cc: Paolo Bonzini <pbonzini@redhat.com>
  56 Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
  57 Cc: Peter Zijlstra <peterz@infradead.org>
  58 Cc: Ravi V. Shankar <ravi.v.shankar@intel.com>
  59 Cc: Shuah Khan <shuah@kernel.org>
  60 Cc: Tony Luck <tony.luck@intel.com>
  61 Cc: Vlastimil Babka <vbabka@suse.cz>
  62 Cc: ricardo.neri@intel.com
  63 Link: http://lkml.kernel.org/r/1509935277-22138-7-git-send-email-ricardo.neri-calderon@linux.intel.com
  64 Signed-off-by: Ingo Molnar <mingo@kernel.org>
  65 (cherry picked from commit a8b4db562e7283a1520f9e9730297ecaab7622ea)
  66 Signed-off-by: Andy Whitcroft <apw@canonical.com>
  67 Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
  68 (cherry picked from commit 6193ddb9de38665ba45f7f17dd9713baec3673ca)
  69 Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
  70 ---
  71  arch/x86/include/asm/cpufeatures.h | 1 +
  72  1 file changed, 1 insertion(+)
  73
  74 diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
  75 index 6db782ed9cdb..0ea630bb3e74 100644
  76 --- a/arch/x86/include/asm/cpufeatures.h
  77 +++ b/arch/x86/include/asm/cpufeatures.h
  78 @@ -295,6 +295,7 @@
  79
  80  /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
  81  #define X86_FEATURE_AVX512VBMI         (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
  82 +#define X86_FEATURE_UMIP               (16*32+ 2) /* User Mode Instruction Protection */
  83  #define X86_FEATURE_PKU                        (16*32+ 3) /* Protection Keys for Userspace */
  84  #define X86_FEATURE_OSPKE              (16*32+ 4) /* OS Protection Keys Enable */
  85  #define X86_FEATURE_AVX512_VBMI2       (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
  86 --
  87 2.14.2
  88