patches/kernel/0178-x86-mm-Add-comments-to-clarify-which-TLB-flush-funct.patch

   1 From 0e75b184111dbcd07911712bd87991df186c5fd3 Mon Sep 17 00:00:00 2001
   2 From: Peter Zijlstra <peterz@infradead.org>
   3 Date: Tue, 5 Dec 2017 13:34:52 +0100
   4 Subject: [PATCH 178/241] x86/mm: Add comments to clarify which TLB-flush
   5  functions are supposed to flush what
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 CVE-2017-5754
  11
  12 Per popular request..
  13
  14 Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
  15 Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
  16 Cc: Andy Lutomirski <luto@kernel.org>
  17 Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
  18 Cc: Borislav Petkov <bp@alien8.de>
  19 Cc: Brian Gerst <brgerst@gmail.com>
  20 Cc: Dave Hansen <dave.hansen@linux.intel.com>
  21 Cc: David Laight <David.Laight@aculab.com>
  22 Cc: Denys Vlasenko <dvlasenk@redhat.com>
  23 Cc: Eduardo Valentin <eduval@amazon.com>
  24 Cc: Greg KH <gregkh@linuxfoundation.org>
  25 Cc: H. Peter Anvin <hpa@zytor.com>
  26 Cc: Josh Poimboeuf <jpoimboe@redhat.com>
  27 Cc: Juergen Gross <jgross@suse.com>
  28 Cc: Linus Torvalds <torvalds@linux-foundation.org>
  29 Cc: Peter Zijlstra <peterz@infradead.org>
  30 Cc: Will Deacon <will.deacon@arm.com>
  31 Cc: aliguori@amazon.com
  32 Cc: daniel.gruss@iaik.tugraz.at
  33 Cc: hughd@google.com
  34 Cc: keescook@google.com
  35 Cc: linux-mm@kvack.org
  36 Signed-off-by: Ingo Molnar <mingo@kernel.org>
  37 (backported from commit 3f67af51e56f291d7417d77c4f67cd774633c5e1)
  38 Signed-off-by: Andy Whitcroft <apw@canonical.com>
  39 Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
  40 (cherry picked from commit 8394b666c2b3b1fc5279a897c96b196531923f3b)
  41 Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
  42 ---
  43  arch/x86/include/asm/tlbflush.h | 24 ++++++++++++++++++++++--
  44  1 file changed, 22 insertions(+), 2 deletions(-)
  45
  46 diff --git a/arch/x86/include/asm/tlbflush.h b/arch/x86/include/asm/tlbflush.h
  47 index bc1460b4737b..ed5d483c4a1b 100644
  48 --- a/arch/x86/include/asm/tlbflush.h
  49 +++ b/arch/x86/include/asm/tlbflush.h
  50 @@ -216,6 +216,10 @@ static inline void cr4_set_bits_and_update_boot(unsigned long mask)
  51         cr4_set_bits(mask);
  52  }
  53
  54 +
  55 +/*
  56 + * flush the entire current user mapping
  57 + */
  58  static inline void __native_flush_tlb(void)
  59  {
  60         /*
  61 @@ -228,6 +232,9 @@ static inline void __native_flush_tlb(void)
  62         preempt_enable();
  63  }
  64
  65 +/*
  66 + * flush everything
  67 + */
  68  static inline void __native_flush_tlb_global(void)
  69  {
  70         unsigned long cr4, flags;
  71 @@ -257,17 +264,27 @@ static inline void __native_flush_tlb_global(void)
  72         raw_local_irq_restore(flags);
  73  }
  74
  75 +/*
  76 + * flush one page in the user mapping
  77 + */
  78  static inline void __native_flush_tlb_single(unsigned long addr)
  79  {
  80         asm volatile("invlpg (%0)" ::"r" (addr) : "memory");
  81  }
  82
  83 +/*
  84 + * flush everything
  85 + */
  86  static inline void __flush_tlb_all(void)
  87  {
  88 -       if (boot_cpu_has(X86_FEATURE_PGE))
  89 +       if (boot_cpu_has(X86_FEATURE_PGE)) {
  90                 __flush_tlb_global();
  91 -       else
  92 +       } else {
  93 +               /*
  94 +                * !PGE -> !PCID (setup_pcid()), thus every flush is total.
  95 +                */
  96                 __flush_tlb();
  97 +       }
  98
  99         /*
 100          * Note: if we somehow had PCID but not PGE, then this wouldn't work --
 101 @@ -278,6 +295,9 @@ static inline void __flush_tlb_all(void)
 102          */
 103  }
 104
 105 +/*
 106 + * flush one page in the kernel mapping
 107 + */
 108  static inline void __flush_tlb_one(unsigned long addr)
 109  {
 110         count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ONE);
 111 --
 112 2.14.2
 113