+From 78388cbea036c9a9e2fd0c71e21d608cfc63939a Mon Sep 17 00:00:00 2001
+From: Julia Cartwright <julia@ni.com>
+Date: Thu, 1 Jun 2017 13:12:16 +0800
+Subject: [PATCH] pinctrl: amd: make use of raw_spinlock variants
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+BugLink: https://bugs.launchpad.net/bugs/1671360
+
+The amd pinctrl drivers currently implement an irq_chip for handling
+interrupts; due to how irq_chip handling is done, it's necessary for the
+irq_chip methods to be invoked from hardirq context, even on a a
+real-time kernel. Because the spinlock_t type becomes a "sleeping"
+spinlock w/ RT kernels, it is not suitable to be used with irq_chips.
+
+A quick audit of the operations under the lock reveal that they do only
+minimal, bounded work, and are therefore safe to do under a raw spinlock.
+
+Signed-off-by: Julia Cartwright <julia@ni.com>
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+(cherry picked from commit 229710fecdd805abb753c480778ea0de47cbb1e2)
+Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
+Acked-by: Stefan Bader <stefan.bader@canonical.com>
+Acked-by: Seth Forshee <seth.forshee@canonical.com>
+Signed-off-by: Kleber Sacilotto de Souza <kleber.souza@canonical.com>
+Signed-off-by: Fabian Grünbichler <f.gruenbichler@proxmox.com>
+---
+ drivers/pinctrl/pinctrl-amd.h | 2 +-
+ drivers/pinctrl/pinctrl-amd.c | 66 +++++++++++++++++++++----------------------
+ 2 files changed, 34 insertions(+), 34 deletions(-)
+
+diff --git a/drivers/pinctrl/pinctrl-amd.h b/drivers/pinctrl/pinctrl-amd.h
+index 7bfea47dbb47..4d5d5cac48a9 100644
+--- a/drivers/pinctrl/pinctrl-amd.h
++++ b/drivers/pinctrl/pinctrl-amd.h
+@@ -86,7 +86,7 @@ struct amd_function {
+ };
+
+ struct amd_gpio {
+- spinlock_t lock;
++ raw_spinlock_t lock;
+ void __iomem *base;
+
+ const struct amd_pingroup *groups;
+diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c
+index 537b52055756..cfcf9db02c7d 100644
+--- a/drivers/pinctrl/pinctrl-amd.c
++++ b/drivers/pinctrl/pinctrl-amd.c
+@@ -41,11 +41,11 @@ static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
+ u32 pin_reg;
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + offset * 4);
+ pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
+ writel(pin_reg, gpio_dev->base + offset * 4);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+
+ return 0;
+ }
+@@ -57,7 +57,7 @@ static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
+ unsigned long flags;
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + offset * 4);
+ pin_reg |= BIT(OUTPUT_ENABLE_OFF);
+ if (value)
+@@ -65,7 +65,7 @@ static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
+ else
+ pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
+ writel(pin_reg, gpio_dev->base + offset * 4);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+
+ return 0;
+ }
+@@ -76,9 +76,9 @@ static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
+ unsigned long flags;
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + offset * 4);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+
+ return !!(pin_reg & BIT(PIN_STS_OFF));
+ }
+@@ -89,14 +89,14 @@ static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
+ unsigned long flags;
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + offset * 4);
+ if (value)
+ pin_reg |= BIT(OUTPUT_VALUE_OFF);
+ else
+ pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
+ writel(pin_reg, gpio_dev->base + offset * 4);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ }
+
+ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
+@@ -108,7 +108,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
+ unsigned long flags;
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + offset * 4);
+
+ if (debounce) {
+@@ -159,7 +159,7 @@ static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
+ pin_reg &= ~DB_CNTRl_MASK;
+ }
+ writel(pin_reg, gpio_dev->base + offset * 4);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+
+ return ret;
+ }
+@@ -208,9 +208,9 @@ static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
+
+ for (; i < pin_num; i++) {
+ seq_printf(s, "pin%d\t", i);
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + i * 4);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+
+ if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
+ interrupt_enable = "interrupt is enabled|";
+@@ -315,12 +315,12 @@ static void amd_gpio_irq_enable(struct irq_data *d)
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+ pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
+ pin_reg |= BIT(INTERRUPT_MASK_OFF);
+ writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ }
+
+ static void amd_gpio_irq_disable(struct irq_data *d)
+@@ -330,12 +330,12 @@ static void amd_gpio_irq_disable(struct irq_data *d)
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+ pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
+ pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
+ writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ }
+
+ static void amd_gpio_irq_mask(struct irq_data *d)
+@@ -345,11 +345,11 @@ static void amd_gpio_irq_mask(struct irq_data *d)
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+ pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
+ writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ }
+
+ static void amd_gpio_irq_unmask(struct irq_data *d)
+@@ -359,11 +359,11 @@ static void amd_gpio_irq_unmask(struct irq_data *d)
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+ pin_reg |= BIT(INTERRUPT_MASK_OFF);
+ writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ }
+
+ static void amd_gpio_irq_eoi(struct irq_data *d)
+@@ -373,11 +373,11 @@ static void amd_gpio_irq_eoi(struct irq_data *d)
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
+ reg |= EOI_MASK;
+ writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ }
+
+ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+@@ -388,7 +388,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+
+ /* Ignore the settings coming from the client and
+@@ -453,7 +453,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+
+ pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
+ writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+
+ return ret;
+ }
+@@ -494,14 +494,14 @@ static void amd_gpio_irq_handler(struct irq_desc *desc)
+
+ chained_irq_enter(chip, desc);
+ /*enable GPIO interrupt again*/
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
+ reg64 = reg;
+ reg64 = reg64 << 32;
+
+ reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
+ reg64 |= reg;
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+
+ /*
+ * first 46 bits indicates interrupt status.
+@@ -529,11 +529,11 @@ static void amd_gpio_irq_handler(struct irq_desc *desc)
+ if (handled == 0)
+ handle_bad_irq(desc);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
+ reg |= EOI_MASK;
+ writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+
+ chained_irq_exit(chip, desc);
+ }
+@@ -585,9 +585,9 @@ static int amd_pinconf_get(struct pinctrl_dev *pctldev,
+ struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
+ enum pin_config_param param = pinconf_to_config_param(*config);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + pin*4);
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+ switch (param) {
+ case PIN_CONFIG_INPUT_DEBOUNCE:
+ arg = pin_reg & DB_TMR_OUT_MASK;
+@@ -627,7 +627,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+ enum pin_config_param param;
+ struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
+
+- spin_lock_irqsave(&gpio_dev->lock, flags);
++ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ for (i = 0; i < num_configs; i++) {
+ param = pinconf_to_config_param(configs[i]);
+ arg = pinconf_to_config_argument(configs[i]);
+@@ -666,7 +666,7 @@ static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
+
+ writel(pin_reg, gpio_dev->base + pin*4);
+ }
+- spin_unlock_irqrestore(&gpio_dev->lock, flags);
++ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+
+ return ret;
+ }
+@@ -734,7 +734,7 @@ static int amd_gpio_probe(struct platform_device *pdev)
+ if (!gpio_dev)
+ return -ENOMEM;
+
+- spin_lock_init(&gpio_dev->lock);
++ raw_spin_lock_init(&gpio_dev->lock);
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+--
+2.11.0
+