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Commit | Line | Data |
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3dcc8d3b | 1 | From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 |
90a6d957 WB |
2 | From: Wolfgang Bumiller <w.bumiller@proxmox.com> |
3 | Date: Mon, 4 Jul 2016 15:02:26 +0200 | |
3dcc8d3b | 4 | Subject: [PATCH] Revert "target-i386: disable LINT0 after reset" |
90a6d957 WB |
5 | |
6 | This reverts commit b8eb5512fd8a115f164edbbe897cdf8884920ccb. | |
7 | --- | |
8 | hw/intc/apic_common.c | 9 +++++++++ | |
9 | 1 file changed, 9 insertions(+) | |
10 | ||
11 | diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c | |
6838f038 | 12 | index 78903ea909..cdfbec5e47 100644 |
90a6d957 WB |
13 | --- a/hw/intc/apic_common.c |
14 | +++ b/hw/intc/apic_common.c | |
15 | @@ -257,6 +257,15 @@ static void apic_reset_common(DeviceState *dev) | |
16 | info->vapic_base_update(s); | |
17 | ||
18 | apic_init_reset(dev); | |
19 | + | |
20 | + if (bsp) { | |
21 | + /* | |
22 | + * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization | |
23 | + * time typically by BIOS, so PIC interrupt can be delivered to the | |
24 | + * processor when local APIC is enabled. | |
25 | + */ | |
26 | + s->lvt[APIC_LVT_LINT0] = 0x700; | |
27 | + } | |
28 | } | |
29 | ||
30 | /* This function is only used for old state version 1 and 2 */ | |
31 | -- | |
32 | 2.11.0 | |
33 |