[qemu.git] / dis-asm.h

/* Interface between the opcode library and its callers.
   Written by Cygnus Support, 1993.

   The opcode library (libopcodes.a) provides instruction decoders for
   a large variety of instruction sets, callable with an identical
   interface, for making instruction-processing programs more independent
   of the instruction set being processed.  */

#ifndef DIS_ASM_H
#define DIS_ASM_H

#include "qemu-common.h"

typedef void *PTR;
typedef uint64_t bfd_vma;
typedef int64_t bfd_signed_vma;
typedef uint8_t bfd_byte;
#define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x)
#define snprintf_vma(s,ss,x) snprintf (s, ss, "%0" PRIx64, x)

#define BFD64

enum bfd_flavour {
  bfd_target_unknown_flavour,
  bfd_target_aout_flavour,
  bfd_target_coff_flavour,
  bfd_target_ecoff_flavour,
  bfd_target_elf_flavour,
  bfd_target_ieee_flavour,
  bfd_target_nlm_flavour,
  bfd_target_oasys_flavour,
  bfd_target_tekhex_flavour,
  bfd_target_srec_flavour,
  bfd_target_ihex_flavour,
  bfd_target_som_flavour,
  bfd_target_os9k_flavour,
  bfd_target_versados_flavour,
  bfd_target_msdos_flavour,
  bfd_target_evax_flavour
};

enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };

enum bfd_architecture
{
  bfd_arch_unknown,    /* File arch not known */
  bfd_arch_obscure,    /* Arch known, not one of these */
  bfd_arch_m68k,       /* Motorola 68xxx */
#define bfd_mach_m68000 1
#define bfd_mach_m68008 2
#define bfd_mach_m68010 3
#define bfd_mach_m68020 4
#define bfd_mach_m68030 5
#define bfd_mach_m68040 6
#define bfd_mach_m68060 7
#define bfd_mach_cpu32  8
#define bfd_mach_mcf5200  9
#define bfd_mach_mcf5206e 10
#define bfd_mach_mcf5307  11
#define bfd_mach_mcf5407  12
#define bfd_mach_mcf528x  13
#define bfd_mach_mcfv4e   14
#define bfd_mach_mcf521x   15
#define bfd_mach_mcf5249   16
#define bfd_mach_mcf547x   17
#define bfd_mach_mcf548x   18
  bfd_arch_vax,        /* DEC Vax */
  bfd_arch_i960,       /* Intel 960 */
     /* The order of the following is important.
       lower number indicates a machine type that
       only accepts a subset of the instructions
       available to machines with higher numbers.
       The exception is the "ca", which is
       incompatible with all other machines except
       "core". */

#define bfd_mach_i960_core      1
#define bfd_mach_i960_ka_sa     2
#define bfd_mach_i960_kb_sb     3
#define bfd_mach_i960_mc        4
#define bfd_mach_i960_xa        5
#define bfd_mach_i960_ca        6
#define bfd_mach_i960_jx        7
#define bfd_mach_i960_hx        8

  bfd_arch_a29k,       /* AMD 29000 */
  bfd_arch_sparc,      /* SPARC */
#define bfd_mach_sparc                 1
/* The difference between v8plus and v9 is that v9 is a true 64 bit env.  */
#define bfd_mach_sparc_sparclet        2
#define bfd_mach_sparc_sparclite       3
#define bfd_mach_sparc_v8plus          4
#define bfd_mach_sparc_v8plusa         5 /* with ultrasparc add'ns.  */
#define bfd_mach_sparc_sparclite_le    6
#define bfd_mach_sparc_v9              7
#define bfd_mach_sparc_v9a             8 /* with ultrasparc add'ns.  */
#define bfd_mach_sparc_v8plusb         9 /* with cheetah add'ns.  */
#define bfd_mach_sparc_v9b             10 /* with cheetah add'ns.  */
/* Nonzero if MACH has the v9 instruction set.  */
#define bfd_mach_sparc_v9_p(mach) \
  ((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
   && (mach) != bfd_mach_sparc_sparclite_le)
  bfd_arch_mips,       /* MIPS Rxxxx */
#define bfd_mach_mips3000              3000
#define bfd_mach_mips3900              3900
#define bfd_mach_mips4000              4000
#define bfd_mach_mips4010              4010
#define bfd_mach_mips4100              4100
#define bfd_mach_mips4300              4300
#define bfd_mach_mips4400              4400
#define bfd_mach_mips4600              4600
#define bfd_mach_mips4650              4650
#define bfd_mach_mips5000              5000
#define bfd_mach_mips6000              6000
#define bfd_mach_mips8000              8000
#define bfd_mach_mips10000             10000
#define bfd_mach_mips16                16
  bfd_arch_i386,       /* Intel 386 */
#define bfd_mach_i386_i386 0
#define bfd_mach_i386_i8086 1
#define bfd_mach_i386_i386_intel_syntax 2
#define bfd_mach_x86_64 3
#define bfd_mach_x86_64_intel_syntax 4
  bfd_arch_we32k,      /* AT&T WE32xxx */
  bfd_arch_tahoe,      /* CCI/Harris Tahoe */
  bfd_arch_i860,       /* Intel 860 */
  bfd_arch_romp,       /* IBM ROMP PC/RT */
  bfd_arch_alliant,    /* Alliant */
  bfd_arch_convex,     /* Convex */
  bfd_arch_m88k,       /* Motorola 88xxx */
  bfd_arch_pyramid,    /* Pyramid Technology */
  bfd_arch_h8300,      /* Hitachi H8/300 */
#define bfd_mach_h8300   1
#define bfd_mach_h8300h  2
#define bfd_mach_h8300s  3
  bfd_arch_powerpc,    /* PowerPC */
#define bfd_mach_ppc           0
#define bfd_mach_ppc64         1
#define bfd_mach_ppc_403       403
#define bfd_mach_ppc_403gc     4030
#define bfd_mach_ppc_e500      500
#define bfd_mach_ppc_505       505
#define bfd_mach_ppc_601       601
#define bfd_mach_ppc_602       602
#define bfd_mach_ppc_603       603
#define bfd_mach_ppc_ec603e    6031
#define bfd_mach_ppc_604       604
#define bfd_mach_ppc_620       620
#define bfd_mach_ppc_630       630
#define bfd_mach_ppc_750       750
#define bfd_mach_ppc_860       860
#define bfd_mach_ppc_a35       35
#define bfd_mach_ppc_rs64ii    642
#define bfd_mach_ppc_rs64iii   643
#define bfd_mach_ppc_7400      7400
  bfd_arch_rs6000,     /* IBM RS/6000 */
  bfd_arch_hppa,       /* HP PA RISC */
#define bfd_mach_hppa10        10
#define bfd_mach_hppa11        11
#define bfd_mach_hppa20        20
#define bfd_mach_hppa20w       25
  bfd_arch_d10v,       /* Mitsubishi D10V */
  bfd_arch_z8k,        /* Zilog Z8000 */
#define bfd_mach_z8001         1
#define bfd_mach_z8002         2
  bfd_arch_h8500,      /* Hitachi H8/500 */
  bfd_arch_sh,         /* Hitachi SH */
#define bfd_mach_sh            1
#define bfd_mach_sh2        0x20
#define bfd_mach_sh_dsp     0x2d
#define bfd_mach_sh2a       0x2a
#define bfd_mach_sh2a_nofpu 0x2b
#define bfd_mach_sh2e       0x2e
#define bfd_mach_sh3        0x30
#define bfd_mach_sh3_nommu  0x31
#define bfd_mach_sh3_dsp    0x3d
#define bfd_mach_sh3e       0x3e
#define bfd_mach_sh4        0x40
#define bfd_mach_sh4_nofpu  0x41
#define bfd_mach_sh4_nommu_nofpu  0x42
#define bfd_mach_sh4a       0x4a
#define bfd_mach_sh4a_nofpu 0x4b
#define bfd_mach_sh4al_dsp  0x4d
#define bfd_mach_sh5        0x50
  bfd_arch_alpha,      /* Dec Alpha */
#define bfd_mach_alpha 1
  bfd_arch_arm,        /* Advanced Risc Machines ARM */
#define bfd_mach_arm_unknown	0
#define bfd_mach_arm_2		1
#define bfd_mach_arm_2a		2
#define bfd_mach_arm_3		3
#define bfd_mach_arm_3M 	4
#define bfd_mach_arm_4 		5
#define bfd_mach_arm_4T 	6
#define bfd_mach_arm_5 		7
#define bfd_mach_arm_5T		8
#define bfd_mach_arm_5TE	9
#define bfd_mach_arm_XScale	10
#define bfd_mach_arm_ep9312	11
#define bfd_mach_arm_iWMMXt	12
#define bfd_mach_arm_iWMMXt2	13
  bfd_arch_ns32k,      /* National Semiconductors ns32000 */
  bfd_arch_w65,        /* WDC 65816 */
  bfd_arch_tic30,      /* Texas Instruments TMS320C30 */
  bfd_arch_v850,       /* NEC V850 */
#define bfd_mach_v850          0
  bfd_arch_arc,        /* Argonaut RISC Core */
#define bfd_mach_arc_base 0
  bfd_arch_m32r,       /* Mitsubishi M32R/D */
#define bfd_mach_m32r          0  /* backwards compatibility */
  bfd_arch_mn10200,    /* Matsushita MN10200 */
  bfd_arch_mn10300,    /* Matsushita MN10300 */
  bfd_arch_cris,       /* Axis CRIS */
#define bfd_mach_cris_v0_v10   255
#define bfd_mach_cris_v32      32
#define bfd_mach_cris_v10_v32  1032
  bfd_arch_microblaze, /* Xilinx MicroBlaze.  */
  bfd_arch_ia64,      /* HP/Intel ia64 */
#define bfd_mach_ia64_elf64    64
#define bfd_mach_ia64_elf32    32
  bfd_arch_last
  };
#define bfd_mach_s390_31 31
#define bfd_mach_s390_64 64

typedef struct symbol_cache_entry
{
    const char *name;
    union
    {
        PTR p;
        bfd_vma i;
    } udata;
} asymbol;

enum dis_insn_type {
  dis_noninsn,			/* Not a valid instruction */
  dis_nonbranch,		/* Not a branch instruction */
  dis_branch,			/* Unconditional branch */
  dis_condbranch,		/* Conditional branch */
  dis_jsr,			/* Jump to subroutine */
  dis_condjsr,			/* Conditional jump to subroutine */
  dis_dref,			/* Data reference instruction */
  dis_dref2			/* Two data references in instruction */
};

/* This struct is passed into the instruction decoding routine,
   and is passed back out into each callback.  The various fields are used
   for conveying information from your main routine into your callbacks,
   for passing information into the instruction decoders (such as the
   addresses of the callback functions), or for passing information
   back from the instruction decoders to their callers.

   It must be initialized before it is first passed; this can be done
   by hand, or using one of the initialization macros below.  */

typedef struct disassemble_info {
  fprintf_function fprintf_func;
  FILE *stream;
  PTR application_data;

  /* Target description.  We could replace this with a pointer to the bfd,
     but that would require one.  There currently isn't any such requirement
     so to avoid introducing one we record these explicitly.  */
  /* The bfd_flavour.  This can be bfd_target_unknown_flavour.  */
  enum bfd_flavour flavour;
  /* The bfd_arch value.  */
  enum bfd_architecture arch;
  /* The bfd_mach value.  */
  unsigned long mach;
  /* Endianness (for bi-endian cpus).  Mono-endian cpus can ignore this.  */
  enum bfd_endian endian;

  /* An array of pointers to symbols either at the location being disassembled
     or at the start of the function being disassembled.  The array is sorted
     so that the first symbol is intended to be the one used.  The others are
     present for any misc. purposes.  This is not set reliably, but if it is
     not NULL, it is correct.  */
  asymbol **symbols;
  /* Number of symbols in array.  */
  int num_symbols;

  /* For use by the disassembler.
     The top 16 bits are reserved for public use (and are documented here).
     The bottom 16 bits are for the internal use of the disassembler.  */
  unsigned long flags;
#define INSN_HAS_RELOC	0x80000000
  PTR private_data;

  /* Function used to get bytes to disassemble.  MEMADDR is the
     address of the stuff to be disassembled, MYADDR is the address to
     put the bytes in, and LENGTH is the number of bytes to read.
     INFO is a pointer to this struct.
     Returns an errno value or 0 for success.  */
  int (*read_memory_func)
    (bfd_vma memaddr, bfd_byte *myaddr, int length,
	     struct disassemble_info *info);

  /* Function which should be called if we get an error that we can't
     recover from.  STATUS is the errno value from read_memory_func and
     MEMADDR is the address that we were trying to read.  INFO is a
     pointer to this struct.  */
  void (*memory_error_func)
    (int status, bfd_vma memaddr, struct disassemble_info *info);

  /* Function called to print ADDR.  */
  void (*print_address_func)
    (bfd_vma addr, struct disassemble_info *info);

  /* Function called to determine if there is a symbol at the given ADDR.
     If there is, the function returns 1, otherwise it returns 0.
     This is used by ports which support an overlay manager where
     the overlay number is held in the top part of an address.  In
     some circumstances we want to include the overlay number in the
     address, (normally because there is a symbol associated with
     that address), but sometimes we want to mask out the overlay bits.  */
  int (* symbol_at_address_func)
    (bfd_vma addr, struct disassemble_info * info);

  /* These are for buffer_read_memory.  */
  bfd_byte *buffer;
  bfd_vma buffer_vma;
  int buffer_length;

  /* This variable may be set by the instruction decoder.  It suggests
      the number of bytes objdump should display on a single line.  If
      the instruction decoder sets this, it should always set it to
      the same value in order to get reasonable looking output.  */
  int bytes_per_line;

  /* the next two variables control the way objdump displays the raw data */
  /* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
  /* output will look like this:
     00:   00000000 00000000
     with the chunks displayed according to "display_endian". */
  int bytes_per_chunk;
  enum bfd_endian display_endian;

  /* Results from instruction decoders.  Not all decoders yet support
     this information.  This info is set each time an instruction is
     decoded, and is only valid for the last such instruction.

     To determine whether this decoder supports this information, set
     insn_info_valid to 0, decode an instruction, then check it.  */

  char insn_info_valid;		/* Branch info has been set. */
  char branch_delay_insns;	/* How many sequential insn's will run before
				   a branch takes effect.  (0 = normal) */
  char data_size;		/* Size of data reference in insn, in bytes */
  enum dis_insn_type insn_type;	/* Type of instruction */
  bfd_vma target;		/* Target address of branch or dref, if known;
				   zero if unknown.  */
  bfd_vma target2;		/* Second target address for dref2 */

  /* Command line options specific to the target disassembler.  */
  char * disassembler_options;

} disassemble_info;

\f
/* Standard disassemblers.  Disassemble one instruction at the given
   target address.  Return number of bytes processed.  */
typedef int (*disassembler_ftype) (bfd_vma, disassemble_info *);

int print_insn_big_mips         (bfd_vma, disassemble_info*);
int print_insn_little_mips      (bfd_vma, disassemble_info*);
int print_insn_i386             (bfd_vma, disassemble_info*);
int print_insn_m68k             (bfd_vma, disassemble_info*);
int print_insn_z8001            (bfd_vma, disassemble_info*);
int print_insn_z8002            (bfd_vma, disassemble_info*);
int print_insn_h8300            (bfd_vma, disassemble_info*);
int print_insn_h8300h           (bfd_vma, disassemble_info*);
int print_insn_h8300s           (bfd_vma, disassemble_info*);
int print_insn_h8500            (bfd_vma, disassemble_info*);
int print_insn_alpha            (bfd_vma, disassemble_info*);
disassembler_ftype arc_get_disassembler (int, int);
int print_insn_arm              (bfd_vma, disassemble_info*);
int print_insn_sparc            (bfd_vma, disassemble_info*);
int print_insn_big_a29k         (bfd_vma, disassemble_info*);
int print_insn_little_a29k      (bfd_vma, disassemble_info*);
int print_insn_i960             (bfd_vma, disassemble_info*);
int print_insn_sh               (bfd_vma, disassemble_info*);
int print_insn_shl              (bfd_vma, disassemble_info*);
int print_insn_hppa             (bfd_vma, disassemble_info*);
int print_insn_m32r             (bfd_vma, disassemble_info*);
int print_insn_m88k             (bfd_vma, disassemble_info*);
int print_insn_mn10200          (bfd_vma, disassemble_info*);
int print_insn_mn10300          (bfd_vma, disassemble_info*);
int print_insn_ns32k            (bfd_vma, disassemble_info*);
int print_insn_big_powerpc      (bfd_vma, disassemble_info*);
int print_insn_little_powerpc   (bfd_vma, disassemble_info*);
int print_insn_rs6000           (bfd_vma, disassemble_info*);
int print_insn_w65              (bfd_vma, disassemble_info*);
int print_insn_d10v             (bfd_vma, disassemble_info*);
int print_insn_v850             (bfd_vma, disassemble_info*);
int print_insn_tic30            (bfd_vma, disassemble_info*);
int print_insn_ppc              (bfd_vma, disassemble_info*);
int print_insn_s390             (bfd_vma, disassemble_info*);
int print_insn_crisv32          (bfd_vma, disassemble_info*);
int print_insn_crisv10          (bfd_vma, disassemble_info*);
int print_insn_microblaze       (bfd_vma, disassemble_info*);
int print_insn_ia64             (bfd_vma, disassemble_info*);

#if 0
/* Fetch the disassembler for a given BFD, if that support is available.  */
disassembler_ftype disassembler(bfd *);
#endif

\f
/* This block of definitions is for particular callers who read instructions
   into a buffer before calling the instruction decoder.  */

/* Here is a function which callers may wish to use for read_memory_func.
   It gets bytes from a buffer.  */
int buffer_read_memory(bfd_vma, bfd_byte *, int, struct disassemble_info *);

/* This function goes with buffer_read_memory.
   It prints a message using info->fprintf_func and info->stream.  */
void perror_memory(int, bfd_vma, struct disassemble_info *);


/* Just print the address in hex.  This is included for completeness even
   though both GDB and objdump provide their own (to print symbolic
   addresses).  */
void generic_print_address(bfd_vma, struct disassemble_info *);

/* Always true.  */
int generic_symbol_at_address(bfd_vma, struct disassemble_info *);

/* Macro to initialize a disassemble_info struct.  This should be called
   by all applications creating such a struct.  */
#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
  (INFO).flavour = bfd_target_unknown_flavour, \
  (INFO).arch = bfd_arch_unknown, \
  (INFO).mach = 0, \
  (INFO).endian = BFD_ENDIAN_UNKNOWN, \
  INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC)

/* Call this macro to initialize only the internal variables for the
   disassembler.  Architecture dependent things such as byte order, or machine
   variant are not touched by this macro.  This makes things much easier for
   GDB which must initialize these things separately.  */

#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
  (INFO).fprintf_func = (FPRINTF_FUNC), \
  (INFO).stream = (STREAM), \
  (INFO).symbols = NULL, \
  (INFO).num_symbols = 0, \
  (INFO).private_data = NULL, \
  (INFO).buffer = NULL, \
  (INFO).buffer_vma = 0, \
  (INFO).buffer_length = 0, \
  (INFO).read_memory_func = buffer_read_memory, \
  (INFO).memory_error_func = perror_memory, \
  (INFO).print_address_func = generic_print_address, \
  (INFO).symbol_at_address_func = generic_symbol_at_address, \
  (INFO).flags = 0, \
  (INFO).bytes_per_line = 0, \
  (INFO).bytes_per_chunk = 0, \
  (INFO).display_endian = BFD_ENDIAN_UNKNOWN, \
  (INFO).disassembler_options = NULL, \
  (INFO).insn_info_valid = 0

#define _(x) x
#define ATTRIBUTE_UNUSED __attribute__((unused))

/* from libbfd */

bfd_vma bfd_getl64 (const bfd_byte *addr);
bfd_vma bfd_getl32 (const bfd_byte *addr);
bfd_vma bfd_getb32 (const bfd_byte *addr);
bfd_vma bfd_getl16 (const bfd_byte *addr);
bfd_vma bfd_getb16 (const bfd_byte *addr);
typedef bool bfd_boolean;

#endif /* ! defined (DIS_ASM_H) */
Commit	Line	Data
dc99065b FB	1	/* Interface between the opcode library and its callers.
	2	Written by Cygnus Support, 1993.
	3
	4	The opcode library (libopcodes.a) provides instruction decoders for
	5	a large variety of instruction sets, callable with an identical
	6	interface, for making instruction-processing programs more independent
	7	of the instruction set being processed. */
	8
	9	#ifndef DIS_ASM_H
	10	#define DIS_ASM_H
	11
6e2d864e	12	#include "qemu-common.h"
43d4145a	13
43d4145a FB	14	typedef void *PTR;
43d4145a FB	15	typedef uint64_t bfd_vma;
bc51c5c9	16	typedef int64_t bfd_signed_vma;
43d4145a	17	typedef uint8_t bfd_byte;
bc51c5c9	18	#define sprintf_vma(s,x) sprintf (s, "%0" PRIx64, x)
363a37d5	19	#define snprintf_vma(s,ss,x) snprintf (s, ss, "%0" PRIx64, x)
43d4145a	20
c27004ec FB	21	#define BFD64
c27004ec FB	22
43d4145a FB	23	enum bfd_flavour {
	24	bfd_target_unknown_flavour,
	25	bfd_target_aout_flavour,
	26	bfd_target_coff_flavour,
	27	bfd_target_ecoff_flavour,
	28	bfd_target_elf_flavour,
	29	bfd_target_ieee_flavour,
	30	bfd_target_nlm_flavour,
	31	bfd_target_oasys_flavour,
	32	bfd_target_tekhex_flavour,
	33	bfd_target_srec_flavour,
	34	bfd_target_ihex_flavour,
	35	bfd_target_som_flavour,
	36	bfd_target_os9k_flavour,
	37	bfd_target_versados_flavour,
	38	bfd_target_msdos_flavour,
	39	bfd_target_evax_flavour
	40	};
	41
	42	enum bfd_endian { BFD_ENDIAN_BIG, BFD_ENDIAN_LITTLE, BFD_ENDIAN_UNKNOWN };
	43
5fafdf24	44	enum bfd_architecture
43d4145a FB	45	{
	46	bfd_arch_unknown, /* File arch not known */
	47	bfd_arch_obscure, /* Arch known, not one of these */
	48	bfd_arch_m68k, /* Motorola 68xxx */
	49	#define bfd_mach_m68000 1
	50	#define bfd_mach_m68008 2
	51	#define bfd_mach_m68010 3
	52	#define bfd_mach_m68020 4
	53	#define bfd_mach_m68030 5
	54	#define bfd_mach_m68040 6
	55	#define bfd_mach_m68060 7
48024e4a FB	56	#define bfd_mach_cpu32 8
	57	#define bfd_mach_mcf5200 9
	58	#define bfd_mach_mcf5206e 10
	59	#define bfd_mach_mcf5307 11
	60	#define bfd_mach_mcf5407 12
	61	#define bfd_mach_mcf528x 13
	62	#define bfd_mach_mcfv4e 14
	63	#define bfd_mach_mcf521x 15
	64	#define bfd_mach_mcf5249 16
	65	#define bfd_mach_mcf547x 17
	66	#define bfd_mach_mcf548x 18
3b46e624	67	bfd_arch_vax, /* DEC Vax */
43d4145a FB	68	bfd_arch_i960, /* Intel 960 */
43d4145a FB	69	/* The order of the following is important.
5fafdf24	70	lower number indicates a machine type that
43d4145a FB	71	only accepts a subset of the instructions
	72	available to machines with higher numbers.
	73	The exception is the "ca", which is
5fafdf24	74	incompatible with all other machines except
43d4145a FB	75	"core". */
	76
	77	#define bfd_mach_i960_core 1
	78	#define bfd_mach_i960_ka_sa 2
	79	#define bfd_mach_i960_kb_sb 3
	80	#define bfd_mach_i960_mc 4
	81	#define bfd_mach_i960_xa 5
	82	#define bfd_mach_i960_ca 6
	83	#define bfd_mach_i960_jx 7
	84	#define bfd_mach_i960_hx 8
	85
	86	bfd_arch_a29k, /* AMD 29000 */
	87	bfd_arch_sparc, /* SPARC */
	88	#define bfd_mach_sparc 1
aa0aa4fa	89	/* The difference between v8plus and v9 is that v9 is a true 64 bit env. */
43d4145a FB	90	#define bfd_mach_sparc_sparclet 2
	91	#define bfd_mach_sparc_sparclite 3
	92	#define bfd_mach_sparc_v8plus 4
aa0aa4fa FB	93	#define bfd_mach_sparc_v8plusa 5 /* with ultrasparc add'ns. */
	94	#define bfd_mach_sparc_sparclite_le 6
	95	#define bfd_mach_sparc_v9 7
	96	#define bfd_mach_sparc_v9a 8 /* with ultrasparc add'ns. */
	97	#define bfd_mach_sparc_v8plusb 9 /* with cheetah add'ns. */
	98	#define bfd_mach_sparc_v9b 10 /* with cheetah add'ns. */
	99	/* Nonzero if MACH has the v9 instruction set. */
43d4145a	100	#define bfd_mach_sparc_v9_p(mach) \
aa0aa4fa FB	101	((mach) >= bfd_mach_sparc_v8plus && (mach) <= bfd_mach_sparc_v9b \
aa0aa4fa FB	102	&& (mach) != bfd_mach_sparc_sparclite_le)
43d4145a FB	103	bfd_arch_mips, /* MIPS Rxxxx */
	104	#define bfd_mach_mips3000 3000
	105	#define bfd_mach_mips3900 3900
	106	#define bfd_mach_mips4000 4000
	107	#define bfd_mach_mips4010 4010
	108	#define bfd_mach_mips4100 4100
	109	#define bfd_mach_mips4300 4300
	110	#define bfd_mach_mips4400 4400
	111	#define bfd_mach_mips4600 4600
	112	#define bfd_mach_mips4650 4650
	113	#define bfd_mach_mips5000 5000
	114	#define bfd_mach_mips6000 6000
	115	#define bfd_mach_mips8000 8000
	116	#define bfd_mach_mips10000 10000
	117	#define bfd_mach_mips16 16
	118	bfd_arch_i386, /* Intel 386 */
	119	#define bfd_mach_i386_i386 0
	120	#define bfd_mach_i386_i8086 1
bc51c5c9 FB	121	#define bfd_mach_i386_i386_intel_syntax 2
	122	#define bfd_mach_x86_64 3
	123	#define bfd_mach_x86_64_intel_syntax 4
43d4145a FB	124	bfd_arch_we32k, /* AT&T WE32xxx */
	125	bfd_arch_tahoe, /* CCI/Harris Tahoe */
	126	bfd_arch_i860, /* Intel 860 */
	127	bfd_arch_romp, /* IBM ROMP PC/RT */
	128	bfd_arch_alliant, /* Alliant */
	129	bfd_arch_convex, /* Convex */
	130	bfd_arch_m88k, /* Motorola 88xxx */
	131	bfd_arch_pyramid, /* Pyramid Technology */
	132	bfd_arch_h8300, /* Hitachi H8/300 */
	133	#define bfd_mach_h8300 1
	134	#define bfd_mach_h8300h 2
	135	#define bfd_mach_h8300s 3
	136	bfd_arch_powerpc, /* PowerPC */
a2458627 FB	137	#define bfd_mach_ppc 0
	138	#define bfd_mach_ppc64 1
	139	#define bfd_mach_ppc_403 403
	140	#define bfd_mach_ppc_403gc 4030
eca8f888	141	#define bfd_mach_ppc_e500 500
a2458627 FB	142	#define bfd_mach_ppc_505 505
	143	#define bfd_mach_ppc_601 601
	144	#define bfd_mach_ppc_602 602
	145	#define bfd_mach_ppc_603 603
	146	#define bfd_mach_ppc_ec603e 6031
	147	#define bfd_mach_ppc_604 604
	148	#define bfd_mach_ppc_620 620
	149	#define bfd_mach_ppc_630 630
	150	#define bfd_mach_ppc_750 750
	151	#define bfd_mach_ppc_860 860
	152	#define bfd_mach_ppc_a35 35
	153	#define bfd_mach_ppc_rs64ii 642
	154	#define bfd_mach_ppc_rs64iii 643
	155	#define bfd_mach_ppc_7400 7400
43d4145a FB	156	bfd_arch_rs6000, /* IBM RS/6000 */
43d4145a FB	157	bfd_arch_hppa, /* HP PA RISC */
f54b3f92 AJ	158	#define bfd_mach_hppa10 10
	159	#define bfd_mach_hppa11 11
	160	#define bfd_mach_hppa20 20
	161	#define bfd_mach_hppa20w 25
43d4145a FB	162	bfd_arch_d10v, /* Mitsubishi D10V */
	163	bfd_arch_z8k, /* Zilog Z8000 */
	164	#define bfd_mach_z8001 1
	165	#define bfd_mach_z8002 2
	166	bfd_arch_h8500, /* Hitachi H8/500 */
	167	bfd_arch_sh, /* Hitachi SH */
fdf9b3e8 FB	168	#define bfd_mach_sh 1
	169	#define bfd_mach_sh2 0x20
	170	#define bfd_mach_sh_dsp 0x2d
	171	#define bfd_mach_sh2a 0x2a
	172	#define bfd_mach_sh2a_nofpu 0x2b
	173	#define bfd_mach_sh2e 0x2e
43d4145a	174	#define bfd_mach_sh3 0x30
fdf9b3e8 FB	175	#define bfd_mach_sh3_nommu 0x31
fdf9b3e8 FB	176	#define bfd_mach_sh3_dsp 0x3d
43d4145a FB	177	#define bfd_mach_sh3e 0x3e
43d4145a FB	178	#define bfd_mach_sh4 0x40
fdf9b3e8 FB	179	#define bfd_mach_sh4_nofpu 0x41
	180	#define bfd_mach_sh4_nommu_nofpu 0x42
	181	#define bfd_mach_sh4a 0x4a
	182	#define bfd_mach_sh4a_nofpu 0x4b
	183	#define bfd_mach_sh4al_dsp 0x4d
	184	#define bfd_mach_sh5 0x50
43d4145a	185	bfd_arch_alpha, /* Dec Alpha */
eddf68a6	186	#define bfd_mach_alpha 1
43d4145a	187	bfd_arch_arm, /* Advanced Risc Machines ARM */
4b0f1a8b PB	188	#define bfd_mach_arm_unknown 0
	189	#define bfd_mach_arm_2 1
	190	#define bfd_mach_arm_2a 2
	191	#define bfd_mach_arm_3 3
	192	#define bfd_mach_arm_3M 4
	193	#define bfd_mach_arm_4 5
	194	#define bfd_mach_arm_4T 6
	195	#define bfd_mach_arm_5 7
	196	#define bfd_mach_arm_5T 8
	197	#define bfd_mach_arm_5TE 9
	198	#define bfd_mach_arm_XScale 10
	199	#define bfd_mach_arm_ep9312 11
	200	#define bfd_mach_arm_iWMMXt 12
	201	#define bfd_mach_arm_iWMMXt2 13
43d4145a FB	202	bfd_arch_ns32k, /* National Semiconductors ns32000 */
	203	bfd_arch_w65, /* WDC 65816 */
	204	bfd_arch_tic30, /* Texas Instruments TMS320C30 */
	205	bfd_arch_v850, /* NEC V850 */
	206	#define bfd_mach_v850 0
	207	bfd_arch_arc, /* Argonaut RISC Core */
	208	#define bfd_mach_arc_base 0
	209	bfd_arch_m32r, /* Mitsubishi M32R/D */
	210	#define bfd_mach_m32r 0 /* backwards compatibility */
	211	bfd_arch_mn10200, /* Matsushita MN10200 */
	212	bfd_arch_mn10300, /* Matsushita MN10300 */
a25fd137 TS	213	bfd_arch_cris, /* Axis CRIS */
	214	#define bfd_mach_cris_v0_v10 255
	215	#define bfd_mach_cris_v32 32
	216	#define bfd_mach_cris_v10_v32 1032
e90e390c	217	bfd_arch_microblaze, /* Xilinx MicroBlaze. */
903ec55c AJ	218	bfd_arch_ia64, /* HP/Intel ia64 */
	219	#define bfd_mach_ia64_elf64 64
	220	#define bfd_mach_ia64_elf32 32
43d4145a FB	221	bfd_arch_last
43d4145a FB	222	};
8f860bb8 TS	223	#define bfd_mach_s390_31 31
8f860bb8 TS	224	#define bfd_mach_s390_64 64
43d4145a FB	225
	226	typedef struct symbol_cache_entry
	227	{
	228	const char *name;
	229	union
	230	{
	231	PTR p;
	232	bfd_vma i;
	233	} udata;
	234	} asymbol;
dc99065b	235
dc99065b FB	236	enum dis_insn_type {
	237	dis_noninsn, /* Not a valid instruction */
	238	dis_nonbranch, /* Not a branch instruction */
	239	dis_branch, /* Unconditional branch */
	240	dis_condbranch, /* Conditional branch */
	241	dis_jsr, /* Jump to subroutine */
	242	dis_condjsr, /* Conditional jump to subroutine */
	243	dis_dref, /* Data reference instruction */
	244	dis_dref2 /* Two data references in instruction */
	245	};
	246
5fafdf24	247	/* This struct is passed into the instruction decoding routine,
dc99065b FB	248	and is passed back out into each callback. The various fields are used
	249	for conveying information from your main routine into your callbacks,
	250	for passing information into the instruction decoders (such as the
	251	addresses of the callback functions), or for passing information
	252	back from the instruction decoders to their callers.
	253
	254	It must be initialized before it is first passed; this can be done
	255	by hand, or using one of the initialization macros below. */
	256
	257	typedef struct disassemble_info {
6e2d864e	258	fprintf_function fprintf_func;
dc99065b FB	259	FILE *stream;
	260	PTR application_data;
	261
	262	/* Target description. We could replace this with a pointer to the bfd,
	263	but that would require one. There currently isn't any such requirement
	264	so to avoid introducing one we record these explicitly. */
	265	/* The bfd_flavour. This can be bfd_target_unknown_flavour. */
	266	enum bfd_flavour flavour;
	267	/* The bfd_arch value. */
	268	enum bfd_architecture arch;
	269	/* The bfd_mach value. */
	270	unsigned long mach;
	271	/* Endianness (for bi-endian cpus). Mono-endian cpus can ignore this. */
	272	enum bfd_endian endian;
	273
	274	/* An array of pointers to symbols either at the location being disassembled
	275	or at the start of the function being disassembled. The array is sorted
	276	so that the first symbol is intended to be the one used. The others are
	277	present for any misc. purposes. This is not set reliably, but if it is
	278	not NULL, it is correct. */
	279	asymbol **symbols;
	280	/* Number of symbols in array. */
	281	int num_symbols;
	282
	283	/* For use by the disassembler.
	284	The top 16 bits are reserved for public use (and are documented here).
	285	The bottom 16 bits are for the internal use of the disassembler. */
	286	unsigned long flags;
	287	#define INSN_HAS_RELOC 0x80000000
	288	PTR private_data;
	289
	290	/* Function used to get bytes to disassemble. MEMADDR is the
	291	address of the stuff to be disassembled, MYADDR is the address to
	292	put the bytes in, and LENGTH is the number of bytes to read.
	293	INFO is a pointer to this struct.
	294	Returns an errno value or 0 for success. */
	295	int (*read_memory_func)
9262f384 JQ	296	(bfd_vma memaddr, bfd_byte *myaddr, int length,
9262f384 JQ	297	struct disassemble_info *info);
dc99065b FB	298
	299	/* Function which should be called if we get an error that we can't
	300	recover from. STATUS is the errno value from read_memory_func and
	301	MEMADDR is the address that we were trying to read. INFO is a
	302	pointer to this struct. */
	303	void (*memory_error_func)
9262f384	304	(int status, bfd_vma memaddr, struct disassemble_info *info);
dc99065b FB	305
	306	/* Function called to print ADDR. */
	307	void (*print_address_func)
9262f384	308	(bfd_vma addr, struct disassemble_info *info);
dc99065b FB	309
	310	/* Function called to determine if there is a symbol at the given ADDR.
	311	If there is, the function returns 1, otherwise it returns 0.
	312	This is used by ports which support an overlay manager where
	313	the overlay number is held in the top part of an address. In
	314	some circumstances we want to include the overlay number in the
	315	address, (normally because there is a symbol associated with
	316	that address), but sometimes we want to mask out the overlay bits. */
	317	int (* symbol_at_address_func)
9262f384	318	(bfd_vma addr, struct disassemble_info * info);
dc99065b FB	319
	320	/* These are for buffer_read_memory. */
	321	bfd_byte *buffer;
	322	bfd_vma buffer_vma;
	323	int buffer_length;
	324
	325	/* This variable may be set by the instruction decoder. It suggests
	326	the number of bytes objdump should display on a single line. If
	327	the instruction decoder sets this, it should always set it to
	328	the same value in order to get reasonable looking output. */
	329	int bytes_per_line;
	330
	331	/* the next two variables control the way objdump displays the raw data */
	332	/* For example, if bytes_per_line is 8 and bytes_per_chunk is 4, the */
	333	/* output will look like this:
	334	00: 00000000 00000000
	335	with the chunks displayed according to "display_endian". */
	336	int bytes_per_chunk;
	337	enum bfd_endian display_endian;
	338
	339	/* Results from instruction decoders. Not all decoders yet support
	340	this information. This info is set each time an instruction is
	341	decoded, and is only valid for the last such instruction.
	342
	343	To determine whether this decoder supports this information, set
	344	insn_info_valid to 0, decode an instruction, then check it. */
	345
	346	char insn_info_valid; /* Branch info has been set. */
	347	char branch_delay_insns; /* How many sequential insn's will run before
	348	a branch takes effect. (0 = normal) */
	349	char data_size; /* Size of data reference in insn, in bytes */
	350	enum dis_insn_type insn_type; /* Type of instruction */
	351	bfd_vma target; /* Target address of branch or dref, if known;
	352	zero if unknown. */
	353	bfd_vma target2; /* Second target address for dref2 */
	354
aa0aa4fa FB	355	/* Command line options specific to the target disassembler. */
	356	char * disassembler_options;
	357
dc99065b FB	358	} disassemble_info;
	359
	360	\f
	361	/* Standard disassemblers. Disassemble one instruction at the given
	362	target address. Return number of bytes processed. */
9262f384 JQ	363	typedef int (disassembler_ftype) (bfd_vma, disassemble_info );
9262f384 JQ	364
64b85a8f BS	365	int print_insn_big_mips (bfd_vma, disassemble_info*);
	366	int print_insn_little_mips (bfd_vma, disassemble_info*);
	367	int print_insn_i386 (bfd_vma, disassemble_info*);
	368	int print_insn_m68k (bfd_vma, disassemble_info*);
	369	int print_insn_z8001 (bfd_vma, disassemble_info*);
	370	int print_insn_z8002 (bfd_vma, disassemble_info*);
	371	int print_insn_h8300 (bfd_vma, disassemble_info*);
	372	int print_insn_h8300h (bfd_vma, disassemble_info*);
	373	int print_insn_h8300s (bfd_vma, disassemble_info*);
	374	int print_insn_h8500 (bfd_vma, disassemble_info*);
	375	int print_insn_alpha (bfd_vma, disassemble_info*);
	376	disassembler_ftype arc_get_disassembler (int, int);
	377	int print_insn_arm (bfd_vma, disassemble_info*);
	378	int print_insn_sparc (bfd_vma, disassemble_info*);
	379	int print_insn_big_a29k (bfd_vma, disassemble_info*);
	380	int print_insn_little_a29k (bfd_vma, disassemble_info*);
	381	int print_insn_i960 (bfd_vma, disassemble_info*);
	382	int print_insn_sh (bfd_vma, disassemble_info*);
	383	int print_insn_shl (bfd_vma, disassemble_info*);
	384	int print_insn_hppa (bfd_vma, disassemble_info*);
	385	int print_insn_m32r (bfd_vma, disassemble_info*);
	386	int print_insn_m88k (bfd_vma, disassemble_info*);
	387	int print_insn_mn10200 (bfd_vma, disassemble_info*);
	388	int print_insn_mn10300 (bfd_vma, disassemble_info*);
	389	int print_insn_ns32k (bfd_vma, disassemble_info*);
	390	int print_insn_big_powerpc (bfd_vma, disassemble_info*);
	391	int print_insn_little_powerpc (bfd_vma, disassemble_info*);
	392	int print_insn_rs6000 (bfd_vma, disassemble_info*);
	393	int print_insn_w65 (bfd_vma, disassemble_info*);
	394	int print_insn_d10v (bfd_vma, disassemble_info*);
	395	int print_insn_v850 (bfd_vma, disassemble_info*);
	396	int print_insn_tic30 (bfd_vma, disassemble_info*);
	397	int print_insn_ppc (bfd_vma, disassemble_info*);
	398	int print_insn_s390 (bfd_vma, disassemble_info*);
	399	int print_insn_crisv32 (bfd_vma, disassemble_info*);
	400	int print_insn_crisv10 (bfd_vma, disassemble_info*);
	401	int print_insn_microblaze (bfd_vma, disassemble_info*);
	402	int print_insn_ia64 (bfd_vma, disassemble_info*);
dc99065b	403
43d4145a	404	#if 0
dc99065b	405	/* Fetch the disassembler for a given BFD, if that support is available. */
64b85a8f	406	disassembler_ftype disassembler(bfd *);
43d4145a	407	#endif
dc99065b FB	408
	409	\f
	410	/* This block of definitions is for particular callers who read instructions
	411	into a buffer before calling the instruction decoder. */
	412
	413	/* Here is a function which callers may wish to use for read_memory_func.
	414	It gets bytes from a buffer. */
64b85a8f	415	int buffer_read_memory(bfd_vma, bfd_byte , int, struct disassemble_info );
dc99065b FB	416
	417	/* This function goes with buffer_read_memory.
	418	It prints a message using info->fprintf_func and info->stream. */
64b85a8f	419	void perror_memory(int, bfd_vma, struct disassemble_info *);
dc99065b FB	420
	421
	422	/* Just print the address in hex. This is included for completeness even
	423	though both GDB and objdump provide their own (to print symbolic
	424	addresses). */
64b85a8f	425	void generic_print_address(bfd_vma, struct disassemble_info *);
dc99065b FB	426
dc99065b FB	427	/* Always true. */
64b85a8f	428	int generic_symbol_at_address(bfd_vma, struct disassemble_info *);
dc99065b FB	429
	430	/* Macro to initialize a disassemble_info struct. This should be called
	431	by all applications creating such a struct. */
	432	#define INIT_DISASSEMBLE_INFO(INFO, STREAM, FPRINTF_FUNC) \
	433	(INFO).flavour = bfd_target_unknown_flavour, \
	434	(INFO).arch = bfd_arch_unknown, \
	435	(INFO).mach = 0, \
	436	(INFO).endian = BFD_ENDIAN_UNKNOWN, \
	437	INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC)
	438
	439	/* Call this macro to initialize only the internal variables for the
	440	disassembler. Architecture dependent things such as byte order, or machine
	441	variant are not touched by this macro. This makes things much easier for
aa1f17c1	442	GDB which must initialize these things separately. */
dc99065b FB	443
	444	#define INIT_DISASSEMBLE_INFO_NO_ARCH(INFO, STREAM, FPRINTF_FUNC) \
	445	(INFO).fprintf_func = (FPRINTF_FUNC), \
	446	(INFO).stream = (STREAM), \
	447	(INFO).symbols = NULL, \
	448	(INFO).num_symbols = 0, \
77b087cd	449	(INFO).private_data = NULL, \
dc99065b FB	450	(INFO).buffer = NULL, \
	451	(INFO).buffer_vma = 0, \
	452	(INFO).buffer_length = 0, \
	453	(INFO).read_memory_func = buffer_read_memory, \
	454	(INFO).memory_error_func = perror_memory, \
	455	(INFO).print_address_func = generic_print_address, \
	456	(INFO).symbol_at_address_func = generic_symbol_at_address, \
	457	(INFO).flags = 0, \
	458	(INFO).bytes_per_line = 0, \
	459	(INFO).bytes_per_chunk = 0, \
	460	(INFO).display_endian = BFD_ENDIAN_UNKNOWN, \
aa0aa4fa	461	(INFO).disassembler_options = NULL, \
dc99065b FB	462	(INFO).insn_info_valid = 0
dc99065b FB	463
aa0aa4fa	464	#define _(x) x
48024e4a	465	#define ATTRIBUTE_UNUSED __attribute__((unused))
aa0aa4fa FB	466
	467	/* from libbfd */
	468
903ec55c	469	bfd_vma bfd_getl64 (const bfd_byte *addr);
aa0aa4fa FB	470	bfd_vma bfd_getl32 (const bfd_byte *addr);
aa0aa4fa FB	471	bfd_vma bfd_getb32 (const bfd_byte *addr);
6af0bf9c FB	472	bfd_vma bfd_getl16 (const bfd_byte *addr);
6af0bf9c FB	473	bfd_vma bfd_getb16 (const bfd_byte *addr);
47cbc7aa	474	typedef bool bfd_boolean;
aa0aa4fa	475
dc99065b	476	#endif /* ! defined (DIS_ASM_H) */