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b4608c04
FB
1/*
2 * gdb server stub
5fafdf24 3 *
3475187d 4 * Copyright (c) 2003-2005 Fabrice Bellard
b4608c04
FB
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
978efd6a 20#include "config.h"
1fddef4b
FB
21#ifdef CONFIG_USER_ONLY
22#include <stdlib.h>
23#include <stdio.h>
24#include <stdarg.h>
25#include <string.h>
26#include <errno.h>
27#include <unistd.h>
978efd6a 28#include <fcntl.h>
1fddef4b
FB
29
30#include "qemu.h"
31#else
87ecb68b
PB
32#include "qemu-common.h"
33#include "qemu-char.h"
34#include "sysemu.h"
35#include "gdbstub.h"
1fddef4b 36#endif
67b915a5 37
8f447cc7
FB
38#include "qemu_socket.h"
39#ifdef _WIN32
40/* XXX: these constants may be independent of the host ones even for Unix */
41#ifndef SIGTRAP
42#define SIGTRAP 5
43#endif
44#ifndef SIGINT
45#define SIGINT 2
46#endif
47#else
b4608c04 48#include <signal.h>
8f447cc7 49#endif
b4608c04 50
4abe615b 51//#define DEBUG_GDB
b4608c04 52
858693c6
FB
53enum RSState {
54 RS_IDLE,
55 RS_GETLINE,
56 RS_CHKSUM1,
57 RS_CHKSUM2,
a2d1ebaf 58 RS_SYSCALL,
858693c6 59};
858693c6 60typedef struct GDBState {
6a00d601 61 CPUState *env; /* current CPU */
41625033 62 enum RSState state; /* parsing state */
858693c6
FB
63 char line_buf[4096];
64 int line_buf_index;
65 int line_csum;
60fe76f3 66 uint8_t last_packet[4100];
4046d913 67 int last_packet_len;
41625033 68#ifdef CONFIG_USER_ONLY
4046d913 69 int fd;
41625033 70 int running_state;
4046d913
PB
71#else
72 CharDriverState *chr;
41625033 73#endif
858693c6 74} GDBState;
b4608c04 75
60897d36
EI
76/* By default use no IRQs and no timers while single stepping so as to
77 * make single stepping like an ICE HW step.
78 */
79static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
80
1fddef4b 81#ifdef CONFIG_USER_ONLY
4046d913
PB
82/* XXX: This is not thread safe. Do we care? */
83static int gdbserver_fd = -1;
84
1fddef4b
FB
85/* XXX: remove this hack. */
86static GDBState gdbserver_state;
1fddef4b 87
858693c6 88static int get_char(GDBState *s)
b4608c04
FB
89{
90 uint8_t ch;
91 int ret;
92
93 for(;;) {
8f447cc7 94 ret = recv(s->fd, &ch, 1, 0);
b4608c04
FB
95 if (ret < 0) {
96 if (errno != EINTR && errno != EAGAIN)
97 return -1;
98 } else if (ret == 0) {
99 return -1;
100 } else {
101 break;
102 }
103 }
104 return ch;
105}
4046d913 106#endif
b4608c04 107
a2d1ebaf
PB
108/* GDB stub state for use by semihosting syscalls. */
109static GDBState *gdb_syscall_state;
110static gdb_syscall_complete_cb gdb_current_syscall_cb;
111
112enum {
113 GDB_SYS_UNKNOWN,
114 GDB_SYS_ENABLED,
115 GDB_SYS_DISABLED,
116} gdb_syscall_mode;
117
118/* If gdb is connected when the first semihosting syscall occurs then use
119 remote gdb syscalls. Otherwise use native file IO. */
120int use_gdb_syscalls(void)
121{
122 if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
123 gdb_syscall_mode = (gdb_syscall_state ? GDB_SYS_ENABLED
124 : GDB_SYS_DISABLED);
125 }
126 return gdb_syscall_mode == GDB_SYS_ENABLED;
127}
128
ba70a624
EI
129/* Resume execution. */
130static inline void gdb_continue(GDBState *s)
131{
132#ifdef CONFIG_USER_ONLY
133 s->running_state = 1;
134#else
135 vm_start();
136#endif
137}
138
858693c6 139static void put_buffer(GDBState *s, const uint8_t *buf, int len)
b4608c04 140{
4046d913 141#ifdef CONFIG_USER_ONLY
b4608c04
FB
142 int ret;
143
144 while (len > 0) {
8f447cc7 145 ret = send(s->fd, buf, len, 0);
b4608c04
FB
146 if (ret < 0) {
147 if (errno != EINTR && errno != EAGAIN)
148 return;
149 } else {
150 buf += ret;
151 len -= ret;
152 }
153 }
4046d913
PB
154#else
155 qemu_chr_write(s->chr, buf, len);
156#endif
b4608c04
FB
157}
158
159static inline int fromhex(int v)
160{
161 if (v >= '0' && v <= '9')
162 return v - '0';
163 else if (v >= 'A' && v <= 'F')
164 return v - 'A' + 10;
165 else if (v >= 'a' && v <= 'f')
166 return v - 'a' + 10;
167 else
168 return 0;
169}
170
171static inline int tohex(int v)
172{
173 if (v < 10)
174 return v + '0';
175 else
176 return v - 10 + 'a';
177}
178
179static void memtohex(char *buf, const uint8_t *mem, int len)
180{
181 int i, c;
182 char *q;
183 q = buf;
184 for(i = 0; i < len; i++) {
185 c = mem[i];
186 *q++ = tohex(c >> 4);
187 *q++ = tohex(c & 0xf);
188 }
189 *q = '\0';
190}
191
192static void hextomem(uint8_t *mem, const char *buf, int len)
193{
194 int i;
195
196 for(i = 0; i < len; i++) {
197 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
198 buf += 2;
199 }
200}
201
b4608c04 202/* return -1 if error, 0 if OK */
858693c6 203static int put_packet(GDBState *s, char *buf)
b4608c04 204{
4046d913 205 int len, csum, i;
60fe76f3 206 uint8_t *p;
b4608c04
FB
207
208#ifdef DEBUG_GDB
209 printf("reply='%s'\n", buf);
210#endif
211
212 for(;;) {
4046d913
PB
213 p = s->last_packet;
214 *(p++) = '$';
b4608c04 215 len = strlen(buf);
4046d913
PB
216 memcpy(p, buf, len);
217 p += len;
b4608c04
FB
218 csum = 0;
219 for(i = 0; i < len; i++) {
220 csum += buf[i];
221 }
4046d913
PB
222 *(p++) = '#';
223 *(p++) = tohex((csum >> 4) & 0xf);
224 *(p++) = tohex((csum) & 0xf);
b4608c04 225
4046d913 226 s->last_packet_len = p - s->last_packet;
ffe8ab83 227 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
b4608c04 228
4046d913
PB
229#ifdef CONFIG_USER_ONLY
230 i = get_char(s);
231 if (i < 0)
b4608c04 232 return -1;
4046d913 233 if (i == '+')
b4608c04 234 break;
4046d913
PB
235#else
236 break;
237#endif
b4608c04
FB
238 }
239 return 0;
240}
241
fde3fd61 242#if defined(TARGET_I386)
6da41eaf
FB
243static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
244{
245 int i, fpus;
5ad265ee
AZ
246 uint32_t *registers = (uint32_t *)mem_buf;
247
248#ifdef TARGET_X86_64
249 /* This corresponds with amd64_register_info[] in gdb/amd64-tdep.c */
250 uint64_t *registers64 = (uint64_t *)mem_buf;
251
252 if (env->hflags & HF_CS64_MASK) {
253 registers64[0] = tswap64(env->regs[R_EAX]);
254 registers64[1] = tswap64(env->regs[R_EBX]);
255 registers64[2] = tswap64(env->regs[R_ECX]);
256 registers64[3] = tswap64(env->regs[R_EDX]);
257 registers64[4] = tswap64(env->regs[R_ESI]);
258 registers64[5] = tswap64(env->regs[R_EDI]);
259 registers64[6] = tswap64(env->regs[R_EBP]);
260 registers64[7] = tswap64(env->regs[R_ESP]);
261 for(i = 8; i < 16; i++) {
262 registers64[i] = tswap64(env->regs[i]);
263 }
264 registers64[16] = tswap64(env->eip);
265
266 registers = (uint32_t *)&registers64[17];
267 registers[0] = tswap32(env->eflags);
268 registers[1] = tswap32(env->segs[R_CS].selector);
269 registers[2] = tswap32(env->segs[R_SS].selector);
270 registers[3] = tswap32(env->segs[R_DS].selector);
271 registers[4] = tswap32(env->segs[R_ES].selector);
272 registers[5] = tswap32(env->segs[R_FS].selector);
273 registers[6] = tswap32(env->segs[R_GS].selector);
274 /* XXX: convert floats */
275 for(i = 0; i < 8; i++) {
276 memcpy(mem_buf + 16 * 8 + 7 * 4 + i * 10, &env->fpregs[i], 10);
277 }
278 registers[27] = tswap32(env->fpuc); /* fctrl */
279 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
280 registers[28] = tswap32(fpus); /* fstat */
281 registers[29] = 0; /* ftag */
282 registers[30] = 0; /* fiseg */
283 registers[31] = 0; /* fioff */
284 registers[32] = 0; /* foseg */
285 registers[33] = 0; /* fooff */
286 registers[34] = 0; /* fop */
287 for(i = 0; i < 16; i++) {
288 memcpy(mem_buf + 16 * 8 + 35 * 4 + i * 16, &env->xmm_regs[i], 16);
289 }
290 registers[99] = tswap32(env->mxcsr);
291
292 return 8 * 17 + 4 * 7 + 10 * 8 + 4 * 8 + 16 * 16 + 4;
293 }
294#endif
6da41eaf
FB
295
296 for(i = 0; i < 8; i++) {
e95c8d51 297 registers[i] = env->regs[i];
6da41eaf 298 }
e95c8d51
FB
299 registers[8] = env->eip;
300 registers[9] = env->eflags;
301 registers[10] = env->segs[R_CS].selector;
302 registers[11] = env->segs[R_SS].selector;
303 registers[12] = env->segs[R_DS].selector;
304 registers[13] = env->segs[R_ES].selector;
305 registers[14] = env->segs[R_FS].selector;
306 registers[15] = env->segs[R_GS].selector;
6da41eaf
FB
307 /* XXX: convert floats */
308 for(i = 0; i < 8; i++) {
309 memcpy(mem_buf + 16 * 4 + i * 10, &env->fpregs[i], 10);
310 }
e95c8d51 311 registers[36] = env->fpuc;
6da41eaf 312 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
e95c8d51
FB
313 registers[37] = fpus;
314 registers[38] = 0; /* XXX: convert tags */
315 registers[39] = 0; /* fiseg */
316 registers[40] = 0; /* fioff */
317 registers[41] = 0; /* foseg */
318 registers[42] = 0; /* fooff */
319 registers[43] = 0; /* fop */
3b46e624 320
e95c8d51
FB
321 for(i = 0; i < 16; i++)
322 tswapls(&registers[i]);
323 for(i = 36; i < 44; i++)
324 tswapls(&registers[i]);
6da41eaf
FB
325 return 44 * 4;
326}
327
328static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
329{
330 uint32_t *registers = (uint32_t *)mem_buf;
331 int i;
332
333 for(i = 0; i < 8; i++) {
334 env->regs[i] = tswapl(registers[i]);
335 }
e95c8d51
FB
336 env->eip = tswapl(registers[8]);
337 env->eflags = tswapl(registers[9]);
6da41eaf
FB
338#if defined(CONFIG_USER_ONLY)
339#define LOAD_SEG(index, sreg)\
340 if (tswapl(registers[index]) != env->segs[sreg].selector)\
341 cpu_x86_load_seg(env, sreg, tswapl(registers[index]));
342 LOAD_SEG(10, R_CS);
343 LOAD_SEG(11, R_SS);
344 LOAD_SEG(12, R_DS);
345 LOAD_SEG(13, R_ES);
346 LOAD_SEG(14, R_FS);
347 LOAD_SEG(15, R_GS);
348#endif
349}
350
9e62fd7f 351#elif defined (TARGET_PPC)
9e62fd7f
FB
352static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
353{
a541f297 354 uint32_t *registers = (uint32_t *)mem_buf, tmp;
9e62fd7f
FB
355 int i;
356
357 /* fill in gprs */
a541f297 358 for(i = 0; i < 32; i++) {
e95c8d51 359 registers[i] = tswapl(env->gpr[i]);
9e62fd7f
FB
360 }
361 /* fill in fprs */
362 for (i = 0; i < 32; i++) {
e95c8d51
FB
363 registers[(i * 2) + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
364 registers[(i * 2) + 33] = tswapl(*((uint32_t *)&env->fpr[i] + 1));
9e62fd7f
FB
365 }
366 /* nip, msr, ccr, lnk, ctr, xer, mq */
e95c8d51 367 registers[96] = tswapl(env->nip);
0411a972 368 registers[97] = tswapl(env->msr);
9e62fd7f
FB
369 tmp = 0;
370 for (i = 0; i < 8; i++)
a541f297 371 tmp |= env->crf[i] << (32 - ((i + 1) * 4));
e95c8d51
FB
372 registers[98] = tswapl(tmp);
373 registers[99] = tswapl(env->lr);
374 registers[100] = tswapl(env->ctr);
76a66253 375 registers[101] = tswapl(ppc_load_xer(env));
e95c8d51 376 registers[102] = 0;
a541f297
FB
377
378 return 103 * 4;
9e62fd7f
FB
379}
380
381static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
382{
383 uint32_t *registers = (uint32_t *)mem_buf;
384 int i;
385
386 /* fill in gprs */
387 for (i = 0; i < 32; i++) {
e95c8d51 388 env->gpr[i] = tswapl(registers[i]);
9e62fd7f
FB
389 }
390 /* fill in fprs */
391 for (i = 0; i < 32; i++) {
e95c8d51
FB
392 *((uint32_t *)&env->fpr[i]) = tswapl(registers[(i * 2) + 32]);
393 *((uint32_t *)&env->fpr[i] + 1) = tswapl(registers[(i * 2) + 33]);
9e62fd7f
FB
394 }
395 /* nip, msr, ccr, lnk, ctr, xer, mq */
e95c8d51 396 env->nip = tswapl(registers[96]);
0411a972 397 ppc_store_msr(env, tswapl(registers[97]));
e95c8d51 398 registers[98] = tswapl(registers[98]);
9e62fd7f 399 for (i = 0; i < 8; i++)
a541f297 400 env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF;
e95c8d51
FB
401 env->lr = tswapl(registers[99]);
402 env->ctr = tswapl(registers[100]);
76a66253 403 ppc_store_xer(env, tswapl(registers[101]));
e95c8d51
FB
404}
405#elif defined (TARGET_SPARC)
406static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
407{
3475187d 408 target_ulong *registers = (target_ulong *)mem_buf;
e95c8d51
FB
409 int i;
410
411 /* fill in g0..g7 */
48b2c193 412 for(i = 0; i < 8; i++) {
e95c8d51
FB
413 registers[i] = tswapl(env->gregs[i]);
414 }
415 /* fill in register window */
416 for(i = 0; i < 24; i++) {
417 registers[i + 8] = tswapl(env->regwptr[i]);
418 }
9d9754a3 419#ifndef TARGET_SPARC64
e95c8d51
FB
420 /* fill in fprs */
421 for (i = 0; i < 32; i++) {
422 registers[i + 32] = tswapl(*((uint32_t *)&env->fpr[i]));
423 }
424 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
425 registers[64] = tswapl(env->y);
3475187d
FB
426 {
427 target_ulong tmp;
428
429 tmp = GET_PSR(env);
430 registers[65] = tswapl(tmp);
431 }
e95c8d51
FB
432 registers[66] = tswapl(env->wim);
433 registers[67] = tswapl(env->tbr);
434 registers[68] = tswapl(env->pc);
435 registers[69] = tswapl(env->npc);
436 registers[70] = tswapl(env->fsr);
437 registers[71] = 0; /* csr */
438 registers[72] = 0;
3475187d
FB
439 return 73 * sizeof(target_ulong);
440#else
9d9754a3
FB
441 /* fill in fprs */
442 for (i = 0; i < 64; i += 2) {
443 uint64_t tmp;
444
8979596d
BS
445 tmp = ((uint64_t)*(uint32_t *)&env->fpr[i]) << 32;
446 tmp |= *(uint32_t *)&env->fpr[i + 1];
447 registers[i / 2 + 32] = tswap64(tmp);
3475187d 448 }
9d9754a3
FB
449 registers[64] = tswapl(env->pc);
450 registers[65] = tswapl(env->npc);
17d996e1
BS
451 registers[66] = tswapl(((uint64_t)GET_CCR(env) << 32) |
452 ((env->asi & 0xff) << 24) |
453 ((env->pstate & 0xfff) << 8) |
454 GET_CWP64(env));
9d9754a3
FB
455 registers[67] = tswapl(env->fsr);
456 registers[68] = tswapl(env->fprs);
457 registers[69] = tswapl(env->y);
458 return 70 * sizeof(target_ulong);
3475187d 459#endif
e95c8d51
FB
460}
461
462static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
463{
3475187d 464 target_ulong *registers = (target_ulong *)mem_buf;
e95c8d51
FB
465 int i;
466
467 /* fill in g0..g7 */
468 for(i = 0; i < 7; i++) {
469 env->gregs[i] = tswapl(registers[i]);
470 }
471 /* fill in register window */
472 for(i = 0; i < 24; i++) {
3475187d 473 env->regwptr[i] = tswapl(registers[i + 8]);
e95c8d51 474 }
9d9754a3 475#ifndef TARGET_SPARC64
e95c8d51
FB
476 /* fill in fprs */
477 for (i = 0; i < 32; i++) {
478 *((uint32_t *)&env->fpr[i]) = tswapl(registers[i + 32]);
479 }
480 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
481 env->y = tswapl(registers[64]);
e80cfcfc 482 PUT_PSR(env, tswapl(registers[65]));
e95c8d51
FB
483 env->wim = tswapl(registers[66]);
484 env->tbr = tswapl(registers[67]);
485 env->pc = tswapl(registers[68]);
486 env->npc = tswapl(registers[69]);
487 env->fsr = tswapl(registers[70]);
3475187d 488#else
9d9754a3 489 for (i = 0; i < 64; i += 2) {
8979596d
BS
490 uint64_t tmp;
491
492 tmp = tswap64(registers[i / 2 + 32]);
493 *((uint32_t *)&env->fpr[i]) = tmp >> 32;
494 *((uint32_t *)&env->fpr[i + 1]) = tmp & 0xffffffff;
3475187d 495 }
9d9754a3
FB
496 env->pc = tswapl(registers[64]);
497 env->npc = tswapl(registers[65]);
17d996e1
BS
498 {
499 uint64_t tmp = tswapl(registers[66]);
500
501 PUT_CCR(env, tmp >> 32);
502 env->asi = (tmp >> 24) & 0xff;
503 env->pstate = (tmp >> 8) & 0xfff;
504 PUT_CWP64(env, tmp & 0xff);
505 }
9d9754a3
FB
506 env->fsr = tswapl(registers[67]);
507 env->fprs = tswapl(registers[68]);
508 env->y = tswapl(registers[69]);
3475187d 509#endif
9e62fd7f 510}
1fddef4b
FB
511#elif defined (TARGET_ARM)
512static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
513{
514 int i;
515 uint8_t *ptr;
516
517 ptr = mem_buf;
518 /* 16 core integer registers (4 bytes each). */
519 for (i = 0; i < 16; i++)
520 {
521 *(uint32_t *)ptr = tswapl(env->regs[i]);
522 ptr += 4;
523 }
524 /* 8 FPA registers (12 bytes each), FPS (4 bytes).
525 Not yet implemented. */
526 memset (ptr, 0, 8 * 12 + 4);
527 ptr += 8 * 12 + 4;
528 /* CPSR (4 bytes). */
b5ff1b31 529 *(uint32_t *)ptr = tswapl (cpsr_read(env));
1fddef4b
FB
530 ptr += 4;
531
532 return ptr - mem_buf;
533}
6da41eaf 534
1fddef4b
FB
535static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
536{
537 int i;
538 uint8_t *ptr;
539
540 ptr = mem_buf;
541 /* Core integer registers. */
542 for (i = 0; i < 16; i++)
543 {
544 env->regs[i] = tswapl(*(uint32_t *)ptr);
545 ptr += 4;
546 }
547 /* Ignore FPA regs and scr. */
548 ptr += 8 * 12 + 4;
b5ff1b31 549 cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
1fddef4b 550}
e6e5906b
PB
551#elif defined (TARGET_M68K)
552static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
553{
554 int i;
555 uint8_t *ptr;
556 CPU_DoubleU u;
557
558 ptr = mem_buf;
559 /* D0-D7 */
560 for (i = 0; i < 8; i++) {
561 *(uint32_t *)ptr = tswapl(env->dregs[i]);
562 ptr += 4;
563 }
564 /* A0-A7 */
565 for (i = 0; i < 8; i++) {
566 *(uint32_t *)ptr = tswapl(env->aregs[i]);
567 ptr += 4;
568 }
569 *(uint32_t *)ptr = tswapl(env->sr);
570 ptr += 4;
571 *(uint32_t *)ptr = tswapl(env->pc);
572 ptr += 4;
573 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
574 ColdFire has 8-bit double precision registers. */
575 for (i = 0; i < 8; i++) {
576 u.d = env->fregs[i];
577 *(uint32_t *)ptr = tswap32(u.l.upper);
578 *(uint32_t *)ptr = tswap32(u.l.lower);
579 }
580 /* FP control regs (not implemented). */
581 memset (ptr, 0, 3 * 4);
582 ptr += 3 * 4;
583
584 return ptr - mem_buf;
585}
586
587static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
588{
589 int i;
590 uint8_t *ptr;
591 CPU_DoubleU u;
592
593 ptr = mem_buf;
594 /* D0-D7 */
595 for (i = 0; i < 8; i++) {
596 env->dregs[i] = tswapl(*(uint32_t *)ptr);
597 ptr += 4;
598 }
599 /* A0-A7 */
600 for (i = 0; i < 8; i++) {
601 env->aregs[i] = tswapl(*(uint32_t *)ptr);
602 ptr += 4;
603 }
604 env->sr = tswapl(*(uint32_t *)ptr);
605 ptr += 4;
606 env->pc = tswapl(*(uint32_t *)ptr);
607 ptr += 4;
608 /* F0-F7. The 68881/68040 have 12-bit extended precision registers.
609 ColdFire has 8-bit double precision registers. */
610 for (i = 0; i < 8; i++) {
5fafdf24 611 u.l.upper = tswap32(*(uint32_t *)ptr);
e6e5906b
PB
612 u.l.lower = tswap32(*(uint32_t *)ptr);
613 env->fregs[i] = u.d;
614 }
615 /* FP control regs (not implemented). */
616 ptr += 3 * 4;
617}
6f970bd9
FB
618#elif defined (TARGET_MIPS)
619static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
620{
621 int i;
622 uint8_t *ptr;
623
624 ptr = mem_buf;
625 for (i = 0; i < 32; i++)
626 {
d0dc7dc3 627 *(target_ulong *)ptr = tswapl(env->gpr[env->current_tc][i]);
2052caa7 628 ptr += sizeof(target_ulong);
6f970bd9
FB
629 }
630
7ac256b8 631 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status);
2052caa7 632 ptr += sizeof(target_ulong);
6f970bd9 633
d0dc7dc3 634 *(target_ulong *)ptr = tswapl(env->LO[env->current_tc][0]);
2052caa7 635 ptr += sizeof(target_ulong);
6f970bd9 636
d0dc7dc3 637 *(target_ulong *)ptr = tswapl(env->HI[env->current_tc][0]);
2052caa7 638 ptr += sizeof(target_ulong);
6f970bd9 639
2052caa7
TS
640 *(target_ulong *)ptr = tswapl(env->CP0_BadVAddr);
641 ptr += sizeof(target_ulong);
6f970bd9 642
7ac256b8 643 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Cause);
2052caa7 644 ptr += sizeof(target_ulong);
6f970bd9 645
ead9360e 646 *(target_ulong *)ptr = tswapl(env->PC[env->current_tc]);
2052caa7 647 ptr += sizeof(target_ulong);
6f970bd9 648
36d23958 649 if (env->CP0_Config1 & (1 << CP0C1_FP))
8e33c08c 650 {
36d23958
TS
651 for (i = 0; i < 32; i++)
652 {
7ac256b8
TS
653 if (env->CP0_Status & (1 << CP0St_FR))
654 *(target_ulong *)ptr = tswapl(env->fpu->fpr[i].d);
655 else
656 *(target_ulong *)ptr = tswap32(env->fpu->fpr[i].w[FP_ENDIAN_IDX]);
2052caa7 657 ptr += sizeof(target_ulong);
36d23958 658 }
8e33c08c 659
7ac256b8 660 *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr31);
2052caa7 661 ptr += sizeof(target_ulong);
8e33c08c 662
7ac256b8 663 *(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr0);
2052caa7 664 ptr += sizeof(target_ulong);
36d23958 665 }
8e33c08c 666
7ac256b8
TS
667 /* "fp", pseudo frame pointer. Not yet implemented in gdb. */
668 *(target_ulong *)ptr = 0;
669 ptr += sizeof(target_ulong);
670
671 /* Registers for embedded use, we just pad them. */
672 for (i = 0; i < 16; i++)
673 {
674 *(target_ulong *)ptr = 0;
675 ptr += sizeof(target_ulong);
676 }
677
678 /* Processor ID. */
679 *(target_ulong *)ptr = (int32_t)tswap32(env->CP0_PRid);
680 ptr += sizeof(target_ulong);
6f970bd9
FB
681
682 return ptr - mem_buf;
683}
684
8e33c08c
TS
685/* convert MIPS rounding mode in FCR31 to IEEE library */
686static unsigned int ieee_rm[] =
687 {
688 float_round_nearest_even,
689 float_round_to_zero,
690 float_round_up,
691 float_round_down
692 };
693#define RESTORE_ROUNDING_MODE \
ead9360e 694 set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
8e33c08c 695
6f970bd9
FB
696static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
697{
698 int i;
699 uint8_t *ptr;
700
701 ptr = mem_buf;
702 for (i = 0; i < 32; i++)
703 {
d0dc7dc3 704 env->gpr[env->current_tc][i] = tswapl(*(target_ulong *)ptr);
2052caa7 705 ptr += sizeof(target_ulong);
6f970bd9
FB
706 }
707
2052caa7
TS
708 env->CP0_Status = tswapl(*(target_ulong *)ptr);
709 ptr += sizeof(target_ulong);
6f970bd9 710
d0dc7dc3 711 env->LO[env->current_tc][0] = tswapl(*(target_ulong *)ptr);
2052caa7 712 ptr += sizeof(target_ulong);
6f970bd9 713
d0dc7dc3 714 env->HI[env->current_tc][0] = tswapl(*(target_ulong *)ptr);
2052caa7 715 ptr += sizeof(target_ulong);
6f970bd9 716
2052caa7
TS
717 env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr);
718 ptr += sizeof(target_ulong);
6f970bd9 719
2052caa7
TS
720 env->CP0_Cause = tswapl(*(target_ulong *)ptr);
721 ptr += sizeof(target_ulong);
6f970bd9 722
ead9360e 723 env->PC[env->current_tc] = tswapl(*(target_ulong *)ptr);
2052caa7 724 ptr += sizeof(target_ulong);
8e33c08c 725
36d23958 726 if (env->CP0_Config1 & (1 << CP0C1_FP))
8e33c08c 727 {
36d23958
TS
728 for (i = 0; i < 32; i++)
729 {
7ac256b8
TS
730 if (env->CP0_Status & (1 << CP0St_FR))
731 env->fpu->fpr[i].d = tswapl(*(target_ulong *)ptr);
732 else
733 env->fpu->fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr);
2052caa7 734 ptr += sizeof(target_ulong);
36d23958 735 }
8e33c08c 736
7ac256b8 737 env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF;
2052caa7 738 ptr += sizeof(target_ulong);
8e33c08c 739
7ac256b8 740 /* The remaining registers are assumed to be read-only. */
8e33c08c 741
36d23958
TS
742 /* set rounding mode */
743 RESTORE_ROUNDING_MODE;
8e33c08c
TS
744
745#ifndef CONFIG_SOFTFLOAT
36d23958
TS
746 /* no floating point exception for native float */
747 SET_FP_ENABLE(env->fcr31, 0);
8e33c08c 748#endif
36d23958 749 }
6f970bd9 750}
fdf9b3e8 751#elif defined (TARGET_SH4)
6ef99fc5
TS
752
753/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
754
fdf9b3e8
FB
755static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
756{
757 uint32_t *ptr = (uint32_t *)mem_buf;
758 int i;
759
760#define SAVE(x) *ptr++=tswapl(x)
9c2a9ea1
PB
761 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
762 for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
763 } else {
764 for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
765 }
766 for (i = 8; i < 16; i++) SAVE(env->gregs[i]);
fdf9b3e8
FB
767 SAVE (env->pc);
768 SAVE (env->pr);
769 SAVE (env->gbr);
770 SAVE (env->vbr);
771 SAVE (env->mach);
772 SAVE (env->macl);
773 SAVE (env->sr);
6ef99fc5
TS
774 SAVE (env->fpul);
775 SAVE (env->fpscr);
776 for (i = 0; i < 16; i++)
777 SAVE(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
778 SAVE (env->ssr);
779 SAVE (env->spc);
780 for (i = 0; i < 8; i++) SAVE(env->gregs[i]);
781 for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]);
fdf9b3e8
FB
782 return ((uint8_t *)ptr - mem_buf);
783}
784
785static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
786{
787 uint32_t *ptr = (uint32_t *)mem_buf;
788 int i;
789
790#define LOAD(x) (x)=*ptr++;
9c2a9ea1
PB
791 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
792 for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
793 } else {
794 for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
795 }
796 for (i = 8; i < 16; i++) LOAD(env->gregs[i]);
fdf9b3e8
FB
797 LOAD (env->pc);
798 LOAD (env->pr);
799 LOAD (env->gbr);
800 LOAD (env->vbr);
801 LOAD (env->mach);
802 LOAD (env->macl);
803 LOAD (env->sr);
6ef99fc5
TS
804 LOAD (env->fpul);
805 LOAD (env->fpscr);
806 for (i = 0; i < 16; i++)
807 LOAD(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
808 LOAD (env->ssr);
809 LOAD (env->spc);
810 for (i = 0; i < 8; i++) LOAD(env->gregs[i]);
811 for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]);
fdf9b3e8 812}
f1ccf904
TS
813#elif defined (TARGET_CRIS)
814
815static int cris_save_32 (unsigned char *d, uint32_t value)
816{
817 *d++ = (value);
818 *d++ = (value >>= 8);
819 *d++ = (value >>= 8);
820 *d++ = (value >>= 8);
821 return 4;
822}
823static int cris_save_16 (unsigned char *d, uint32_t value)
824{
825 *d++ = (value);
826 *d++ = (value >>= 8);
827 return 2;
828}
829static int cris_save_8 (unsigned char *d, uint32_t value)
830{
831 *d++ = (value);
832 return 1;
833}
834
835/* FIXME: this will bug on archs not supporting unaligned word accesses. */
836static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
837{
838 uint8_t *ptr = mem_buf;
839 uint8_t srs;
840 int i;
841
842 for (i = 0; i < 16; i++)
843 ptr += cris_save_32 (ptr, env->regs[i]);
844
9004627f 845 srs = env->pregs[PR_SRS];
f1ccf904
TS
846
847 ptr += cris_save_8 (ptr, env->pregs[0]);
848 ptr += cris_save_8 (ptr, env->pregs[1]);
849 ptr += cris_save_32 (ptr, env->pregs[2]);
850 ptr += cris_save_8 (ptr, srs);
851 ptr += cris_save_16 (ptr, env->pregs[4]);
852
853 for (i = 5; i < 16; i++)
854 ptr += cris_save_32 (ptr, env->pregs[i]);
855
856 ptr += cris_save_32 (ptr, env->pc);
857
858 for (i = 0; i < 16; i++)
859 ptr += cris_save_32 (ptr, env->sregs[srs][i]);
860
861 return ((uint8_t *)ptr - mem_buf);
862}
863
864static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
865{
866 uint32_t *ptr = (uint32_t *)mem_buf;
867 int i;
868
869#define LOAD(x) (x)=*ptr++;
870 for (i = 0; i < 16; i++) LOAD(env->regs[i]);
871 LOAD (env->pc);
872}
1fddef4b 873#else
6da41eaf
FB
874static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf)
875{
876 return 0;
877}
878
879static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size)
880{
881}
882
883#endif
b4608c04 884
1fddef4b 885static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf)
b4608c04 886{
b4608c04 887 const char *p;
858693c6 888 int ch, reg_size, type;
b4608c04 889 char buf[4096];
f1ccf904 890 uint8_t mem_buf[4096];
b4608c04 891 uint32_t *registers;
9d9754a3 892 target_ulong addr, len;
3b46e624 893
858693c6
FB
894#ifdef DEBUG_GDB
895 printf("command='%s'\n", line_buf);
896#endif
897 p = line_buf;
898 ch = *p++;
899 switch(ch) {
900 case '?':
1fddef4b 901 /* TODO: Make this return the correct value for user-mode. */
858693c6
FB
902 snprintf(buf, sizeof(buf), "S%02x", SIGTRAP);
903 put_packet(s, buf);
904 break;
905 case 'c':
906 if (*p != '\0') {
9d9754a3 907 addr = strtoull(p, (char **)&p, 16);
4c3a88a2 908#if defined(TARGET_I386)
858693c6 909 env->eip = addr;
5be1a8e0 910#elif defined (TARGET_PPC)
858693c6 911 env->nip = addr;
8d5f07fa
FB
912#elif defined (TARGET_SPARC)
913 env->pc = addr;
914 env->npc = addr + 4;
b5ff1b31
FB
915#elif defined (TARGET_ARM)
916 env->regs[15] = addr;
fdf9b3e8 917#elif defined (TARGET_SH4)
8fac5803
TS
918 env->pc = addr;
919#elif defined (TARGET_MIPS)
ead9360e 920 env->PC[env->current_tc] = addr;
f1ccf904
TS
921#elif defined (TARGET_CRIS)
922 env->pc = addr;
4c3a88a2 923#endif
858693c6 924 }
ba70a624 925 gdb_continue(s);
41625033 926 return RS_IDLE;
858693c6
FB
927 case 's':
928 if (*p != '\0') {
8fac5803 929 addr = strtoull(p, (char **)&p, 16);
c33a346e 930#if defined(TARGET_I386)
858693c6 931 env->eip = addr;
5be1a8e0 932#elif defined (TARGET_PPC)
858693c6 933 env->nip = addr;
8d5f07fa
FB
934#elif defined (TARGET_SPARC)
935 env->pc = addr;
936 env->npc = addr + 4;
b5ff1b31
FB
937#elif defined (TARGET_ARM)
938 env->regs[15] = addr;
fdf9b3e8 939#elif defined (TARGET_SH4)
8fac5803
TS
940 env->pc = addr;
941#elif defined (TARGET_MIPS)
ead9360e 942 env->PC[env->current_tc] = addr;
f1ccf904
TS
943#elif defined (TARGET_CRIS)
944 env->pc = addr;
c33a346e 945#endif
858693c6 946 }
60897d36 947 cpu_single_step(env, sstep_flags);
ba70a624 948 gdb_continue(s);
41625033 949 return RS_IDLE;
a2d1ebaf
PB
950 case 'F':
951 {
952 target_ulong ret;
953 target_ulong err;
954
955 ret = strtoull(p, (char **)&p, 16);
956 if (*p == ',') {
957 p++;
958 err = strtoull(p, (char **)&p, 16);
959 } else {
960 err = 0;
961 }
962 if (*p == ',')
963 p++;
964 type = *p;
965 if (gdb_current_syscall_cb)
966 gdb_current_syscall_cb(s->env, ret, err);
967 if (type == 'C') {
968 put_packet(s, "T02");
969 } else {
ba70a624 970 gdb_continue(s);
a2d1ebaf
PB
971 }
972 }
973 break;
858693c6
FB
974 case 'g':
975 reg_size = cpu_gdb_read_registers(env, mem_buf);
976 memtohex(buf, mem_buf, reg_size);
977 put_packet(s, buf);
978 break;
979 case 'G':
980 registers = (void *)mem_buf;
981 len = strlen(p) / 2;
982 hextomem((uint8_t *)registers, p, len);
983 cpu_gdb_write_registers(env, mem_buf, len);
984 put_packet(s, "OK");
985 break;
986 case 'm':
9d9754a3 987 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
988 if (*p == ',')
989 p++;
9d9754a3 990 len = strtoull(p, NULL, 16);
6f970bd9
FB
991 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 0) != 0) {
992 put_packet (s, "E14");
993 } else {
994 memtohex(buf, mem_buf, len);
995 put_packet(s, buf);
996 }
858693c6
FB
997 break;
998 case 'M':
9d9754a3 999 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
1000 if (*p == ',')
1001 p++;
9d9754a3 1002 len = strtoull(p, (char **)&p, 16);
b328f873 1003 if (*p == ':')
858693c6
FB
1004 p++;
1005 hextomem(mem_buf, p, len);
1006 if (cpu_memory_rw_debug(env, addr, mem_buf, len, 1) != 0)
905f20b1 1007 put_packet(s, "E14");
858693c6
FB
1008 else
1009 put_packet(s, "OK");
1010 break;
1011 case 'Z':
1012 type = strtoul(p, (char **)&p, 16);
1013 if (*p == ',')
1014 p++;
9d9754a3 1015 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
1016 if (*p == ',')
1017 p++;
9d9754a3 1018 len = strtoull(p, (char **)&p, 16);
858693c6
FB
1019 if (type == 0 || type == 1) {
1020 if (cpu_breakpoint_insert(env, addr) < 0)
1021 goto breakpoint_error;
1022 put_packet(s, "OK");
6658ffb8
PB
1023#ifndef CONFIG_USER_ONLY
1024 } else if (type == 2) {
1025 if (cpu_watchpoint_insert(env, addr) < 0)
1026 goto breakpoint_error;
1027 put_packet(s, "OK");
1028#endif
858693c6
FB
1029 } else {
1030 breakpoint_error:
905f20b1 1031 put_packet(s, "E22");
858693c6
FB
1032 }
1033 break;
1034 case 'z':
1035 type = strtoul(p, (char **)&p, 16);
1036 if (*p == ',')
1037 p++;
9d9754a3 1038 addr = strtoull(p, (char **)&p, 16);
858693c6
FB
1039 if (*p == ',')
1040 p++;
9d9754a3 1041 len = strtoull(p, (char **)&p, 16);
858693c6
FB
1042 if (type == 0 || type == 1) {
1043 cpu_breakpoint_remove(env, addr);
1044 put_packet(s, "OK");
6658ffb8
PB
1045#ifndef CONFIG_USER_ONLY
1046 } else if (type == 2) {
1047 cpu_watchpoint_remove(env, addr);
1048 put_packet(s, "OK");
1049#endif
858693c6
FB
1050 } else {
1051 goto breakpoint_error;
1052 }
1053 break;
978efd6a 1054 case 'q':
60897d36
EI
1055 case 'Q':
1056 /* parse any 'q' packets here */
1057 if (!strcmp(p,"qemu.sstepbits")) {
1058 /* Query Breakpoint bit definitions */
1059 sprintf(buf,"ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
1060 SSTEP_ENABLE,
1061 SSTEP_NOIRQ,
1062 SSTEP_NOTIMER);
1063 put_packet(s, buf);
1064 break;
1065 } else if (strncmp(p,"qemu.sstep",10) == 0) {
1066 /* Display or change the sstep_flags */
1067 p += 10;
1068 if (*p != '=') {
1069 /* Display current setting */
1070 sprintf(buf,"0x%x", sstep_flags);
1071 put_packet(s, buf);
1072 break;
1073 }
1074 p++;
1075 type = strtoul(p, (char **)&p, 16);
1076 sstep_flags = type;
1077 put_packet(s, "OK");
1078 break;
1079 }
1080#ifdef CONFIG_LINUX_USER
1081 else if (strncmp(p, "Offsets", 7) == 0) {
978efd6a
PB
1082 TaskState *ts = env->opaque;
1083
fe834d04 1084 sprintf(buf,
cd041681
PB
1085 "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
1086 ";Bss=" TARGET_ABI_FMT_lx,
fe834d04
TS
1087 ts->info->code_offset,
1088 ts->info->data_offset,
1089 ts->info->data_offset);
978efd6a
PB
1090 put_packet(s, buf);
1091 break;
1092 }
978efd6a 1093#endif
60897d36 1094 /* Fall through. */
858693c6 1095 default:
858693c6
FB
1096 /* put empty packet */
1097 buf[0] = '\0';
1098 put_packet(s, buf);
1099 break;
1100 }
1101 return RS_IDLE;
1102}
1103
612458f5
FB
1104extern void tb_flush(CPUState *env);
1105
1fddef4b 1106#ifndef CONFIG_USER_ONLY
858693c6
FB
1107static void gdb_vm_stopped(void *opaque, int reason)
1108{
1109 GDBState *s = opaque;
1110 char buf[256];
1111 int ret;
1112
a2d1ebaf
PB
1113 if (s->state == RS_SYSCALL)
1114 return;
1115
858693c6 1116 /* disable single step if it was enable */
6a00d601 1117 cpu_single_step(s->env, 0);
858693c6 1118
e80cfcfc 1119 if (reason == EXCP_DEBUG) {
6658ffb8 1120 if (s->env->watchpoint_hit) {
aa6290b7
PB
1121 snprintf(buf, sizeof(buf), "T%02xwatch:" TARGET_FMT_lx ";",
1122 SIGTRAP,
6658ffb8
PB
1123 s->env->watchpoint[s->env->watchpoint_hit - 1].vaddr);
1124 put_packet(s, buf);
1125 s->env->watchpoint_hit = 0;
1126 return;
1127 }
6a00d601 1128 tb_flush(s->env);
858693c6 1129 ret = SIGTRAP;
bbeb7b5c
FB
1130 } else if (reason == EXCP_INTERRUPT) {
1131 ret = SIGINT;
1132 } else {
858693c6 1133 ret = 0;
bbeb7b5c 1134 }
858693c6
FB
1135 snprintf(buf, sizeof(buf), "S%02x", ret);
1136 put_packet(s, buf);
1137}
1fddef4b 1138#endif
858693c6 1139
a2d1ebaf
PB
1140/* Send a gdb syscall request.
1141 This accepts limited printf-style format specifiers, specifically:
a87295e8
PB
1142 %x - target_ulong argument printed in hex.
1143 %lx - 64-bit argument printed in hex.
1144 %s - string pointer (target_ulong) and length (int) pair. */
a2d1ebaf
PB
1145void gdb_do_syscall(gdb_syscall_complete_cb cb, char *fmt, ...)
1146{
1147 va_list va;
1148 char buf[256];
1149 char *p;
1150 target_ulong addr;
a87295e8 1151 uint64_t i64;
a2d1ebaf
PB
1152 GDBState *s;
1153
1154 s = gdb_syscall_state;
1155 if (!s)
1156 return;
1157 gdb_current_syscall_cb = cb;
1158 s->state = RS_SYSCALL;
1159#ifndef CONFIG_USER_ONLY
1160 vm_stop(EXCP_DEBUG);
1161#endif
1162 s->state = RS_IDLE;
1163 va_start(va, fmt);
1164 p = buf;
1165 *(p++) = 'F';
1166 while (*fmt) {
1167 if (*fmt == '%') {
1168 fmt++;
1169 switch (*fmt++) {
1170 case 'x':
1171 addr = va_arg(va, target_ulong);
1172 p += sprintf(p, TARGET_FMT_lx, addr);
1173 break;
a87295e8
PB
1174 case 'l':
1175 if (*(fmt++) != 'x')
1176 goto bad_format;
1177 i64 = va_arg(va, uint64_t);
1178 p += sprintf(p, "%" PRIx64, i64);
1179 break;
a2d1ebaf
PB
1180 case 's':
1181 addr = va_arg(va, target_ulong);
1182 p += sprintf(p, TARGET_FMT_lx "/%x", addr, va_arg(va, int));
1183 break;
1184 default:
a87295e8 1185 bad_format:
a2d1ebaf
PB
1186 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
1187 fmt - 1);
1188 break;
1189 }
1190 } else {
1191 *(p++) = *(fmt++);
1192 }
1193 }
8a93e02a 1194 *p = 0;
a2d1ebaf
PB
1195 va_end(va);
1196 put_packet(s, buf);
1197#ifdef CONFIG_USER_ONLY
1198 gdb_handlesig(s->env, 0);
1199#else
1200 cpu_interrupt(s->env, CPU_INTERRUPT_EXIT);
1201#endif
1202}
1203
6a00d601 1204static void gdb_read_byte(GDBState *s, int ch)
858693c6 1205{
6a00d601 1206 CPUState *env = s->env;
858693c6 1207 int i, csum;
60fe76f3 1208 uint8_t reply;
858693c6 1209
1fddef4b 1210#ifndef CONFIG_USER_ONLY
4046d913
PB
1211 if (s->last_packet_len) {
1212 /* Waiting for a response to the last packet. If we see the start
1213 of a new command then abandon the previous response. */
1214 if (ch == '-') {
1215#ifdef DEBUG_GDB
1216 printf("Got NACK, retransmitting\n");
1217#endif
ffe8ab83 1218 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
4046d913
PB
1219 }
1220#ifdef DEBUG_GDB
1221 else if (ch == '+')
1222 printf("Got ACK\n");
1223 else
1224 printf("Got '%c' when expecting ACK/NACK\n", ch);
1225#endif
1226 if (ch == '+' || ch == '$')
1227 s->last_packet_len = 0;
1228 if (ch != '$')
1229 return;
1230 }
858693c6
FB
1231 if (vm_running) {
1232 /* when the CPU is running, we cannot do anything except stop
1233 it when receiving a char */
1234 vm_stop(EXCP_INTERRUPT);
5fafdf24 1235 } else
1fddef4b 1236#endif
41625033 1237 {
858693c6
FB
1238 switch(s->state) {
1239 case RS_IDLE:
1240 if (ch == '$') {
1241 s->line_buf_index = 0;
1242 s->state = RS_GETLINE;
c33a346e 1243 }
b4608c04 1244 break;
858693c6
FB
1245 case RS_GETLINE:
1246 if (ch == '#') {
1247 s->state = RS_CHKSUM1;
1248 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
1249 s->state = RS_IDLE;
4c3a88a2 1250 } else {
858693c6 1251 s->line_buf[s->line_buf_index++] = ch;
4c3a88a2
FB
1252 }
1253 break;
858693c6
FB
1254 case RS_CHKSUM1:
1255 s->line_buf[s->line_buf_index] = '\0';
1256 s->line_csum = fromhex(ch) << 4;
1257 s->state = RS_CHKSUM2;
1258 break;
1259 case RS_CHKSUM2:
1260 s->line_csum |= fromhex(ch);
1261 csum = 0;
1262 for(i = 0; i < s->line_buf_index; i++) {
1263 csum += s->line_buf[i];
1264 }
1265 if (s->line_csum != (csum & 0xff)) {
60fe76f3
TS
1266 reply = '-';
1267 put_buffer(s, &reply, 1);
858693c6 1268 s->state = RS_IDLE;
4c3a88a2 1269 } else {
60fe76f3
TS
1270 reply = '+';
1271 put_buffer(s, &reply, 1);
1fddef4b 1272 s->state = gdb_handle_packet(s, env, s->line_buf);
4c3a88a2
FB
1273 }
1274 break;
a2d1ebaf
PB
1275 default:
1276 abort();
858693c6
FB
1277 }
1278 }
1279}
1280
1fddef4b
FB
1281#ifdef CONFIG_USER_ONLY
1282int
1283gdb_handlesig (CPUState *env, int sig)
1284{
1285 GDBState *s;
1286 char buf[256];
1287 int n;
1288
1289 if (gdbserver_fd < 0)
1290 return sig;
1291
1292 s = &gdbserver_state;
1293
1294 /* disable single step if it was enabled */
1295 cpu_single_step(env, 0);
1296 tb_flush(env);
1297
1298 if (sig != 0)
1299 {
1300 snprintf(buf, sizeof(buf), "S%02x", sig);
1301 put_packet(s, buf);
1302 }
1303
1fddef4b
FB
1304 sig = 0;
1305 s->state = RS_IDLE;
41625033
FB
1306 s->running_state = 0;
1307 while (s->running_state == 0) {
1fddef4b
FB
1308 n = read (s->fd, buf, 256);
1309 if (n > 0)
1310 {
1311 int i;
1312
1313 for (i = 0; i < n; i++)
6a00d601 1314 gdb_read_byte (s, buf[i]);
1fddef4b
FB
1315 }
1316 else if (n == 0 || errno != EAGAIN)
1317 {
1318 /* XXX: Connection closed. Should probably wait for annother
1319 connection before continuing. */
1320 return sig;
1321 }
41625033 1322 }
1fddef4b
FB
1323 return sig;
1324}
e9009676
FB
1325
1326/* Tell the remote gdb that the process has exited. */
1327void gdb_exit(CPUState *env, int code)
1328{
1329 GDBState *s;
1330 char buf[4];
1331
1332 if (gdbserver_fd < 0)
1333 return;
1334
1335 s = &gdbserver_state;
1336
1337 snprintf(buf, sizeof(buf), "W%02x", code);
1338 put_packet(s, buf);
1339}
1340
1fddef4b 1341
7c9d8e07 1342static void gdb_accept(void *opaque)
858693c6
FB
1343{
1344 GDBState *s;
1345 struct sockaddr_in sockaddr;
1346 socklen_t len;
1347 int val, fd;
1348
1349 for(;;) {
1350 len = sizeof(sockaddr);
1351 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
1352 if (fd < 0 && errno != EINTR) {
1353 perror("accept");
1354 return;
1355 } else if (fd >= 0) {
b4608c04
FB
1356 break;
1357 }
1358 }
858693c6
FB
1359
1360 /* set short latency */
1361 val = 1;
8f447cc7 1362 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
3b46e624 1363
1fddef4b
FB
1364 s = &gdbserver_state;
1365 memset (s, 0, sizeof (GDBState));
6a00d601 1366 s->env = first_cpu; /* XXX: allow to change CPU */
858693c6
FB
1367 s->fd = fd;
1368
a2d1ebaf
PB
1369 gdb_syscall_state = s;
1370
858693c6 1371 fcntl(fd, F_SETFL, O_NONBLOCK);
858693c6
FB
1372}
1373
1374static int gdbserver_open(int port)
1375{
1376 struct sockaddr_in sockaddr;
1377 int fd, val, ret;
1378
1379 fd = socket(PF_INET, SOCK_STREAM, 0);
1380 if (fd < 0) {
1381 perror("socket");
1382 return -1;
1383 }
1384
1385 /* allow fast reuse */
1386 val = 1;
8f447cc7 1387 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
858693c6
FB
1388
1389 sockaddr.sin_family = AF_INET;
1390 sockaddr.sin_port = htons(port);
1391 sockaddr.sin_addr.s_addr = 0;
1392 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
1393 if (ret < 0) {
1394 perror("bind");
1395 return -1;
1396 }
1397 ret = listen(fd, 0);
1398 if (ret < 0) {
1399 perror("listen");
1400 return -1;
1401 }
858693c6
FB
1402 return fd;
1403}
1404
1405int gdbserver_start(int port)
1406{
1407 gdbserver_fd = gdbserver_open(port);
1408 if (gdbserver_fd < 0)
1409 return -1;
1410 /* accept connections */
7c9d8e07 1411 gdb_accept (NULL);
4046d913
PB
1412 return 0;
1413}
1fddef4b 1414#else
aa1f17c1 1415static int gdb_chr_can_receive(void *opaque)
4046d913
PB
1416{
1417 return 1;
1418}
1419
aa1f17c1 1420static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
4046d913
PB
1421{
1422 GDBState *s = opaque;
1423 int i;
1424
1425 for (i = 0; i < size; i++) {
1426 gdb_read_byte(s, buf[i]);
1427 }
1428}
1429
1430static void gdb_chr_event(void *opaque, int event)
1431{
1432 switch (event) {
1433 case CHR_EVENT_RESET:
1434 vm_stop(EXCP_INTERRUPT);
a2d1ebaf 1435 gdb_syscall_state = opaque;
4046d913
PB
1436 break;
1437 default:
1438 break;
1439 }
1440}
1441
cfc3475a 1442int gdbserver_start(const char *port)
4046d913
PB
1443{
1444 GDBState *s;
cfc3475a
PB
1445 char gdbstub_port_name[128];
1446 int port_num;
1447 char *p;
1448 CharDriverState *chr;
1449
1450 if (!port || !*port)
1451 return -1;
4046d913 1452
cfc3475a
PB
1453 port_num = strtol(port, &p, 10);
1454 if (*p == 0) {
1455 /* A numeric value is interpreted as a port number. */
1456 snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
1457 "tcp::%d,nowait,nodelay,server", port_num);
1458 port = gdbstub_port_name;
1459 }
1460
1461 chr = qemu_chr_open(port);
4046d913
PB
1462 if (!chr)
1463 return -1;
1464
1465 s = qemu_mallocz(sizeof(GDBState));
1466 if (!s) {
1467 return -1;
1468 }
1469 s->env = first_cpu; /* XXX: allow to change CPU */
1470 s->chr = chr;
aa1f17c1 1471 qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
4046d913
PB
1472 gdb_chr_event, s);
1473 qemu_add_vm_stop_handler(gdb_vm_stopped, s);
b4608c04
FB
1474 return 0;
1475}
4046d913 1476#endif