[qemu.git] / hw / arm_timer.c

/*
 * ARM PrimeCell Timer modules.
 *
 * Copyright (c) 2005-2006 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "sysbus.h"
#include "qemu-timer.h"

/* Common timer implementation.  */

#define TIMER_CTRL_ONESHOT      (1 << 0)
#define TIMER_CTRL_32BIT        (1 << 1)
#define TIMER_CTRL_DIV1         (0 << 2)
#define TIMER_CTRL_DIV16        (1 << 2)
#define TIMER_CTRL_DIV256       (2 << 2)
#define TIMER_CTRL_IE           (1 << 5)
#define TIMER_CTRL_PERIODIC     (1 << 6)
#define TIMER_CTRL_ENABLE       (1 << 7)

typedef struct {
    ptimer_state *timer;
    uint32_t control;
    uint32_t limit;
    int freq;
    int int_level;
    qemu_irq irq;
} arm_timer_state;

/* Check all active timers, and schedule the next timer interrupt.  */

static void arm_timer_update(arm_timer_state *s)
{
    /* Update interrupts.  */
    if (s->int_level && (s->control & TIMER_CTRL_IE)) {
        qemu_irq_raise(s->irq);
    } else {
        qemu_irq_lower(s->irq);
    }
}

static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
{
    arm_timer_state *s = (arm_timer_state *)opaque;

    switch (offset >> 2) {
    case 0: /* TimerLoad */
    case 6: /* TimerBGLoad */
        return s->limit;
    case 1: /* TimerValue */
        return ptimer_get_count(s->timer);
    case 2: /* TimerControl */
        return s->control;
    case 4: /* TimerRIS */
        return s->int_level;
    case 5: /* TimerMIS */
        if ((s->control & TIMER_CTRL_IE) == 0)
            return 0;
        return s->int_level;
    default:
        hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
        return 0;
    }
}

/* Reset the timer limit after settings have changed.  */
static void arm_timer_recalibrate(arm_timer_state *s, int reload)
{
    uint32_t limit;

    if ((s->control & (TIMER_CTRL_PERIODIC | TIMER_CTRL_ONESHOT)) == 0) {
        /* Free running.  */
        if (s->control & TIMER_CTRL_32BIT)
            limit = 0xffffffff;
        else
            limit = 0xffff;
    } else {
          /* Periodic.  */
          limit = s->limit;
    }
    ptimer_set_limit(s->timer, limit, reload);
}

static void arm_timer_write(void *opaque, target_phys_addr_t offset,
                            uint32_t value)
{
    arm_timer_state *s = (arm_timer_state *)opaque;
    int freq;

    switch (offset >> 2) {
    case 0: /* TimerLoad */
        s->limit = value;
        arm_timer_recalibrate(s, 1);
        break;
    case 1: /* TimerValue */
        /* ??? Linux seems to want to write to this readonly register.
           Ignore it.  */
        break;
    case 2: /* TimerControl */
        if (s->control & TIMER_CTRL_ENABLE) {
            /* Pause the timer if it is running.  This may cause some
               inaccuracy dure to rounding, but avoids a whole lot of other
               messyness.  */
            ptimer_stop(s->timer);
        }
        s->control = value;
        freq = s->freq;
        /* ??? Need to recalculate expiry time after changing divisor.  */
        switch ((value >> 2) & 3) {
        case 1: freq >>= 4; break;
        case 2: freq >>= 8; break;
        }
        arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
        ptimer_set_freq(s->timer, freq);
        if (s->control & TIMER_CTRL_ENABLE) {
            /* Restart the timer if still enabled.  */
            ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
        }
        break;
    case 3: /* TimerIntClr */
        s->int_level = 0;
        break;
    case 6: /* TimerBGLoad */
        s->limit = value;
        arm_timer_recalibrate(s, 0);
        break;
    default:
        hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
    }
    arm_timer_update(s);
}

static void arm_timer_tick(void *opaque)
{
    arm_timer_state *s = (arm_timer_state *)opaque;
    s->int_level = 1;
    arm_timer_update(s);
}

static const VMStateDescription vmstate_arm_timer = {
    .name = "arm_timer",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_UINT32(control, arm_timer_state),
        VMSTATE_UINT32(limit, arm_timer_state),
        VMSTATE_INT32(int_level, arm_timer_state),
        VMSTATE_PTIMER(timer, arm_timer_state),
        VMSTATE_END_OF_LIST()
    }
};

static arm_timer_state *arm_timer_init(uint32_t freq)
{
    arm_timer_state *s;
    QEMUBH *bh;

    s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
    s->freq = freq;
    s->control = TIMER_CTRL_IE;

    bh = qemu_bh_new(arm_timer_tick, s);
    s->timer = ptimer_init(bh);
    vmstate_register(NULL, -1, &vmstate_arm_timer, s);
    return s;
}

/* ARM PrimeCell SP804 dual timer module.
   Docs for this device don't seem to be publicly available.  This
   implementation is based on guesswork, the linux kernel sources and the
   Integrator/CP timer modules.  */

typedef struct {
    SysBusDevice busdev;
    arm_timer_state *timer[2];
    int level[2];
    qemu_irq irq;
} sp804_state;

/* Merge the IRQs from the two component devices.  */
static void sp804_set_irq(void *opaque, int irq, int level)
{
    sp804_state *s = (sp804_state *)opaque;

    s->level[irq] = level;
    qemu_set_irq(s->irq, s->level[0] || s->level[1]);
}

static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
{
    sp804_state *s = (sp804_state *)opaque;

    /* ??? Don't know the PrimeCell ID for this device.  */
    if (offset < 0x20) {
        return arm_timer_read(s->timer[0], offset);
    } else {
        return arm_timer_read(s->timer[1], offset - 0x20);
    }
}

static void sp804_write(void *opaque, target_phys_addr_t offset,
                        uint32_t value)
{
    sp804_state *s = (sp804_state *)opaque;

    if (offset < 0x20) {
        arm_timer_write(s->timer[0], offset, value);
    } else {
        arm_timer_write(s->timer[1], offset - 0x20, value);
    }
}

static CPUReadMemoryFunc * const sp804_readfn[] = {
   sp804_read,
   sp804_read,
   sp804_read
};

static CPUWriteMemoryFunc * const sp804_writefn[] = {
   sp804_write,
   sp804_write,
   sp804_write
};


static const VMStateDescription vmstate_sp804 = {
    .name = "sp804",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields      = (VMStateField[]) {
        VMSTATE_INT32_ARRAY(level, sp804_state, 2),
        VMSTATE_END_OF_LIST()
    }
};

static int sp804_init(SysBusDevice *dev)
{
    int iomemtype;
    sp804_state *s = FROM_SYSBUS(sp804_state, dev);
    qemu_irq *qi;

    qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
    sysbus_init_irq(dev, &s->irq);
    /* ??? The timers are actually configurable between 32kHz and 1MHz, but
       we don't implement that.  */
    s->timer[0] = arm_timer_init(1000000);
    s->timer[1] = arm_timer_init(1000000);
    s->timer[0]->irq = qi[0];
    s->timer[1]->irq = qi[1];
    iomemtype = cpu_register_io_memory(sp804_readfn,
                                       sp804_writefn, s, DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
    return 0;
}


/* Integrator/CP timer module.  */

typedef struct {
    SysBusDevice busdev;
    arm_timer_state *timer[3];
} icp_pit_state;

static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
{
    icp_pit_state *s = (icp_pit_state *)opaque;
    int n;

    /* ??? Don't know the PrimeCell ID for this device.  */
    n = offset >> 8;
    if (n > 3) {
        hw_error("sp804_read: Bad timer %d\n", n);
    }

    return arm_timer_read(s->timer[n], offset & 0xff);
}

static void icp_pit_write(void *opaque, target_phys_addr_t offset,
                          uint32_t value)
{
    icp_pit_state *s = (icp_pit_state *)opaque;
    int n;

    n = offset >> 8;
    if (n > 3) {
        hw_error("sp804_write: Bad timer %d\n", n);
    }

    arm_timer_write(s->timer[n], offset & 0xff, value);
}


static CPUReadMemoryFunc * const icp_pit_readfn[] = {
   icp_pit_read,
   icp_pit_read,
   icp_pit_read
};

static CPUWriteMemoryFunc * const icp_pit_writefn[] = {
   icp_pit_write,
   icp_pit_write,
   icp_pit_write
};

static int icp_pit_init(SysBusDevice *dev)
{
    int iomemtype;
    icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);

    /* Timer 0 runs at the system clock speed (40MHz).  */
    s->timer[0] = arm_timer_init(40000000);
    /* The other two timers run at 1MHz.  */
    s->timer[1] = arm_timer_init(1000000);
    s->timer[2] = arm_timer_init(1000000);

    sysbus_init_irq(dev, &s->timer[0]->irq);
    sysbus_init_irq(dev, &s->timer[1]->irq);
    sysbus_init_irq(dev, &s->timer[2]->irq);

    iomemtype = cpu_register_io_memory(icp_pit_readfn,
                                       icp_pit_writefn, s,
                                       DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x1000, iomemtype);
    /* This device has no state to save/restore.  The component timers will
       save themselves.  */
    return 0;
}

static void arm_timer_register_devices(void)
{
    sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
    sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
}

device_init(arm_timer_register_devices)
Commit	Line	Data
5fafdf24	1	/*
cdbdb648 PB	2	* ARM PrimeCell Timer modules.
	3	*
	4	* Copyright (c) 2005-2006 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
cdbdb648 PB	8	*/
cdbdb648 PB	9
6a824ec3	10	#include "sysbus.h"
87ecb68b	11	#include "qemu-timer.h"
cdbdb648 PB	12
	13	/* Common timer implementation. */
	14
	15	#define TIMER_CTRL_ONESHOT (1 << 0)
	16	#define TIMER_CTRL_32BIT (1 << 1)
	17	#define TIMER_CTRL_DIV1 (0 << 2)
	18	#define TIMER_CTRL_DIV16 (1 << 2)
	19	#define TIMER_CTRL_DIV256 (2 << 2)
	20	#define TIMER_CTRL_IE (1 << 5)
	21	#define TIMER_CTRL_PERIODIC (1 << 6)
	22	#define TIMER_CTRL_ENABLE (1 << 7)
	23
	24	typedef struct {
423f0742	25	ptimer_state *timer;
cdbdb648	26	uint32_t control;
cdbdb648	27	uint32_t limit;
cdbdb648 PB	28	int freq;
cdbdb648 PB	29	int int_level;
d537cf6c	30	qemu_irq irq;
cdbdb648 PB	31	} arm_timer_state;
cdbdb648 PB	32
cdbdb648 PB	33	/* Check all active timers, and schedule the next timer interrupt. */
cdbdb648 PB	34
423f0742	35	static void arm_timer_update(arm_timer_state *s)
cdbdb648	36	{
cdbdb648 PB	37	/* Update interrupts. */
cdbdb648 PB	38	if (s->int_level && (s->control & TIMER_CTRL_IE)) {
d537cf6c	39	qemu_irq_raise(s->irq);
cdbdb648	40	} else {
d537cf6c	41	qemu_irq_lower(s->irq);
cdbdb648	42	}
cdbdb648 PB	43	}
cdbdb648 PB	44
c227f099	45	static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset)
cdbdb648 PB	46	{
	47	arm_timer_state s = (arm_timer_state )opaque;
	48
	49	switch (offset >> 2) {
	50	case 0: /* TimerLoad */
	51	case 6: /* TimerBGLoad */
	52	return s->limit;
	53	case 1: /* TimerValue */
423f0742	54	return ptimer_get_count(s->timer);
cdbdb648 PB	55	case 2: /* TimerControl */
	56	return s->control;
	57	case 4: /* TimerRIS */
	58	return s->int_level;
	59	case 5: /* TimerMIS */
	60	if ((s->control & TIMER_CTRL_IE) == 0)
	61	return 0;
	62	return s->int_level;
	63	default:
2ac71179	64	hw_error("arm_timer_read: Bad offset %x\n", (int)offset);
cdbdb648 PB	65	return 0;
	66	}
	67	}
	68
423f0742 PB	69	/* Reset the timer limit after settings have changed. */
	70	static void arm_timer_recalibrate(arm_timer_state *s, int reload)
	71	{
	72	uint32_t limit;
	73
a9cf98d9	74	if ((s->control & (TIMER_CTRL_PERIODIC \| TIMER_CTRL_ONESHOT)) == 0) {
423f0742 PB	75	/* Free running. */
	76	if (s->control & TIMER_CTRL_32BIT)
	77	limit = 0xffffffff;
	78	else
	79	limit = 0xffff;
	80	} else {
	81	/* Periodic. */
	82	limit = s->limit;
	83	}
	84	ptimer_set_limit(s->timer, limit, reload);
	85	}
	86
c227f099	87	static void arm_timer_write(void *opaque, target_phys_addr_t offset,
cdbdb648 PB	88	uint32_t value)
	89	{
	90	arm_timer_state s = (arm_timer_state )opaque;
423f0742	91	int freq;
cdbdb648	92
cdbdb648 PB	93	switch (offset >> 2) {
	94	case 0: /* TimerLoad */
	95	s->limit = value;
423f0742	96	arm_timer_recalibrate(s, 1);
cdbdb648 PB	97	break;
	98	case 1: /* TimerValue */
	99	/* ??? Linux seems to want to write to this readonly register.
	100	Ignore it. */
	101	break;
	102	case 2: /* TimerControl */
	103	if (s->control & TIMER_CTRL_ENABLE) {
	104	/* Pause the timer if it is running. This may cause some
	105	inaccuracy dure to rounding, but avoids a whole lot of other
	106	messyness. */
423f0742	107	ptimer_stop(s->timer);
cdbdb648 PB	108	}
cdbdb648 PB	109	s->control = value;
423f0742	110	freq = s->freq;
cdbdb648 PB	111	/* ??? Need to recalculate expiry time after changing divisor. */
cdbdb648 PB	112	switch ((value >> 2) & 3) {
423f0742 PB	113	case 1: freq >>= 4; break;
423f0742 PB	114	case 2: freq >>= 8; break;
cdbdb648	115	}
d6759902	116	arm_timer_recalibrate(s, s->control & TIMER_CTRL_ENABLE);
423f0742	117	ptimer_set_freq(s->timer, freq);
cdbdb648 PB	118	if (s->control & TIMER_CTRL_ENABLE) {
cdbdb648 PB	119	/* Restart the timer if still enabled. */
423f0742	120	ptimer_run(s->timer, (s->control & TIMER_CTRL_ONESHOT) != 0);
cdbdb648 PB	121	}
	122	break;
	123	case 3: /* TimerIntClr */
	124	s->int_level = 0;
	125	break;
	126	case 6: /* TimerBGLoad */
	127	s->limit = value;
423f0742	128	arm_timer_recalibrate(s, 0);
cdbdb648 PB	129	break;
cdbdb648 PB	130	default:
2ac71179	131	hw_error("arm_timer_write: Bad offset %x\n", (int)offset);
cdbdb648	132	}
423f0742	133	arm_timer_update(s);
cdbdb648 PB	134	}
	135
	136	static void arm_timer_tick(void *opaque)
	137	{
423f0742 PB	138	arm_timer_state s = (arm_timer_state )opaque;
	139	s->int_level = 1;
	140	arm_timer_update(s);
cdbdb648 PB	141	}
cdbdb648 PB	142
eecd33a5 JQ	143	static const VMStateDescription vmstate_arm_timer = {
	144	.name = "arm_timer",
	145	.version_id = 1,
	146	.minimum_version_id = 1,
	147	.minimum_version_id_old = 1,
	148	.fields = (VMStateField[]) {
	149	VMSTATE_UINT32(control, arm_timer_state),
	150	VMSTATE_UINT32(limit, arm_timer_state),
	151	VMSTATE_INT32(int_level, arm_timer_state),
	152	VMSTATE_PTIMER(timer, arm_timer_state),
	153	VMSTATE_END_OF_LIST()
	154	}
	155	};
23e39294	156
6a824ec3	157	static arm_timer_state *arm_timer_init(uint32_t freq)
cdbdb648 PB	158	{
cdbdb648 PB	159	arm_timer_state *s;
423f0742	160	QEMUBH *bh;
cdbdb648	161
7267c094	162	s = (arm_timer_state *)g_malloc0(sizeof(arm_timer_state));
423f0742	163	s->freq = freq;
cdbdb648	164	s->control = TIMER_CTRL_IE;
cdbdb648	165
423f0742 PB	166	bh = qemu_bh_new(arm_timer_tick, s);
423f0742 PB	167	s->timer = ptimer_init(bh);
eecd33a5	168	vmstate_register(NULL, -1, &vmstate_arm_timer, s);
cdbdb648 PB	169	return s;
	170	}
	171
	172	/* ARM PrimeCell SP804 dual timer module.
	173	Docs for this device don't seem to be publicly available. This
d85fb99b	174	implementation is based on guesswork, the linux kernel sources and the
cdbdb648 PB	175	Integrator/CP timer modules. */
	176
	177	typedef struct {
6a824ec3 PB	178	SysBusDevice busdev;
6a824ec3 PB	179	arm_timer_state *timer[2];
cdbdb648	180	int level[2];
d537cf6c	181	qemu_irq irq;
cdbdb648 PB	182	} sp804_state;
cdbdb648 PB	183
d537cf6c	184	/* Merge the IRQs from the two component devices. */
cdbdb648 PB	185	static void sp804_set_irq(void *opaque, int irq, int level)
	186	{
	187	sp804_state s = (sp804_state )opaque;
	188
	189	s->level[irq] = level;
d537cf6c	190	qemu_set_irq(s->irq, s->level[0] \|\| s->level[1]);
cdbdb648 PB	191	}
cdbdb648 PB	192
c227f099	193	static uint32_t sp804_read(void *opaque, target_phys_addr_t offset)
cdbdb648 PB	194	{
	195	sp804_state s = (sp804_state )opaque;
	196
	197	/* ??? Don't know the PrimeCell ID for this device. */
cdbdb648 PB	198	if (offset < 0x20) {
	199	return arm_timer_read(s->timer[0], offset);
	200	} else {
	201	return arm_timer_read(s->timer[1], offset - 0x20);
	202	}
	203	}
	204
c227f099	205	static void sp804_write(void *opaque, target_phys_addr_t offset,
cdbdb648 PB	206	uint32_t value)
	207	{
	208	sp804_state s = (sp804_state )opaque;
	209
cdbdb648 PB	210	if (offset < 0x20) {
	211	arm_timer_write(s->timer[0], offset, value);
	212	} else {
	213	arm_timer_write(s->timer[1], offset - 0x20, value);
	214	}
	215	}
	216
d60efc6b	217	static CPUReadMemoryFunc * const sp804_readfn[] = {
cdbdb648 PB	218	sp804_read,
	219	sp804_read,
	220	sp804_read
	221	};
	222
d60efc6b	223	static CPUWriteMemoryFunc * const sp804_writefn[] = {
cdbdb648 PB	224	sp804_write,
	225	sp804_write,
	226	sp804_write
	227	};
	228
23e39294	229
81986ac4 JQ	230	static const VMStateDescription vmstate_sp804 = {
	231	.name = "sp804",
	232	.version_id = 1,
	233	.minimum_version_id = 1,
	234	.minimum_version_id_old = 1,
	235	.fields = (VMStateField[]) {
	236	VMSTATE_INT32_ARRAY(level, sp804_state, 2),
	237	VMSTATE_END_OF_LIST()
	238	}
	239	};
23e39294	240
81a322d4	241	static int sp804_init(SysBusDevice *dev)
cdbdb648 PB	242	{
cdbdb648 PB	243	int iomemtype;
6a824ec3	244	sp804_state *s = FROM_SYSBUS(sp804_state, dev);
d537cf6c	245	qemu_irq *qi;
cdbdb648	246
d537cf6c	247	qi = qemu_allocate_irqs(sp804_set_irq, s, 2);
6a824ec3	248	sysbus_init_irq(dev, &s->irq);
cdbdb648 PB	249	/* ??? The timers are actually configurable between 32kHz and 1MHz, but
cdbdb648 PB	250	we don't implement that. */
6a824ec3 PB	251	s->timer[0] = arm_timer_init(1000000);
	252	s->timer[1] = arm_timer_init(1000000);
	253	s->timer[0]->irq = qi[0];
	254	s->timer[1]->irq = qi[1];
1eed09cb	255	iomemtype = cpu_register_io_memory(sp804_readfn,
2507c12a	256	sp804_writefn, s, DEVICE_NATIVE_ENDIAN);
6a824ec3	257	sysbus_init_mmio(dev, 0x1000, iomemtype);
81986ac4	258	vmstate_register(&dev->qdev, -1, &vmstate_sp804, s);
81a322d4	259	return 0;
cdbdb648 PB	260	}
	261
	262
	263	/* Integrator/CP timer module. */
	264
	265	typedef struct {
6a824ec3 PB	266	SysBusDevice busdev;
6a824ec3 PB	267	arm_timer_state *timer[3];
cdbdb648 PB	268	} icp_pit_state;
cdbdb648 PB	269
c227f099	270	static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset)
cdbdb648 PB	271	{
	272	icp_pit_state s = (icp_pit_state )opaque;
	273	int n;
	274
	275	/* ??? Don't know the PrimeCell ID for this device. */
cdbdb648	276	n = offset >> 8;
2ac71179 PB	277	if (n > 3) {
	278	hw_error("sp804_read: Bad timer %d\n", n);
	279	}
cdbdb648 PB	280
	281	return arm_timer_read(s->timer[n], offset & 0xff);
	282	}
	283
c227f099	284	static void icp_pit_write(void *opaque, target_phys_addr_t offset,
cdbdb648 PB	285	uint32_t value)
	286	{
	287	icp_pit_state s = (icp_pit_state )opaque;
	288	int n;
	289
cdbdb648	290	n = offset >> 8;
2ac71179 PB	291	if (n > 3) {
	292	hw_error("sp804_write: Bad timer %d\n", n);
	293	}
cdbdb648 PB	294
	295	arm_timer_write(s->timer[n], offset & 0xff, value);
	296	}
	297
	298
d60efc6b	299	static CPUReadMemoryFunc * const icp_pit_readfn[] = {
cdbdb648 PB	300	icp_pit_read,
	301	icp_pit_read,
	302	icp_pit_read
	303	};
	304
d60efc6b	305	static CPUWriteMemoryFunc * const icp_pit_writefn[] = {
cdbdb648 PB	306	icp_pit_write,
	307	icp_pit_write,
	308	icp_pit_write
	309	};
	310
81a322d4	311	static int icp_pit_init(SysBusDevice *dev)
cdbdb648 PB	312	{
cdbdb648 PB	313	int iomemtype;
6a824ec3	314	icp_pit_state *s = FROM_SYSBUS(icp_pit_state, dev);
cdbdb648	315
cdbdb648	316	/* Timer 0 runs at the system clock speed (40MHz). */
6a824ec3	317	s->timer[0] = arm_timer_init(40000000);
cdbdb648	318	/* The other two timers run at 1MHz. */
6a824ec3 PB	319	s->timer[1] = arm_timer_init(1000000);
	320	s->timer[2] = arm_timer_init(1000000);
	321
	322	sysbus_init_irq(dev, &s->timer[0]->irq);
	323	sysbus_init_irq(dev, &s->timer[1]->irq);
	324	sysbus_init_irq(dev, &s->timer[2]->irq);
cdbdb648	325
1eed09cb	326	iomemtype = cpu_register_io_memory(icp_pit_readfn,
2507c12a AG	327	icp_pit_writefn, s,
2507c12a AG	328	DEVICE_NATIVE_ENDIAN);
6a824ec3	329	sysbus_init_mmio(dev, 0x1000, iomemtype);
23e39294 PB	330	/* This device has no state to save/restore. The component timers will
23e39294 PB	331	save themselves. */
81a322d4	332	return 0;
cdbdb648	333	}
6a824ec3 PB	334
	335	static void arm_timer_register_devices(void)
	336	{
	337	sysbus_register_dev("integrator_pit", sizeof(icp_pit_state), icp_pit_init);
	338	sysbus_register_dev("sp804", sizeof(sp804_state), sp804_init);
	339	}
	340
	341	device_init(arm_timer_register_devices)