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f7c70325 PB |
1 | /* |
2 | * Cortex-A9MPCore internal peripheral emulation. | |
3 | * | |
4 | * Copyright (c) 2009 CodeSourcery. | |
b12080cd PM |
5 | * Copyright (c) 2011 Linaro Limited. |
6 | * Written by Paul Brook, Peter Maydell. | |
f7c70325 | 7 | * |
8e31bf38 | 8 | * This code is licensed under the GPL. |
f7c70325 PB |
9 | */ |
10 | ||
de4c2dcf | 11 | #include "hw/cpu/a9mpcore.h" |
b12080cd | 12 | |
ddd76165 PM |
13 | static void a9mp_priv_set_irq(void *opaque, int irq, int level) |
14 | { | |
845769fc | 15 | A9MPPrivState *s = (A9MPPrivState *)opaque; |
9b5f952b AF |
16 | |
17 | qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); | |
ddd76165 PM |
18 | } |
19 | ||
753bc6e9 AF |
20 | static void a9mp_priv_initfn(Object *obj) |
21 | { | |
22 | A9MPPrivState *s = A9MPCORE_PRIV(obj); | |
23 | ||
24 | memory_region_init(&s->container, obj, "a9mp-priv-container", 0x2000); | |
25 | sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->container); | |
9b5f952b AF |
26 | |
27 | object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); | |
28 | qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); | |
fc719d77 AF |
29 | |
30 | object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU); | |
31 | qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); | |
eb110bd8 AF |
32 | |
33 | object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER); | |
34 | qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default()); | |
35 | ||
36 | object_initialize(&s->wdt, sizeof(s->wdt), TYPE_ARM_MPTIMER); | |
37 | qdev_set_parent_bus(DEVICE(&s->wdt), sysbus_get_default()); | |
753bc6e9 AF |
38 | } |
39 | ||
837cf101 | 40 | static void a9mp_priv_realize(DeviceState *dev, Error **errp) |
b12080cd | 41 | { |
837cf101 | 42 | SysBusDevice *sbd = SYS_BUS_DEVICE(dev); |
5126fec7 | 43 | A9MPPrivState *s = A9MPCORE_PRIV(dev); |
eb110bd8 | 44 | DeviceState *gicdev, *scudev, *mptimerdev, *wdtdev; |
353575f0 | 45 | SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev; |
837cf101 | 46 | Error *err = NULL; |
b12080cd PM |
47 | int i; |
48 | ||
9b5f952b AF |
49 | gicdev = DEVICE(&s->gic); |
50 | qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); | |
51 | qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); | |
837cf101 AF |
52 | object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); |
53 | if (err != NULL) { | |
54 | error_propagate(errp, err); | |
55 | return; | |
56 | } | |
9b5f952b | 57 | gicbusdev = SYS_BUS_DEVICE(&s->gic); |
ddd76165 PM |
58 | |
59 | /* Pass through outbound IRQ lines from the GIC */ | |
837cf101 | 60 | sysbus_pass_irq(sbd, gicbusdev); |
ddd76165 PM |
61 | |
62 | /* Pass through inbound GPIO lines to the GIC */ | |
837cf101 | 63 | qdev_init_gpio_in(dev, a9mp_priv_set_irq, s->num_irq - 32); |
b12080cd | 64 | |
fc719d77 AF |
65 | scudev = DEVICE(&s->scu); |
66 | qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); | |
837cf101 AF |
67 | object_property_set_bool(OBJECT(&s->scu), true, "realized", &err); |
68 | if (err != NULL) { | |
69 | error_propagate(errp, err); | |
70 | return; | |
71 | } | |
fc719d77 | 72 | scubusdev = SYS_BUS_DEVICE(&s->scu); |
353575f0 | 73 | |
eb110bd8 AF |
74 | mptimerdev = DEVICE(&s->mptimer); |
75 | qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu); | |
837cf101 AF |
76 | object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err); |
77 | if (err != NULL) { | |
78 | error_propagate(errp, err); | |
79 | return; | |
80 | } | |
eb110bd8 | 81 | timerbusdev = SYS_BUS_DEVICE(&s->mptimer); |
cde4577f | 82 | |
eb110bd8 AF |
83 | wdtdev = DEVICE(&s->wdt); |
84 | qdev_prop_set_uint32(wdtdev, "num-cpu", s->num_cpu); | |
837cf101 AF |
85 | object_property_set_bool(OBJECT(&s->wdt), true, "realized", &err); |
86 | if (err != NULL) { | |
87 | error_propagate(errp, err); | |
88 | return; | |
89 | } | |
eb110bd8 | 90 | wdtbusdev = SYS_BUS_DEVICE(&s->wdt); |
b12080cd PM |
91 | |
92 | /* Memory map (addresses are offsets from PERIPHBASE): | |
93 | * 0x0000-0x00ff -- Snoop Control Unit | |
94 | * 0x0100-0x01ff -- GIC CPU interface | |
95 | * 0x0200-0x02ff -- Global Timer | |
96 | * 0x0300-0x05ff -- nothing | |
97 | * 0x0600-0x06ff -- private timers and watchdogs | |
98 | * 0x0700-0x0fff -- nothing | |
99 | * 0x1000-0x1fff -- GIC Distributor | |
100 | * | |
101 | * We should implement the global timer but don't currently do so. | |
102 | */ | |
353575f0 PC |
103 | memory_region_add_subregion(&s->container, 0, |
104 | sysbus_mmio_get_region(scubusdev, 0)); | |
b12080cd | 105 | /* GIC CPU interface */ |
ddd76165 PM |
106 | memory_region_add_subregion(&s->container, 0x100, |
107 | sysbus_mmio_get_region(gicbusdev, 1)); | |
b12080cd PM |
108 | /* Note that the A9 exposes only the "timer/watchdog for this core" |
109 | * memory region, not the "timer/watchdog for core X" ones 11MPcore has. | |
110 | */ | |
111 | memory_region_add_subregion(&s->container, 0x600, | |
cde4577f | 112 | sysbus_mmio_get_region(timerbusdev, 0)); |
b12080cd | 113 | memory_region_add_subregion(&s->container, 0x620, |
cde4577f | 114 | sysbus_mmio_get_region(wdtbusdev, 0)); |
ddd76165 PM |
115 | memory_region_add_subregion(&s->container, 0x1000, |
116 | sysbus_mmio_get_region(gicbusdev, 0)); | |
b12080cd | 117 | |
ddd76165 PM |
118 | /* Wire up the interrupt from each watchdog and timer. |
119 | * For each core the timer is PPI 29 and the watchdog PPI 30. | |
120 | */ | |
121 | for (i = 0; i < s->num_cpu; i++) { | |
122 | int ppibase = (s->num_irq - 32) + i * 32; | |
cde4577f | 123 | sysbus_connect_irq(timerbusdev, i, |
9b5f952b | 124 | qdev_get_gpio_in(gicdev, ppibase + 29)); |
cde4577f | 125 | sysbus_connect_irq(wdtbusdev, i, |
9b5f952b | 126 | qdev_get_gpio_in(gicdev, ppibase + 30)); |
b12080cd | 127 | } |
b12080cd PM |
128 | } |
129 | ||
39bffca2 | 130 | static Property a9mp_priv_properties[] = { |
845769fc | 131 | DEFINE_PROP_UINT32("num-cpu", A9MPPrivState, num_cpu, 1), |
39bffca2 AL |
132 | /* The Cortex-A9MP may have anything from 0 to 224 external interrupt |
133 | * IRQ lines (with another 32 internal). We default to 64+32, which | |
134 | * is the number provided by the Cortex-A9MP test chip in the | |
135 | * Realview PBX-A9 and Versatile Express A9 development boards. | |
136 | * Other boards may differ and should set this property appropriately. | |
137 | */ | |
845769fc | 138 | DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), |
39bffca2 AL |
139 | DEFINE_PROP_END_OF_LIST(), |
140 | }; | |
141 | ||
999e12bb AL |
142 | static void a9mp_priv_class_init(ObjectClass *klass, void *data) |
143 | { | |
39bffca2 | 144 | DeviceClass *dc = DEVICE_CLASS(klass); |
999e12bb | 145 | |
837cf101 | 146 | dc->realize = a9mp_priv_realize; |
39bffca2 | 147 | dc->props = a9mp_priv_properties; |
999e12bb AL |
148 | } |
149 | ||
8c43a6f0 | 150 | static const TypeInfo a9mp_priv_info = { |
5126fec7 | 151 | .name = TYPE_A9MPCORE_PRIV, |
39bffca2 | 152 | .parent = TYPE_SYS_BUS_DEVICE, |
845769fc | 153 | .instance_size = sizeof(A9MPPrivState), |
753bc6e9 | 154 | .instance_init = a9mp_priv_initfn, |
39bffca2 | 155 | .class_init = a9mp_priv_class_init, |
f7c70325 PB |
156 | }; |
157 | ||
83f7d43a | 158 | static void a9mp_register_types(void) |
f7c70325 | 159 | { |
39bffca2 | 160 | type_register_static(&a9mp_priv_info); |
f7c70325 PB |
161 | } |
162 | ||
83f7d43a | 163 | type_init(a9mp_register_types) |