[qemu.git] / hw / cpu / arm11mpcore.c

/*
 * ARM11MPCore internal peripheral emulation.
 *
 * Copyright (c) 2006-2007 CodeSourcery.
 * Written by Paul Brook
 *
 * This code is licensed under the GPL.
 */

#include "hw/sysbus.h"
#include "hw/misc/arm11scu.h"
#include "hw/intc/arm_gic.h"
#include "hw/timer/arm_mptimer.h"
#include "qemu/timer.h"

/* MPCore private memory region.  */

#define TYPE_ARM11MPCORE_PRIV "arm11mpcore_priv"
#define ARM11MPCORE_PRIV(obj) \
    OBJECT_CHECK(ARM11MPCorePriveState, (obj), TYPE_ARM11MPCORE_PRIV)

typedef struct ARM11MPCorePriveState {
    SysBusDevice parent_obj;

    uint32_t num_cpu;
    MemoryRegion container;
    uint32_t num_irq;

    ARM11SCUState scu;
    GICState gic;
    ARMMPTimerState mptimer;
    ARMMPTimerState wdtimer;
} ARM11MPCorePriveState;

/* Per-CPU private memory mapped IO.  */


static void mpcore_priv_set_irq(void *opaque, int irq, int level)
{
    ARM11MPCorePriveState *s = (ARM11MPCorePriveState *)opaque;

    qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
}

static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
{
    int i;
    SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu);
    DeviceState *gicdev = DEVICE(&s->gic);
    SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic);
    SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer);
    SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer);

    memory_region_add_subregion(&s->container, 0,
                                sysbus_mmio_get_region(scubusdev, 0));
    /* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
     * at 0x200, 0x300...
     */
    for (i = 0; i < (s->num_cpu + 1); i++) {
        hwaddr offset = 0x100 + (i * 0x100);
        memory_region_add_subregion(&s->container, offset,
                                    sysbus_mmio_get_region(gicbusdev, i + 1));
    }
    /* Add the regions for timer and watchdog for "current CPU" and
     * for each specific CPU.
     */
    for (i = 0; i < (s->num_cpu + 1); i++) {
        /* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
        hwaddr offset = 0x600 + i * 0x100;
        memory_region_add_subregion(&s->container, offset,
                                    sysbus_mmio_get_region(timerbusdev, i));
        memory_region_add_subregion(&s->container, offset + 0x20,
                                    sysbus_mmio_get_region(wdtbusdev, i));
    }
    memory_region_add_subregion(&s->container, 0x1000,
                                sysbus_mmio_get_region(gicbusdev, 0));
    /* Wire up the interrupt from each watchdog and timer.
     * For each core the timer is PPI 29 and the watchdog PPI 30.
     */
    for (i = 0; i < s->num_cpu; i++) {
        int ppibase = (s->num_irq - 32) + i * 32;
        sysbus_connect_irq(timerbusdev, i,
                           qdev_get_gpio_in(gicdev, ppibase + 29));
        sysbus_connect_irq(wdtbusdev, i,
                           qdev_get_gpio_in(gicdev, ppibase + 30));
    }
}

static void mpcore_priv_realize(DeviceState *dev, Error **errp)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
    ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
    DeviceState *scudev = DEVICE(&s->scu);
    DeviceState *gicdev = DEVICE(&s->gic);
    DeviceState *mptimerdev = DEVICE(&s->mptimer);
    DeviceState *wdtimerdev = DEVICE(&s->wdtimer);
    Error *err = NULL;

    qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
    object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }

    qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
    qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
    object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }

    /* Pass through outbound IRQ lines from the GIC */
    sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic));

    /* Pass through inbound GPIO lines to the GIC */
    qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);

    qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
    object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }

    qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu);
    object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err);
    if (err != NULL) {
        error_propagate(errp, err);
        return;
    }

    mpcore_priv_map_setup(s);
}

static void mpcore_priv_initfn(Object *obj)
{
    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
    ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj);

    memory_region_init(&s->container, OBJECT(s),
                       "mpcore-priv-container", 0x2000);
    sysbus_init_mmio(sbd, &s->container);

    object_initialize(&s->scu, sizeof(s->scu), TYPE_ARM11_SCU);
    qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());

    object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
    qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
    /* Request the legacy 11MPCore GIC behaviour: */
    qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0);

    object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER);
    qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default());

    object_initialize(&s->wdtimer, sizeof(s->wdtimer), TYPE_ARM_MPTIMER);
    qdev_set_parent_bus(DEVICE(&s->wdtimer), sysbus_get_default());
}

#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
#define REALVIEW_MPCORE_RIRQ(obj) \
    OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)

/* Dummy PIC to route IRQ lines.  The baseboard has 4 independent IRQ
   controllers.  The output of these, plus some of the raw input lines
   are fed into a single SMP-aware interrupt controller on the CPU.  */
typedef struct {
    SysBusDevice parent_obj;

    SysBusDevice *priv;
    qemu_irq cpuic[32];
    qemu_irq rvic[4][64];
    uint32_t num_cpu;
} mpcore_rirq_state;

/* Map baseboard IRQs onto CPU IRQ lines.  */
static const int mpcore_irq_map[32] = {
    -1, -1, -1, -1,  1,  2, -1, -1,
    -1, -1,  6, -1,  4,  5, -1, -1,
    -1, 14, 15,  0,  7,  8, -1, -1,
    -1, -1, -1, -1,  9,  3, -1, -1,
};

static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
{
    mpcore_rirq_state *s = (mpcore_rirq_state *)opaque;
    int i;

    for (i = 0; i < 4; i++) {
        qemu_set_irq(s->rvic[i][irq], level);
    }
    if (irq < 32) {
        irq = mpcore_irq_map[irq];
        if (irq >= 0) {
            qemu_set_irq(s->cpuic[irq], level);
        }
    }
}

static int realview_mpcore_init(SysBusDevice *sbd)
{
    DeviceState *dev = DEVICE(sbd);
    mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
    DeviceState *gic;
    DeviceState *priv;
    int n;
    int i;

    priv = qdev_create(NULL, TYPE_ARM11MPCORE_PRIV);
    qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
    qdev_init_nofail(priv);
    s->priv = SYS_BUS_DEVICE(priv);
    sysbus_pass_irq(sbd, s->priv);
    for (i = 0; i < 32; i++) {
        s->cpuic[i] = qdev_get_gpio_in(priv, i);
    }
    /* ??? IRQ routing is hardcoded to "normal" mode.  */
    for (n = 0; n < 4; n++) {
        gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
                                   s->cpuic[10 + n]);
        for (i = 0; i < 64; i++) {
            s->rvic[n][i] = qdev_get_gpio_in(gic, i);
        }
    }
    qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
    sysbus_init_mmio(sbd, sysbus_mmio_get_region(s->priv, 0));
    return 0;
}

static Property mpcore_rirq_properties[] = {
    DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
    DEFINE_PROP_END_OF_LIST(),
};

static void mpcore_rirq_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);
    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);

    k->init = realview_mpcore_init;
    dc->props = mpcore_rirq_properties;
}

static const TypeInfo mpcore_rirq_info = {
    .name          = TYPE_REALVIEW_MPCORE_RIRQ,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(mpcore_rirq_state),
    .class_init    = mpcore_rirq_class_init,
};

static Property mpcore_priv_properties[] = {
    DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
    /* The ARM11 MPCORE TRM says the on-chip controller may have
     * anything from 0 to 224 external interrupt IRQ lines (with another
     * 32 internal). We default to 32+32, which is the number provided by
     * the ARM11 MPCore test chip in the Realview Versatile Express
     * coretile. Other boards may differ and should set this property
     * appropriately. Some Linux kernels may not boot if the hardware
     * has more IRQ lines than the kernel expects.
     */
    DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64),
    DEFINE_PROP_END_OF_LIST(),
};

static void mpcore_priv_class_init(ObjectClass *klass, void *data)
{
    DeviceClass *dc = DEVICE_CLASS(klass);

    dc->realize = mpcore_priv_realize;
    dc->props = mpcore_priv_properties;
}

static const TypeInfo mpcore_priv_info = {
    .name          = TYPE_ARM11MPCORE_PRIV,
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(ARM11MPCorePriveState),
    .instance_init = mpcore_priv_initfn,
    .class_init    = mpcore_priv_class_init,
};

static void arm11mpcore_register_types(void)
{
    type_register_static(&mpcore_rirq_info);
    type_register_static(&mpcore_priv_info);
}

type_init(arm11mpcore_register_types)
Commit	Line	Data
f7c70325 PB	1	/*
	2	* ARM11MPCore internal peripheral emulation.
	3	*
	4	* Copyright (c) 2006-2007 CodeSourcery.
	5	* Written by Paul Brook
	6	*
8e31bf38	7	* This code is licensed under the GPL.
f7c70325 PB	8	*/
f7c70325 PB	9
83c9f4ca	10	#include "hw/sysbus.h"
53cb9a1c	11	#include "hw/misc/arm11scu.h"
08602ac5 AF	12	#include "hw/intc/arm_gic.h"
08602ac5 AF	13	#include "hw/timer/arm_mptimer.h"
1de7afc9	14	#include "qemu/timer.h"
2a6ab1e3	15
2a6ab1e3 PM	16	/* MPCore private memory region. */
2a6ab1e3 PM	17
56fc0281 AF	18	#define TYPE_ARM11MPCORE_PRIV "arm11mpcore_priv"
	19	#define ARM11MPCORE_PRIV(obj) \
	20	OBJECT_CHECK(ARM11MPCorePriveState, (obj), TYPE_ARM11MPCORE_PRIV)
	21
845769fc	22	typedef struct ARM11MPCorePriveState {
56fc0281 AF	23	SysBusDevice parent_obj;
56fc0281 AF	24
2a6ab1e3	25	uint32_t num_cpu;
2a6ab1e3	26	MemoryRegion container;
a32134aa	27	uint32_t num_irq;
53cb9a1c AF	28
53cb9a1c AF	29	ARM11SCUState scu;
08602ac5 AF	30	GICState gic;
	31	ARMMPTimerState mptimer;
	32	ARMMPTimerState wdtimer;
845769fc	33	} ARM11MPCorePriveState;
2a6ab1e3 PM	34
	35	/* Per-CPU private memory mapped IO. */
	36
2a6ab1e3	37
2e9dfe20	38	static void mpcore_priv_set_irq(void *opaque, int irq, int level)
2a6ab1e3	39	{
845769fc	40	ARM11MPCorePriveState s = (ARM11MPCorePriveState )opaque;
08602ac5 AF	41
08602ac5 AF	42	qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level);
2a6ab1e3 PM	43	}
2a6ab1e3 PM	44
845769fc	45	static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
2a6ab1e3 PM	46	{
2a6ab1e3 PM	47	int i;
53cb9a1c	48	SysBusDevice *scubusdev = SYS_BUS_DEVICE(&s->scu);
08602ac5 AF	49	DeviceState *gicdev = DEVICE(&s->gic);
	50	SysBusDevice *gicbusdev = SYS_BUS_DEVICE(&s->gic);
	51	SysBusDevice *timerbusdev = SYS_BUS_DEVICE(&s->mptimer);
	52	SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(&s->wdtimer);
53cb9a1c AF	53
	54	memory_region_add_subregion(&s->container, 0,
	55	sysbus_mmio_get_region(scubusdev, 0));
2a6ab1e3 PM	56	/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
	57	* at 0x200, 0x300...
	58	*/
	59	for (i = 0; i < (s->num_cpu + 1); i++) {
a8170e5e	60	hwaddr offset = 0x100 + (i * 0x100);
2e9dfe20 PM	61	memory_region_add_subregion(&s->container, offset,
2e9dfe20 PM	62	sysbus_mmio_get_region(gicbusdev, i + 1));
2a6ab1e3 PM	63	}
	64	/* Add the regions for timer and watchdog for "current CPU" and
	65	* for each specific CPU.
	66	*/
cde4577f	67	for (i = 0; i < (s->num_cpu + 1); i++) {
2a6ab1e3	68	/* Timers at 0x600, 0x700, ...; watchdogs at 0x620, 0x720, ... */
cde4577f	69	hwaddr offset = 0x600 + i * 0x100;
2a6ab1e3	70	memory_region_add_subregion(&s->container, offset,
cde4577f PC	71	sysbus_mmio_get_region(timerbusdev, i));
	72	memory_region_add_subregion(&s->container, offset + 0x20,
	73	sysbus_mmio_get_region(wdtbusdev, i));
2a6ab1e3	74	}
2e9dfe20 PM	75	memory_region_add_subregion(&s->container, 0x1000,
	76	sysbus_mmio_get_region(gicbusdev, 0));
	77	/* Wire up the interrupt from each watchdog and timer.
	78	* For each core the timer is PPI 29 and the watchdog PPI 30.
	79	*/
	80	for (i = 0; i < s->num_cpu; i++) {
	81	int ppibase = (s->num_irq - 32) + i * 32;
cde4577f	82	sysbus_connect_irq(timerbusdev, i,
08602ac5	83	qdev_get_gpio_in(gicdev, ppibase + 29));
cde4577f	84	sysbus_connect_irq(wdtbusdev, i,
08602ac5	85	qdev_get_gpio_in(gicdev, ppibase + 30));
2a6ab1e3 PM	86	}
	87	}
	88
08602ac5	89	static void mpcore_priv_realize(DeviceState dev, Error *errp)
2a6ab1e3	90	{
08602ac5	91	SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
56fc0281	92	ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(dev);
53cb9a1c	93	DeviceState *scudev = DEVICE(&s->scu);
08602ac5 AF	94	DeviceState *gicdev = DEVICE(&s->gic);
	95	DeviceState *mptimerdev = DEVICE(&s->mptimer);
	96	DeviceState *wdtimerdev = DEVICE(&s->wdtimer);
	97	Error *err = NULL;
53cb9a1c AF	98
53cb9a1c AF	99	qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu);
08602ac5 AF	100	object_property_set_bool(OBJECT(&s->scu), true, "realized", &err);
	101	if (err != NULL) {
	102	error_propagate(errp, err);
	103	return;
	104	}
2e9dfe20	105
08602ac5 AF	106	qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu);
	107	qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq);
	108	object_property_set_bool(OBJECT(&s->gic), true, "realized", &err);
	109	if (err != NULL) {
	110	error_propagate(errp, err);
	111	return;
	112	}
2e9dfe20 PM	113
2e9dfe20 PM	114	/* Pass through outbound IRQ lines from the GIC */
08602ac5	115	sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->gic));
2e9dfe20 PM	116
2e9dfe20 PM	117	/* Pass through inbound GPIO lines to the GIC */
56fc0281	118	qdev_init_gpio_in(dev, mpcore_priv_set_irq, s->num_irq - 32);
2a6ab1e3	119
08602ac5 AF	120	qdev_prop_set_uint32(mptimerdev, "num-cpu", s->num_cpu);
	121	object_property_set_bool(OBJECT(&s->mptimer), true, "realized", &err);
	122	if (err != NULL) {
	123	error_propagate(errp, err);
	124	return;
	125	}
cde4577f	126
08602ac5 AF	127	qdev_prop_set_uint32(wdtimerdev, "num-cpu", s->num_cpu);
	128	object_property_set_bool(OBJECT(&s->wdtimer), true, "realized", &err);
	129	if (err != NULL) {
	130	error_propagate(errp, err);
	131	return;
	132	}
cde4577f	133
2a6ab1e3	134	mpcore_priv_map_setup(s);
2a6ab1e3	135	}
f7c70325	136
2c42c3a0 AF	137	static void mpcore_priv_initfn(Object *obj)
	138	{
	139	SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
	140	ARM11MPCorePriveState *s = ARM11MPCORE_PRIV(obj);
	141
	142	memory_region_init(&s->container, OBJECT(s),
	143	"mpcore-priv-container", 0x2000);
	144	sysbus_init_mmio(sbd, &s->container);
53cb9a1c AF	145
	146	object_initialize(&s->scu, sizeof(s->scu), TYPE_ARM11_SCU);
	147	qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default());
08602ac5 AF	148
	149	object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC);
	150	qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default());
	151	/* Request the legacy 11MPCore GIC behaviour: */
	152	qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 0);
	153
	154	object_initialize(&s->mptimer, sizeof(s->mptimer), TYPE_ARM_MPTIMER);
	155	qdev_set_parent_bus(DEVICE(&s->mptimer), sysbus_get_default());
	156
	157	object_initialize(&s->wdtimer, sizeof(s->wdtimer), TYPE_ARM_MPTIMER);
	158	qdev_set_parent_bus(DEVICE(&s->wdtimer), sysbus_get_default());
2c42c3a0 AF	159	}
2c42c3a0 AF	160
45c0a675 AF	161	#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore"
	162	#define REALVIEW_MPCORE_RIRQ(obj) \
	163	OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ)
	164
f7c70325 PB	165	/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ
	166	controllers. The output of these, plus some of the raw input lines
	167	are fed into a single SMP-aware interrupt controller on the CPU. */
	168	typedef struct {
45c0a675 AF	169	SysBusDevice parent_obj;
45c0a675 AF	170
f7c70325 PB	171	SysBusDevice *priv;
	172	qemu_irq cpuic[32];
	173	qemu_irq rvic[4][64];
	174	uint32_t num_cpu;
	175	} mpcore_rirq_state;
	176
	177	/* Map baseboard IRQs onto CPU IRQ lines. */
	178	static const int mpcore_irq_map[32] = {
	179	-1, -1, -1, -1, 1, 2, -1, -1,
	180	-1, -1, 6, -1, 4, 5, -1, -1,
	181	-1, 14, 15, 0, 7, 8, -1, -1,
	182	-1, -1, -1, -1, 9, 3, -1, -1,
	183	};
	184
	185	static void mpcore_rirq_set_irq(void *opaque, int irq, int level)
	186	{
	187	mpcore_rirq_state s = (mpcore_rirq_state )opaque;
	188	int i;
	189
	190	for (i = 0; i < 4; i++) {
	191	qemu_set_irq(s->rvic[i][irq], level);
	192	}
	193	if (irq < 32) {
	194	irq = mpcore_irq_map[irq];
	195	if (irq >= 0) {
	196	qemu_set_irq(s->cpuic[irq], level);
	197	}
	198	}
	199	}
	200
45c0a675	201	static int realview_mpcore_init(SysBusDevice *sbd)
f7c70325	202	{
45c0a675 AF	203	DeviceState *dev = DEVICE(sbd);
45c0a675 AF	204	mpcore_rirq_state *s = REALVIEW_MPCORE_RIRQ(dev);
f7c70325 PB	205	DeviceState *gic;
	206	DeviceState *priv;
	207	int n;
	208	int i;
	209
56fc0281	210	priv = qdev_create(NULL, TYPE_ARM11MPCORE_PRIV);
f7c70325 PB	211	qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu);
f7c70325 PB	212	qdev_init_nofail(priv);
1356b98d	213	s->priv = SYS_BUS_DEVICE(priv);
45c0a675	214	sysbus_pass_irq(sbd, s->priv);
f7c70325 PB	215	for (i = 0; i < 32; i++) {
	216	s->cpuic[i] = qdev_get_gpio_in(priv, i);
	217	}
	218	/* ??? IRQ routing is hardcoded to "normal" mode. */
	219	for (n = 0; n < 4; n++) {
	220	gic = sysbus_create_simple("realview_gic", 0x10040000 + n * 0x10000,
	221	s->cpuic[10 + n]);
	222	for (i = 0; i < 64; i++) {
	223	s->rvic[n][i] = qdev_get_gpio_in(gic, i);
	224	}
	225	}
45c0a675 AF	226	qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64);
45c0a675 AF	227	sysbus_init_mmio(sbd, sysbus_mmio_get_region(s->priv, 0));
f7c70325 PB	228	return 0;
	229	}
	230
999e12bb	231	static Property mpcore_rirq_properties[] = {
0f58a188	232	DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1),
999e12bb	233	DEFINE_PROP_END_OF_LIST(),
f7c70325 PB	234	};
f7c70325 PB	235
999e12bb AL	236	static void mpcore_rirq_class_init(ObjectClass klass, void data)
999e12bb AL	237	{
39bffca2	238	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	239	SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
	240
	241	k->init = realview_mpcore_init;
39bffca2	242	dc->props = mpcore_rirq_properties;
999e12bb AL	243	}
999e12bb AL	244
8c43a6f0	245	static const TypeInfo mpcore_rirq_info = {
45c0a675	246	.name = TYPE_REALVIEW_MPCORE_RIRQ,
39bffca2 AL	247	.parent = TYPE_SYS_BUS_DEVICE,
	248	.instance_size = sizeof(mpcore_rirq_state),
	249	.class_init = mpcore_rirq_class_init,
999e12bb AL	250	};
	251
	252	static Property mpcore_priv_properties[] = {
845769fc	253	DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1),
0f58a188 PM	254	/* The ARM11 MPCORE TRM says the on-chip controller may have
	255	* anything from 0 to 224 external interrupt IRQ lines (with another
	256	* 32 internal). We default to 32+32, which is the number provided by
	257	* the ARM11 MPCore test chip in the Realview Versatile Express
	258	* coretile. Other boards may differ and should set this property
	259	* appropriately. Some Linux kernels may not boot if the hardware
	260	* has more IRQ lines than the kernel expects.
	261	*/
845769fc	262	DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64),
999e12bb AL	263	DEFINE_PROP_END_OF_LIST(),
	264	};
	265
	266	static void mpcore_priv_class_init(ObjectClass klass, void data)
	267	{
39bffca2	268	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb	269
08602ac5	270	dc->realize = mpcore_priv_realize;
39bffca2	271	dc->props = mpcore_priv_properties;
999e12bb AL	272	}
999e12bb AL	273
8c43a6f0	274	static const TypeInfo mpcore_priv_info = {
56fc0281	275	.name = TYPE_ARM11MPCORE_PRIV,
39bffca2	276	.parent = TYPE_SYS_BUS_DEVICE,
845769fc	277	.instance_size = sizeof(ARM11MPCorePriveState),
2c42c3a0	278	.instance_init = mpcore_priv_initfn,
39bffca2	279	.class_init = mpcore_priv_class_init,
f7c70325 PB	280	};
f7c70325 PB	281
83f7d43a	282	static void arm11mpcore_register_types(void)
f7c70325	283	{
39bffca2 AL	284	type_register_static(&mpcore_rirq_info);
39bffca2 AL	285	type_register_static(&mpcore_priv_info);
f7c70325 PB	286	}
f7c70325 PB	287
83f7d43a	288	type_init(arm11mpcore_register_types)