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30aa5c0d
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1/*
2 * QEMU NVRAM emulation for DS1225Y chip
02cb1585 3 *
bcc4e41f 4 * Copyright (c) 2007-2008 Hervé Poussineau
02cb1585 5 *
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6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
83c9f4ca 25#include "hw/sysbus.h"
d43ed9ec 26#include "trace.h"
30aa5c0d 27
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28typedef struct {
29 DeviceState qdev;
871321ac 30 MemoryRegion iomem;
02cb1585 31 uint32_t chip_size;
cd3e2409 32 char *filename;
3a230256 33 FILE *file;
02cb1585 34 uint8_t *contents;
cd3e2409 35} NvRamState;
30aa5c0d 36
a8170e5e 37static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size)
30aa5c0d 38{
cd3e2409 39 NvRamState *s = opaque;
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40 uint32_t val;
41
8da3ff18 42 val = s->contents[addr];
d43ed9ec 43 trace_nvram_read(addr, val);
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44 return val;
45}
30aa5c0d 46
a8170e5e 47static void nvram_write(void *opaque, hwaddr addr, uint64_t val,
871321ac 48 unsigned size)
30aa5c0d 49{
cd3e2409 50 NvRamState *s = opaque;
30aa5c0d 51
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52 val &= 0xff;
53 trace_nvram_write(addr, s->contents[addr], val);
02cb1585 54
d43ed9ec 55 s->contents[addr] = val;
02cb1585 56 if (s->file) {
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57 fseek(s->file, addr, SEEK_SET);
58 fputc(val, s->file);
59 fflush(s->file);
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60 }
61}
62
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63static const MemoryRegionOps nvram_ops = {
64 .read = nvram_read,
65 .write = nvram_write,
66 .impl = {
67 .min_access_size = 1,
68 .max_access_size = 1,
69 },
70 .endianness = DEVICE_LITTLE_ENDIAN,
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71};
72
cd3e2409 73static int nvram_post_load(void *opaque, int version_id)
30aa5c0d 74{
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75 NvRamState *s = opaque;
76
77 /* Close file, as filename may has changed in load/store process */
78 if (s->file) {
3a230256 79 fclose(s->file);
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80 }
81
82 /* Write back nvram contents */
3a230256 83 s->file = fopen(s->filename, "wb");
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84 if (s->file) {
85 /* Write back contents, as 'wb' mode cleaned the file */
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86 if (fwrite(s->contents, s->chip_size, 1, s->file) != 1) {
87 printf("nvram_post_load: short write\n");
88 }
89 fflush(s->file);
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90 }
91
92 return 0;
93}
94
95static const VMStateDescription vmstate_nvram = {
96 .name = "nvram",
97 .version_id = 0,
98 .minimum_version_id = 0,
99 .minimum_version_id_old = 0,
100 .post_load = nvram_post_load,
101 .fields = (VMStateField[]) {
102 VMSTATE_VARRAY_UINT32(contents, NvRamState, chip_size, 0,
103 vmstate_info_uint8, uint8_t),
104 VMSTATE_END_OF_LIST()
105 }
106};
107
108typedef struct {
109 SysBusDevice busdev;
110 NvRamState nvram;
111} SysBusNvRamState;
112
113static int nvram_sysbus_initfn(SysBusDevice *dev)
114{
115 NvRamState *s = &FROM_SYSBUS(SysBusNvRamState, dev)->nvram;
3a230256 116 FILE *file;
30aa5c0d 117
7267c094 118 s->contents = g_malloc0(s->chip_size);
02cb1585 119
871321ac 120 memory_region_init_io(&s->iomem, &nvram_ops, s, "nvram", s->chip_size);
750ecd44 121 sysbus_init_mmio(dev, &s->iomem);
cd3e2409 122
02cb1585 123 /* Read current file */
3a230256 124 file = fopen(s->filename, "rb");
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125 if (file) {
126 /* Read nvram contents */
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127 if (fread(s->contents, s->chip_size, 1, file) != 1) {
128 printf("nvram_sysbus_initfn: short read\n");
129 }
130 fclose(file);
02cb1585 131 }
cd3e2409 132 nvram_post_load(s, 0);
30aa5c0d 133
cd3e2409 134 return 0;
30aa5c0d 135}
cd3e2409 136
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137static Property nvram_sysbus_properties[] = {
138 DEFINE_PROP_UINT32("size", SysBusNvRamState, nvram.chip_size, 0x2000),
139 DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename),
140 DEFINE_PROP_END_OF_LIST(),
141};
142
143static void nvram_sysbus_class_init(ObjectClass *klass, void *data)
144{
39bffca2 145 DeviceClass *dc = DEVICE_CLASS(klass);
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146 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
147
148 k->init = nvram_sysbus_initfn;
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149 dc->vmsd = &vmstate_nvram;
150 dc->props = nvram_sysbus_properties;
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151}
152
8c43a6f0 153static const TypeInfo nvram_sysbus_info = {
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154 .name = "ds1225y",
155 .parent = TYPE_SYS_BUS_DEVICE,
156 .instance_size = sizeof(SysBusNvRamState),
157 .class_init = nvram_sysbus_class_init,
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158};
159
83f7d43a 160static void nvram_register_types(void)
cd3e2409 161{
39bffca2 162 type_register_static(&nvram_sysbus_info);
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163}
164
83f7d43a 165type_init(nvram_register_types)