[qemu.git] / hw / highbank.c

/*
 * Calxeda Highbank SoC emulation
 *
 * Copyright (c) 2010-2012 Calxeda
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2 or later, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 *
 */

#include "sysbus.h"
#include "arm-misc.h"
#include "devices.h"
#include "loader.h"
#include "net/net.h"
#include "sysemu/sysemu.h"
#include "boards.h"
#include "sysbus.h"
#include "sysemu/blockdev.h"
#include "exec/address-spaces.h"

#define SMP_BOOT_ADDR 0x100
#define SMP_BOOT_REG  0x40
#define GIC_BASE_ADDR 0xfff10000

#define NIRQ_GIC      160

/* Board init.  */

static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
{
    int n;
    uint32_t smpboot[] = {
        0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
        0xe210000f, /* ands r0, r0, #0x0f */
        0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
        0xe0830200, /* add r0, r3, r0, lsl #4 */
        0xe59f2024, /* ldr r2, privbase */
        0xe3a01001, /* mov r1, #1 */
        0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
        0xe3a010ff, /* mov r1, #0xff */
        0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
        0xf57ff04f, /* dsb */
        0xe320f003, /* wfi */
        0xe5901000, /* ldr     r1, [r0] */
        0xe1110001, /* tst     r1, r1 */
        0x0afffffb, /* beq     <wfi> */
        0xe12fff11, /* bx      r1 */
        GIC_BASE_ADDR      /* privbase: gic address.  */
    };
    for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
        smpboot[n] = tswap32(smpboot[n]);
    }
    rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
}

static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
{
    CPUARMState *env = &cpu->env;

    switch (info->nb_cpus) {
    case 4:
        stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
    case 3:
        stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
    case 2:
        stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
        env->regs[15] = SMP_BOOT_ADDR;
        break;
    default:
        break;
    }
}

#define NUM_REGS      0x200
static void hb_regs_write(void *opaque, hwaddr offset,
                          uint64_t value, unsigned size)
{
    uint32_t *regs = opaque;

    if (offset == 0xf00) {
        if (value == 1 || value == 2) {
            qemu_system_reset_request();
        } else if (value == 3) {
            qemu_system_shutdown_request();
        }
    }

    regs[offset/4] = value;
}

static uint64_t hb_regs_read(void *opaque, hwaddr offset,
                             unsigned size)
{
    uint32_t *regs = opaque;
    uint32_t value = regs[offset/4];

    if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
        value |= 0x30000000;
    }

    return value;
}

static const MemoryRegionOps hb_mem_ops = {
    .read = hb_regs_read,
    .write = hb_regs_write,
    .endianness = DEVICE_NATIVE_ENDIAN,
};

typedef struct {
    SysBusDevice busdev;
    MemoryRegion *iomem;
    uint32_t regs[NUM_REGS];
} HighbankRegsState;

static VMStateDescription vmstate_highbank_regs = {
    .name = "highbank-regs",
    .version_id = 0,
    .minimum_version_id = 0,
    .minimum_version_id_old = 0,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
        VMSTATE_END_OF_LIST(),
    },
};

static void highbank_regs_reset(DeviceState *dev)
{
    SysBusDevice *sys_dev = sysbus_from_qdev(dev);
    HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, sys_dev);

    s->regs[0x40] = 0x05F20121;
    s->regs[0x41] = 0x2;
    s->regs[0x42] = 0x05F30121;
    s->regs[0x43] = 0x05F40121;
}

static int highbank_regs_init(SysBusDevice *dev)
{
    HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, dev);

    s->iomem = g_new(MemoryRegion, 1);
    memory_region_init_io(s->iomem, &hb_mem_ops, s->regs, "highbank_regs",
                          0x1000);
    sysbus_init_mmio(dev, s->iomem);

    return 0;
}

static void highbank_regs_class_init(ObjectClass *klass, void *data)
{
    SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
    DeviceClass *dc = DEVICE_CLASS(klass);

    sbc->init = highbank_regs_init;
    dc->desc = "Calxeda Highbank registers";
    dc->vmsd = &vmstate_highbank_regs;
    dc->reset = highbank_regs_reset;
}

static TypeInfo highbank_regs_info = {
    .name          = "highbank-regs",
    .parent        = TYPE_SYS_BUS_DEVICE,
    .instance_size = sizeof(HighbankRegsState),
    .class_init    = highbank_regs_class_init,
};

static void highbank_regs_register_types(void)
{
    type_register_static(&highbank_regs_info);
}

type_init(highbank_regs_register_types)

static struct arm_boot_info highbank_binfo;

/* ram_size must be set to match the upper bound of memory in the
 * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 * normally 0xff900000 or -m 4089. When running this board on a
 * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 * device tree and pass -m 2047 to QEMU.
 */
static void highbank_init(QEMUMachineInitArgs *args)
{
    ram_addr_t ram_size = args->ram_size;
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    const char *kernel_cmdline = args->kernel_cmdline;
    const char *initrd_filename = args->initrd_filename;
    DeviceState *dev;
    SysBusDevice *busdev;
    qemu_irq *irqp;
    qemu_irq pic[128];
    int n;
    qemu_irq cpu_irq[4];
    MemoryRegion *sysram;
    MemoryRegion *dram;
    MemoryRegion *sysmem;
    char *sysboot_filename;

    if (!cpu_model) {
        cpu_model = "cortex-a9";
    }

    for (n = 0; n < smp_cpus; n++) {
        ARMCPU *cpu;
        cpu = cpu_arm_init(cpu_model);
        if (cpu == NULL) {
            fprintf(stderr, "Unable to find CPU definition\n");
            exit(1);
        }

        /* This will become a QOM property eventually */
        cpu->reset_cbar = GIC_BASE_ADDR;
        irqp = arm_pic_init_cpu(cpu);
        cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
    }

    sysmem = get_system_memory();
    dram = g_new(MemoryRegion, 1);
    memory_region_init_ram(dram, "highbank.dram", ram_size);
    /* SDRAM at address zero.  */
    memory_region_add_subregion(sysmem, 0, dram);

    sysram = g_new(MemoryRegion, 1);
    memory_region_init_ram(sysram, "highbank.sysram", 0x8000);
    memory_region_add_subregion(sysmem, 0xfff88000, sysram);
    if (bios_name != NULL) {
        sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
        if (sysboot_filename != NULL) {
            uint32_t filesize = get_image_size(sysboot_filename);
            if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
                hw_error("Unable to load %s\n", bios_name);
            }
        } else {
           hw_error("Unable to find %s\n", bios_name);
        }
    }

    dev = qdev_create(NULL, "a9mpcore_priv");
    qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
    qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
    qdev_init_nofail(dev);
    busdev = sysbus_from_qdev(dev);
    sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
    for (n = 0; n < smp_cpus; n++) {
        sysbus_connect_irq(busdev, n, cpu_irq[n]);
    }

    for (n = 0; n < 128; n++) {
        pic[n] = qdev_get_gpio_in(dev, n);
    }

    dev = qdev_create(NULL, "l2x0");
    qdev_init_nofail(dev);
    busdev = sysbus_from_qdev(dev);
    sysbus_mmio_map(busdev, 0, 0xfff12000);

    dev = qdev_create(NULL, "sp804");
    qdev_prop_set_uint32(dev, "freq0", 150000000);
    qdev_prop_set_uint32(dev, "freq1", 150000000);
    qdev_init_nofail(dev);
    busdev = sysbus_from_qdev(dev);
    sysbus_mmio_map(busdev, 0, 0xfff34000);
    sysbus_connect_irq(busdev, 0, pic[18]);
    sysbus_create_simple("pl011", 0xfff36000, pic[20]);

    dev = qdev_create(NULL, "highbank-regs");
    qdev_init_nofail(dev);
    busdev = sysbus_from_qdev(dev);
    sysbus_mmio_map(busdev, 0, 0xfff3c000);

    sysbus_create_simple("pl061", 0xfff30000, pic[14]);
    sysbus_create_simple("pl061", 0xfff31000, pic[15]);
    sysbus_create_simple("pl061", 0xfff32000, pic[16]);
    sysbus_create_simple("pl061", 0xfff33000, pic[17]);
    sysbus_create_simple("pl031", 0xfff35000, pic[19]);
    sysbus_create_simple("pl022", 0xfff39000, pic[23]);

    sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);

    if (nd_table[0].used) {
        qemu_check_nic_model(&nd_table[0], "xgmac");
        dev = qdev_create(NULL, "xgmac");
        qdev_set_nic_properties(dev, &nd_table[0]);
        qdev_init_nofail(dev);
        sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff50000);
        sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[77]);
        sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[78]);
        sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[79]);

        qemu_check_nic_model(&nd_table[1], "xgmac");
        dev = qdev_create(NULL, "xgmac");
        qdev_set_nic_properties(dev, &nd_table[1]);
        qdev_init_nofail(dev);
        sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff51000);
        sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[80]);
        sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[81]);
        sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[82]);
    }

    highbank_binfo.ram_size = ram_size;
    highbank_binfo.kernel_filename = kernel_filename;
    highbank_binfo.kernel_cmdline = kernel_cmdline;
    highbank_binfo.initrd_filename = initrd_filename;
    /* highbank requires a dtb in order to boot, and the dtb will override
     * the board ID. The following value is ignored, so set it to -1 to be
     * clear that the value is meaningless.
     */
    highbank_binfo.board_id = -1;
    highbank_binfo.nb_cpus = smp_cpus;
    highbank_binfo.loader_start = 0;
    highbank_binfo.write_secondary_boot = hb_write_secondary;
    highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
    arm_load_kernel(arm_env_get_cpu(first_cpu), &highbank_binfo);
}

static QEMUMachine highbank_machine = {
    .name = "highbank",
    .desc = "Calxeda Highbank (ECX-1000)",
    .init = highbank_init,
    .block_default_type = IF_SCSI,
    .max_cpus = 4,
};

static void highbank_machine_init(void)
{
    qemu_register_machine(&highbank_machine);
}

machine_init(highbank_machine_init);
Commit	Line	Data
2488514c RH	1	/*
	2	* Calxeda Highbank SoC emulation
	3	*
	4	* Copyright (c) 2010-2012 Calxeda
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2 or later, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*
	18	*/
	19
	20	#include "sysbus.h"
	21	#include "arm-misc.h"
2488514c RH	22	#include "devices.h"
2488514c RH	23	#include "loader.h"
1422e32d	24	#include "net/net.h"
9c17d615	25	#include "sysemu/sysemu.h"
2488514c RH	26	#include "boards.h"
2488514c RH	27	#include "sysbus.h"
9c17d615	28	#include "sysemu/blockdev.h"
022c62cb	29	#include "exec/address-spaces.h"
2488514c RH	30
	31	#define SMP_BOOT_ADDR 0x100
	32	#define SMP_BOOT_REG 0x40
	33	#define GIC_BASE_ADDR 0xfff10000
	34
	35	#define NIRQ_GIC 160
	36
	37	/* Board init. */
2488514c	38
9543b0cd	39	static void hb_write_secondary(ARMCPU cpu, const struct arm_boot_info info)
2488514c RH	40	{
	41	int n;
	42	uint32_t smpboot[] = {
	43	0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
	44	0xe210000f, /* ands r0, r0, #0x0f */
	45	0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
	46	0xe0830200, /* add r0, r3, r0, lsl #4 */
bf471f79	47	0xe59f2024, /* ldr r2, privbase */
2488514c	48	0xe3a01001, /* mov r1, #1 */
bf471f79 PM	49	0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
	50	0xe3a010ff, /* mov r1, #0xff */
	51	0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
	52	0xf57ff04f, /* dsb */
2488514c RH	53	0xe320f003, /* wfi */
	54	0xe5901000, /* ldr r1, [r0] */
	55	0xe1110001, /* tst r1, r1 */
	56	0x0afffffb, /* beq <wfi> */
	57	0xe12fff11, /* bx r1 */
	58	GIC_BASE_ADDR /* privbase: gic address. */
	59	};
	60	for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
	61	smpboot[n] = tswap32(smpboot[n]);
	62	}
	63	rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
	64	}
	65
5d309320	66	static void hb_reset_secondary(ARMCPU cpu, const struct arm_boot_info info)
2488514c	67	{
5d309320 AF	68	CPUARMState *env = &cpu->env;
5d309320 AF	69
2488514c RH	70	switch (info->nb_cpus) {
	71	case 4:
	72	stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
	73	case 3:
	74	stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
	75	case 2:
	76	stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
	77	env->regs[15] = SMP_BOOT_ADDR;
	78	break;
	79	default:
	80	break;
	81	}
	82	}
	83
	84	#define NUM_REGS 0x200
a8170e5e	85	static void hb_regs_write(void *opaque, hwaddr offset,
2488514c RH	86	uint64_t value, unsigned size)
	87	{
	88	uint32_t *regs = opaque;
	89
	90	if (offset == 0xf00) {
	91	if (value == 1 \|\| value == 2) {
	92	qemu_system_reset_request();
	93	} else if (value == 3) {
	94	qemu_system_shutdown_request();
	95	}
	96	}
	97
	98	regs[offset/4] = value;
	99	}
	100
a8170e5e	101	static uint64_t hb_regs_read(void *opaque, hwaddr offset,
2488514c RH	102	unsigned size)
	103	{
	104	uint32_t *regs = opaque;
	105	uint32_t value = regs[offset/4];
	106
	107	if ((offset == 0x100) \|\| (offset == 0x108) \|\| (offset == 0x10C)) {
	108	value \|= 0x30000000;
	109	}
	110
	111	return value;
	112	}
	113
	114	static const MemoryRegionOps hb_mem_ops = {
	115	.read = hb_regs_read,
	116	.write = hb_regs_write,
	117	.endianness = DEVICE_NATIVE_ENDIAN,
	118	};
	119
	120	typedef struct {
	121	SysBusDevice busdev;
	122	MemoryRegion *iomem;
	123	uint32_t regs[NUM_REGS];
	124	} HighbankRegsState;
	125
	126	static VMStateDescription vmstate_highbank_regs = {
	127	.name = "highbank-regs",
	128	.version_id = 0,
	129	.minimum_version_id = 0,
	130	.minimum_version_id_old = 0,
	131	.fields = (VMStateField[]) {
	132	VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
	133	VMSTATE_END_OF_LIST(),
	134	},
	135	};
	136
	137	static void highbank_regs_reset(DeviceState *dev)
	138	{
	139	SysBusDevice *sys_dev = sysbus_from_qdev(dev);
	140	HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, sys_dev);
	141
	142	s->regs[0x40] = 0x05F20121;
	143	s->regs[0x41] = 0x2;
	144	s->regs[0x42] = 0x05F30121;
	145	s->regs[0x43] = 0x05F40121;
	146	}
	147
	148	static int highbank_regs_init(SysBusDevice *dev)
	149	{
	150	HighbankRegsState *s = FROM_SYSBUS(HighbankRegsState, dev);
	151
	152	s->iomem = g_new(MemoryRegion, 1);
	153	memory_region_init_io(s->iomem, &hb_mem_ops, s->regs, "highbank_regs",
	154	0x1000);
	155	sysbus_init_mmio(dev, s->iomem);
	156
	157	return 0;
	158	}
	159
999e12bb AL	160	static void highbank_regs_class_init(ObjectClass klass, void data)
	161	{
	162	SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
39bffca2	163	DeviceClass *dc = DEVICE_CLASS(klass);
999e12bb AL	164
999e12bb AL	165	sbc->init = highbank_regs_init;
39bffca2 AL	166	dc->desc = "Calxeda Highbank registers";
	167	dc->vmsd = &vmstate_highbank_regs;
	168	dc->reset = highbank_regs_reset;
999e12bb AL	169	}
999e12bb AL	170
39bffca2 AL	171	static TypeInfo highbank_regs_info = {
	172	.name = "highbank-regs",
	173	.parent = TYPE_SYS_BUS_DEVICE,
	174	.instance_size = sizeof(HighbankRegsState),
	175	.class_init = highbank_regs_class_init,
2488514c RH	176	};
2488514c RH	177
83f7d43a	178	static void highbank_regs_register_types(void)
2488514c	179	{
39bffca2	180	type_register_static(&highbank_regs_info);
2488514c RH	181	}
2488514c RH	182
83f7d43a	183	type_init(highbank_regs_register_types)
2488514c RH	184
	185	static struct arm_boot_info highbank_binfo;
	186
	187	/* ram_size must be set to match the upper bound of memory in the
	188	* device tree (linux/arch/arm/boot/dts/highbank.dts), which is
	189	* normally 0xff900000 or -m 4089. When running this board on a
	190	* 32-bit host, set the reg value of memory to 0xf7ff00000 in the
	191	* device tree and pass -m 2047 to QEMU.
	192	*/
5f072e1f	193	static void highbank_init(QEMUMachineInitArgs *args)
2488514c	194	{
5f072e1f EH	195	ram_addr_t ram_size = args->ram_size;
	196	const char *cpu_model = args->cpu_model;
	197	const char *kernel_filename = args->kernel_filename;
	198	const char *kernel_cmdline = args->kernel_cmdline;
	199	const char *initrd_filename = args->initrd_filename;
2488514c RH	200	DeviceState *dev;
	201	SysBusDevice *busdev;
	202	qemu_irq *irqp;
	203	qemu_irq pic[128];
	204	int n;
	205	qemu_irq cpu_irq[4];
	206	MemoryRegion *sysram;
	207	MemoryRegion *dram;
	208	MemoryRegion *sysmem;
	209	char *sysboot_filename;
	210
	211	if (!cpu_model) {
	212	cpu_model = "cortex-a9";
	213	}
	214
	215	for (n = 0; n < smp_cpus; n++) {
c5fad12f PM	216	ARMCPU *cpu;
	217	cpu = cpu_arm_init(cpu_model);
	218	if (cpu == NULL) {
2488514c RH	219	fprintf(stderr, "Unable to find CPU definition\n");
	220	exit(1);
	221	}
4bd74661	222
c5fad12f PM	223	/* This will become a QOM property eventually */
c5fad12f PM	224	cpu->reset_cbar = GIC_BASE_ADDR;
4bd74661	225	irqp = arm_pic_init_cpu(cpu);
2488514c	226	cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
2488514c RH	227	}
	228
	229	sysmem = get_system_memory();
	230	dram = g_new(MemoryRegion, 1);
	231	memory_region_init_ram(dram, "highbank.dram", ram_size);
	232	/* SDRAM at address zero. */
	233	memory_region_add_subregion(sysmem, 0, dram);
	234
	235	sysram = g_new(MemoryRegion, 1);
	236	memory_region_init_ram(sysram, "highbank.sysram", 0x8000);
	237	memory_region_add_subregion(sysmem, 0xfff88000, sysram);
	238	if (bios_name != NULL) {
	239	sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
	240	if (sysboot_filename != NULL) {
	241	uint32_t filesize = get_image_size(sysboot_filename);
	242	if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
	243	hw_error("Unable to load %s\n", bios_name);
	244	}
	245	} else {
	246	hw_error("Unable to find %s\n", bios_name);
	247	}
	248	}
	249
	250	dev = qdev_create(NULL, "a9mpcore_priv");
	251	qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
	252	qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
	253	qdev_init_nofail(dev);
	254	busdev = sysbus_from_qdev(dev);
	255	sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
	256	for (n = 0; n < smp_cpus; n++) {
	257	sysbus_connect_irq(busdev, n, cpu_irq[n]);
	258	}
	259
	260	for (n = 0; n < 128; n++) {
	261	pic[n] = qdev_get_gpio_in(dev, n);
	262	}
	263
	264	dev = qdev_create(NULL, "l2x0");
	265	qdev_init_nofail(dev);
	266	busdev = sysbus_from_qdev(dev);
	267	sysbus_mmio_map(busdev, 0, 0xfff12000);
	268
	269	dev = qdev_create(NULL, "sp804");
	270	qdev_prop_set_uint32(dev, "freq0", 150000000);
	271	qdev_prop_set_uint32(dev, "freq1", 150000000);
	272	qdev_init_nofail(dev);
	273	busdev = sysbus_from_qdev(dev);
	274	sysbus_mmio_map(busdev, 0, 0xfff34000);
	275	sysbus_connect_irq(busdev, 0, pic[18]);
	276	sysbus_create_simple("pl011", 0xfff36000, pic[20]);
	277
	278	dev = qdev_create(NULL, "highbank-regs");
	279	qdev_init_nofail(dev);
	280	busdev = sysbus_from_qdev(dev);
	281	sysbus_mmio_map(busdev, 0, 0xfff3c000);
	282
	283	sysbus_create_simple("pl061", 0xfff30000, pic[14]);
	284	sysbus_create_simple("pl061", 0xfff31000, pic[15]);
	285	sysbus_create_simple("pl061", 0xfff32000, pic[16]);
	286	sysbus_create_simple("pl061", 0xfff33000, pic[17]);
	287	sysbus_create_simple("pl031", 0xfff35000, pic[19]);
	288	sysbus_create_simple("pl022", 0xfff39000, pic[23]);
	289
	290	sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
291
a005d073	292	if (nd_table[0].used) {
2488514c RH	293	qemu_check_nic_model(&nd_table[0], "xgmac");
	294	dev = qdev_create(NULL, "xgmac");
	295	qdev_set_nic_properties(dev, &nd_table[0]);
	296	qdev_init_nofail(dev);
	297	sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff50000);
	298	sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[77]);
	299	sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[78]);
	300	sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[79]);
	301
	302	qemu_check_nic_model(&nd_table[1], "xgmac");
	303	dev = qdev_create(NULL, "xgmac");
	304	qdev_set_nic_properties(dev, &nd_table[1]);
	305	qdev_init_nofail(dev);
	306	sysbus_mmio_map(sysbus_from_qdev(dev), 0, 0xfff51000);
	307	sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[80]);
	308	sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[81]);
	309	sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[82]);
	310	}
	311
	312	highbank_binfo.ram_size = ram_size;
	313	highbank_binfo.kernel_filename = kernel_filename;
	314	highbank_binfo.kernel_cmdline = kernel_cmdline;
	315	highbank_binfo.initrd_filename = initrd_filename;
	316	/* highbank requires a dtb in order to boot, and the dtb will override
	317	* the board ID. The following value is ignored, so set it to -1 to be
	318	* clear that the value is meaningless.
	319	*/
	320	highbank_binfo.board_id = -1;
	321	highbank_binfo.nb_cpus = smp_cpus;
	322	highbank_binfo.loader_start = 0;
	323	highbank_binfo.write_secondary_boot = hb_write_secondary;
	324	highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
3aaa8dfa	325	arm_load_kernel(arm_env_get_cpu(first_cpu), &highbank_binfo);
2488514c RH	326	}
	327
	328	static QEMUMachine highbank_machine = {
	329	.name = "highbank",
	330	.desc = "Calxeda Highbank (ECX-1000)",
	331	.init = highbank_init,
2d0d2837	332	.block_default_type = IF_SCSI,
2488514c RH	333	.max_cpus = 4,
	334	};
	335
	336	static void highbank_machine_init(void)
	337	{
	338	qemu_register_machine(&highbank_machine);
	339	}
	340
	341	machine_init(highbank_machine_init);