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5391d806 1/*
38cdea7c 2 * QEMU IDE disk and CD/DVD-ROM Emulator
5fafdf24 3 *
5391d806 4 * Copyright (c) 2003 Fabrice Bellard
201a51fc 5 * Copyright (c) 2006 Openedhand Ltd.
5fafdf24 6 *
5391d806
FB		 7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
59f2a787
GH		 25#include <hw/hw.h>
26#include <hw/pc.h>
a2cb15b0 27#include <hw/pci/pci.h>
4a91d3b3 28#include <hw/isa.h>
1de7afc9
PB		 29#include "qemu/error-report.h"
30#include "qemu/timer.h"
87ecb68b 31#include "sysemu.h"
1fb8648d 32#include "dma.h"
9db1c0f7 33#include "hw/block-common.h"
2446333c 34#include "blockdev.h"
59f2a787
GH		 35
36#include <hw/ide/internal.h>
e8b54394 37
b93af93d
BW		 38/* These values were based on a Seagate ST3500418AS but have been modified
39 to make more sense in QEMU */
40static const int smart_attributes[][12] = {
41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
42 /* raw read error rate*/
43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
44 /* spin up */
45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
46 /* start stop count */
47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
48 /* remapped sectors */
49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
50 /* power on hours */
51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* power cycle count */
53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* airflow-temperature-celsius */
55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
e8b54394
BW		 56};
57
ce4b6522 58static int ide_handle_rw_error(IDEState *s, int error, int op);
40c4ed3f 59static void ide_dummy_transfer_stop(IDEState *s);
98087450 60
5391d806
FB		 61static void padstr(char *str, const char *src, int len)
62{
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69b34976 69 str[i^1] = v;
5391d806
FB		 70 }
71}
72
67b915a5
FB		 73static void put_le16(uint16_t *p, unsigned int v)
74{
0c4ad8dc 75 *p = cpu_to_le16(v);
67b915a5
FB		 76}
77
5391d806
FB		 78static void ide_identify(IDEState *s)
79{
80 uint16_t *p;
81 unsigned int oldsize;
d353fb72 82 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
5391d806 83
94458802
FB		 84 if (s->identify_set) {
85 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
86 return;
87 }
88
5391d806
FB		 89 memset(s->io_buffer, 0, 512);
90 p = (uint16_t *)s->io_buffer;
67b915a5 91 put_le16(p + 0, 0x0040);
5fafdf24 92 put_le16(p + 1, s->cylinders);
67b915a5
FB		 93 put_le16(p + 3, s->heads);
94 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
95 put_le16(p + 5, 512); /* XXX: retired, remove ? */
5fafdf24 96 put_le16(p + 6, s->sectors);
fa879c64 97 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 98 put_le16(p + 20, 3); /* XXX: retired, remove ? */
99 put_le16(p + 21, 512); /* cache size in sectors */
100 put_le16(p + 22, 4); /* ecc bytes */
47c06340 101 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 102 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
3b46e624 103#if MAX_MULT_SECTORS > 1
67b915a5 104 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
5391d806 105#endif
67b915a5 106 put_le16(p + 48, 1); /* dword I/O */
94458802 107 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
67b915a5
FB		 108 put_le16(p + 51, 0x200); /* PIO transfer cycle */
109 put_le16(p + 52, 0x200); /* DMA transfer cycle */
94458802 110 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
67b915a5
FB		 111 put_le16(p + 54, s->cylinders);
112 put_le16(p + 55, s->heads);
113 put_le16(p + 56, s->sectors);
5391d806 114 oldsize = s->cylinders * s->heads * s->sectors;
67b915a5
FB		 115 put_le16(p + 57, oldsize);
116 put_le16(p + 58, oldsize >> 16);
5391d806 117 if (s->mult_sectors)
67b915a5
FB		 118 put_le16(p + 59, 0x100 | s->mult_sectors);
119 put_le16(p + 60, s->nb_sectors);
120 put_le16(p + 61, s->nb_sectors >> 16);
d1b5c20d 121 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
94458802 122 put_le16(p + 63, 0x07); /* mdma0-2 supported */
79d1d331 123 put_le16(p + 64, 0x03); /* pio3-4 supported */
94458802
FB		 124 put_le16(p + 65, 120);
125 put_le16(p + 66, 120);
126 put_le16(p + 67, 120);
127 put_le16(p + 68, 120);
d353fb72
CH		 128 if (dev && dev->conf.discard_granularity) {
129 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
130 }
ccf0fd8b
RE		 131
132 if (s->ncq_queues) {
133 put_le16(p + 75, s->ncq_queues - 1);
134 /* NCQ supported */
135 put_le16(p + 76, (1 << 8));
136 }
137
94458802
FB		 138 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
139 put_le16(p + 81, 0x16); /* conforms to ata5 */
a58b8d54
CH		 140 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
141 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
c2ff060f
FB		 142 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
143 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 144 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
145 if (s->wwn) {
146 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
147 } else {
148 put_le16(p + 84, (1 << 14) | 0);
149 }
e900a7b7
CH		 150 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
151 if (bdrv_enable_write_cache(s->bs))
152 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
153 else
154 put_le16(p + 85, (1 << 14) | 1);
c2ff060f 155 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
2844bdd9 156 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
95ebda85
FB		 157 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
158 if (s->wwn) {
159 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
160 } else {
161 put_le16(p + 87, (1 << 14) | 0);
162 }
94458802
FB		 163 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
164 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
c2ff060f
FB		 165 put_le16(p + 100, s->nb_sectors);
166 put_le16(p + 101, s->nb_sectors >> 16);
167 put_le16(p + 102, s->nb_sectors >> 32);
168 put_le16(p + 103, s->nb_sectors >> 48);
d353fb72 169
57dac7ef
MA		 170 if (dev && dev->conf.physical_block_size)
171 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
95ebda85
FB		 172 if (s->wwn) {
173 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
174 put_le16(p + 108, s->wwn >> 48);
175 put_le16(p + 109, s->wwn >> 32);
176 put_le16(p + 110, s->wwn >> 16);
177 put_le16(p + 111, s->wwn);
178 }
d353fb72
CH		 179 if (dev && dev->conf.discard_granularity) {
180 put_le16(p + 169, 1); /* TRIM support */
181 }
94458802
FB		 182
183 memcpy(s->identify_data, p, sizeof(s->identify_data));
184 s->identify_set = 1;
5391d806
FB		 185}
186
187static void ide_atapi_identify(IDEState *s)
188{
189 uint16_t *p;
190
94458802
FB		 191 if (s->identify_set) {
192 memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
193 return;
194 }
195
5391d806
FB		 196 memset(s->io_buffer, 0, 512);
197 p = (uint16_t *)s->io_buffer;
198 /* Removable CDROM, 50us response, 12 byte packets */
67b915a5 199 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
fa879c64 200 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
67b915a5
FB		 201 put_le16(p + 20, 3); /* buffer type */
202 put_le16(p + 21, 512); /* cache size in sectors */
203 put_le16(p + 22, 4); /* ecc bytes */
47c06340 204 padstr((char *)(p + 23), s->version, 8); /* firmware version */
27e0c9a1 205 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
67b915a5 206 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
8ccad811
FB		 207#ifdef USE_DMA_CDROM
208 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
209 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
d1b5c20d 210 put_le16(p + 62, 7); /* single word dma0-2 supported */
8ccad811 211 put_le16(p + 63, 7); /* mdma0-2 supported */
8ccad811 212#else
67b915a5
FB		 213 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
214 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
215 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
8ccad811 216#endif
79d1d331 217 put_le16(p + 64, 3); /* pio3-4 supported */
67b915a5
FB		 218 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
219 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
220 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
221 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
94458802 222
67b915a5
FB		 223 put_le16(p + 71, 30); /* in ns */
224 put_le16(p + 72, 30); /* in ns */
5391d806 225
1bdaa28d
AG		 226 if (s->ncq_queues) {
227 put_le16(p + 75, s->ncq_queues - 1);
228 /* NCQ supported */
229 put_le16(p + 76, (1 << 8));
230 }
231
67b915a5 232 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
8ccad811
FB		 233#ifdef USE_DMA_CDROM
234 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
235#endif
94458802
FB		 236 memcpy(s->identify_data, p, sizeof(s->identify_data));
237 s->identify_set = 1;
5391d806
FB		 238}
239
201a51fc
AZ		 240static void ide_cfata_identify(IDEState *s)
241{
242 uint16_t *p;
243 uint32_t cur_sec;
201a51fc
AZ		 244
245 p = (uint16_t *) s->identify_data;
246 if (s->identify_set)
247 goto fill_buffer;
248
249 memset(p, 0, sizeof(s->identify_data));
250
251 cur_sec = s->cylinders * s->heads * s->sectors;
252
253 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
254 put_le16(p + 1, s->cylinders); /* Default cylinders */
255 put_le16(p + 3, s->heads); /* Default heads */
256 put_le16(p + 6, s->sectors); /* Default sectors per track */
257 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
258 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
fa879c64 259 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
201a51fc 260 put_le16(p + 22, 0x0004); /* ECC bytes */
47c06340 261 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
27e0c9a1 262 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
201a51fc
AZ		 263#if MAX_MULT_SECTORS > 1
264 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
265#else
266 put_le16(p + 47, 0x0000);
267#endif
268 put_le16(p + 49, 0x0f00); /* Capabilities */
269 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
270 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
271 put_le16(p + 53, 0x0003); /* Translation params valid */
272 put_le16(p + 54, s->cylinders); /* Current cylinders */
273 put_le16(p + 55, s->heads); /* Current heads */
274 put_le16(p + 56, s->sectors); /* Current sectors */
275 put_le16(p + 57, cur_sec); /* Current capacity */
276 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
277 if (s->mult_sectors) /* Multiple sector setting */
278 put_le16(p + 59, 0x100 | s->mult_sectors);
279 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
280 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
281 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
282 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
283 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
284 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
285 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
286 put_le16(p + 82, 0x400c); /* Command Set supported */
287 put_le16(p + 83, 0x7068); /* Command Set supported */
288 put_le16(p + 84, 0x4000); /* Features supported */
289 put_le16(p + 85, 0x000c); /* Command Set enabled */
290 put_le16(p + 86, 0x7044); /* Command Set enabled */
291 put_le16(p + 87, 0x4000); /* Features enabled */
292 put_le16(p + 91, 0x4060); /* Current APM level */
293 put_le16(p + 129, 0x0002); /* Current features option */
294 put_le16(p + 130, 0x0005); /* Reassigned sectors */
295 put_le16(p + 131, 0x0001); /* Initial power mode */
296 put_le16(p + 132, 0x0000); /* User signature */
297 put_le16(p + 160, 0x8100); /* Power requirement */
298 put_le16(p + 161, 0x8001); /* CF command set */
299
300 s->identify_set = 1;
301
302fill_buffer:
303 memcpy(s->io_buffer, p, sizeof(s->identify_data));
304}
305
5391d806
FB		 306static void ide_set_signature(IDEState *s)
307{
308 s->select &= 0xf0; /* clear head */
309 /* put signature */
310 s->nsector = 1;
311 s->sector = 1;
cd8722bb 312 if (s->drive_kind == IDE_CD) {
5391d806
FB		 313 s->lcyl = 0x14;
314 s->hcyl = 0xeb;
315 } else if (s->bs) {
316 s->lcyl = 0;
317 s->hcyl = 0;
318 } else {
319 s->lcyl = 0xff;
320 s->hcyl = 0xff;
321 }
322}
323
d353fb72
CH		 324typedef struct TrimAIOCB {
325 BlockDriverAIOCB common;
326 QEMUBH *bh;
327 int ret;
328} TrimAIOCB;
329
330static void trim_aio_cancel(BlockDriverAIOCB *acb)
331{
332 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
333
334 qemu_bh_delete(iocb->bh);
335 iocb->bh = NULL;
336 qemu_aio_release(iocb);
337}
338
d7331bed 339static const AIOCBInfo trim_aiocb_info = {
d353fb72
CH		 340 .aiocb_size = sizeof(TrimAIOCB),
341 .cancel = trim_aio_cancel,
342};
343
344static void ide_trim_bh_cb(void *opaque)
345{
346 TrimAIOCB *iocb = opaque;
347
348 iocb->common.cb(iocb->common.opaque, iocb->ret);
349
350 qemu_bh_delete(iocb->bh);
351 iocb->bh = NULL;
352
353 qemu_aio_release(iocb);
354}
355
356BlockDriverAIOCB *ide_issue_trim(BlockDriverState *bs,
357 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
358 BlockDriverCompletionFunc *cb, void *opaque)
359{
360 TrimAIOCB *iocb;
361 int i, j, ret;
362
d7331bed 363 iocb = qemu_aio_get(&trim_aiocb_info, bs, cb, opaque);
d353fb72
CH		 364 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
365 iocb->ret = 0;
366
367 for (j = 0; j < qiov->niov; j++) {
368 uint64_t *buffer = qiov->iov[j].iov_base;
369
370 for (i = 0; i < qiov->iov[j].iov_len / 8; i++) {
371 /* 6-byte LBA + 2-byte range per entry */
372 uint64_t entry = le64_to_cpu(buffer[i]);
373 uint64_t sector = entry & 0x0000ffffffffffffULL;
374 uint16_t count = entry >> 48;
375
376 if (count == 0) {
377 break;
378 }
379
380 ret = bdrv_discard(bs, sector, count);
381 if (!iocb->ret) {
382 iocb->ret = ret;
383 }
384 }
385 }
386
387 qemu_bh_schedule(iocb->bh);
388
389 return &iocb->common;
390}
391
5391d806
FB		 392static inline void ide_abort_command(IDEState *s)
393{
394 s->status = READY_STAT | ERR_STAT;
395 s->error = ABRT_ERR;
396}
397
5391d806 398/* prepare data transfer and tell what to do after */
33231e0e
KW		 399void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
400 EndTransferFunc *end_transfer_func)
5391d806
FB		 401{
402 s->end_transfer_func = end_transfer_func;
403 s->data_ptr = buf;
404 s->data_end = buf + size;
40a6238a 405 if (!(s->status & ERR_STAT)) {
7603d156 406 s->status |= DRQ_STAT;
40a6238a
AG		 407 }
408 s->bus->dma->ops->start_transfer(s->bus->dma);
5391d806
FB		 409}
410
33231e0e 411void ide_transfer_stop(IDEState *s)
5391d806
FB		 412{
413 s->end_transfer_func = ide_transfer_stop;
414 s->data_ptr = s->io_buffer;
415 s->data_end = s->io_buffer;
416 s->status &= ~DRQ_STAT;
417}
418
356721ae 419int64_t ide_get_sector(IDEState *s)
5391d806
FB		 420{
421 int64_t sector_num;
422 if (s->select & 0x40) {
423 /* lba */
c2ff060f
FB		 424 if (!s->lba48) {
425 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
426 (s->lcyl << 8) | s->sector;
427 } else {
428 sector_num = ((int64_t)s->hob_hcyl << 40) |
429 ((int64_t) s->hob_lcyl << 32) |
430 ((int64_t) s->hob_sector << 24) |
431 ((int64_t) s->hcyl << 16) |
432 ((int64_t) s->lcyl << 8) | s->sector;
433 }
5391d806
FB		 434 } else {
435 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
c2ff060f 436 (s->select & 0x0f) * s->sectors + (s->sector - 1);
5391d806
FB		 437 }
438 return sector_num;
439}
440
356721ae 441void ide_set_sector(IDEState *s, int64_t sector_num)
5391d806
FB		 442{
443 unsigned int cyl, r;
444 if (s->select & 0x40) {
c2ff060f
FB		 445 if (!s->lba48) {
446 s->select = (s->select & 0xf0) | (sector_num >> 24);
447 s->hcyl = (sector_num >> 16);
448 s->lcyl = (sector_num >> 8);
449 s->sector = (sector_num);
450 } else {
451 s->sector = sector_num;
452 s->lcyl = sector_num >> 8;
453 s->hcyl = sector_num >> 16;
454 s->hob_sector = sector_num >> 24;
455 s->hob_lcyl = sector_num >> 32;
456 s->hob_hcyl = sector_num >> 40;
457 }
5391d806
FB		 458 } else {
459 cyl = sector_num / (s->heads * s->sectors);
460 r = sector_num % (s->heads * s->sectors);
461 s->hcyl = cyl >> 8;
462 s->lcyl = cyl;
1b8eb456 463 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
5391d806
FB		 464 s->sector = (r % s->sectors) + 1;
465 }
466}
467
e162cfb0
AZ		 468static void ide_rw_error(IDEState *s) {
469 ide_abort_command(s);
9cdd03a7 470 ide_set_irq(s->bus);
e162cfb0
AZ		 471}
472
bef0fd59
SH		 473static void ide_sector_read_cb(void *opaque, int ret)
474{
475 IDEState *s = opaque;
476 int n;
477
478 s->pio_aiocb = NULL;
479 s->status &= ~BUSY_STAT;
480
481 bdrv_acct_done(s->bs, &s->acct);
482 if (ret != 0) {
483 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY |
484 BM_STATUS_RETRY_READ)) {
485 return;
486 }
487 }
488
489 n = s->nsector;
490 if (n > s->req_nb_sectors) {
491 n = s->req_nb_sectors;
492 }
493
494 /* Allow the guest to read the io_buffer */
495 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
496
497 ide_set_irq(s->bus);
498
499 ide_set_sector(s, ide_get_sector(s) + n);
500 s->nsector -= n;
501}
502
40a6238a 503void ide_sector_read(IDEState *s)
5391d806
FB		 504{
505 int64_t sector_num;
bef0fd59 506 int n;
5391d806
FB		 507
508 s->status = READY_STAT | SEEK_STAT;
a136e5a8 509 s->error = 0; /* not needed by IDE spec, but needed by Windows */
5391d806
FB		 510 sector_num = ide_get_sector(s);
511 n = s->nsector;
bef0fd59 512
5391d806 513 if (n == 0) {
5391d806 514 ide_transfer_stop(s);
bef0fd59
SH		 515 return;
516 }
517
518 s->status |= BUSY_STAT;
519
520 if (n > s->req_nb_sectors) {
521 n = s->req_nb_sectors;
522 }
523
5391d806 524#if defined(DEBUG_IDE)
bef0fd59 525 printf("sector=%" PRId64 "\n", sector_num);
5391d806 526#endif
a597e79c 527
bef0fd59
SH		 528 s->iov.iov_base = s->io_buffer;
529 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
530 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
531
532 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
533 s->pio_aiocb = bdrv_aio_readv(s->bs, sector_num, &s->qiov, n,
534 ide_sector_read_cb, s);
5391d806
FB		 535}
536
b61744b3 537static void dma_buf_commit(IDEState *s)
7aea4412 538{
1fb8648d 539 qemu_sglist_destroy(&s->sg);
7aea4412
AL		 540}
541
33231e0e 542void ide_set_inactive(IDEState *s)
8337606d 543{
40a6238a
AG		 544 s->bus->dma->aiocb = NULL;
545 s->bus->dma->ops->set_inactive(s->bus->dma);
8337606d
KW		 546}
547
356721ae 548void ide_dma_error(IDEState *s)
e162cfb0
AZ		 549{
550 ide_transfer_stop(s);
551 s->error = ABRT_ERR;
552 s->status = READY_STAT | ERR_STAT;
40a6238a 553 ide_set_inactive(s);
9cdd03a7 554 ide_set_irq(s->bus);
e162cfb0
AZ		 555}
556
ce4b6522 557static int ide_handle_rw_error(IDEState *s, int error, int op)
428c5705 558{
1ceee0d5 559 bool is_read = (op & BM_STATUS_RETRY_READ) != 0;
3e1caa5f 560 BlockErrorAction action = bdrv_get_error_action(s->bs, is_read, error);
428c5705 561
3e1caa5f 562 if (action == BDRV_ACTION_STOP) {
40a6238a 563 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
def93791 564 s->bus->error_status = op;
3e1caa5f 565 } else if (action == BDRV_ACTION_REPORT) {
ce4b6522 566 if (op & BM_STATUS_DMA_RETRY) {
b61744b3 567 dma_buf_commit(s);
428c5705 568 ide_dma_error(s);
7aea4412 569 } else {
428c5705 570 ide_rw_error(s);
7aea4412 571 }
428c5705 572 }
3e1caa5f
PB		 573 bdrv_error_action(s->bs, action, is_read, error);
574 return action != BDRV_ACTION_IGNORE;
428c5705
AL		 575}
576
cd369c46 577void ide_dma_cb(void *opaque, int ret)
98087450 578{
40a6238a 579 IDEState *s = opaque;
8ccad811
FB		 580 int n;
581 int64_t sector_num;
038268e2 582 bool stay_active = false;
8ccad811 583
e162cfb0 584 if (ret < 0) {
cd369c46
CH		 585 int op = BM_STATUS_DMA_RETRY;
586
4e1e0051 587 if (s->dma_cmd == IDE_DMA_READ)
cd369c46 588 op |= BM_STATUS_RETRY_READ;
d353fb72
CH		 589 else if (s->dma_cmd == IDE_DMA_TRIM)
590 op |= BM_STATUS_RETRY_TRIM;
591
cd369c46 592 if (ide_handle_rw_error(s, -ret, op)) {
ce4b6522
KW		 593 return;
594 }
e162cfb0
AZ		 595 }
596
8ccad811 597 n = s->io_buffer_size >> 9;
038268e2
KW		 598 if (n > s->nsector) {
599 /* The PRDs were longer than needed for this request. Shorten them so
600 * we don't get a negative remainder. The Active bit must remain set
601 * after the request completes. */
602 n = s->nsector;
603 stay_active = true;
604 }
605
8ccad811
FB		 606 sector_num = ide_get_sector(s);
607 if (n > 0) {
b61744b3 608 dma_buf_commit(s);
8ccad811
FB		 609 sector_num += n;
610 ide_set_sector(s, sector_num);
611 s->nsector -= n;
8ccad811
FB		 612 }
613
614 /* end of transfer ? */
615 if (s->nsector == 0) {
98087450 616 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 617 ide_set_irq(s->bus);
cd369c46 618 goto eot;
98087450 619 }
8ccad811
FB		 620
621 /* launch next transfer */
622 n = s->nsector;
596bb44d 623 s->io_buffer_index = 0;
8ccad811 624 s->io_buffer_size = n * 512;
4e1e0051 625 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
69c38b8f
KW		 626 /* The PRDs were too short. Reset the Active bit, but don't raise an
627 * interrupt. */
72bcca73 628 s->status = READY_STAT | SEEK_STAT;
7aea4412 629 goto eot;
69c38b8f 630 }
cd369c46 631
8ccad811 632#ifdef DEBUG_AIO
4e1e0051
CH		 633 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
634 sector_num, n, s->dma_cmd);
8ccad811 635#endif
cd369c46 636
4e1e0051
CH		 637 switch (s->dma_cmd) {
638 case IDE_DMA_READ:
cd369c46
CH		 639 s->bus->dma->aiocb = dma_bdrv_read(s->bs, &s->sg, sector_num,
640 ide_dma_cb, s);
4e1e0051
CH		 641 break;
642 case IDE_DMA_WRITE:
cd369c46
CH		 643 s->bus->dma->aiocb = dma_bdrv_write(s->bs, &s->sg, sector_num,
644 ide_dma_cb, s);
4e1e0051 645 break;
d353fb72
CH		 646 case IDE_DMA_TRIM:
647 s->bus->dma->aiocb = dma_bdrv_io(s->bs, &s->sg, sector_num,
43cf8ae6
DG		 648 ide_issue_trim, ide_dma_cb, s,
649 DMA_DIRECTION_TO_DEVICE);
d353fb72 650 break;
cd369c46 651 }
cd369c46
CH		 652 return;
653
654eot:
a597e79c
CH		 655 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
656 bdrv_acct_done(s->bs, &s->acct);
657 }
658 ide_set_inactive(s);
038268e2
KW		 659 if (stay_active) {
660 s->bus->dma->ops->add_status(s->bus->dma, BM_STATUS_DMAING);
661 }
98087450
FB		 662}
663
4e1e0051 664static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
98087450 665{
8ccad811 666 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
98087450
FB		 667 s->io_buffer_index = 0;
668 s->io_buffer_size = 0;
4e1e0051 669 s->dma_cmd = dma_cmd;
a597e79c
CH		 670
671 switch (dma_cmd) {
672 case IDE_DMA_READ:
673 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
674 BDRV_ACCT_READ);
675 break;
676 case IDE_DMA_WRITE:
677 bdrv_acct_start(s->bs, &s->acct, s->nsector * BDRV_SECTOR_SIZE,
678 BDRV_ACCT_WRITE);
679 break;
680 default:
681 break;
682 }
683
cd369c46 684 s->bus->dma->ops->start_dma(s->bus->dma, s, ide_dma_cb);
98087450
FB		 685}
686
a09db21f
FB		 687static void ide_sector_write_timer_cb(void *opaque)
688{
689 IDEState *s = opaque;
9cdd03a7 690 ide_set_irq(s->bus);
a09db21f
FB		 691}
692
e82dabd8 693static void ide_sector_write_cb(void *opaque, int ret)
5391d806 694{
e82dabd8
SH		 695 IDEState *s = opaque;
696 int n;
a597e79c 697
a597e79c 698 bdrv_acct_done(s->bs, &s->acct);
428c5705 699
e82dabd8
SH		 700 s->pio_aiocb = NULL;
701 s->status &= ~BUSY_STAT;
702
e162cfb0 703 if (ret != 0) {
e82dabd8 704 if (ide_handle_rw_error(s, -ret, BM_STATUS_PIO_RETRY)) {
428c5705 705 return;
e82dabd8 706 }
e162cfb0
AZ		 707 }
708
e82dabd8
SH		 709 n = s->nsector;
710 if (n > s->req_nb_sectors) {
711 n = s->req_nb_sectors;
712 }
5391d806
FB		 713 s->nsector -= n;
714 if (s->nsector == 0) {
292eef5a 715 /* no more sectors to write */
5391d806
FB		 716 ide_transfer_stop(s);
717 } else {
e82dabd8
SH		 718 int n1 = s->nsector;
719 if (n1 > s->req_nb_sectors) {
5391d806 720 n1 = s->req_nb_sectors;
e82dabd8
SH		 721 }
722 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
723 ide_sector_write);
5391d806 724 }
e82dabd8 725 ide_set_sector(s, ide_get_sector(s) + n);
3b46e624 726
31c2a146
TS		 727 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
728 /* It seems there is a bug in the Windows 2000 installer HDD
729 IDE driver which fills the disk with empty logs when the
730 IDE write IRQ comes too early. This hack tries to correct
731 that at the expense of slower write performances. Use this
732 option _only_ to install Windows 2000. You must disable it
733 for normal use. */
f7736b91 734 qemu_mod_timer(s->sector_write_timer,
74475455 735 qemu_get_clock_ns(vm_clock) + (get_ticks_per_sec() / 1000));
f7736b91 736 } else {
9cdd03a7 737 ide_set_irq(s->bus);
31c2a146 738 }
5391d806
FB		 739}
740
e82dabd8
SH		 741void ide_sector_write(IDEState *s)
742{
743 int64_t sector_num;
744 int n;
745
746 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
747 sector_num = ide_get_sector(s);
748#if defined(DEBUG_IDE)
749 printf("sector=%" PRId64 "\n", sector_num);
750#endif
751 n = s->nsector;
752 if (n > s->req_nb_sectors) {
753 n = s->req_nb_sectors;
754 }
755
756 s->iov.iov_base = s->io_buffer;
757 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
758 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
759
760 bdrv_acct_start(s->bs, &s->acct, n * BDRV_SECTOR_SIZE, BDRV_ACCT_READ);
761 s->pio_aiocb = bdrv_aio_writev(s->bs, sector_num, &s->qiov, n,
762 ide_sector_write_cb, s);
763}
764
b0484ae4
CH		 765static void ide_flush_cb(void *opaque, int ret)
766{
767 IDEState *s = opaque;
768
e2bcadad
KW		 769 if (ret < 0) {
770 /* XXX: What sector number to set here? */
771 if (ide_handle_rw_error(s, -ret, BM_STATUS_RETRY_FLUSH)) {
772 return;
773 }
774 }
b0484ae4 775
a597e79c 776 bdrv_acct_done(s->bs, &s->acct);
b0484ae4
CH		 777 s->status = READY_STAT | SEEK_STAT;
778 ide_set_irq(s->bus);
779}
780
40a6238a 781void ide_flush_cache(IDEState *s)
6bcb1a79 782{
b2df7531 783 if (s->bs == NULL) {
6bcb1a79 784 ide_flush_cb(s, 0);
b2df7531
KW		 785 return;
786 }
787
a597e79c 788 bdrv_acct_start(s->bs, &s->acct, 0, BDRV_ACCT_FLUSH);
ad54ae80 789 bdrv_aio_flush(s->bs, ide_flush_cb, s);
6bcb1a79
KW		 790}
791
201a51fc
AZ		 792static void ide_cfata_metadata_inquiry(IDEState *s)
793{
794 uint16_t *p;
795 uint32_t spd;
796
797 p = (uint16_t *) s->io_buffer;
798 memset(p, 0, 0x200);
799 spd = ((s->mdata_size - 1) >> 9) + 1;
800
801 put_le16(p + 0, 0x0001); /* Data format revision */
802 put_le16(p + 1, 0x0000); /* Media property: silicon */
803 put_le16(p + 2, s->media_changed); /* Media status */
804 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
805 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
806 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
807 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
808}
809
810static void ide_cfata_metadata_read(IDEState *s)
811{
812 uint16_t *p;
813
814 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
815 s->status = ERR_STAT;
816 s->error = ABRT_ERR;
817 return;
818 }
819
820 p = (uint16_t *) s->io_buffer;
821 memset(p, 0, 0x200);
822
823 put_le16(p + 0, s->media_changed); /* Media status */
824 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
825 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
826 s->nsector << 9), 0x200 - 2));
827}
828
829static void ide_cfata_metadata_write(IDEState *s)
830{
831 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
832 s->status = ERR_STAT;
833 s->error = ABRT_ERR;
834 return;
835 }
836
837 s->media_changed = 0;
838
839 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
840 s->io_buffer + 2,
841 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
842 s->nsector << 9), 0x200 - 2));
843}
844
bd491d6a 845/* called when the inserted state of the media has changed */
7d4b4ba5 846static void ide_cd_change_cb(void *opaque, bool load)
bd491d6a
TS		 847{
848 IDEState *s = opaque;
96b8f136 849 uint64_t nb_sectors;
bd491d6a 850
25ad22bc 851 s->tray_open = !load;
bd491d6a
TS		 852 bdrv_get_geometry(s->bs, &nb_sectors);
853 s->nb_sectors = nb_sectors;
9118e7f0 854
4b9b7092
AS		 855 /*
856 * First indicate to the guest that a CD has been removed. That's
857 * done on the next command the guest sends us.
858 *
67cc61e4 859 * Then we set UNIT_ATTENTION, by which the guest will
4b9b7092
AS		 860 * detect a new CD in the drive. See ide_atapi_cmd() for details.
861 */
93c8cfd9 862 s->cdrom_changed = 1;
996faf1a 863 s->events.new_media = true;
2df0a3a3
PB		 864 s->events.eject_request = false;
865 ide_set_irq(s->bus);
866}
867
868static void ide_cd_eject_request_cb(void *opaque, bool force)
869{
870 IDEState *s = opaque;
871
872 s->events.eject_request = true;
873 if (force) {
874 s->tray_locked = false;
875 }
9cdd03a7 876 ide_set_irq(s->bus);
bd491d6a
TS		 877}
878
c2ff060f
FB		 879static void ide_cmd_lba48_transform(IDEState *s, int lba48)
880{
881 s->lba48 = lba48;
882
883 /* handle the 'magic' 0 nsector count conversion here. to avoid
884 * fiddling with the rest of the read logic, we just store the
885 * full sector count in ->nsector and ignore ->hob_nsector from now
886 */
887 if (!s->lba48) {
888 if (!s->nsector)
889 s->nsector = 256;
890 } else {
891 if (!s->nsector && !s->hob_nsector)
892 s->nsector = 65536;
893 else {
894 int lo = s->nsector;
895 int hi = s->hob_nsector;
896
897 s->nsector = (hi << 8) | lo;
898 }
899 }
900}
901
bcbdc4d3 902static void ide_clear_hob(IDEBus *bus)
c2ff060f
FB		 903{
904 /* any write clears HOB high bit of device control register */
bcbdc4d3
GH		 905 bus->ifs[0].select &= ~(1 << 7);
906 bus->ifs[1].select &= ~(1 << 7);
c2ff060f
FB		 907}
908
356721ae 909void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
caed8802 910{
bcbdc4d3 911 IDEBus *bus = opaque;
5391d806
FB		 912
913#ifdef DEBUG_IDE
914 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
915#endif
c2ff060f 916
5391d806 917 addr &= 7;
fcdd25ab
AL		 918
919 /* ignore writes to command block while busy with previous command */
bcbdc4d3 920 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
fcdd25ab
AL		 921 return;
922
5391d806
FB		 923 switch(addr) {
924 case 0:
925 break;
926 case 1:
bcbdc4d3 927 ide_clear_hob(bus);
c45c3d00 928 /* NOTE: data is written to the two drives */
bcbdc4d3
GH		 929 bus->ifs[0].hob_feature = bus->ifs[0].feature;
930 bus->ifs[1].hob_feature = bus->ifs[1].feature;
931 bus->ifs[0].feature = val;
932 bus->ifs[1].feature = val;
5391d806
FB		 933 break;
934 case 2:
bcbdc4d3
GH		 935 ide_clear_hob(bus);
936 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
937 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
938 bus->ifs[0].nsector = val;
939 bus->ifs[1].nsector = val;
5391d806
FB		 940 break;
941 case 3:
bcbdc4d3
GH		 942 ide_clear_hob(bus);
943 bus->ifs[0].hob_sector = bus->ifs[0].sector;
944 bus->ifs[1].hob_sector = bus->ifs[1].sector;
945 bus->ifs[0].sector = val;
946 bus->ifs[1].sector = val;
5391d806
FB		 947 break;
948 case 4:
bcbdc4d3
GH		 949 ide_clear_hob(bus);
950 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
951 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
952 bus->ifs[0].lcyl = val;
953 bus->ifs[1].lcyl = val;
5391d806
FB		 954 break;
955 case 5:
bcbdc4d3
GH		 956 ide_clear_hob(bus);
957 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
958 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
959 bus->ifs[0].hcyl = val;
960 bus->ifs[1].hcyl = val;
5391d806
FB		 961 break;
962 case 6:
c2ff060f 963 /* FIXME: HOB readback uses bit 7 */
bcbdc4d3
GH		 964 bus->ifs[0].select = (val & ~0x10) | 0xa0;
965 bus->ifs[1].select = (val | 0x10) | 0xa0;
5391d806 966 /* select drive */
bcbdc4d3 967 bus->unit = (val >> 4) & 1;
5391d806
FB		 968 break;
969 default:
970 case 7:
971 /* command */
7cff87ff
AG		 972 ide_exec_cmd(bus, val);
973 break;
974 }
975}
976
844505b1
MA		 977#define HD_OK (1u << IDE_HD)
978#define CD_OK (1u << IDE_CD)
979#define CFA_OK (1u << IDE_CFATA)
980#define HD_CFA_OK (HD_OK | CFA_OK)
981#define ALL_OK (HD_OK | CD_OK | CFA_OK)
982
983/* See ACS-2 T13/2015-D Table B.2 Command codes */
984static const uint8_t ide_cmd_table[0x100] = {
985 /* NOP not implemented, mandatory for CD */
986 [CFA_REQ_EXT_ERROR_CODE] = CFA_OK,
987 [WIN_DSM] = ALL_OK,
988 [WIN_DEVICE_RESET] = CD_OK,
3cfc2269 989 [WIN_RECAL] = HD_CFA_OK,
844505b1
MA		 990 [WIN_READ] = ALL_OK,
991 [WIN_READ_ONCE] = ALL_OK,
3cfc2269
MA		 992 [WIN_READ_EXT] = HD_CFA_OK,
993 [WIN_READDMA_EXT] = HD_CFA_OK,
994 [WIN_READ_NATIVE_MAX_EXT] = HD_CFA_OK,
995 [WIN_MULTREAD_EXT] = HD_CFA_OK,
996 [WIN_WRITE] = HD_CFA_OK,
997 [WIN_WRITE_ONCE] = HD_CFA_OK,
998 [WIN_WRITE_EXT] = HD_CFA_OK,
999 [WIN_WRITEDMA_EXT] = HD_CFA_OK,
1000 [CFA_WRITE_SECT_WO_ERASE] = CFA_OK,
1001 [WIN_MULTWRITE_EXT] = HD_CFA_OK,
1002 [WIN_WRITE_VERIFY] = HD_CFA_OK,
1003 [WIN_VERIFY] = HD_CFA_OK,
1004 [WIN_VERIFY_ONCE] = HD_CFA_OK,
1005 [WIN_VERIFY_EXT] = HD_CFA_OK,
844505b1
MA		 1006 [WIN_SEEK] = HD_CFA_OK,
1007 [CFA_TRANSLATE_SECTOR] = CFA_OK,
1008 [WIN_DIAGNOSE] = ALL_OK,
3cfc2269 1009 [WIN_SPECIFY] = HD_CFA_OK,
844505b1
MA		 1010 [WIN_STANDBYNOW2] = ALL_OK,
1011 [WIN_IDLEIMMEDIATE2] = ALL_OK,
1012 [WIN_STANDBY2] = ALL_OK,
1013 [WIN_SETIDLE2] = ALL_OK,
1014 [WIN_CHECKPOWERMODE2] = ALL_OK,
1015 [WIN_SLEEPNOW2] = ALL_OK,
1016 [WIN_PACKETCMD] = CD_OK,
1017 [WIN_PIDENTIFY] = CD_OK,
1018 [WIN_SMART] = HD_CFA_OK,
1019 [CFA_ACCESS_METADATA_STORAGE] = CFA_OK,
1020 [CFA_ERASE_SECTORS] = CFA_OK,
3cfc2269
MA		 1021 [WIN_MULTREAD] = HD_CFA_OK,
1022 [WIN_MULTWRITE] = HD_CFA_OK,
1023 [WIN_SETMULT] = HD_CFA_OK,
1024 [WIN_READDMA] = HD_CFA_OK,
1025 [WIN_READDMA_ONCE] = HD_CFA_OK,
1026 [WIN_WRITEDMA] = HD_CFA_OK,
1027 [WIN_WRITEDMA_ONCE] = HD_CFA_OK,
1028 [CFA_WRITE_MULTI_WO_ERASE] = CFA_OK,
844505b1
MA		 1029 [WIN_STANDBYNOW1] = ALL_OK,
1030 [WIN_IDLEIMMEDIATE] = ALL_OK,
1031 [WIN_STANDBY] = ALL_OK,
1032 [WIN_SETIDLE1] = ALL_OK,
1033 [WIN_CHECKPOWERMODE1] = ALL_OK,
1034 [WIN_SLEEPNOW1] = ALL_OK,
1035 [WIN_FLUSH_CACHE] = ALL_OK,
3cfc2269 1036 [WIN_FLUSH_CACHE_EXT] = HD_CFA_OK,
844505b1
MA		 1037 [WIN_IDENTIFY] = ALL_OK,
1038 [WIN_SETFEATURES] = ALL_OK,
1039 [IBM_SENSE_CONDITION] = CFA_OK,
d5b406d9 1040 [CFA_WEAR_LEVEL] = HD_CFA_OK,
844505b1
MA		 1041 [WIN_READ_NATIVE_MAX] = ALL_OK,
1042};
1043
1044static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1045{
1046 return cmd < ARRAY_SIZE(ide_cmd_table)
1047 && (ide_cmd_table[cmd] & (1u << s->drive_kind));
1048}
7cff87ff
AG		 1049
1050void ide_exec_cmd(IDEBus *bus, uint32_t val)
1051{
7cdd481c 1052 uint16_t *identify_data;
7cff87ff
AG		 1053 IDEState *s;
1054 int n;
1055 int lba48 = 0;
1056
5391d806 1057#if defined(DEBUG_IDE)
6ef2ba5e 1058 printf("ide: CMD=%02x\n", val);
5391d806 1059#endif
6ef2ba5e 1060 s = idebus_active_if(bus);
66a0a2cb 1061 /* ignore commands to non existent slave */
6ef2ba5e
AG		 1062 if (s != bus->ifs && !s->bs)
1063 return;
c2ff060f 1064
6ef2ba5e
AG		 1065 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1066 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1067 return;
fcdd25ab 1068
844505b1
MA		 1069 if (!ide_cmd_permitted(s, val)) {
1070 goto abort_cmd;
1071 }
1072
6ef2ba5e 1073 switch(val) {
d353fb72
CH		 1074 case WIN_DSM:
1075 switch (s->feature) {
1076 case DSM_TRIM:
1077 if (!s->bs) {
1078 goto abort_cmd;
1079 }
1080 ide_sector_start_dma(s, IDE_DMA_TRIM);
1081 break;
1082 default:
1083 goto abort_cmd;
1084 }
1085 break;
6ef2ba5e
AG		 1086 case WIN_IDENTIFY:
1087 if (s->bs && s->drive_kind != IDE_CD) {
1088 if (s->drive_kind != IDE_CFATA)
1089 ide_identify(s);
1090 else
1091 ide_cfata_identify(s);
769bec72 1092 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1093 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1094 } else {
1095 if (s->drive_kind == IDE_CD) {
1096 ide_set_signature(s);
5391d806 1097 }
6ef2ba5e
AG		 1098 ide_abort_command(s);
1099 }
1100 ide_set_irq(s->bus);
1101 break;
1102 case WIN_SPECIFY:
1103 case WIN_RECAL:
1104 s->error = 0;
1105 s->status = READY_STAT | SEEK_STAT;
1106 ide_set_irq(s->bus);
1107 break;
1108 case WIN_SETMULT:
1109 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1110 /* Disable Read and Write Multiple */
1111 s->mult_sectors = 0;
41a2b959 1112 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1113 } else if ((s->nsector & 0xff) != 0 &&
1114 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1115 (s->nsector & (s->nsector - 1)) != 0)) {
1116 ide_abort_command(s);
1117 } else {
1118 s->mult_sectors = s->nsector & 0xff;
1119 s->status = READY_STAT | SEEK_STAT;
1120 }
1121 ide_set_irq(s->bus);
1122 break;
1123 case WIN_VERIFY_EXT:
1124 lba48 = 1;
1125 case WIN_VERIFY:
1126 case WIN_VERIFY_ONCE:
1127 /* do sector number check ? */
1128 ide_cmd_lba48_transform(s, lba48);
1129 s->status = READY_STAT | SEEK_STAT;
1130 ide_set_irq(s->bus);
1131 break;
814839c0 1132 case WIN_READ_EXT:
6ef2ba5e
AG		 1133 lba48 = 1;
1134 case WIN_READ:
1135 case WIN_READ_ONCE:
3f76a7c3
MA		 1136 if (s->drive_kind == IDE_CD) {
1137 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
6ef2ba5e 1138 goto abort_cmd;
3f76a7c3 1139 }
d53cdb30
PB		 1140 if (!s->bs) {
1141 goto abort_cmd;
1142 }
6ef2ba5e
AG		 1143 ide_cmd_lba48_transform(s, lba48);
1144 s->req_nb_sectors = 1;
1145 ide_sector_read(s);
1146 break;
814839c0 1147 case WIN_WRITE_EXT:
6ef2ba5e
AG		 1148 lba48 = 1;
1149 case WIN_WRITE:
1150 case WIN_WRITE_ONCE:
1151 case CFA_WRITE_SECT_WO_ERASE:
1152 case WIN_WRITE_VERIFY:
d53cdb30
PB		 1153 if (!s->bs) {
1154 goto abort_cmd;
1155 }
6ef2ba5e
AG		 1156 ide_cmd_lba48_transform(s, lba48);
1157 s->error = 0;
1158 s->status = SEEK_STAT | READY_STAT;
1159 s->req_nb_sectors = 1;
1160 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1161 s->media_changed = 1;
1162 break;
814839c0 1163 case WIN_MULTREAD_EXT:
6ef2ba5e
AG		 1164 lba48 = 1;
1165 case WIN_MULTREAD:
d53cdb30
PB		 1166 if (!s->bs) {
1167 goto abort_cmd;
1168 }
1169 if (!s->mult_sectors) {
6ef2ba5e 1170 goto abort_cmd;
d53cdb30 1171 }
6ef2ba5e
AG		 1172 ide_cmd_lba48_transform(s, lba48);
1173 s->req_nb_sectors = s->mult_sectors;
1174 ide_sector_read(s);
1175 break;
1176 case WIN_MULTWRITE_EXT:
1177 lba48 = 1;
1178 case WIN_MULTWRITE:
1179 case CFA_WRITE_MULTI_WO_ERASE:
d53cdb30
PB		 1180 if (!s->bs) {
1181 goto abort_cmd;
1182 }
1183 if (!s->mult_sectors) {
6ef2ba5e 1184 goto abort_cmd;
d53cdb30 1185 }
6ef2ba5e
AG		 1186 ide_cmd_lba48_transform(s, lba48);
1187 s->error = 0;
1188 s->status = SEEK_STAT | READY_STAT;
1189 s->req_nb_sectors = s->mult_sectors;
1190 n = s->nsector;
1191 if (n > s->req_nb_sectors)
1192 n = s->req_nb_sectors;
1193 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1194 s->media_changed = 1;
1195 break;
814839c0 1196 case WIN_READDMA_EXT:
6ef2ba5e
AG		 1197 lba48 = 1;
1198 case WIN_READDMA:
1199 case WIN_READDMA_ONCE:
d53cdb30 1200 if (!s->bs) {
6ef2ba5e 1201 goto abort_cmd;
d53cdb30 1202 }
6ef2ba5e 1203 ide_cmd_lba48_transform(s, lba48);
4e1e0051 1204 ide_sector_start_dma(s, IDE_DMA_READ);
6ef2ba5e 1205 break;
814839c0 1206 case WIN_WRITEDMA_EXT:
6ef2ba5e
AG		 1207 lba48 = 1;
1208 case WIN_WRITEDMA:
1209 case WIN_WRITEDMA_ONCE:
d53cdb30 1210 if (!s->bs) {
6ef2ba5e 1211 goto abort_cmd;
d53cdb30 1212 }
6ef2ba5e 1213 ide_cmd_lba48_transform(s, lba48);
4e1e0051 1214 ide_sector_start_dma(s, IDE_DMA_WRITE);
6ef2ba5e
AG		 1215 s->media_changed = 1;
1216 break;
1217 case WIN_READ_NATIVE_MAX_EXT:
1218 lba48 = 1;
1219 case WIN_READ_NATIVE_MAX:
1220 ide_cmd_lba48_transform(s, lba48);
1221 ide_set_sector(s, s->nb_sectors - 1);
1222 s->status = READY_STAT | SEEK_STAT;
1223 ide_set_irq(s->bus);
1224 break;
1225 case WIN_CHECKPOWERMODE1:
1226 case WIN_CHECKPOWERMODE2:
b93af93d 1227 s->error = 0;
6ef2ba5e
AG		 1228 s->nsector = 0xff; /* device active or idle */
1229 s->status = READY_STAT | SEEK_STAT;
1230 ide_set_irq(s->bus);
1231 break;
1232 case WIN_SETFEATURES:
1233 if (!s->bs)
1234 goto abort_cmd;
1235 /* XXX: valid for CDROM ? */
1236 switch(s->feature) {
6ef2ba5e 1237 case 0x02: /* write cache enable */
7cdd481c
PB		 1238 bdrv_set_enable_write_cache(s->bs, true);
1239 identify_data = (uint16_t *)s->identify_data;
1240 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1241 s->status = READY_STAT | SEEK_STAT;
1242 ide_set_irq(s->bus);
1243 break;
6ef2ba5e 1244 case 0x82: /* write cache disable */
7cdd481c
PB		 1245 bdrv_set_enable_write_cache(s->bs, false);
1246 identify_data = (uint16_t *)s->identify_data;
1247 put_le16(identify_data + 85, (1 << 14) | 1);
1248 ide_flush_cache(s);
1249 break;
1250 case 0xcc: /* reverting to power-on defaults enable */
1251 case 0x66: /* reverting to power-on defaults disable */
6ef2ba5e
AG		 1252 case 0xaa: /* read look-ahead enable */
1253 case 0x55: /* read look-ahead disable */
1254 case 0x05: /* set advanced power management mode */
1255 case 0x85: /* disable advanced power management mode */
1256 case 0x69: /* NOP */
1257 case 0x67: /* NOP */
1258 case 0x96: /* NOP */
1259 case 0x9a: /* NOP */
1260 case 0x42: /* enable Automatic Acoustic Mode */
1261 case 0xc2: /* disable Automatic Acoustic Mode */
41a2b959 1262 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1263 ide_set_irq(s->bus);
a136e5a8 1264 break;
6ef2ba5e 1265 case 0x03: { /* set transfer mode */
94458802 1266 uint8_t val = s->nsector & 0x07;
7cdd481c 1267 identify_data = (uint16_t *)s->identify_data;
94458802
FB		 1268
1269 switch (s->nsector >> 3) {
6ef2ba5e
AG		 1270 case 0x00: /* pio default */
1271 case 0x01: /* pio mode */
96c35ceb
JQ		 1272 put_le16(identify_data + 62,0x07);
1273 put_le16(identify_data + 63,0x07);
1274 put_le16(identify_data + 88,0x3f);
d1b5c20d 1275 break;
6ef2ba5e 1276 case 0x02: /* sigle word dma mode*/
96c35ceb
JQ		 1277 put_le16(identify_data + 62,0x07 | (1 << (val + 8)));
1278 put_le16(identify_data + 63,0x07);
1279 put_le16(identify_data + 88,0x3f);
94458802 1280 break;
6ef2ba5e 1281 case 0x04: /* mdma mode */
96c35ceb
JQ		 1282 put_le16(identify_data + 62,0x07);
1283 put_le16(identify_data + 63,0x07 | (1 << (val + 8)));
1284 put_le16(identify_data + 88,0x3f);
94458802 1285 break;
6ef2ba5e 1286 case 0x08: /* udma mode */
96c35ceb
JQ		 1287 put_le16(identify_data + 62,0x07);
1288 put_le16(identify_data + 63,0x07);
1289 put_le16(identify_data + 88,0x3f | (1 << (val + 8)));
94458802 1290 break;
6ef2ba5e 1291 default:
94458802
FB		 1292 goto abort_cmd;
1293 }
4fbfcd6d 1294 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1295 ide_set_irq(s->bus);
4fbfcd6d 1296 break;
6ef2ba5e
AG		 1297 }
1298 default:
1299 goto abort_cmd;
1300 }
1301 break;
1302 case WIN_FLUSH_CACHE:
1303 case WIN_FLUSH_CACHE_EXT:
1304 ide_flush_cache(s);
1305 break;
1306 case WIN_STANDBY:
1307 case WIN_STANDBY2:
1308 case WIN_STANDBYNOW1:
1309 case WIN_STANDBYNOW2:
1310 case WIN_IDLEIMMEDIATE:
1d4316d3 1311 case WIN_IDLEIMMEDIATE2:
6ef2ba5e
AG		 1312 case WIN_SETIDLE1:
1313 case WIN_SETIDLE2:
1314 case WIN_SLEEPNOW1:
1315 case WIN_SLEEPNOW2:
1316 s->status = READY_STAT;
1317 ide_set_irq(s->bus);
1318 break;
1319 case WIN_SEEK:
6ef2ba5e
AG		 1320 /* XXX: Check that seek is within bounds */
1321 s->status = READY_STAT | SEEK_STAT;
1322 ide_set_irq(s->bus);
1323 break;
1324 /* ATAPI commands */
1325 case WIN_PIDENTIFY:
844505b1
MA		 1326 ide_atapi_identify(s);
1327 s->status = READY_STAT | SEEK_STAT;
1328 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
6ef2ba5e
AG		 1329 ide_set_irq(s->bus);
1330 break;
1331 case WIN_DIAGNOSE:
1332 ide_set_signature(s);
1333 if (s->drive_kind == IDE_CD)
1334 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1335 * devices to return a clear status register
1336 * with READY_STAT *not* set. */
1337 else
41a2b959 1338 s->status = READY_STAT | SEEK_STAT;
6ef2ba5e
AG		 1339 s->error = 0x01; /* Device 0 passed, Device 1 passed or not
1340 * present.
1341 */
1342 ide_set_irq(s->bus);
1343 break;
1d4316d3 1344 case WIN_DEVICE_RESET:
6ef2ba5e
AG		 1345 ide_set_signature(s);
1346 s->status = 0x00; /* NOTE: READY is _not_ set */
1347 s->error = 0x01;
1348 break;
1349 case WIN_PACKETCMD:
6ef2ba5e
AG		 1350 /* overlapping commands not supported */
1351 if (s->feature & 0x02)
1352 goto abort_cmd;
1353 s->status = READY_STAT | SEEK_STAT;
1354 s->atapi_dma = s->feature & 1;
1355 s->nsector = 1;
1356 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1357 ide_atapi_cmd);
1358 break;
1359 /* CF-ATA commands */
1360 case CFA_REQ_EXT_ERROR_CODE:
6ef2ba5e
AG		 1361 s->error = 0x09; /* miscellaneous error */
1362 s->status = READY_STAT | SEEK_STAT;
1363 ide_set_irq(s->bus);
1364 break;
1365 case CFA_ERASE_SECTORS:
1366 case CFA_WEAR_LEVEL:
d5b406d9
AG		 1367#if 0
1368 /* This one has the same ID as CFA_WEAR_LEVEL and is required for
1369 Windows 8 to work with AHCI */
1370 case WIN_SECURITY_FREEZE_LOCK:
1371#endif
6ef2ba5e
AG		 1372 if (val == CFA_WEAR_LEVEL)
1373 s->nsector = 0;
1374 if (val == CFA_ERASE_SECTORS)
1375 s->media_changed = 1;
1376 s->error = 0x00;
1377 s->status = READY_STAT | SEEK_STAT;
1378 ide_set_irq(s->bus);
1379 break;
1380 case CFA_TRANSLATE_SECTOR:
6ef2ba5e
AG		 1381 s->error = 0x00;
1382 s->status = READY_STAT | SEEK_STAT;
1383 memset(s->io_buffer, 0, 0x200);
1384 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1385 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1386 s->io_buffer[0x02] = s->select; /* Head */
1387 s->io_buffer[0x03] = s->sector; /* Sector */
1388 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1389 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1390 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1391 s->io_buffer[0x13] = 0x00; /* Erase flag */
1392 s->io_buffer[0x18] = 0x00; /* Hot count */
1393 s->io_buffer[0x19] = 0x00; /* Hot count */
1394 s->io_buffer[0x1a] = 0x01; /* Hot count */
1395 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1396 ide_set_irq(s->bus);
1397 break;
1398 case CFA_ACCESS_METADATA_STORAGE:
6ef2ba5e
AG		 1399 switch (s->feature) {
1400 case 0x02: /* Inquiry Metadata Storage */
1401 ide_cfata_metadata_inquiry(s);
201a51fc 1402 break;
6ef2ba5e
AG		 1403 case 0x03: /* Read Metadata Storage */
1404 ide_cfata_metadata_read(s);
201a51fc 1405 break;
6ef2ba5e
AG		 1406 case 0x04: /* Write Metadata Storage */
1407 ide_cfata_metadata_write(s);
201a51fc 1408 break;
6ef2ba5e
AG		 1409 default:
1410 goto abort_cmd;
1411 }
1412 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1413 s->status = 0x00; /* NOTE: READY is _not_ set */
1414 ide_set_irq(s->bus);
1415 break;
1416 case IBM_SENSE_CONDITION:
6ef2ba5e
AG		 1417 switch (s->feature) {
1418 case 0x01: /* sense temperature in device */
1419 s->nsector = 0x50; /* +20 C */
201a51fc 1420 break;
6ef2ba5e
AG		 1421 default:
1422 goto abort_cmd;
1423 }
1424 s->status = READY_STAT | SEEK_STAT;
1425 ide_set_irq(s->bus);
1426 break;
e8b54394 1427
814839c0 1428 case WIN_SMART:
6ef2ba5e 1429 if (s->hcyl != 0xc2 || s->lcyl != 0x4f)
e8b54394 1430 goto abort_cmd;
6ef2ba5e 1431 if (!s->smart_enabled && s->feature != SMART_ENABLE)
e8b54394 1432 goto abort_cmd;
6ef2ba5e
AG		 1433 switch (s->feature) {
1434 case SMART_DISABLE:
e8b54394
BW		 1435 s->smart_enabled = 0;
1436 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1437 ide_set_irq(s->bus);
e8b54394 1438 break;
6ef2ba5e 1439 case SMART_ENABLE:
e8b54394
BW		 1440 s->smart_enabled = 1;
1441 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1442 ide_set_irq(s->bus);
e8b54394 1443 break;
6ef2ba5e 1444 case SMART_ATTR_AUTOSAVE:
e8b54394
BW		 1445 switch (s->sector) {
1446 case 0x00:
6ef2ba5e
AG		 1447 s->smart_autosave = 0;
1448 break;
e8b54394 1449 case 0xf1:
6ef2ba5e
AG		 1450 s->smart_autosave = 1;
1451 break;
e8b54394 1452 default:
6ef2ba5e 1453 goto abort_cmd;
e8b54394
BW		 1454 }
1455 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1456 ide_set_irq(s->bus);
e8b54394 1457 break;
6ef2ba5e 1458 case SMART_STATUS:
e8b54394 1459 if (!s->smart_errors) {
6ef2ba5e
AG		 1460 s->hcyl = 0xc2;
1461 s->lcyl = 0x4f;
e8b54394 1462 } else {
6ef2ba5e
AG		 1463 s->hcyl = 0x2c;
1464 s->lcyl = 0xf4;
e8b54394
BW		 1465 }
1466 s->status = READY_STAT | SEEK_STAT;
9cdd03a7 1467 ide_set_irq(s->bus);
e8b54394 1468 break;
6ef2ba5e 1469 case SMART_READ_THRESH:
e8b54394
BW		 1470 memset(s->io_buffer, 0, 0x200);
1471 s->io_buffer[0] = 0x01; /* smart struct version */
1e53537f 1472 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
6ef2ba5e 1473 s->io_buffer[2+0+(n*12)] = smart_attributes[n][0];
b93af93d 1474 s->io_buffer[2+1+(n*12)] = smart_attributes[n][11];
e8b54394
BW		 1475 }
1476 for (n=0; n<511; n++) /* checksum */
6ef2ba5e 1477 s->io_buffer[511] += s->io_buffer[n];
e8b54394
BW		 1478 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1479 s->status = READY_STAT | SEEK_STAT;
1480 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1481 ide_set_irq(s->bus);
e8b54394 1482 break;
6ef2ba5e 1483 case SMART_READ_DATA:
e8b54394
BW		 1484 memset(s->io_buffer, 0, 0x200);
1485 s->io_buffer[0] = 0x01; /* smart struct version */
1e53537f 1486 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
b93af93d
BW		 1487 int i;
1488 for(i = 0; i < 11; i++) {
1489 s->io_buffer[2+i+(n*12)] = smart_attributes[n][i];
1490 }
e8b54394
BW		 1491 }
1492 s->io_buffer[362] = 0x02 | (s->smart_autosave?0x80:0x00);
1493 if (s->smart_selftest_count == 0) {
6ef2ba5e 1494 s->io_buffer[363] = 0;
e8b54394 1495 } else {
6ef2ba5e 1496 s->io_buffer[363] =
e8b54394 1497 s->smart_selftest_data[3 +
6ef2ba5e
AG		 1498 (s->smart_selftest_count - 1) *
1499 24];
e8b54394
BW		 1500 }
1501 s->io_buffer[364] = 0x20;
1502 s->io_buffer[365] = 0x01;
1503 /* offline data collection capacity: execute + self-test*/
1504 s->io_buffer[367] = (1<<4 | 1<<3 | 1);
1505 s->io_buffer[368] = 0x03; /* smart capability (1) */
1506 s->io_buffer[369] = 0x00; /* smart capability (2) */
1507 s->io_buffer[370] = 0x01; /* error logging supported */
1508 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1509 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1510 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1511
1512 for (n=0; n<511; n++)
6ef2ba5e 1513 s->io_buffer[511] += s->io_buffer[n];
e8b54394
BW		 1514 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1515 s->status = READY_STAT | SEEK_STAT;
1516 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1517 ide_set_irq(s->bus);
e8b54394 1518 break;
6ef2ba5e 1519 case SMART_READ_LOG:
e8b54394
BW		 1520 switch (s->sector) {
1521 case 0x01: /* summary smart error log */
6ef2ba5e
AG		 1522 memset(s->io_buffer, 0, 0x200);
1523 s->io_buffer[0] = 0x01;
1524 s->io_buffer[1] = 0x00; /* no error entries */
1525 s->io_buffer[452] = s->smart_errors & 0xff;
1526 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
e8b54394 1527
6ef2ba5e 1528 for (n=0; n<511; n++)
e8b54394 1529 s->io_buffer[511] += s->io_buffer[n];
6ef2ba5e
AG		 1530 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1531 break;
e8b54394 1532 case 0x06: /* smart self test log */
6ef2ba5e
AG		 1533 memset(s->io_buffer, 0, 0x200);
1534 s->io_buffer[0] = 0x01;
1535 if (s->smart_selftest_count == 0) {
e8b54394 1536 s->io_buffer[508] = 0;
6ef2ba5e 1537 } else {
e8b54394
BW		 1538 s->io_buffer[508] = s->smart_selftest_count;
1539 for (n=2; n<506; n++)
6ef2ba5e
AG		 1540 s->io_buffer[n] = s->smart_selftest_data[n];
1541 }
1542 for (n=0; n<511; n++)
e8b54394 1543 s->io_buffer[511] += s->io_buffer[n];
6ef2ba5e
AG		 1544 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1545 break;
e8b54394 1546 default:
6ef2ba5e 1547 goto abort_cmd;
e8b54394
BW		 1548 }
1549 s->status = READY_STAT | SEEK_STAT;
1550 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
9cdd03a7 1551 ide_set_irq(s->bus);
e8b54394 1552 break;
6ef2ba5e 1553 case SMART_EXECUTE_OFFLINE:
e8b54394
BW		 1554 switch (s->sector) {
1555 case 0: /* off-line routine */
1556 case 1: /* short self test */
1557 case 2: /* extended self test */
6ef2ba5e
AG		 1558 s->smart_selftest_count++;
1559 if(s->smart_selftest_count > 21)
e8b54394 1560 s->smart_selftest_count = 0;
6ef2ba5e
AG		 1561 n = 2 + (s->smart_selftest_count - 1) * 24;
1562 s->smart_selftest_data[n] = s->sector;
1563 s->smart_selftest_data[n+1] = 0x00; /* OK and finished */
1564 s->smart_selftest_data[n+2] = 0x34; /* hour count lsb */
1565 s->smart_selftest_data[n+3] = 0x12; /* hour count msb */
1566 s->status = READY_STAT | SEEK_STAT;
1567 ide_set_irq(s->bus);
1568 break;
e8b54394 1569 default:
6ef2ba5e 1570 goto abort_cmd;
e8b54394
BW		 1571 }
1572 break;
6ef2ba5e 1573 default:
e8b54394 1574 goto abort_cmd;
6ef2ba5e
AG		 1575 }
1576 break;
1577 default:
844505b1 1578 /* should not be reachable */
6ef2ba5e
AG		 1579 abort_cmd:
1580 ide_abort_command(s);
1581 ide_set_irq(s->bus);
1582 break;
1583 }
5391d806
FB		 1584}
1585
356721ae 1586uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
5391d806 1587{
bcbdc4d3
GH		 1588 IDEBus *bus = opaque;
1589 IDEState *s = idebus_active_if(bus);
5391d806 1590 uint32_t addr;
c2ff060f 1591 int ret, hob;
5391d806
FB		 1592
1593 addr = addr1 & 7;
c2ff060f
FB		 1594 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1595 //hob = s->select & (1 << 7);
1596 hob = 0;
5391d806
FB		 1597 switch(addr) {
1598 case 0:
1599 ret = 0xff;
1600 break;
1601 case 1:
bcbdc4d3
GH		 1602 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1603 (s != bus->ifs && !s->bs))
c45c3d00 1604 ret = 0;
c2ff060f 1605 else if (!hob)
c45c3d00 1606 ret = s->error;
c2ff060f
FB		 1607 else
1608 ret = s->hob_feature;
5391d806
FB		 1609 break;
1610 case 2:
bcbdc4d3 1611 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1612 ret = 0;
c2ff060f 1613 else if (!hob)
c45c3d00 1614 ret = s->nsector & 0xff;
c2ff060f
FB		 1615 else
1616 ret = s->hob_nsector;
5391d806
FB		 1617 break;
1618 case 3:
bcbdc4d3 1619 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1620 ret = 0;
c2ff060f 1621 else if (!hob)
c45c3d00 1622 ret = s->sector;
c2ff060f
FB		 1623 else
1624 ret = s->hob_sector;
5391d806
FB		 1625 break;
1626 case 4:
bcbdc4d3 1627 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1628 ret = 0;
c2ff060f 1629 else if (!hob)
c45c3d00 1630 ret = s->lcyl;
c2ff060f
FB		 1631 else
1632 ret = s->hob_lcyl;
5391d806
FB		 1633 break;
1634 case 5:
bcbdc4d3 1635 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00 1636 ret = 0;
c2ff060f 1637 else if (!hob)
c45c3d00 1638 ret = s->hcyl;
c2ff060f
FB		 1639 else
1640 ret = s->hob_hcyl;
5391d806
FB		 1641 break;
1642 case 6:
bcbdc4d3 1643 if (!bus->ifs[0].bs && !bus->ifs[1].bs)
c45c3d00
FB		 1644 ret = 0;
1645 else
7ae98627 1646 ret = s->select;
5391d806
FB		 1647 break;
1648 default:
1649 case 7:
bcbdc4d3
GH		 1650 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1651 (s != bus->ifs && !s->bs))
c45c3d00
FB		 1652 ret = 0;
1653 else
1654 ret = s->status;
9cdd03a7 1655 qemu_irq_lower(bus->irq);
5391d806
FB		 1656 break;
1657 }
1658#ifdef DEBUG_IDE
1659 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1660#endif
1661 return ret;
1662}
1663
356721ae 1664uint32_t ide_status_read(void *opaque, uint32_t addr)
5391d806 1665{
bcbdc4d3
GH		 1666 IDEBus *bus = opaque;
1667 IDEState *s = idebus_active_if(bus);
5391d806 1668 int ret;
7ae98627 1669
bcbdc4d3
GH		 1670 if ((!bus->ifs[0].bs && !bus->ifs[1].bs) ||
1671 (s != bus->ifs && !s->bs))
7ae98627
FB		 1672 ret = 0;
1673 else
1674 ret = s->status;
5391d806
FB		 1675#ifdef DEBUG_IDE
1676 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1677#endif
1678 return ret;
1679}
1680
356721ae 1681void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
5391d806 1682{
bcbdc4d3 1683 IDEBus *bus = opaque;
5391d806
FB		 1684 IDEState *s;
1685 int i;
1686
1687#ifdef DEBUG_IDE
1688 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1689#endif
1690 /* common for both drives */
9cdd03a7 1691 if (!(bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1692 (val & IDE_CMD_RESET)) {
1693 /* reset low to high */
1694 for(i = 0;i < 2; i++) {
bcbdc4d3 1695 s = &bus->ifs[i];
5391d806
FB		 1696 s->status = BUSY_STAT | SEEK_STAT;
1697 s->error = 0x01;
1698 }
9cdd03a7 1699 } else if ((bus->cmd & IDE_CMD_RESET) &&
5391d806
FB		 1700 !(val & IDE_CMD_RESET)) {
1701 /* high to low */
1702 for(i = 0;i < 2; i++) {
bcbdc4d3 1703 s = &bus->ifs[i];
cd8722bb 1704 if (s->drive_kind == IDE_CD)
6b136f9e
FB		 1705 s->status = 0x00; /* NOTE: READY is _not_ set */
1706 else
56bf1d37 1707 s->status = READY_STAT | SEEK_STAT;
5391d806
FB		 1708 ide_set_signature(s);
1709 }
1710 }
1711
9cdd03a7 1712 bus->cmd = val;
5391d806
FB		 1713}
1714
40c4ed3f
KW		 1715/*
1716 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1717 * transferred from the device to the guest), false if it's a PIO in
1718 */
1719static bool ide_is_pio_out(IDEState *s)
1720{
1721 if (s->end_transfer_func == ide_sector_write ||
1722 s->end_transfer_func == ide_atapi_cmd) {
1723 return false;
1724 } else if (s->end_transfer_func == ide_sector_read ||
1725 s->end_transfer_func == ide_transfer_stop ||
1726 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1727 s->end_transfer_func == ide_dummy_transfer_stop) {
1728 return true;
1729 }
1730
1731 abort();
1732}
1733
356721ae 1734void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
5391d806 1735{
bcbdc4d3
GH		 1736 IDEBus *bus = opaque;
1737 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1738 uint8_t *p;
1739
40c4ed3f
KW		 1740 /* PIO data access allowed only when DRQ bit is set. The result of a write
1741 * during PIO out is indeterminate, just ignore it. */
1742 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1743 return;
40c4ed3f 1744 }
fcdd25ab 1745
5391d806 1746 p = s->data_ptr;
0c4ad8dc 1747 *(uint16_t *)p = le16_to_cpu(val);
5391d806
FB		 1748 p += 2;
1749 s->data_ptr = p;
1750 if (p >= s->data_end)
1751 s->end_transfer_func(s);
1752}
1753
356721ae 1754uint32_t ide_data_readw(void *opaque, uint32_t addr)
5391d806 1755{
bcbdc4d3
GH		 1756 IDEBus *bus = opaque;
1757 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1758 uint8_t *p;
1759 int ret;
fcdd25ab 1760
40c4ed3f
KW		 1761 /* PIO data access allowed only when DRQ bit is set. The result of a read
1762 * during PIO in is indeterminate, return 0 and don't move forward. */
1763 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1764 return 0;
40c4ed3f 1765 }
fcdd25ab 1766
5391d806 1767 p = s->data_ptr;
0c4ad8dc 1768 ret = cpu_to_le16(*(uint16_t *)p);
5391d806
FB		 1769 p += 2;
1770 s->data_ptr = p;
1771 if (p >= s->data_end)
1772 s->end_transfer_func(s);
1773 return ret;
1774}
1775
356721ae 1776void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
5391d806 1777{
bcbdc4d3
GH		 1778 IDEBus *bus = opaque;
1779 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1780 uint8_t *p;
1781
40c4ed3f
KW		 1782 /* PIO data access allowed only when DRQ bit is set. The result of a write
1783 * during PIO out is indeterminate, just ignore it. */
1784 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
fcdd25ab 1785 return;
40c4ed3f 1786 }
fcdd25ab 1787
5391d806 1788 p = s->data_ptr;
0c4ad8dc 1789 *(uint32_t *)p = le32_to_cpu(val);
5391d806
FB		 1790 p += 4;
1791 s->data_ptr = p;
1792 if (p >= s->data_end)
1793 s->end_transfer_func(s);
1794}
1795
356721ae 1796uint32_t ide_data_readl(void *opaque, uint32_t addr)
5391d806 1797{
bcbdc4d3
GH		 1798 IDEBus *bus = opaque;
1799 IDEState *s = idebus_active_if(bus);
5391d806
FB		 1800 uint8_t *p;
1801 int ret;
3b46e624 1802
40c4ed3f
KW		 1803 /* PIO data access allowed only when DRQ bit is set. The result of a read
1804 * during PIO in is indeterminate, return 0 and don't move forward. */
1805 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
fcdd25ab 1806 return 0;
40c4ed3f 1807 }
fcdd25ab 1808
5391d806 1809 p = s->data_ptr;
0c4ad8dc 1810 ret = cpu_to_le32(*(uint32_t *)p);
5391d806
FB		 1811 p += 4;
1812 s->data_ptr = p;
1813 if (p >= s->data_end)
1814 s->end_transfer_func(s);
1815 return ret;
1816}
1817
a7dfe172
FB		 1818static void ide_dummy_transfer_stop(IDEState *s)
1819{
1820 s->data_ptr = s->io_buffer;
1821 s->data_end = s->io_buffer;
1822 s->io_buffer[0] = 0xff;
1823 s->io_buffer[1] = 0xff;
1824 s->io_buffer[2] = 0xff;
1825 s->io_buffer[3] = 0xff;
1826}
1827
4a643563 1828static void ide_reset(IDEState *s)
5391d806 1829{
4a643563
BS		 1830#ifdef DEBUG_IDE
1831 printf("ide: reset\n");
1832#endif
bef0fd59
SH		 1833
1834 if (s->pio_aiocb) {
1835 bdrv_aio_cancel(s->pio_aiocb);
1836 s->pio_aiocb = NULL;
1837 }
1838
cd8722bb 1839 if (s->drive_kind == IDE_CFATA)
201a51fc
AZ		 1840 s->mult_sectors = 0;
1841 else
1842 s->mult_sectors = MAX_MULT_SECTORS;
4a643563
BS		 1843 /* ide regs */
1844 s->feature = 0;
1845 s->error = 0;
1846 s->nsector = 0;
1847 s->sector = 0;
1848 s->lcyl = 0;
1849 s->hcyl = 0;
1850
1851 /* lba48 */
1852 s->hob_feature = 0;
1853 s->hob_sector = 0;
1854 s->hob_nsector = 0;
1855 s->hob_lcyl = 0;
1856 s->hob_hcyl = 0;
1857
5391d806 1858 s->select = 0xa0;
41a2b959 1859 s->status = READY_STAT | SEEK_STAT;
4a643563
BS		 1860
1861 s->lba48 = 0;
1862
1863 /* ATAPI specific */
1864 s->sense_key = 0;
1865 s->asc = 0;
1866 s->cdrom_changed = 0;
1867 s->packet_transfer_size = 0;
1868 s->elementary_transfer_size = 0;
1869 s->io_buffer_index = 0;
1870 s->cd_sector_size = 0;
1871 s->atapi_dma = 0;
a7f3d65b
PH		 1872 s->tray_locked = 0;
1873 s->tray_open = 0;
4a643563
BS		 1874 /* ATA DMA state */
1875 s->io_buffer_size = 0;
1876 s->req_nb_sectors = 0;
1877
5391d806 1878 ide_set_signature(s);
a7dfe172
FB		 1879 /* init the transfer handler so that 0xffff is returned on data
1880 accesses */
1881 s->end_transfer_func = ide_dummy_transfer_stop;
1882 ide_dummy_transfer_stop(s);
201a51fc 1883 s->media_changed = 0;
5391d806
FB		 1884}
1885
4a643563
BS		 1886void ide_bus_reset(IDEBus *bus)
1887{
1888 bus->unit = 0;
1889 bus->cmd = 0;
1890 ide_reset(&bus->ifs[0]);
1891 ide_reset(&bus->ifs[1]);
1892 ide_clear_hob(bus);
40a6238a
AG		 1893
1894 /* pending async DMA */
1895 if (bus->dma->aiocb) {
1896#ifdef DEBUG_AIO
1897 printf("aio_cancel\n");
1898#endif
1899 bdrv_aio_cancel(bus->dma->aiocb);
1900 bus->dma->aiocb = NULL;
1901 }
1902
1903 /* reset dma provider too */
1904 bus->dma->ops->reset(bus->dma);
4a643563
BS		 1905}
1906
e4def80b
MA		 1907static bool ide_cd_is_tray_open(void *opaque)
1908{
1909 return ((IDEState *)opaque)->tray_open;
1910}
1911
f107639a
MA		 1912static bool ide_cd_is_medium_locked(void *opaque)
1913{
1914 return ((IDEState *)opaque)->tray_locked;
1915}
1916
0e49de52 1917static const BlockDevOps ide_cd_block_ops = {
145feb17 1918 .change_media_cb = ide_cd_change_cb,
2df0a3a3 1919 .eject_request_cb = ide_cd_eject_request_cb,
e4def80b 1920 .is_tray_open = ide_cd_is_tray_open,
f107639a 1921 .is_medium_locked = ide_cd_is_medium_locked,
0e49de52
MA		 1922};
1923
1f56e32a 1924int ide_init_drive(IDEState *s, BlockDriverState *bs, IDEDriveKind kind,
95ebda85 1925 const char *version, const char *serial, const char *model,
ba801960
MA		 1926 uint64_t wwn,
1927 uint32_t cylinders, uint32_t heads, uint32_t secs,
1928 int chs_trans)
88804180 1929{
88804180
GH		 1930 uint64_t nb_sectors;
1931
f8b6cc00 1932 s->bs = bs;
1f56e32a
MA		 1933 s->drive_kind = kind;
1934
f8b6cc00 1935 bdrv_get_geometry(bs, &nb_sectors);
870111c8
MA		 1936 s->cylinders = cylinders;
1937 s->heads = heads;
1938 s->sectors = secs;
ba801960 1939 s->chs_trans = chs_trans;
870111c8 1940 s->nb_sectors = nb_sectors;
95ebda85 1941 s->wwn = wwn;
870111c8
MA		 1942 /* The SMART values should be preserved across power cycles
1943 but they aren't. */
1944 s->smart_enabled = 1;
1945 s->smart_autosave = 1;
1946 s->smart_errors = 0;
1947 s->smart_selftest_count = 0;
1f56e32a 1948 if (kind == IDE_CD) {
0e49de52 1949 bdrv_set_dev_ops(bs, &ide_cd_block_ops, s);
7b6f9300 1950 bdrv_set_buffer_alignment(bs, 2048);
7aa9c811 1951 } else {
98f28ad7
MA		 1952 if (!bdrv_is_inserted(s->bs)) {
1953 error_report("Device needs media, but drive is empty");
1954 return -1;
1955 }
7aa9c811
MA		 1956 if (bdrv_is_read_only(bs)) {
1957 error_report("Can't use a read-only drive");
1958 return -1;
1959 }
88804180 1960 }
f8b6cc00 1961 if (serial) {
aa2c91bd 1962 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
6ced55a5 1963 } else {
88804180
GH		 1964 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
1965 "QM%05d", s->drive_serial);
870111c8 1966 }
27e0c9a1
FB		 1967 if (model) {
1968 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
1969 } else {
1970 switch (kind) {
1971 case IDE_CD:
1972 strcpy(s->drive_model_str, "QEMU DVD-ROM");
1973 break;
1974 case IDE_CFATA:
1975 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
1976 break;
1977 default:
1978 strcpy(s->drive_model_str, "QEMU HARDDISK");
1979 break;
1980 }
1981 }
1982
47c06340
GH		 1983 if (version) {
1984 pstrcpy(s->version, sizeof(s->version), version);
1985 } else {
93bfef4c 1986 pstrcpy(s->version, sizeof(s->version), qemu_get_version());
47c06340 1987 }
40a6238a 1988
88804180 1989 ide_reset(s);
50fb1900 1990 bdrv_iostatus_enable(bs);
c4d74df7 1991 return 0;
88804180
GH		 1992}
1993
57234ee4 1994static void ide_init1(IDEBus *bus, int unit)
d459da0e
MA		 1995{
1996 static int drive_serial = 1;
1997 IDEState *s = &bus->ifs[unit];
1998
1999 s->bus = bus;
2000 s->unit = unit;
2001 s->drive_serial = drive_serial++;
1b2adf28 2002 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
50641c5c 2003 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
c925400b
KW		 2004 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2005 memset(s->io_buffer, 0, s->io_buffer_total_len);
2006
d459da0e 2007 s->smart_selftest_data = qemu_blockalign(s->bs, 512);
c925400b
KW		 2008 memset(s->smart_selftest_data, 0, 512);
2009
74475455 2010 s->sector_write_timer = qemu_new_timer_ns(vm_clock,
d459da0e 2011 ide_sector_write_timer_cb, s);
57234ee4
MA		 2012}
2013
40a6238a
AG		 2014static void ide_nop_start(IDEDMA *dma, IDEState *s,
2015 BlockDriverCompletionFunc *cb)
2016{
2017}
2018
2019static int ide_nop(IDEDMA *dma)
2020{
2021 return 0;
2022}
2023
2024static int ide_nop_int(IDEDMA *dma, int x)
2025{
2026 return 0;
2027}
2028
1dfb4dd9 2029static void ide_nop_restart(void *opaque, int x, RunState y)
40a6238a
AG		 2030{
2031}
2032
2033static const IDEDMAOps ide_dma_nop_ops = {
2034 .start_dma = ide_nop_start,
2035 .start_transfer = ide_nop,
2036 .prepare_buf = ide_nop_int,
2037 .rw_buf = ide_nop_int,
2038 .set_unit = ide_nop_int,
2039 .add_status = ide_nop_int,
2040 .set_inactive = ide_nop,
2041 .restart_cb = ide_nop_restart,
2042 .reset = ide_nop,
2043};
2044
2045static IDEDMA ide_dma_nop = {
2046 .ops = &ide_dma_nop_ops,
2047 .aiocb = NULL,
2048};
2049
57234ee4
MA		 2050void ide_init2(IDEBus *bus, qemu_irq irq)
2051{
2052 int i;
2053
2054 for(i = 0; i < 2; i++) {
2055 ide_init1(bus, i);
2056 ide_reset(&bus->ifs[i]);
870111c8 2057 }
57234ee4 2058 bus->irq = irq;
40a6238a 2059 bus->dma = &ide_dma_nop;
d459da0e
MA		 2060}
2061
57234ee4
MA		 2062/* TODO convert users to qdev and remove */
2063void ide_init2_with_non_qdev_drives(IDEBus *bus, DriveInfo *hd0,
2064 DriveInfo *hd1, qemu_irq irq)
5391d806 2065{
ba801960 2066 int i, trans;
57234ee4 2067 DriveInfo *dinfo;
ba801960 2068 uint32_t cyls, heads, secs;
5391d806 2069
caed8802 2070 for(i = 0; i < 2; i++) {
57234ee4
MA		 2071 dinfo = i == 0 ? hd0 : hd1;
2072 ide_init1(bus, i);
2073 if (dinfo) {
ba801960
MA		 2074 cyls = dinfo->cyls;
2075 heads = dinfo->heads;
2076 secs = dinfo->secs;
2077 trans = dinfo->trans;
2078 if (!cyls && !heads && !secs) {
2079 hd_geometry_guess(dinfo->bdrv, &cyls, &heads, &secs, &trans);
2adc99b2
MA		 2080 } else if (trans == BIOS_ATA_TRANSLATION_AUTO) {
2081 trans = hd_bios_chs_auto_trans(cyls, heads, secs);
ba801960 2082 }
b7eb0c9f
MA		 2083 if (cyls < 1 || cyls > 65535) {
2084 error_report("cyls must be between 1 and 65535");
2085 exit(1);
2086 }
2087 if (heads < 1 || heads > 16) {
2088 error_report("heads must be between 1 and 16");
2089 exit(1);
2090 }
2091 if (secs < 1 || secs > 255) {
2092 error_report("secs must be between 1 and 255");
2093 exit(1);
2094 }
1f56e32a 2095 if (ide_init_drive(&bus->ifs[i], dinfo->bdrv,
577d0a38
MA		 2096 dinfo->media_cd ? IDE_CD : IDE_HD,
2097 NULL, dinfo->serial, NULL, 0,
2098 cyls, heads, secs, trans) < 0) {
c4d74df7
MA		 2099 error_report("Can't set up IDE drive %s", dinfo->id);
2100 exit(1);
2101 }
fa879d62 2102 bdrv_attach_dev_nofail(dinfo->bdrv, &bus->ifs[i]);
57234ee4
MA		 2103 } else {
2104 ide_reset(&bus->ifs[i]);
2105 }
5391d806 2106 }
9cdd03a7 2107 bus->irq = irq;
40a6238a 2108 bus->dma = &ide_dma_nop;
69b91039
FB		 2109}
2110
4a91d3b3
RH		 2111static const MemoryRegionPortio ide_portio_list[] = {
2112 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2113 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
2114 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
2115 PORTIO_END_OF_LIST(),
2116};
2117
2118static const MemoryRegionPortio ide_portio2_list[] = {
2119 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2120 PORTIO_END_OF_LIST(),
2121};
2122
2123void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
69b91039 2124{
4a91d3b3
RH		 2125 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2126 bridge has been setup properly to always register with ISA. */
2127 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2128
caed8802 2129 if (iobase2) {
4a91d3b3 2130 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
5391d806 2131 }
5391d806 2132}
69b91039 2133
37159f13 2134static bool is_identify_set(void *opaque, int version_id)
aa941b94 2135{
37159f13
JQ		 2136 IDEState *s = opaque;
2137
2138 return s->identify_set != 0;
2139}
2140
50641c5c
JQ		 2141static EndTransferFunc* transfer_end_table[] = {
2142 ide_sector_read,
2143 ide_sector_write,
2144 ide_transfer_stop,
2145 ide_atapi_cmd_reply_end,
2146 ide_atapi_cmd,
2147 ide_dummy_transfer_stop,
2148};
2149
2150static int transfer_end_table_idx(EndTransferFunc *fn)
2151{
2152 int i;
2153
2154 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2155 if (transfer_end_table[i] == fn)
2156 return i;
2157
2158 return -1;
2159}
2160
37159f13 2161static int ide_drive_post_load(void *opaque, int version_id)
aa941b94 2162{
37159f13
JQ		 2163 IDEState *s = opaque;
2164
7cdd481c
PB		 2165 if (s->identify_set) {
2166 bdrv_set_enable_write_cache(s->bs, !!(s->identify_data[85] & (1 << 5)));
2167 }
37159f13 2168 return 0;
aa941b94
AZ		 2169}
2170
50641c5c
JQ		 2171static int ide_drive_pio_post_load(void *opaque, int version_id)
2172{
2173 IDEState *s = opaque;
2174
fb60105d 2175 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
50641c5c
JQ		 2176 return -EINVAL;
2177 }
2178 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2179 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2180 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2181
2182 return 0;
2183}
2184
2185static void ide_drive_pio_pre_save(void *opaque)
2186{
2187 IDEState *s = opaque;
2188 int idx;
2189
2190 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2191 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2192
2193 idx = transfer_end_table_idx(s->end_transfer_func);
2194 if (idx == -1) {
2195 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2196 __func__);
2197 s->end_transfer_fn_idx = 2;
2198 } else {
2199 s->end_transfer_fn_idx = idx;
2200 }
2201}
2202
2203static bool ide_drive_pio_state_needed(void *opaque)
2204{
2205 IDEState *s = opaque;
2206
fdc650d7
KW		 2207 return ((s->status & DRQ_STAT) != 0)
2208 || (s->bus->error_status & BM_STATUS_PIO_RETRY);
50641c5c
JQ		 2209}
2210
db118fe7
MA		 2211static bool ide_tray_state_needed(void *opaque)
2212{
2213 IDEState *s = opaque;
2214
2215 return s->tray_open || s->tray_locked;
2216}
2217
996faf1a
AS		 2218static bool ide_atapi_gesn_needed(void *opaque)
2219{
2220 IDEState *s = opaque;
2221
2222 return s->events.new_media || s->events.eject_request;
2223}
2224
def93791
KW		 2225static bool ide_error_needed(void *opaque)
2226{
2227 IDEBus *bus = opaque;
2228
2229 return (bus->error_status != 0);
2230}
2231
996faf1a 2232/* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
656fbeff 2233static const VMStateDescription vmstate_ide_atapi_gesn_state = {
996faf1a
AS		 2234 .name ="ide_drive/atapi/gesn_state",
2235 .version_id = 1,
2236 .minimum_version_id = 1,
2237 .minimum_version_id_old = 1,
2238 .fields = (VMStateField []) {
2239 VMSTATE_BOOL(events.new_media, IDEState),
2240 VMSTATE_BOOL(events.eject_request, IDEState),
0754f9ec 2241 VMSTATE_END_OF_LIST()
996faf1a
AS		 2242 }
2243};
2244
db118fe7
MA		 2245static const VMStateDescription vmstate_ide_tray_state = {
2246 .name = "ide_drive/tray_state",
2247 .version_id = 1,
2248 .minimum_version_id = 1,
2249 .minimum_version_id_old = 1,
db118fe7
MA		 2250 .fields = (VMStateField[]) {
2251 VMSTATE_BOOL(tray_open, IDEState),
2252 VMSTATE_BOOL(tray_locked, IDEState),
2253 VMSTATE_END_OF_LIST()
2254 }
2255};
2256
656fbeff 2257static const VMStateDescription vmstate_ide_drive_pio_state = {
50641c5c
JQ		 2258 .name = "ide_drive/pio_state",
2259 .version_id = 1,
2260 .minimum_version_id = 1,
2261 .minimum_version_id_old = 1,
2262 .pre_save = ide_drive_pio_pre_save,
2263 .post_load = ide_drive_pio_post_load,
2264 .fields = (VMStateField []) {
2265 VMSTATE_INT32(req_nb_sectors, IDEState),
2266 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2267 vmstate_info_uint8, uint8_t),
2268 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2269 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2270 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2271 VMSTATE_INT32(elementary_transfer_size, IDEState),
2272 VMSTATE_INT32(packet_transfer_size, IDEState),
2273 VMSTATE_END_OF_LIST()
2274 }
2275};
2276
37159f13
JQ		 2277const VMStateDescription vmstate_ide_drive = {
2278 .name = "ide_drive",
3abb6260 2279 .version_id = 3,
37159f13
JQ		 2280 .minimum_version_id = 0,
2281 .minimum_version_id_old = 0,
2282 .post_load = ide_drive_post_load,
2283 .fields = (VMStateField []) {
2284 VMSTATE_INT32(mult_sectors, IDEState),
2285 VMSTATE_INT32(identify_set, IDEState),
2286 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2287 VMSTATE_UINT8(feature, IDEState),
2288 VMSTATE_UINT8(error, IDEState),
2289 VMSTATE_UINT32(nsector, IDEState),
2290 VMSTATE_UINT8(sector, IDEState),
2291 VMSTATE_UINT8(lcyl, IDEState),
2292 VMSTATE_UINT8(hcyl, IDEState),
2293 VMSTATE_UINT8(hob_feature, IDEState),
2294 VMSTATE_UINT8(hob_sector, IDEState),
2295 VMSTATE_UINT8(hob_nsector, IDEState),
2296 VMSTATE_UINT8(hob_lcyl, IDEState),
2297 VMSTATE_UINT8(hob_hcyl, IDEState),
2298 VMSTATE_UINT8(select, IDEState),
2299 VMSTATE_UINT8(status, IDEState),
2300 VMSTATE_UINT8(lba48, IDEState),
2301 VMSTATE_UINT8(sense_key, IDEState),
2302 VMSTATE_UINT8(asc, IDEState),
2303 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
37159f13 2304 VMSTATE_END_OF_LIST()
50641c5c
JQ		 2305 },
2306 .subsections = (VMStateSubsection []) {
2307 {
2308 .vmsd = &vmstate_ide_drive_pio_state,
2309 .needed = ide_drive_pio_state_needed,
db118fe7
MA		 2310 }, {
2311 .vmsd = &vmstate_ide_tray_state,
2312 .needed = ide_tray_state_needed,
996faf1a
AS		 2313 }, {
2314 .vmsd = &vmstate_ide_atapi_gesn_state,
2315 .needed = ide_atapi_gesn_needed,
50641c5c
JQ		 2316 }, {
2317 /* empty */
2318 }
37159f13
JQ		 2319 }
2320};
2321
656fbeff 2322static const VMStateDescription vmstate_ide_error_status = {
def93791
KW		 2323 .name ="ide_bus/error",
2324 .version_id = 1,
2325 .minimum_version_id = 1,
2326 .minimum_version_id_old = 1,
2327 .fields = (VMStateField []) {
2328 VMSTATE_INT32(error_status, IDEBus),
2329 VMSTATE_END_OF_LIST()
2330 }
2331};
2332
6521dc62
JQ		 2333const VMStateDescription vmstate_ide_bus = {
2334 .name = "ide_bus",
2335 .version_id = 1,
2336 .minimum_version_id = 1,
2337 .minimum_version_id_old = 1,
2338 .fields = (VMStateField []) {
2339 VMSTATE_UINT8(cmd, IDEBus),
2340 VMSTATE_UINT8(unit, IDEBus),
2341 VMSTATE_END_OF_LIST()
def93791
KW		 2342 },
2343 .subsections = (VMStateSubsection []) {
2344 {
2345 .vmsd = &vmstate_ide_error_status,
2346 .needed = ide_error_needed,
2347 }, {
2348 /* empty */
2349 }
6521dc62
JQ		 2350 }
2351};
75717903
IY		 2352
2353void ide_drive_get(DriveInfo **hd, int max_bus)
2354{
2355 int i;
2356
2357 if (drive_get_max_bus(IF_IDE) >= max_bus) {
2358 fprintf(stderr, "qemu: too many IDE bus: %d\n", max_bus);
2359 exit(1);
2360 }
2361
2362 for(i = 0; i < max_bus * MAX_IDE_DEVS; i++) {
2363 hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS, i % MAX_IDE_DEVS);
2364 }
2365}
Qemu copy for testing