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3d2bf4a1 GH |
1 | /* |
2 | * QEMU IDE Emulation: mmio support (for embedded). | |
3 | * | |
4 | * Copyright (c) 2003 Fabrice Bellard | |
5 | * Copyright (c) 2006 Openedhand Ltd. | |
6 | * | |
7 | * Permission is hereby granted, free of charge, to any person obtaining a copy | |
8 | * of this software and associated documentation files (the "Software"), to deal | |
9 | * in the Software without restriction, including without limitation the rights | |
10 | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell | |
11 | * copies of the Software, and to permit persons to whom the Software is | |
12 | * furnished to do so, subject to the following conditions: | |
13 | * | |
14 | * The above copyright notice and this permission notice shall be included in | |
15 | * all copies or substantial portions of the Software. | |
16 | * | |
17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
18 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
19 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
20 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
21 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
22 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN | |
23 | * THE SOFTWARE. | |
24 | */ | |
59f2a787 | 25 | #include <hw/hw.h> |
3d2bf4a1 GH |
26 | #include "block.h" |
27 | #include "block_int.h" | |
3d2bf4a1 | 28 | #include "dma.h" |
59f2a787 GH |
29 | |
30 | #include <hw/ide/internal.h> | |
3d2bf4a1 GH |
31 | |
32 | /***********************************************************/ | |
33 | /* MMIO based ide port | |
34 | * This emulates IDE device connected directly to the CPU bus without | |
35 | * dedicated ide controller, which is often seen on embedded boards. | |
36 | */ | |
37 | ||
38 | typedef struct { | |
0ce51e92 | 39 | IDEBus bus; |
3d2bf4a1 GH |
40 | int shift; |
41 | } MMIOState; | |
42 | ||
4a643563 BS |
43 | static void mmio_ide_reset(void *opaque) |
44 | { | |
45 | MMIOState *s = opaque; | |
46 | ||
47 | ide_bus_reset(&s->bus); | |
48 | } | |
49 | ||
c227f099 | 50 | static uint32_t mmio_ide_read (void *opaque, target_phys_addr_t addr) |
3d2bf4a1 | 51 | { |
18c0fb30 | 52 | MMIOState *s = opaque; |
3d2bf4a1 GH |
53 | addr >>= s->shift; |
54 | if (addr & 7) | |
0ce51e92 | 55 | return ide_ioport_read(&s->bus, addr); |
3d2bf4a1 | 56 | else |
0ce51e92 | 57 | return ide_data_readw(&s->bus, 0); |
3d2bf4a1 GH |
58 | } |
59 | ||
c227f099 | 60 | static void mmio_ide_write (void *opaque, target_phys_addr_t addr, |
3d2bf4a1 GH |
61 | uint32_t val) |
62 | { | |
18c0fb30 | 63 | MMIOState *s = opaque; |
3d2bf4a1 GH |
64 | addr >>= s->shift; |
65 | if (addr & 7) | |
0ce51e92 | 66 | ide_ioport_write(&s->bus, addr, val); |
3d2bf4a1 | 67 | else |
0ce51e92 | 68 | ide_data_writew(&s->bus, 0, val); |
3d2bf4a1 GH |
69 | } |
70 | ||
71 | static CPUReadMemoryFunc * const mmio_ide_reads[] = { | |
72 | mmio_ide_read, | |
73 | mmio_ide_read, | |
74 | mmio_ide_read, | |
75 | }; | |
76 | ||
77 | static CPUWriteMemoryFunc * const mmio_ide_writes[] = { | |
78 | mmio_ide_write, | |
79 | mmio_ide_write, | |
80 | mmio_ide_write, | |
81 | }; | |
82 | ||
c227f099 | 83 | static uint32_t mmio_ide_status_read (void *opaque, target_phys_addr_t addr) |
3d2bf4a1 | 84 | { |
18c0fb30 | 85 | MMIOState *s= opaque; |
0ce51e92 | 86 | return ide_status_read(&s->bus, 0); |
3d2bf4a1 GH |
87 | } |
88 | ||
c227f099 | 89 | static void mmio_ide_cmd_write (void *opaque, target_phys_addr_t addr, |
3d2bf4a1 GH |
90 | uint32_t val) |
91 | { | |
18c0fb30 | 92 | MMIOState *s = opaque; |
0ce51e92 | 93 | ide_cmd_write(&s->bus, 0, val); |
3d2bf4a1 GH |
94 | } |
95 | ||
96 | static CPUReadMemoryFunc * const mmio_ide_status[] = { | |
97 | mmio_ide_status_read, | |
98 | mmio_ide_status_read, | |
99 | mmio_ide_status_read, | |
100 | }; | |
101 | ||
102 | static CPUWriteMemoryFunc * const mmio_ide_cmd[] = { | |
103 | mmio_ide_cmd_write, | |
104 | mmio_ide_cmd_write, | |
105 | mmio_ide_cmd_write, | |
106 | }; | |
107 | ||
24daf35c JQ |
108 | static const VMStateDescription vmstate_ide_mmio = { |
109 | .name = "mmio-ide", | |
110 | .version_id = 3, | |
111 | .minimum_version_id = 0, | |
112 | .minimum_version_id_old = 0, | |
113 | .fields = (VMStateField []) { | |
114 | VMSTATE_IDE_BUS(bus, MMIOState), | |
115 | VMSTATE_IDE_DRIVES(bus.ifs, MMIOState), | |
116 | VMSTATE_END_OF_LIST() | |
117 | } | |
118 | }; | |
2bcbf7e4 | 119 | |
c227f099 | 120 | void mmio_ide_init (target_phys_addr_t membase, target_phys_addr_t membase2, |
3d2bf4a1 | 121 | qemu_irq irq, int shift, |
f455e98c | 122 | DriveInfo *hd0, DriveInfo *hd1) |
3d2bf4a1 GH |
123 | { |
124 | MMIOState *s = qemu_mallocz(sizeof(MMIOState)); | |
3d2bf4a1 GH |
125 | int mem1, mem2; |
126 | ||
57234ee4 | 127 | ide_init2_with_non_qdev_drives(&s->bus, hd0, hd1, irq); |
3d2bf4a1 | 128 | |
3d2bf4a1 GH |
129 | s->shift = shift; |
130 | ||
2507c12a AG |
131 | mem1 = cpu_register_io_memory(mmio_ide_reads, mmio_ide_writes, s, |
132 | DEVICE_NATIVE_ENDIAN); | |
133 | mem2 = cpu_register_io_memory(mmio_ide_status, mmio_ide_cmd, s, | |
134 | DEVICE_NATIVE_ENDIAN); | |
3d2bf4a1 GH |
135 | cpu_register_physical_memory(membase, 16 << shift, mem1); |
136 | cpu_register_physical_memory(membase2, 2 << shift, mem2); | |
0be71e32 | 137 | vmstate_register(NULL, 0, &vmstate_ide_mmio, s); |
4a643563 | 138 | qemu_register_reset(mmio_ide_reset, s); |
3d2bf4a1 GH |
139 | } |
140 |