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d61a4ce8
GH		 1/*
2 * Copyright (C) 2010 Red Hat, Inc.
3 *
4 * written by Gerd Hoffmann <kraxel@redhat.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 or
9 * (at your option) version 3 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "hw.h"
a2cb15b0
MT		 21#include "pci/pci.h"
22#include "pci/msi.h"
1de7afc9 23#include "qemu/timer.h"
d61a4ce8
GH		 24#include "audiodev.h"
25#include "intel-hda.h"
26#include "intel-hda-defs.h"
9c17d615 27#include "sysemu/dma.h"
d61a4ce8
GH		 28
29/* --------------------------------------------------------------------- */
30/* hda bus */
31
3cb75a7c
PB		 32static Property hda_props[] = {
33 DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1),
34 DEFINE_PROP_END_OF_LIST()
35};
36
0d936928
AL		 37static const TypeInfo hda_codec_bus_info = {
38 .name = TYPE_HDA_BUS,
39 .parent = TYPE_BUS,
40 .instance_size = sizeof(HDACodecBus),
d61a4ce8
GH		 41};
42
43void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
44 hda_codec_response_func response,
45 hda_codec_xfer_func xfer)
46{
0d936928 47 qbus_create_inplace(&bus->qbus, TYPE_HDA_BUS, dev, NULL);
d61a4ce8
GH		 48 bus->response = response;
49 bus->xfer = xfer;
50}
51
d307af79 52static int hda_codec_dev_init(DeviceState *qdev)
d61a4ce8
GH		 53{
54 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus);
55 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
dbaa7904 56 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
d61a4ce8 57
d61a4ce8
GH		 58 if (dev->cad == -1) {
59 dev->cad = bus->next_cad;
60 }
df0db221 61 if (dev->cad >= 15) {
d61a4ce8 62 return -1;
df0db221 63 }
d61a4ce8 64 bus->next_cad = dev->cad + 1;
dbaa7904 65 return cdc->init(dev);
d61a4ce8
GH		 66}
67
dc4b9240
GH		 68static int hda_codec_dev_exit(DeviceState *qdev)
69{
70 HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev);
dbaa7904 71 HDACodecDeviceClass *cdc = HDA_CODEC_DEVICE_GET_CLASS(dev);
dc4b9240 72
dbaa7904
AL		 73 if (cdc->exit) {
74 cdc->exit(dev);
dc4b9240
GH		 75 }
76 return 0;
77}
78
d61a4ce8
GH		 79HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad)
80{
0866aca1 81 BusChild *kid;
d61a4ce8
GH		 82 HDACodecDevice *cdev;
83
0866aca1
AL		 84 QTAILQ_FOREACH(kid, &bus->qbus.children, sibling) {
85 DeviceState *qdev = kid->child;
d61a4ce8
GH		 86 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
87 if (cdev->cad == cad) {
88 return cdev;
89 }
90 }
91 return NULL;
92}
93
94void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response)
95{
96 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
97 bus->response(dev, solicited, response);
98}
99
100bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
101 uint8_t *buf, uint32_t len)
102{
103 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
104 return bus->xfer(dev, stnr, output, buf, len);
105}
106
107/* --------------------------------------------------------------------- */
108/* intel hda emulation */
109
110typedef struct IntelHDAStream IntelHDAStream;
111typedef struct IntelHDAState IntelHDAState;
112typedef struct IntelHDAReg IntelHDAReg;
113
114typedef struct bpl {
115 uint64_t addr;
116 uint32_t len;
117 uint32_t flags;
118} bpl;
119
120struct IntelHDAStream {
121 /* registers */
122 uint32_t ctl;
123 uint32_t lpib;
124 uint32_t cbl;
125 uint32_t lvi;
126 uint32_t fmt;
127 uint32_t bdlp_lbase;
128 uint32_t bdlp_ubase;
129
130 /* state */
131 bpl *bpl;
132 uint32_t bentries;
133 uint32_t bsize, be, bp;
134};
135
136struct IntelHDAState {
137 PCIDevice pci;
138 const char *name;
139 HDACodecBus codecs;
140
141 /* registers */
142 uint32_t g_ctl;
143 uint32_t wake_en;
144 uint32_t state_sts;
145 uint32_t int_ctl;
146 uint32_t int_sts;
147 uint32_t wall_clk;
148
149 uint32_t corb_lbase;
150 uint32_t corb_ubase;
151 uint32_t corb_rp;
152 uint32_t corb_wp;
153 uint32_t corb_ctl;
154 uint32_t corb_sts;
155 uint32_t corb_size;
156
157 uint32_t rirb_lbase;
158 uint32_t rirb_ubase;
159 uint32_t rirb_wp;
160 uint32_t rirb_cnt;
161 uint32_t rirb_ctl;
162 uint32_t rirb_sts;
163 uint32_t rirb_size;
164
165 uint32_t dp_lbase;
166 uint32_t dp_ubase;
167
168 uint32_t icw;
169 uint32_t irr;
170 uint32_t ics;
171
172 /* streams */
173 IntelHDAStream st[8];
174
175 /* state */
234bbdf1 176 MemoryRegion mmio;
d61a4ce8
GH		 177 uint32_t rirb_count;
178 int64_t wall_base_ns;
179
180 /* debug logging */
181 const IntelHDAReg *last_reg;
182 uint32_t last_val;
183 uint32_t last_write;
184 uint32_t last_sec;
185 uint32_t repeat_count;
186
187 /* properties */
188 uint32_t debug;
17786d52 189 uint32_t msi;
d61a4ce8
GH		 190};
191
192struct IntelHDAReg {
193 const char *name; /* register name */
194 uint32_t size; /* size in bytes */
195 uint32_t reset; /* reset value */
196 uint32_t wmask; /* write mask */
197 uint32_t wclear; /* write 1 to clear bits */
198 uint32_t offset; /* location in IntelHDAState */
199 uint32_t shift; /* byte access entries for dwords */
200 uint32_t stream;
201 void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old);
202 void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg);
203};
204
205static void intel_hda_reset(DeviceState *dev);
206
207/* --------------------------------------------------------------------- */
208
a8170e5e 209static hwaddr intel_hda_addr(uint32_t lbase, uint32_t ubase)
d61a4ce8 210{
a8170e5e 211 hwaddr addr;
d61a4ce8 212
4be403c8 213 addr = ((uint64_t)ubase << 32) | lbase;
d61a4ce8
GH		 214 return addr;
215}
216
d61a4ce8
GH		 217static void intel_hda_update_int_sts(IntelHDAState *d)
218{
219 uint32_t sts = 0;
220 uint32_t i;
221
222 /* update controller status */
223 if (d->rirb_sts & ICH6_RBSTS_IRQ) {
224 sts |= (1 << 30);
225 }
226 if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
227 sts |= (1 << 30);
228 }
af93485c 229 if (d->state_sts & d->wake_en) {
d61a4ce8
GH		 230 sts |= (1 << 30);
231 }
232
233 /* update stream status */
234 for (i = 0; i < 8; i++) {
235 /* buffer completion interrupt */
236 if (d->st[i].ctl & (1 << 26)) {
237 sts |= (1 << i);
238 }
239 }
240
241 /* update global status */
242 if (sts & d->int_ctl) {
243 sts |= (1 << 31);
244 }
245
246 d->int_sts = sts;
247}
248
249static void intel_hda_update_irq(IntelHDAState *d)
250{
17786d52 251 int msi = d->msi && msi_enabled(&d->pci);
d61a4ce8
GH		 252 int level;
253
254 intel_hda_update_int_sts(d);
255 if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) {
256 level = 1;
257 } else {
258 level = 0;
259 }
17786d52
GH		 260 dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__,
261 level, msi ? "msi" : "intx");
262 if (msi) {
263 if (level) {
264 msi_notify(&d->pci, 0);
265 }
266 } else {
267 qemu_set_irq(d->pci.irq[0], level);
268 }
d61a4ce8
GH		 269}
270
271static int intel_hda_send_command(IntelHDAState *d, uint32_t verb)
272{
273 uint32_t cad, nid, data;
274 HDACodecDevice *codec;
dbaa7904 275 HDACodecDeviceClass *cdc;
d61a4ce8
GH		 276
277 cad = (verb >> 28) & 0x0f;
278 if (verb & (1 << 27)) {
279 /* indirect node addressing, not specified in HDA 1.0 */
280 dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__);
281 return -1;
282 }
283 nid = (verb >> 20) & 0x7f;
284 data = verb & 0xfffff;
285
286 codec = hda_codec_find(&d->codecs, cad);
287 if (codec == NULL) {
288 dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__);
289 return -1;
290 }
dbaa7904
AL		 291 cdc = HDA_CODEC_DEVICE_GET_CLASS(codec);
292 cdc->command(codec, nid, data);
d61a4ce8
GH		 293 return 0;
294}
295
296static void intel_hda_corb_run(IntelHDAState *d)
297{
a8170e5e 298 hwaddr addr;
d61a4ce8
GH		 299 uint32_t rp, verb;
300
301 if (d->ics & ICH6_IRS_BUSY) {
302 dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw);
303 intel_hda_send_command(d, d->icw);
304 return;
305 }
306
307 for (;;) {
308 if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
309 dprint(d, 2, "%s: !run\n", __FUNCTION__);
310 return;
311 }
312 if ((d->corb_rp & 0xff) == d->corb_wp) {
313 dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__);
314 return;
315 }
316 if (d->rirb_count == d->rirb_cnt) {
317 dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__);
318 return;
319 }
320
321 rp = (d->corb_rp + 1) & 0xff;
322 addr = intel_hda_addr(d->corb_lbase, d->corb_ubase);
fa0ce55c 323 verb = ldl_le_pci_dma(&d->pci, addr + 4*rp);
d61a4ce8
GH		 324 d->corb_rp = rp;
325
326 dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb);
327 intel_hda_send_command(d, verb);
328 }
329}
330
331static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response)
332{
333 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
334 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
a8170e5e 335 hwaddr addr;
d61a4ce8
GH		 336 uint32_t wp, ex;
337
338 if (d->ics & ICH6_IRS_BUSY) {
339 dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n",
340 __FUNCTION__, response, dev->cad);
341 d->irr = response;
342 d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
343 d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
344 return;
345 }
346
347 if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
348 dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__);
349 return;
350 }
351
352 ex = (solicited ? 0 : (1 << 4)) | dev->cad;
353 wp = (d->rirb_wp + 1) & 0xff;
354 addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase);
fa0ce55c
DG		 355 stl_le_pci_dma(&d->pci, addr + 8*wp, response);
356 stl_le_pci_dma(&d->pci, addr + 8*wp + 4, ex);
d61a4ce8
GH		 357 d->rirb_wp = wp;
358
359 dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n",
360 __FUNCTION__, wp, response, ex);
361
362 d->rirb_count++;
363 if (d->rirb_count == d->rirb_cnt) {
364 dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count);
365 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
366 d->rirb_sts |= ICH6_RBSTS_IRQ;
367 intel_hda_update_irq(d);
368 }
369 } else if ((d->corb_rp & 0xff) == d->corb_wp) {
370 dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__,
371 d->rirb_count, d->rirb_cnt);
372 if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
373 d->rirb_sts |= ICH6_RBSTS_IRQ;
374 intel_hda_update_irq(d);
375 }
376 }
377}
378
379static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output,
380 uint8_t *buf, uint32_t len)
381{
382 HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus);
383 IntelHDAState *d = container_of(bus, IntelHDAState, codecs);
a8170e5e 384 hwaddr addr;
d61a4ce8 385 uint32_t s, copy, left;
36ac4ad3 386 IntelHDAStream *st;
d61a4ce8
GH		 387 bool irq = false;
388
36ac4ad3
MAL		 389 st = output ? d->st + 4 : d->st;
390 for (s = 0; s < 4; s++) {
391 if (stnr == ((st[s].ctl >> 20) & 0x0f)) {
392 st = st + s;
d61a4ce8
GH		 393 break;
394 }
395 }
18ebcc86 396 if (s == 4) {
d61a4ce8
GH		 397 return false;
398 }
399 if (st->bpl == NULL) {
400 return false;
401 }
402 if (st->ctl & (1 << 26)) {
403 /*
404 * Wait with the next DMA xfer until the guest
405 * has acked the buffer completion interrupt
406 */
407 return false;
408 }
409
410 left = len;
411 while (left > 0) {
412 copy = left;
413 if (copy > st->bsize - st->lpib)
414 copy = st->bsize - st->lpib;
415 if (copy > st->bpl[st->be].len - st->bp)
416 copy = st->bpl[st->be].len - st->bp;
417
418 dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n",
419 st->be, st->bp, st->bpl[st->be].len, copy);
420
fa0ce55c 421 pci_dma_rw(&d->pci, st->bpl[st->be].addr + st->bp, buf, copy, !output);
d61a4ce8
GH		 422 st->lpib += copy;
423 st->bp += copy;
424 buf += copy;
425 left -= copy;
426
427 if (st->bpl[st->be].len == st->bp) {
428 /* bpl entry filled */
429 if (st->bpl[st->be].flags & 0x01) {
430 irq = true;
431 }
432 st->bp = 0;
433 st->be++;
434 if (st->be == st->bentries) {
435 /* bpl wrap around */
436 st->be = 0;
437 st->lpib = 0;
438 }
439 }
440 }
441 if (d->dp_lbase & 0x01) {
442 addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
fa0ce55c 443 stl_le_pci_dma(&d->pci, addr + 8*s, st->lpib);
d61a4ce8
GH		 444 }
445 dprint(d, 3, "dma: --\n");
446
447 if (irq) {
448 st->ctl |= (1 << 26); /* buffer completion interrupt */
449 intel_hda_update_irq(d);
450 }
451 return true;
452}
453
454static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st)
455{
a8170e5e 456 hwaddr addr;
d61a4ce8
GH		 457 uint8_t buf[16];
458 uint32_t i;
459
460 addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase);
461 st->bentries = st->lvi +1;
7267c094
AL		 462 g_free(st->bpl);
463 st->bpl = g_malloc(sizeof(bpl) * st->bentries);
d61a4ce8 464 for (i = 0; i < st->bentries; i++, addr += 16) {
fa0ce55c 465 pci_dma_read(&d->pci, addr, buf, 16);
d61a4ce8
GH		 466 st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf);
467 st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
468 st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
469 dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n",
470 i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags);
471 }
472
473 st->bsize = st->cbl;
474 st->lpib = 0;
475 st->be = 0;
476 st->bp = 0;
477}
478
ba43d289 479static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running, bool output)
d61a4ce8 480{
0866aca1 481 BusChild *kid;
d61a4ce8
GH		 482 HDACodecDevice *cdev;
483
0866aca1
AL		 484 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
485 DeviceState *qdev = kid->child;
dbaa7904
AL		 486 HDACodecDeviceClass *cdc;
487
d61a4ce8 488 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
dbaa7904
AL		 489 cdc = HDA_CODEC_DEVICE_GET_CLASS(cdev);
490 if (cdc->stream) {
491 cdc->stream(cdev, stream, running, output);
d61a4ce8
GH		 492 }
493 }
494}
495
496/* --------------------------------------------------------------------- */
497
498static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
499{
500 if ((d->g_ctl & ICH6_GCTL_RESET) == 0) {
501 intel_hda_reset(&d->pci.qdev);
502 }
503}
504
6a0d02f5
GH		 505static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
506{
507 intel_hda_update_irq(d);
508}
509
d61a4ce8
GH		 510static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
511{
512 intel_hda_update_irq(d);
513}
514
515static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
516{
517 intel_hda_update_irq(d);
518}
519
520static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg)
521{
522 int64_t ns;
523
524 ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns;
525 d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */
526}
527
528static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
529{
530 intel_hda_corb_run(d);
531}
532
533static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
534{
535 intel_hda_corb_run(d);
536}
537
538static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
539{
540 if (d->rirb_wp & ICH6_RIRBWP_RST) {
541 d->rirb_wp = 0;
542 }
543}
544
545static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
546{
547 intel_hda_update_irq(d);
548
549 if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
550 /* cleared ICH6_RBSTS_IRQ */
551 d->rirb_count = 0;
552 intel_hda_corb_run(d);
553 }
554}
555
556static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
557{
558 if (d->ics & ICH6_IRS_BUSY) {
559 intel_hda_corb_run(d);
560 }
561}
562
563static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old)
564{
ba43d289 565 bool output = reg->stream >= 4;
d61a4ce8
GH		 566 IntelHDAStream *st = d->st + reg->stream;
567
568 if (st->ctl & 0x01) {
569 /* reset */
570 dprint(d, 1, "st #%d: reset\n", reg->stream);
571 st->ctl = 0;
572 }
573 if ((st->ctl & 0x02) != (old & 0x02)) {
574 uint32_t stnr = (st->ctl >> 20) & 0x0f;
575 /* run bit flipped */
576 if (st->ctl & 0x02) {
577 /* start */
578 dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n",
579 reg->stream, stnr, st->cbl);
580 intel_hda_parse_bdl(d, st);
ba43d289 581 intel_hda_notify_codecs(d, stnr, true, output);
d61a4ce8
GH		 582 } else {
583 /* stop */
584 dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr);
ba43d289 585 intel_hda_notify_codecs(d, stnr, false, output);
d61a4ce8
GH		 586 }
587 }
588 intel_hda_update_irq(d);
589}
590
591/* --------------------------------------------------------------------- */
592
593#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o))
594
595static const struct IntelHDAReg regtab[] = {
596 /* global */
597 [ ICH6_REG_GCAP ] = {
598 .name = "GCAP",
599 .size = 2,
600 .reset = 0x4401,
601 },
602 [ ICH6_REG_VMIN ] = {
603 .name = "VMIN",
604 .size = 1,
605 },
606 [ ICH6_REG_VMAJ ] = {
607 .name = "VMAJ",
608 .size = 1,
609 .reset = 1,
610 },
611 [ ICH6_REG_OUTPAY ] = {
612 .name = "OUTPAY",
613 .size = 2,
614 .reset = 0x3c,
615 },
616 [ ICH6_REG_INPAY ] = {
617 .name = "INPAY",
618 .size = 2,
619 .reset = 0x1d,
620 },
621 [ ICH6_REG_GCTL ] = {
622 .name = "GCTL",
623 .size = 4,
624 .wmask = 0x0103,
625 .offset = offsetof(IntelHDAState, g_ctl),
626 .whandler = intel_hda_set_g_ctl,
627 },
628 [ ICH6_REG_WAKEEN ] = {
629 .name = "WAKEEN",
630 .size = 2,
df0db221 631 .wmask = 0x7fff,
d61a4ce8 632 .offset = offsetof(IntelHDAState, wake_en),
6a0d02f5 633 .whandler = intel_hda_set_wake_en,
d61a4ce8
GH		 634 },
635 [ ICH6_REG_STATESTS ] = {
636 .name = "STATESTS",
637 .size = 2,
df0db221
GH		 638 .wmask = 0x7fff,
639 .wclear = 0x7fff,
d61a4ce8
GH		 640 .offset = offsetof(IntelHDAState, state_sts),
641 .whandler = intel_hda_set_state_sts,
642 },
643
644 /* interrupts */
645 [ ICH6_REG_INTCTL ] = {
646 .name = "INTCTL",
647 .size = 4,
648 .wmask = 0xc00000ff,
649 .offset = offsetof(IntelHDAState, int_ctl),
650 .whandler = intel_hda_set_int_ctl,
651 },
652 [ ICH6_REG_INTSTS ] = {
653 .name = "INTSTS",
654 .size = 4,
655 .wmask = 0xc00000ff,
656 .wclear = 0xc00000ff,
657 .offset = offsetof(IntelHDAState, int_sts),
658 },
659
660 /* misc */
661 [ ICH6_REG_WALLCLK ] = {
662 .name = "WALLCLK",
663 .size = 4,
664 .offset = offsetof(IntelHDAState, wall_clk),
665 .rhandler = intel_hda_get_wall_clk,
666 },
667 [ ICH6_REG_WALLCLK + 0x2000 ] = {
668 .name = "WALLCLK(alias)",
669 .size = 4,
670 .offset = offsetof(IntelHDAState, wall_clk),
671 .rhandler = intel_hda_get_wall_clk,
672 },
673
674 /* dma engine */
675 [ ICH6_REG_CORBLBASE ] = {
676 .name = "CORBLBASE",
677 .size = 4,
678 .wmask = 0xffffff80,
679 .offset = offsetof(IntelHDAState, corb_lbase),
680 },
681 [ ICH6_REG_CORBUBASE ] = {
682 .name = "CORBUBASE",
683 .size = 4,
684 .wmask = 0xffffffff,
685 .offset = offsetof(IntelHDAState, corb_ubase),
686 },
687 [ ICH6_REG_CORBWP ] = {
688 .name = "CORBWP",
689 .size = 2,
690 .wmask = 0xff,
691 .offset = offsetof(IntelHDAState, corb_wp),
692 .whandler = intel_hda_set_corb_wp,
693 },
694 [ ICH6_REG_CORBRP ] = {
695 .name = "CORBRP",
696 .size = 2,
697 .wmask = 0x80ff,
698 .offset = offsetof(IntelHDAState, corb_rp),
699 },
700 [ ICH6_REG_CORBCTL ] = {
701 .name = "CORBCTL",
702 .size = 1,
703 .wmask = 0x03,
704 .offset = offsetof(IntelHDAState, corb_ctl),
705 .whandler = intel_hda_set_corb_ctl,
706 },
707 [ ICH6_REG_CORBSTS ] = {
708 .name = "CORBSTS",
709 .size = 1,
710 .wmask = 0x01,
711 .wclear = 0x01,
712 .offset = offsetof(IntelHDAState, corb_sts),
713 },
714 [ ICH6_REG_CORBSIZE ] = {
715 .name = "CORBSIZE",
716 .size = 1,
717 .reset = 0x42,
718 .offset = offsetof(IntelHDAState, corb_size),
719 },
720 [ ICH6_REG_RIRBLBASE ] = {
721 .name = "RIRBLBASE",
722 .size = 4,
723 .wmask = 0xffffff80,
724 .offset = offsetof(IntelHDAState, rirb_lbase),
725 },
726 [ ICH6_REG_RIRBUBASE ] = {
727 .name = "RIRBUBASE",
728 .size = 4,
729 .wmask = 0xffffffff,
730 .offset = offsetof(IntelHDAState, rirb_ubase),
731 },
732 [ ICH6_REG_RIRBWP ] = {
733 .name = "RIRBWP",
734 .size = 2,
735 .wmask = 0x8000,
736 .offset = offsetof(IntelHDAState, rirb_wp),
737 .whandler = intel_hda_set_rirb_wp,
738 },
739 [ ICH6_REG_RINTCNT ] = {
740 .name = "RINTCNT",
741 .size = 2,
742 .wmask = 0xff,
743 .offset = offsetof(IntelHDAState, rirb_cnt),
744 },
745 [ ICH6_REG_RIRBCTL ] = {
746 .name = "RIRBCTL",
747 .size = 1,
748 .wmask = 0x07,
749 .offset = offsetof(IntelHDAState, rirb_ctl),
750 },
751 [ ICH6_REG_RIRBSTS ] = {
752 .name = "RIRBSTS",
753 .size = 1,
754 .wmask = 0x05,
755 .wclear = 0x05,
756 .offset = offsetof(IntelHDAState, rirb_sts),
757 .whandler = intel_hda_set_rirb_sts,
758 },
759 [ ICH6_REG_RIRBSIZE ] = {
760 .name = "RIRBSIZE",
761 .size = 1,
762 .reset = 0x42,
763 .offset = offsetof(IntelHDAState, rirb_size),
764 },
765
766 [ ICH6_REG_DPLBASE ] = {
767 .name = "DPLBASE",
768 .size = 4,
769 .wmask = 0xffffff81,
770 .offset = offsetof(IntelHDAState, dp_lbase),
771 },
772 [ ICH6_REG_DPUBASE ] = {
773 .name = "DPUBASE",
774 .size = 4,
775 .wmask = 0xffffffff,
776 .offset = offsetof(IntelHDAState, dp_ubase),
777 },
778
779 [ ICH6_REG_IC ] = {
780 .name = "ICW",
781 .size = 4,
782 .wmask = 0xffffffff,
783 .offset = offsetof(IntelHDAState, icw),
784 },
785 [ ICH6_REG_IR ] = {
786 .name = "IRR",
787 .size = 4,
788 .offset = offsetof(IntelHDAState, irr),
789 },
790 [ ICH6_REG_IRS ] = {
791 .name = "ICS",
792 .size = 2,
793 .wmask = 0x0003,
794 .wclear = 0x0002,
795 .offset = offsetof(IntelHDAState, ics),
796 .whandler = intel_hda_set_ics,
797 },
798
799#define HDA_STREAM(_t, _i) \
800 [ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
801 .stream = _i, \
802 .name = _t stringify(_i) " CTL", \
803 .size = 4, \
804 .wmask = 0x1cff001f, \
805 .offset = offsetof(IntelHDAState, st[_i].ctl), \
806 .whandler = intel_hda_set_st_ctl, \
807 }, \
808 [ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
809 .stream = _i, \
810 .name = _t stringify(_i) " CTL(stnr)", \
811 .size = 1, \
812 .shift = 16, \
813 .wmask = 0x00ff0000, \
814 .offset = offsetof(IntelHDAState, st[_i].ctl), \
815 .whandler = intel_hda_set_st_ctl, \
816 }, \
817 [ ST_REG(_i, ICH6_REG_SD_STS)] = { \
818 .stream = _i, \
819 .name = _t stringify(_i) " CTL(sts)", \
820 .size = 1, \
821 .shift = 24, \
822 .wmask = 0x1c000000, \
823 .wclear = 0x1c000000, \
824 .offset = offsetof(IntelHDAState, st[_i].ctl), \
825 .whandler = intel_hda_set_st_ctl, \
826 }, \
827 [ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
828 .stream = _i, \
829 .name = _t stringify(_i) " LPIB", \
830 .size = 4, \
831 .offset = offsetof(IntelHDAState, st[_i].lpib), \
832 }, \
833 [ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
834 .stream = _i, \
835 .name = _t stringify(_i) " LPIB(alias)", \
836 .size = 4, \
837 .offset = offsetof(IntelHDAState, st[_i].lpib), \
838 }, \
839 [ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
840 .stream = _i, \
841 .name = _t stringify(_i) " CBL", \
842 .size = 4, \
843 .wmask = 0xffffffff, \
844 .offset = offsetof(IntelHDAState, st[_i].cbl), \
845 }, \
846 [ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
847 .stream = _i, \
848 .name = _t stringify(_i) " LVI", \
849 .size = 2, \
850 .wmask = 0x00ff, \
851 .offset = offsetof(IntelHDAState, st[_i].lvi), \
852 }, \
853 [ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
854 .stream = _i, \
855 .name = _t stringify(_i) " FIFOS", \
856 .size = 2, \
857 .reset = HDA_BUFFER_SIZE, \
858 }, \
859 [ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
860 .stream = _i, \
861 .name = _t stringify(_i) " FMT", \
862 .size = 2, \
863 .wmask = 0x7f7f, \
864 .offset = offsetof(IntelHDAState, st[_i].fmt), \
865 }, \
866 [ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
867 .stream = _i, \
868 .name = _t stringify(_i) " BDLPL", \
869 .size = 4, \
870 .wmask = 0xffffff80, \
871 .offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \
872 }, \
873 [ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
874 .stream = _i, \
875 .name = _t stringify(_i) " BDLPU", \
876 .size = 4, \
877 .wmask = 0xffffffff, \
878 .offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \
879 }, \
880
881 HDA_STREAM("IN", 0)
882 HDA_STREAM("IN", 1)
883 HDA_STREAM("IN", 2)
884 HDA_STREAM("IN", 3)
885
886 HDA_STREAM("OUT", 4)
887 HDA_STREAM("OUT", 5)
888 HDA_STREAM("OUT", 6)
889 HDA_STREAM("OUT", 7)
890
891};
892
a8170e5e 893static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, hwaddr addr)
d61a4ce8
GH		 894{
895 const IntelHDAReg *reg;
896
897 if (addr >= sizeof(regtab)/sizeof(regtab[0])) {
898 goto noreg;
899 }
900 reg = regtab+addr;
901 if (reg->name == NULL) {
902 goto noreg;
903 }
904 return reg;
905
906noreg:
907 dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr);
908 return NULL;
909}
910
911static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg)
912{
913 uint8_t *addr = (void*)d;
914
915 addr += reg->offset;
916 return (uint32_t*)addr;
917}
918
919static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val,
920 uint32_t wmask)
921{
922 uint32_t *addr;
923 uint32_t old;
924
925 if (!reg) {
926 return;
927 }
928
929 if (d->debug) {
930 time_t now = time(NULL);
931 if (d->last_write && d->last_reg == reg && d->last_val == val) {
932 d->repeat_count++;
933 if (d->last_sec != now) {
934 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
935 d->last_sec = now;
936 d->repeat_count = 0;
937 }
938 } else {
939 if (d->repeat_count) {
940 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
941 }
942 dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask);
943 d->last_write = 1;
944 d->last_reg = reg;
945 d->last_val = val;
946 d->last_sec = now;
947 d->repeat_count = 0;
948 }
949 }
950 assert(reg->offset != 0);
951
952 addr = intel_hda_reg_addr(d, reg);
953 old = *addr;
954
955 if (reg->shift) {
956 val <<= reg->shift;
957 wmask <<= reg->shift;
958 }
959 wmask &= reg->wmask;
960 *addr &= ~wmask;
961 *addr |= wmask & val;
962 *addr &= ~(val & reg->wclear);
963
964 if (reg->whandler) {
965 reg->whandler(d, reg, old);
966 }
967}
968
969static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg,
970 uint32_t rmask)
971{
972 uint32_t *addr, ret;
973
974 if (!reg) {
975 return 0;
976 }
977
978 if (reg->rhandler) {
979 reg->rhandler(d, reg);
980 }
981
982 if (reg->offset == 0) {
983 /* constant read-only register */
984 ret = reg->reset;
985 } else {
986 addr = intel_hda_reg_addr(d, reg);
987 ret = *addr;
988 if (reg->shift) {
989 ret >>= reg->shift;
990 }
991 ret &= rmask;
992 }
993 if (d->debug) {
994 time_t now = time(NULL);
995 if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
996 d->repeat_count++;
997 if (d->last_sec != now) {
998 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
999 d->last_sec = now;
1000 d->repeat_count = 0;
1001 }
1002 } else {
1003 if (d->repeat_count) {
1004 dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count);
1005 }
1006 dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask);
1007 d->last_write = 0;
1008 d->last_reg = reg;
1009 d->last_val = ret;
1010 d->last_sec = now;
1011 d->repeat_count = 0;
1012 }
1013 }
1014 return ret;
1015}
1016
1017static void intel_hda_regs_reset(IntelHDAState *d)
1018{
1019 uint32_t *addr;
1020 int i;
1021
1022 for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) {
1023 if (regtab[i].name == NULL) {
1024 continue;
1025 }
1026 if (regtab[i].offset == 0) {
1027 continue;
1028 }
1029 addr = intel_hda_reg_addr(d, regtab + i);
1030 *addr = regtab[i].reset;
1031 }
1032}
1033
1034/* --------------------------------------------------------------------- */
1035
a8170e5e 1036static void intel_hda_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
d61a4ce8
GH		 1037{
1038 IntelHDAState *d = opaque;
1039 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1040
1041 intel_hda_reg_write(d, reg, val, 0xff);
1042}
1043
a8170e5e 1044static void intel_hda_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
d61a4ce8
GH		 1045{
1046 IntelHDAState *d = opaque;
1047 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1048
1049 intel_hda_reg_write(d, reg, val, 0xffff);
1050}
1051
a8170e5e 1052static void intel_hda_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
d61a4ce8
GH		 1053{
1054 IntelHDAState *d = opaque;
1055 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1056
1057 intel_hda_reg_write(d, reg, val, 0xffffffff);
1058}
1059
a8170e5e 1060static uint32_t intel_hda_mmio_readb(void *opaque, hwaddr addr)
d61a4ce8
GH		 1061{
1062 IntelHDAState *d = opaque;
1063 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1064
1065 return intel_hda_reg_read(d, reg, 0xff);
1066}
1067
a8170e5e 1068static uint32_t intel_hda_mmio_readw(void *opaque, hwaddr addr)
d61a4ce8
GH		 1069{
1070 IntelHDAState *d = opaque;
1071 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1072
1073 return intel_hda_reg_read(d, reg, 0xffff);
1074}
1075
a8170e5e 1076static uint32_t intel_hda_mmio_readl(void *opaque, hwaddr addr)
d61a4ce8
GH		 1077{
1078 IntelHDAState *d = opaque;
1079 const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
1080
1081 return intel_hda_reg_read(d, reg, 0xffffffff);
1082}
1083
234bbdf1
AK		 1084static const MemoryRegionOps intel_hda_mmio_ops = {
1085 .old_mmio = {
1086 .read = {
1087 intel_hda_mmio_readb,
1088 intel_hda_mmio_readw,
1089 intel_hda_mmio_readl,
1090 },
1091 .write = {
1092 intel_hda_mmio_writeb,
1093 intel_hda_mmio_writew,
1094 intel_hda_mmio_writel,
1095 },
1096 },
1097 .endianness = DEVICE_NATIVE_ENDIAN,
d61a4ce8
GH		 1098};
1099
d61a4ce8
GH		 1100/* --------------------------------------------------------------------- */
1101
1102static void intel_hda_reset(DeviceState *dev)
1103{
0866aca1 1104 BusChild *kid;
d61a4ce8 1105 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev);
d61a4ce8
GH		 1106 HDACodecDevice *cdev;
1107
1108 intel_hda_regs_reset(d);
74475455 1109 d->wall_base_ns = qemu_get_clock_ns(vm_clock);
d61a4ce8
GH		 1110
1111 /* reset codecs */
0866aca1
AL		 1112 QTAILQ_FOREACH(kid, &d->codecs.qbus.children, sibling) {
1113 DeviceState *qdev = kid->child;
d61a4ce8 1114 cdev = DO_UPCAST(HDACodecDevice, qdev, qdev);
94afdadc 1115 device_reset(DEVICE(cdev));
d61a4ce8
GH		 1116 d->state_sts |= (1 << cdev->cad);
1117 }
1118 intel_hda_update_irq(d);
1119}
1120
1121static int intel_hda_init(PCIDevice *pci)
1122{
1123 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1124 uint8_t *conf = d->pci.config;
1125
f79f2bfc 1126 d->name = object_get_typename(OBJECT(d));
d61a4ce8 1127
d61a4ce8
GH		 1128 pci_config_set_interrupt_pin(conf, 1);
1129
1130 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
1131 conf[0x40] = 0x01;
1132
234bbdf1
AK		 1133 memory_region_init_io(&d->mmio, &intel_hda_mmio_ops, d,
1134 "intel-hda", 0x4000);
e824b2cc 1135 pci_register_bar(&d->pci, 0, 0, &d->mmio);
17786d52
GH		 1136 if (d->msi) {
1137 msi_init(&d->pci, 0x50, 1, true, false);
1138 }
d61a4ce8
GH		 1139
1140 hda_codec_bus_init(&d->pci.qdev, &d->codecs,
1141 intel_hda_response, intel_hda_xfer);
1142
1143 return 0;
1144}
1145
f90c2bcd 1146static void intel_hda_exit(PCIDevice *pci)
dc4b9240
GH		 1147{
1148 IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci);
1149
45fe15c2 1150 msi_uninit(&d->pci);
234bbdf1 1151 memory_region_destroy(&d->mmio);
dc4b9240
GH		 1152}
1153
d61a4ce8
GH		 1154static int intel_hda_post_load(void *opaque, int version)
1155{
1156 IntelHDAState* d = opaque;
1157 int i;
1158
1159 dprint(d, 1, "%s\n", __FUNCTION__);
1160 for (i = 0; i < ARRAY_SIZE(d->st); i++) {
1161 if (d->st[i].ctl & 0x02) {
1162 intel_hda_parse_bdl(d, &d->st[i]);
1163 }
1164 }
1165 intel_hda_update_irq(d);
1166 return 0;
1167}
1168
1169static const VMStateDescription vmstate_intel_hda_stream = {
1170 .name = "intel-hda-stream",
1171 .version_id = 1,
1172 .fields = (VMStateField []) {
1173 VMSTATE_UINT32(ctl, IntelHDAStream),
1174 VMSTATE_UINT32(lpib, IntelHDAStream),
1175 VMSTATE_UINT32(cbl, IntelHDAStream),
1176 VMSTATE_UINT32(lvi, IntelHDAStream),
1177 VMSTATE_UINT32(fmt, IntelHDAStream),
1178 VMSTATE_UINT32(bdlp_lbase, IntelHDAStream),
1179 VMSTATE_UINT32(bdlp_ubase, IntelHDAStream),
1180 VMSTATE_END_OF_LIST()
1181 }
1182};
1183
1184static const VMStateDescription vmstate_intel_hda = {
1185 .name = "intel-hda",
1186 .version_id = 1,
1187 .post_load = intel_hda_post_load,
1188 .fields = (VMStateField []) {
1189 VMSTATE_PCI_DEVICE(pci, IntelHDAState),
1190
1191 /* registers */
1192 VMSTATE_UINT32(g_ctl, IntelHDAState),
1193 VMSTATE_UINT32(wake_en, IntelHDAState),
1194 VMSTATE_UINT32(state_sts, IntelHDAState),
1195 VMSTATE_UINT32(int_ctl, IntelHDAState),
1196 VMSTATE_UINT32(int_sts, IntelHDAState),
1197 VMSTATE_UINT32(wall_clk, IntelHDAState),
1198 VMSTATE_UINT32(corb_lbase, IntelHDAState),
1199 VMSTATE_UINT32(corb_ubase, IntelHDAState),
1200 VMSTATE_UINT32(corb_rp, IntelHDAState),
1201 VMSTATE_UINT32(corb_wp, IntelHDAState),
1202 VMSTATE_UINT32(corb_ctl, IntelHDAState),
1203 VMSTATE_UINT32(corb_sts, IntelHDAState),
1204 VMSTATE_UINT32(corb_size, IntelHDAState),
1205 VMSTATE_UINT32(rirb_lbase, IntelHDAState),
1206 VMSTATE_UINT32(rirb_ubase, IntelHDAState),
1207 VMSTATE_UINT32(rirb_wp, IntelHDAState),
1208 VMSTATE_UINT32(rirb_cnt, IntelHDAState),
1209 VMSTATE_UINT32(rirb_ctl, IntelHDAState),
1210 VMSTATE_UINT32(rirb_sts, IntelHDAState),
1211 VMSTATE_UINT32(rirb_size, IntelHDAState),
1212 VMSTATE_UINT32(dp_lbase, IntelHDAState),
1213 VMSTATE_UINT32(dp_ubase, IntelHDAState),
1214 VMSTATE_UINT32(icw, IntelHDAState),
1215 VMSTATE_UINT32(irr, IntelHDAState),
1216 VMSTATE_UINT32(ics, IntelHDAState),
1217 VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0,
1218 vmstate_intel_hda_stream,
1219 IntelHDAStream),
1220
1221 /* additional state info */
1222 VMSTATE_UINT32(rirb_count, IntelHDAState),
1223 VMSTATE_INT64(wall_base_ns, IntelHDAState),
1224
1225 VMSTATE_END_OF_LIST()
1226 }
1227};
1228
40021f08
AL		 1229static Property intel_hda_properties[] = {
1230 DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0),
1231 DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1),
1232 DEFINE_PROP_END_OF_LIST(),
1233};
1234
1235static void intel_hda_class_init(ObjectClass *klass, void *data)
1236{
39bffca2 1237 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 1238 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
1239
1240 k->init = intel_hda_init;
1241 k->exit = intel_hda_exit;
40021f08
AL		 1242 k->vendor_id = PCI_VENDOR_ID_INTEL;
1243 k->device_id = 0x2668;
1244 k->revision = 1;
1245 k->class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO;
39bffca2
AL		 1246 dc->desc = "Intel HD Audio Controller";
1247 dc->reset = intel_hda_reset;
1248 dc->vmsd = &vmstate_intel_hda;
1249 dc->props = intel_hda_properties;
40021f08
AL		 1250}
1251
39bffca2
AL		 1252static TypeInfo intel_hda_info = {
1253 .name = "intel-hda",
1254 .parent = TYPE_PCI_DEVICE,
1255 .instance_size = sizeof(IntelHDAState),
1256 .class_init = intel_hda_class_init,
40021f08
AL		 1257};
1258
39bffca2
AL		 1259static void hda_codec_device_class_init(ObjectClass *klass, void *data)
1260{
1261 DeviceClass *k = DEVICE_CLASS(klass);
1262 k->init = hda_codec_dev_init;
1263 k->exit = hda_codec_dev_exit;
0d936928 1264 k->bus_type = TYPE_HDA_BUS;
bce54474 1265 k->props = hda_props;
39bffca2
AL		 1266}
1267
40021f08
AL		 1268static TypeInfo hda_codec_device_type_info = {
1269 .name = TYPE_HDA_CODEC_DEVICE,
1270 .parent = TYPE_DEVICE,
1271 .instance_size = sizeof(HDACodecDevice),
1272 .abstract = true,
1273 .class_size = sizeof(HDACodecDeviceClass),
39bffca2 1274 .class_init = hda_codec_device_class_init,
d61a4ce8
GH		 1275};
1276
83f7d43a 1277static void intel_hda_register_types(void)
d61a4ce8 1278{
0d936928 1279 type_register_static(&hda_codec_bus_info);
39bffca2 1280 type_register_static(&intel_hda_info);
40021f08 1281 type_register_static(&hda_codec_device_type_info);
d61a4ce8 1282}
83f7d43a
AF		 1283
1284type_init(intel_hda_register_types)
d61a4ce8
GH		 1285
1286/*
1287 * create intel hda controller with codec attached to it,
1288 * so '-soundhw hda' works.
1289 */
1290int intel_hda_and_codec_init(PCIBus *bus)
1291{
1292 PCIDevice *controller;
1293 BusState *hdabus;
1294 DeviceState *codec;
1295
1296 controller = pci_create_simple(bus, -1, "intel-hda");
1297 hdabus = QLIST_FIRST(&controller->qdev.child_bus);
1298 codec = qdev_create(hdabus, "hda-duplex");
1299 qdev_init_nofail(codec);
1300 return 0;
1301}
1302
Qemu copy for testing