[qemu.git] / hw / lm32_boards.c

/*
 *  QEMU models for LatticeMico32 uclinux and evr32 boards.
 *
 *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "sysbus.h"
#include "hw.h"
#include "flash.h"
#include "devices.h"
#include "boards.h"
#include "loader.h"
#include "sysemu/blockdev.h"
#include "elf.h"
#include "lm32_hwsetup.h"
#include "lm32.h"
#include "exec/address-spaces.h"

typedef struct {
    LM32CPU *cpu;
    hwaddr bootstrap_pc;
    hwaddr flash_base;
    hwaddr hwsetup_base;
    hwaddr initrd_base;
    size_t initrd_size;
    hwaddr cmdline_base;
} ResetInfo;

static void cpu_irq_handler(void *opaque, int irq, int level)
{
    CPULM32State *env = opaque;

    if (level) {
        cpu_interrupt(env, CPU_INTERRUPT_HARD);
    } else {
        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
    }
}

static void main_cpu_reset(void *opaque)
{
    ResetInfo *reset_info = opaque;
    CPULM32State *env = &reset_info->cpu->env;

    cpu_reset(CPU(reset_info->cpu));

    /* init defaults */
    env->pc = (uint32_t)reset_info->bootstrap_pc;
    env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
    env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
    env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
    env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
        reset_info->initrd_size);
    env->eba = reset_info->flash_base;
    env->deba = reset_info->flash_base;
}

static void lm32_evr_init(QEMUMachineInitArgs *args)
{
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq *cpu_irq, irq[32];
    ResetInfo *reset_info;
    int i;

    /* memory map */
    hwaddr flash_base  = 0x04000000;
    size_t flash_sector_size       = 256 * 1024;
    size_t flash_size              = 32 * 1024 * 1024;
    hwaddr ram_base    = 0x08000000;
    size_t ram_size                = 64 * 1024 * 1024;
    hwaddr timer0_base = 0x80002000;
    hwaddr uart0_base  = 0x80006000;
    hwaddr timer1_base = 0x8000a000;
    int uart0_irq                  = 0;
    int timer0_irq                 = 1;
    int timer1_irq                 = 3;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    cpu = cpu_lm32_init(cpu_model);
    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_init_ram(phys_ram, "lm32_evr.sdram", ram_size);
    vmstate_register_ram_global(phys_ram);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
                          dinfo ? dinfo->bdrv : NULL, flash_sector_size,
                          flash_size / flash_sector_size, 1, 2,
                          0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
    env->pic_state = lm32_pic_init(*cpu_irq);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, ELF_MACHINE, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static void lm32_uclinux_init(QEMUMachineInitArgs *args)
{
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    const char *kernel_cmdline = args->kernel_cmdline;
    const char *initrd_filename = args->initrd_filename;
    LM32CPU *cpu;
    CPULM32State *env;
    DriveInfo *dinfo;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq *cpu_irq, irq[32];
    HWSetup *hw;
    ResetInfo *reset_info;
    int i;

    /* memory map */
    hwaddr flash_base   = 0x04000000;
    size_t flash_sector_size        = 256 * 1024;
    size_t flash_size               = 32 * 1024 * 1024;
    hwaddr ram_base     = 0x08000000;
    size_t ram_size                 = 64 * 1024 * 1024;
    hwaddr uart0_base   = 0x80000000;
    hwaddr timer0_base  = 0x80002000;
    hwaddr timer1_base  = 0x80010000;
    hwaddr timer2_base  = 0x80012000;
    int uart0_irq                   = 0;
    int timer0_irq                  = 1;
    int timer1_irq                  = 20;
    int timer2_irq                  = 21;
    hwaddr hwsetup_base = 0x0bffe000;
    hwaddr cmdline_base = 0x0bfff000;
    hwaddr initrd_base  = 0x08400000;
    size_t initrd_max               = 0x01000000;

    reset_info = g_malloc0(sizeof(ResetInfo));

    if (cpu_model == NULL) {
        cpu_model = "lm32-full";
    }
    cpu = cpu_lm32_init(cpu_model);
    env = &cpu->env;
    reset_info->cpu = cpu;

    reset_info->flash_base = flash_base;

    memory_region_init_ram(phys_ram, "lm32_uclinux.sdram", ram_size);
    vmstate_register_ram_global(phys_ram);
    memory_region_add_subregion(address_space_mem, ram_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    /* Spansion S29NS128P */
    pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
                          dinfo ? dinfo->bdrv : NULL, flash_sector_size,
                          flash_size / flash_sector_size, 1, 2,
                          0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);

    /* create irq lines */
    cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
    env->pic_state = lm32_pic_init(*cpu_irq);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(env->pic_state, i);
    }

    sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
    sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
    sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
    sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);

    /* make sure juart isn't the first chardev */
    env->juart_state = lm32_juart_init();

    reset_info->bootstrap_pc = flash_base;

    if (kernel_filename) {
        uint64_t entry;
        int kernel_size;

        kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
                               1, ELF_MACHINE, 0);
        reset_info->bootstrap_pc = entry;

        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename, ram_base,
                                              ram_size);
            reset_info->bootstrap_pc = ram_base;
        }

        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    }

    /* generate a rom with the hardware description */
    hw = hwsetup_init();
    hwsetup_add_cpu(hw, "LM32", 75000000);
    hwsetup_add_flash(hw, "flash", flash_base, flash_size);
    hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
    hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
    hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
    hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
    hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
    hwsetup_add_trailer(hw);
    hwsetup_create_rom(hw, hwsetup_base);
    hwsetup_free(hw);

    reset_info->hwsetup_base = hwsetup_base;

    if (kernel_cmdline && strlen(kernel_cmdline)) {
        pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
                kernel_cmdline);
        reset_info->cmdline_base = cmdline_base;
    }

    if (initrd_filename) {
        size_t initrd_size;
        initrd_size = load_image_targphys(initrd_filename, initrd_base,
                initrd_max);
        reset_info->initrd_base = initrd_base;
        reset_info->initrd_size = initrd_size;
    }

    qemu_register_reset(main_cpu_reset, reset_info);
}

static QEMUMachine lm32_evr_machine = {
    .name = "lm32-evr",
    .desc = "LatticeMico32 EVR32 eval system",
    .init = lm32_evr_init,
    .is_default = 1
};

static QEMUMachine lm32_uclinux_machine = {
    .name = "lm32-uclinux",
    .desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
    .init = lm32_uclinux_init,
    .is_default = 0
};

static void lm32_machine_init(void)
{
    qemu_register_machine(&lm32_uclinux_machine);
    qemu_register_machine(&lm32_evr_machine);
}

machine_init(lm32_machine_init);
Commit	Line	Data
d821732a MW	1	/*
	2	* QEMU models for LatticeMico32 uclinux and evr32 boards.
	3	*
	4	* Copyright (c) 2010 Michael Walle <michael@walle.cc>
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "sysbus.h"
	21	#include "hw.h"
d821732a	22	#include "flash.h"
d821732a MW	23	#include "devices.h"
	24	#include "boards.h"
	25	#include "loader.h"
9c17d615	26	#include "sysemu/blockdev.h"
d821732a MW	27	#include "elf.h"
	28	#include "lm32_hwsetup.h"
	29	#include "lm32.h"
022c62cb	30	#include "exec/address-spaces.h"
d821732a MW	31
d821732a MW	32	typedef struct {
b1435596	33	LM32CPU *cpu;
a8170e5e AK	34	hwaddr bootstrap_pc;
	35	hwaddr flash_base;
	36	hwaddr hwsetup_base;
	37	hwaddr initrd_base;
d821732a	38	size_t initrd_size;
a8170e5e	39	hwaddr cmdline_base;
d821732a MW	40	} ResetInfo;
	41
	42	static void cpu_irq_handler(void *opaque, int irq, int level)
	43	{
93a67402	44	CPULM32State *env = opaque;
d821732a MW	45
	46	if (level) {
	47	cpu_interrupt(env, CPU_INTERRUPT_HARD);
	48	} else {
	49	cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
	50	}
	51	}
	52
	53	static void main_cpu_reset(void *opaque)
	54	{
	55	ResetInfo *reset_info = opaque;
b1435596	56	CPULM32State *env = &reset_info->cpu->env;
d821732a	57
b1435596	58	cpu_reset(CPU(reset_info->cpu));
d821732a MW	59
	60	/* init defaults */
	61	env->pc = (uint32_t)reset_info->bootstrap_pc;
	62	env->regs[R_R1] = (uint32_t)reset_info->hwsetup_base;
	63	env->regs[R_R2] = (uint32_t)reset_info->cmdline_base;
	64	env->regs[R_R3] = (uint32_t)reset_info->initrd_base;
	65	env->regs[R_R4] = (uint32_t)(reset_info->initrd_base +
	66	reset_info->initrd_size);
	67	env->eba = reset_info->flash_base;
	68	env->deba = reset_info->flash_base;
	69	}
	70
5f072e1f	71	static void lm32_evr_init(QEMUMachineInitArgs *args)
d821732a	72	{
5f072e1f EH	73	const char *cpu_model = args->cpu_model;
5f072e1f EH	74	const char *kernel_filename = args->kernel_filename;
47dc4fa2	75	LM32CPU *cpu;
93a67402	76	CPULM32State *env;
d821732a	77	DriveInfo *dinfo;
88fa8031 AK	78	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	79	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d821732a MW	80	qemu_irq *cpu_irq, irq[32];
	81	ResetInfo *reset_info;
	82	int i;
	83
	84	/* memory map */
a8170e5e	85	hwaddr flash_base = 0x04000000;
d821732a MW	86	size_t flash_sector_size = 256 * 1024;
d821732a MW	87	size_t flash_size = 32 * 1024 * 1024;
a8170e5e	88	hwaddr ram_base = 0x08000000;
d821732a	89	size_t ram_size = 64 * 1024 * 1024;
a8170e5e AK	90	hwaddr timer0_base = 0x80002000;
	91	hwaddr uart0_base = 0x80006000;
	92	hwaddr timer1_base = 0x8000a000;
d821732a MW	93	int uart0_irq = 0;
	94	int timer0_irq = 1;
	95	int timer1_irq = 3;
	96
7267c094	97	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	98
	99	if (cpu_model == NULL) {
	100	cpu_model = "lm32-full";
	101	}
47dc4fa2 AF	102	cpu = cpu_lm32_init(cpu_model);
47dc4fa2 AF	103	env = &cpu->env;
b1435596	104	reset_info->cpu = cpu;
d821732a MW	105
	106	reset_info->flash_base = flash_base;
	107
c5705a77 AK	108	memory_region_init_ram(phys_ram, "lm32_evr.sdram", ram_size);
c5705a77 AK	109	vmstate_register_ram_global(phys_ram);
88fa8031	110	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	111
d821732a MW	112	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	113	/* Spansion S29NS128P */
cfe5f011	114	pflash_cfi02_register(flash_base, NULL, "lm32_evr.flash", flash_size,
d821732a MW	115	dinfo ? dinfo->bdrv : NULL, flash_sector_size,
d821732a MW	116	flash_size / flash_sector_size, 1, 2,
01e0451a	117	0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	118
	119	/* create irq lines */
	120	cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
	121	env->pic_state = lm32_pic_init(*cpu_irq);
	122	for (i = 0; i < 32; i++) {
	123	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	124	}
	125
	126	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
	127	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	128	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	129
	130	/* make sure juart isn't the first chardev */
	131	env->juart_state = lm32_juart_init();
	132
	133	reset_info->bootstrap_pc = flash_base;
	134
	135	if (kernel_filename) {
	136	uint64_t entry;
	137	int kernel_size;
	138
	139	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
	140	1, ELF_MACHINE, 0);
	141	reset_info->bootstrap_pc = entry;
	142
	143	if (kernel_size < 0) {
	144	kernel_size = load_image_targphys(kernel_filename, ram_base,
	145	ram_size);
	146	reset_info->bootstrap_pc = ram_base;
	147	}
	148
	149	if (kernel_size < 0) {
	150	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	151	kernel_filename);
	152	exit(1);
	153	}
	154	}
	155
	156	qemu_register_reset(main_cpu_reset, reset_info);
	157	}
	158
5f072e1f	159	static void lm32_uclinux_init(QEMUMachineInitArgs *args)
d821732a	160	{
5f072e1f EH	161	const char *cpu_model = args->cpu_model;
	162	const char *kernel_filename = args->kernel_filename;
	163	const char *kernel_cmdline = args->kernel_cmdline;
	164	const char *initrd_filename = args->initrd_filename;
47dc4fa2	165	LM32CPU *cpu;
93a67402	166	CPULM32State *env;
d821732a	167	DriveInfo *dinfo;
88fa8031 AK	168	MemoryRegion *address_space_mem = get_system_memory();
88fa8031 AK	169	MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
d821732a MW	170	qemu_irq *cpu_irq, irq[32];
	171	HWSetup *hw;
	172	ResetInfo *reset_info;
	173	int i;
	174
	175	/* memory map */
a8170e5e	176	hwaddr flash_base = 0x04000000;
d821732a MW	177	size_t flash_sector_size = 256 * 1024;
d821732a MW	178	size_t flash_size = 32 * 1024 * 1024;
a8170e5e	179	hwaddr ram_base = 0x08000000;
d821732a	180	size_t ram_size = 64 * 1024 * 1024;
a8170e5e AK	181	hwaddr uart0_base = 0x80000000;
	182	hwaddr timer0_base = 0x80002000;
	183	hwaddr timer1_base = 0x80010000;
	184	hwaddr timer2_base = 0x80012000;
d821732a MW	185	int uart0_irq = 0;
	186	int timer0_irq = 1;
	187	int timer1_irq = 20;
	188	int timer2_irq = 21;
a8170e5e AK	189	hwaddr hwsetup_base = 0x0bffe000;
	190	hwaddr cmdline_base = 0x0bfff000;
	191	hwaddr initrd_base = 0x08400000;
d821732a MW	192	size_t initrd_max = 0x01000000;
d821732a MW	193
7267c094	194	reset_info = g_malloc0(sizeof(ResetInfo));
d821732a MW	195
	196	if (cpu_model == NULL) {
	197	cpu_model = "lm32-full";
	198	}
47dc4fa2 AF	199	cpu = cpu_lm32_init(cpu_model);
47dc4fa2 AF	200	env = &cpu->env;
b1435596	201	reset_info->cpu = cpu;
d821732a MW	202
	203	reset_info->flash_base = flash_base;
	204
c5705a77 AK	205	memory_region_init_ram(phys_ram, "lm32_uclinux.sdram", ram_size);
c5705a77 AK	206	vmstate_register_ram_global(phys_ram);
88fa8031	207	memory_region_add_subregion(address_space_mem, ram_base, phys_ram);
d821732a	208
d821732a MW	209	dinfo = drive_get(IF_PFLASH, 0, 0);
d821732a MW	210	/* Spansion S29NS128P */
cfe5f011	211	pflash_cfi02_register(flash_base, NULL, "lm32_uclinux.flash", flash_size,
d821732a MW	212	dinfo ? dinfo->bdrv : NULL, flash_sector_size,
d821732a MW	213	flash_size / flash_sector_size, 1, 2,
01e0451a	214	0x01, 0x7e, 0x43, 0x00, 0x555, 0x2aa, 1);
d821732a MW	215
	216	/* create irq lines */
	217	cpu_irq = qemu_allocate_irqs(cpu_irq_handler, env, 1);
	218	env->pic_state = lm32_pic_init(*cpu_irq);
	219	for (i = 0; i < 32; i++) {
	220	irq[i] = qdev_get_gpio_in(env->pic_state, i);
	221	}
	222
	223	sysbus_create_simple("lm32-uart", uart0_base, irq[uart0_irq]);
	224	sysbus_create_simple("lm32-timer", timer0_base, irq[timer0_irq]);
	225	sysbus_create_simple("lm32-timer", timer1_base, irq[timer1_irq]);
	226	sysbus_create_simple("lm32-timer", timer2_base, irq[timer2_irq]);
	227
	228	/* make sure juart isn't the first chardev */
	229	env->juart_state = lm32_juart_init();
	230
	231	reset_info->bootstrap_pc = flash_base;
	232
	233	if (kernel_filename) {
	234	uint64_t entry;
	235	int kernel_size;
	236
	237	kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
	238	1, ELF_MACHINE, 0);
	239	reset_info->bootstrap_pc = entry;
	240
	241	if (kernel_size < 0) {
	242	kernel_size = load_image_targphys(kernel_filename, ram_base,
	243	ram_size);
	244	reset_info->bootstrap_pc = ram_base;
	245	}
	246
	247	if (kernel_size < 0) {
	248	fprintf(stderr, "qemu: could not load kernel '%s'\n",
	249	kernel_filename);
	250	exit(1);
	251	}
	252	}
	253
	254	/* generate a rom with the hardware description */
	255	hw = hwsetup_init();
	256	hwsetup_add_cpu(hw, "LM32", 75000000);
	257	hwsetup_add_flash(hw, "flash", flash_base, flash_size);
	258	hwsetup_add_ddr_sdram(hw, "ddr_sdram", ram_base, ram_size);
	259	hwsetup_add_timer(hw, "timer0", timer0_base, timer0_irq);
	260	hwsetup_add_timer(hw, "timer1_dev_only", timer1_base, timer1_irq);
	261	hwsetup_add_timer(hw, "timer2_dev_only", timer2_base, timer2_irq);
	262	hwsetup_add_uart(hw, "uart", uart0_base, uart0_irq);
	263	hwsetup_add_trailer(hw);
	264	hwsetup_create_rom(hw, hwsetup_base);
	265	hwsetup_free(hw);
	266
	267	reset_info->hwsetup_base = hwsetup_base;
	268
	269	if (kernel_cmdline && strlen(kernel_cmdline)) {
	270	pstrcpy_targphys("cmdline", cmdline_base, TARGET_PAGE_SIZE,
	271	kernel_cmdline);
	272	reset_info->cmdline_base = cmdline_base;
	273	}
	274
	275	if (initrd_filename) {
	276	size_t initrd_size;
	277	initrd_size = load_image_targphys(initrd_filename, initrd_base,
	278	initrd_max);
279	reset_info->initrd_base = initrd_base;
280	reset_info->initrd_size = initrd_size;
281	}
282
283	qemu_register_reset(main_cpu_reset, reset_info);
284	}
285
286	static QEMUMachine lm32_evr_machine = {
287	.name = "lm32-evr",
288	.desc = "LatticeMico32 EVR32 eval system",
289	.init = lm32_evr_init,
290	.is_default = 1
291	};
292
293	static QEMUMachine lm32_uclinux_machine = {
294	.name = "lm32-uclinux",
295	.desc = "lm32 platform for uClinux and u-boot by Theobroma Systems",
296	.init = lm32_uclinux_init,
297	.is_default = 0
298	};
299
300	static void lm32_machine_init(void)
301	{
302	qemu_register_machine(&lm32_uclinux_machine);
303	qemu_register_machine(&lm32_evr_machine);
304	}
305
306	machine_init(lm32_machine_init);