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1/*
2 * QEMU MIPS Jazz support
3 *
4 * Copyright (c) 2007-2008 Hervé Poussineau
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25#include "hw.h"
26#include "mips.h"
b970ea8f 27#include "mips_cpudevs.h"
4ce7ff6e 28#include "pc.h"
488cb996 29#include "serial.h"
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30#include "isa.h"
31#include "fdc.h"
32#include "sysemu.h"
0dfa5ef9 33#include "arch_init.h"
4ce7ff6e 34#include "boards.h"
1422e32d 35#include "net/net.h"
1cd3af54 36#include "esp.h"
bba831e8 37#include "mips-bios.h"
ca20cf32 38#include "loader.h"
1d914fa0 39#include "mc146818rtc.h"
b1277b03 40#include "i8254.h"
302fe51b 41#include "pcspk.h"
2446333c 42#include "blockdev.h"
cd3e2409 43#include "sysbus.h"
be20f9e9 44#include "exec-memory.h"
4ce7ff6e 45
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46enum jazz_model_e
47{
48 JAZZ_MAGNUM,
c171148c 49 JAZZ_PICA61,
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50};
51
52static void main_cpu_reset(void *opaque)
53{
f37f435a
AF
54 MIPSCPU *cpu = opaque;
55
56 cpu_reset(CPU(cpu));
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57}
58
a8170e5e 59static uint64_t rtc_read(void *opaque, hwaddr addr, unsigned size)
4ce7ff6e 60{
afcea8cb 61 return cpu_inw(0x71);
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62}
63
a8170e5e 64static void rtc_write(void *opaque, hwaddr addr,
60581b37 65 uint64_t val, unsigned size)
4ce7ff6e 66{
afcea8cb 67 cpu_outw(0x71, val & 0xff);
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68}
69
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70static const MemoryRegionOps rtc_ops = {
71 .read = rtc_read,
72 .write = rtc_write,
73 .endianness = DEVICE_NATIVE_ENDIAN,
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74};
75
a8170e5e 76static uint64_t dma_dummy_read(void *opaque, hwaddr addr,
60581b37 77 unsigned size)
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78{
79 /* Nothing to do. That is only to ensure that
80 * the current DMA acknowledge cycle is completed. */
60581b37 81 return 0xff;
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82}
83
a8170e5e 84static void dma_dummy_write(void *opaque, hwaddr addr,
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85 uint64_t val, unsigned size)
86{
87 /* Nothing to do. That is only to ensure that
88 * the current DMA acknowledge cycle is completed. */
89}
c6945b15 90
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91static const MemoryRegionOps dma_dummy_ops = {
92 .read = dma_dummy_read,
93 .write = dma_dummy_write,
94 .endianness = DEVICE_NATIVE_ENDIAN,
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95};
96
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97#define MAGNUM_BIOS_SIZE_MAX 0x7e000
98#define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX)
99
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BS
100static void cpu_request_exit(void *opaque, int irq, int level)
101{
61c56c8c 102 CPUMIPSState *env = cpu_single_env;
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103
104 if (env && level) {
105 cpu_exit(env);
106 }
107}
108
c2d0d012
RH
109static void mips_jazz_init(MemoryRegion *address_space,
110 MemoryRegion *address_space_io,
111 ram_addr_t ram_size,
112 const char *cpu_model,
113 enum jazz_model_e jazz_model)
4ce7ff6e 114{
5cea8590 115 char *filename;
4ce7ff6e 116 int bios_size, n;
6bd8da65 117 MIPSCPU *cpu;
61c56c8c 118 CPUMIPSState *env;
4ce7ff6e 119 qemu_irq *rc4030, *i8259;
c6945b15 120 rc4030_dma *dmas;
68238a9e 121 void* rc4030_opaque;
60581b37 122 MemoryRegion *rtc = g_new(MemoryRegion, 1);
dbff76ac 123 MemoryRegion *i8042 = g_new(MemoryRegion, 1);
60581b37 124 MemoryRegion *dma_dummy = g_new(MemoryRegion, 1);
a65f56ee 125 NICInfo *nd;
cd3e2409
HP
126 DeviceState *dev;
127 SysBusDevice *sysbus;
48a18b3c 128 ISABus *isa_bus;
64d7e9a4 129 ISADevice *pit;
fd8014e1 130 DriveInfo *fds[MAX_FD];
73d74342 131 qemu_irq esp_reset, dma_enable;
4556bd8b 132 qemu_irq *cpu_exit_irq;
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133 MemoryRegion *ram = g_new(MemoryRegion, 1);
134 MemoryRegion *bios = g_new(MemoryRegion, 1);
135 MemoryRegion *bios2 = g_new(MemoryRegion, 1);
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136
137 /* init CPUs */
138 if (cpu_model == NULL) {
139#ifdef TARGET_MIPS64
140 cpu_model = "R4000";
141#else
142 /* FIXME: All wrong, this maybe should be R3000 for the older JAZZs. */
143 cpu_model = "24Kf";
144#endif
145 }
6bd8da65
AF
146 cpu = cpu_mips_init(cpu_model);
147 if (cpu == NULL) {
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148 fprintf(stderr, "Unable to find CPU definition\n");
149 exit(1);
150 }
6bd8da65 151 env = &cpu->env;
f37f435a 152 qemu_register_reset(main_cpu_reset, cpu);
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153
154 /* allocate RAM */
c5705a77
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155 memory_region_init_ram(ram, "mips_jazz.ram", ram_size);
156 vmstate_register_ram_global(ram);
60581b37 157 memory_region_add_subregion(address_space, 0, ram);
dcac9679 158
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159 memory_region_init_ram(bios, "mips_jazz.bios", MAGNUM_BIOS_SIZE);
160 vmstate_register_ram_global(bios);
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161 memory_region_set_readonly(bios, true);
162 memory_region_init_alias(bios2, "mips_jazz.bios", bios,
163 0, MAGNUM_BIOS_SIZE);
164 memory_region_add_subregion(address_space, 0x1fc00000LL, bios);
165 memory_region_add_subregion(address_space, 0xfff00000LL, bios2);
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166
167 /* load the BIOS image. */
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168 if (bios_name == NULL)
169 bios_name = BIOS_FILENAME;
5cea8590
PB
170 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
171 if (filename) {
172 bios_size = load_image_targphys(filename, 0xfff00000LL,
173 MAGNUM_BIOS_SIZE);
7267c094 174 g_free(filename);
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PB
175 } else {
176 bios_size = -1;
177 }
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178 if (bios_size < 0 || bios_size > MAGNUM_BIOS_SIZE) {
179 fprintf(stderr, "qemu: Could not load MIPS bios '%s'\n",
5cea8590 180 bios_name);
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181 exit(1);
182 }
183
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184 /* Init CPU internal devices */
185 cpu_mips_irq_init_cpu(env);
186 cpu_mips_clock_init(env);
187
188 /* Chipset */
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189 rc4030_opaque = rc4030_init(env->irq[6], env->irq[3], &rc4030, &dmas,
190 address_space);
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191 memory_region_init_io(dma_dummy, &dma_dummy_ops, NULL, "dummy_dma", 0x1000);
192 memory_region_add_subregion(address_space, 0x8000d000, dma_dummy);
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193
194 /* ISA devices */
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HP
195 isa_bus = isa_bus_new(NULL, address_space_io);
196 i8259 = i8259_init(isa_bus, env->irq[4]);
197 isa_bus_irqs(isa_bus, i8259);
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BS
198 cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
199 DMA_init(0, cpu_exit_irq);
319ba9f5 200 pit = pit_init(isa_bus, 0x40, 0, NULL);
302fe51b 201 pcspk_init(isa_bus, pit);
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202
203 /* ISA IO space at 0x90000000 */
968d683c 204 isa_mmio_init(0x90000000, 0x01000000);
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205 isa_mem_base = 0x11000000;
206
207 /* Video card */
208 switch (jazz_model) {
209 case JAZZ_MAGNUM:
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HP
210 dev = qdev_create(NULL, "sysbus-g364");
211 qdev_init_nofail(dev);
212 sysbus = sysbus_from_qdev(dev);
213 sysbus_mmio_map(sysbus, 0, 0x60080000);
214 sysbus_mmio_map(sysbus, 1, 0x40000000);
215 sysbus_connect_irq(sysbus, 0, rc4030[3]);
216 {
217 /* Simple ROM, so user doesn't have to provide one */
60581b37 218 MemoryRegion *rom_mr = g_new(MemoryRegion, 1);
c5705a77
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219 memory_region_init_ram(rom_mr, "g364fb.rom", 0x80000);
220 vmstate_register_ram_global(rom_mr);
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221 memory_region_set_readonly(rom_mr, true);
222 uint8_t *rom = memory_region_get_ram_ptr(rom_mr);
223 memory_region_add_subregion(address_space, 0x60000000, rom_mr);
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HP
224 rom[0] = 0x10; /* Mips G364 */
225 }
4ce7ff6e 226 break;
c171148c 227 case JAZZ_PICA61:
be20f9e9 228 isa_vga_mm_init(0x40000000, 0x60000000, 0, get_system_memory());
c171148c 229 break;
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230 default:
231 break;
232 }
233
234 /* Network controller */
a65f56ee
AJ
235 for (n = 0; n < nb_nics; n++) {
236 nd = &nd_table[n];
237 if (!nd->model)
7267c094 238 nd->model = g_strdup("dp83932");
a65f56ee 239 if (strcmp(nd->model, "dp83932") == 0) {
024e5bb6 240 dp83932_init(nd, 0x80001000, 2, get_system_memory(), rc4030[4],
a65f56ee
AJ
241 rc4030_opaque, rc4030_dma_memory_rw);
242 break;
c8057f95 243 } else if (is_help_option(nd->model)) {
a65f56ee
AJ
244 fprintf(stderr, "qemu: Supported NICs: dp83932\n");
245 exit(1);
246 } else {
247 fprintf(stderr, "qemu: Unsupported NIC: %s\n", nd->model);
248 exit(1);
249 }
250 }
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251
252 /* SCSI adapter */
cfb9de9c
PB
253 esp_init(0x80002000, 0,
254 rc4030_dma_read, rc4030_dma_write, dmas[0],
73d74342 255 rc4030[5], &esp_reset, &dma_enable);
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256
257 /* Floppy */
258 if (drive_get_max_bus(IF_FLOPPY) >= MAX_FD) {
259 fprintf(stderr, "qemu: too many floppy drives\n");
260 exit(1);
261 }
262 for (n = 0; n < MAX_FD; n++) {
fd8014e1 263 fds[n] = drive_get(IF_FLOPPY, 0, n);
4ce7ff6e 264 }
2091ba23 265 fdctrl_init_sysbus(rc4030[1], 0, 0x80003000, fds);
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266
267 /* Real time clock */
48a18b3c 268 rtc_init(isa_bus, 1980, NULL);
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269 memory_region_init_io(rtc, &rtc_ops, NULL, "rtc", 0x1000);
270 memory_region_add_subregion(address_space, 0x80004000, rtc);
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271
272 /* Keyboard (i8042) */
dbff76ac
RH
273 i8042_mm_init(rc4030[6], rc4030[7], i8042, 0x1000, 0x1);
274 memory_region_add_subregion(address_space, 0x80005000, i8042);
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275
276 /* Serial ports */
2d48377a 277 if (serial_hds[0]) {
39186d8a
RH
278 serial_mm_init(address_space, 0x80006000, 0, rc4030[8], 8000000/16,
279 serial_hds[0], DEVICE_NATIVE_ENDIAN);
2d48377a
BS
280 }
281 if (serial_hds[1]) {
39186d8a
RH
282 serial_mm_init(address_space, 0x80007000, 0, rc4030[9], 8000000/16,
283 serial_hds[1], DEVICE_NATIVE_ENDIAN);
2d48377a 284 }
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285
286 /* Parallel port */
287 if (parallel_hds[0])
63858cd9
AK
288 parallel_mm_init(address_space, 0x80008000, 0, rc4030[0],
289 parallel_hds[0]);
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290
291 /* Sound card */
292 /* FIXME: missing Jazz sound at 0x8000c000, rc4030[2] */
4a0f031d 293 audio_init(isa_bus, NULL);
4ce7ff6e 294
cd3e2409
HP
295 /* NVRAM */
296 dev = qdev_create(NULL, "ds1225y");
297 qdev_init_nofail(dev);
298 sysbus = sysbus_from_qdev(dev);
299 sysbus_mmio_map(sysbus, 0, 0x80009000);
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300
301 /* LED indicator */
b39506e4 302 sysbus_create_simple("jazz-led", 0x8000f000, NULL);
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303}
304
305static
5f072e1f 306void mips_magnum_init(QEMUMachineInitArgs *args)
4ce7ff6e 307{
5f072e1f
EH
308 ram_addr_t ram_size = args->ram_size;
309 const char *cpu_model = args->cpu_model;
c2d0d012
RH
310 mips_jazz_init(get_system_memory(), get_system_io(),
311 ram_size, cpu_model, JAZZ_MAGNUM);
4ce7ff6e
AJ
312}
313
c171148c 314static
5f072e1f 315void mips_pica61_init(QEMUMachineInitArgs *args)
c171148c 316{
5f072e1f
EH
317 ram_addr_t ram_size = args->ram_size;
318 const char *cpu_model = args->cpu_model;
c2d0d012
RH
319 mips_jazz_init(get_system_memory(), get_system_io(),
320 ram_size, cpu_model, JAZZ_PICA61);
c171148c
AJ
321}
322
f80f9ec9 323static QEMUMachine mips_magnum_machine = {
eec2743e
TS
324 .name = "magnum",
325 .desc = "MIPS Magnum",
326 .init = mips_magnum_init,
2d0d2837 327 .block_default_type = IF_SCSI,
4ce7ff6e 328};
c171148c 329
f80f9ec9 330static QEMUMachine mips_pica61_machine = {
eec2743e
TS
331 .name = "pica61",
332 .desc = "Acer Pica 61",
333 .init = mips_pica61_init,
2d0d2837 334 .block_default_type = IF_SCSI,
c171148c 335};
f80f9ec9
AL
336
337static void mips_jazz_machine_init(void)
338{
339 qemu_register_machine(&mips_magnum_machine);
340 qemu_register_machine(&mips_pica61_machine);
341}
342
343machine_init(mips_jazz_machine_init);