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3cbee15b
JM
1/*
2 * PowerMac MacIO device emulation
3 *
4 * Copyright (c) 2005-2007 Fabrice Bellard
5 * Copyright (c) 2007 Jocelyn Mayer
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
83c9f4ca
PB
25#include "hw/hw.h"
26#include "hw/ppc/mac.h"
27#include "hw/pci/pci.h"
0d09e41a
PB
28#include "hw/ppc/mac_dbdma.h"
29#include "hw/char/escc.h"
3cbee15b 30
fcf1bbab
AF
31#define TYPE_MACIO "macio"
32#define MACIO(obj) OBJECT_CHECK(MacIOState, (obj), TYPE_MACIO)
33
d8c51b05
AL
34typedef struct MacIOState
35{
fcf1bbab 36 /*< private >*/
d8c51b05 37 PCIDevice parent;
fcf1bbab
AF
38 /*< public >*/
39
23c5e4ca 40 MemoryRegion bar;
45fa67fb 41 CUDAState cuda;
07a7484e 42 void *dbdma;
23c5e4ca 43 MemoryRegion *pic_mem;
23c5e4ca 44 MemoryRegion *escc_mem;
d8c51b05 45} MacIOState;
3cbee15b 46
95ed3b7c
AF
47#define OLDWORLD_MACIO(obj) \
48 OBJECT_CHECK(OldWorldMacIOState, (obj), TYPE_OLDWORLD_MACIO)
49
50typedef struct OldWorldMacIOState {
51 /*< private >*/
52 MacIOState parent_obj;
53 /*< public >*/
54
14eefd0e 55 qemu_irq irqs[5];
07a7484e 56
95ed3b7c 57 MacIONVRAMState nvram;
14eefd0e 58 MACIOIDEState ide[2];
95ed3b7c
AF
59} OldWorldMacIOState;
60
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AF
61#define NEWWORLD_MACIO(obj) \
62 OBJECT_CHECK(NewWorldMacIOState, (obj), TYPE_NEWWORLD_MACIO)
63
64typedef struct NewWorldMacIOState {
65 /*< private >*/
66 MacIOState parent_obj;
67 /*< public >*/
45fa67fb 68 qemu_irq irqs[5];
07a7484e
AF
69 MACIOIDEState ide[2];
70} NewWorldMacIOState;
71
0d54a502
AG
72/*
73 * The mac-io has two interfaces to the ESCC. One is called "escc-legacy",
74 * while the other one is the normal, current ESCC interface.
75 *
76 * The magic below creates memory aliases to spawn the escc-legacy device
77 * purely by rerouting the respective registers to our escc region. This
78 * works because the only difference between the two memory regions is the
79 * register layout, not their semantics.
80 *
81 * Reference: ftp://ftp.software.ibm.com/rs6000/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
82 */
83static void macio_escc_legacy_setup(MacIOState *macio_state)
84{
85 MemoryRegion *escc_legacy = g_new(MemoryRegion, 1);
86 MemoryRegion *bar = &macio_state->bar;
87 int i;
88 static const int maps[] = {
89 0x00, 0x00,
90 0x02, 0x20,
91 0x04, 0x10,
92 0x06, 0x30,
93 0x08, 0x40,
94 0x0A, 0x50,
95 0x60, 0x60,
96 0x70, 0x70,
97 0x80, 0x70,
98 0x90, 0x80,
99 0xA0, 0x90,
100 0xB0, 0xA0,
101 0xC0, 0xB0,
102 0xD0, 0xC0,
103 0xE0, 0xD0,
104 0xF0, 0xE0,
105 };
106
2c9b15ca 107 memory_region_init(escc_legacy, NULL, "escc-legacy", 256);
0d54a502
AG
108 for (i = 0; i < ARRAY_SIZE(maps); i += 2) {
109 MemoryRegion *port = g_new(MemoryRegion, 1);
2c9b15ca
PB
110 memory_region_init_alias(port, NULL, "escc-legacy-port",
111 macio_state->escc_mem, maps[i+1], 0x2);
0d54a502
AG
112 memory_region_add_subregion(escc_legacy, maps[i], port);
113 }
114
115 memory_region_add_subregion(bar, 0x12000, escc_legacy);
116}
117
d8c51b05 118static void macio_bar_setup(MacIOState *macio_state)
3cbee15b 119{
23c5e4ca 120 MemoryRegion *bar = &macio_state->bar;
3cbee15b 121
23c5e4ca
AK
122 if (macio_state->escc_mem) {
123 memory_region_add_subregion(bar, 0x13000, macio_state->escc_mem);
0d54a502 124 macio_escc_legacy_setup(macio_state);
7fa9ae1a 125 }
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JM
126}
127
d037834a 128static int macio_common_initfn(PCIDevice *d)
d8c51b05 129{
7b925079 130 MacIOState *s = MACIO(d);
45fa67fb
AF
131 SysBusDevice *sysbus_dev;
132 int ret;
7b925079 133
d8c51b05 134 d->config[0x3d] = 0x01; // interrupt on pin 1
7b925079 135
45fa67fb
AF
136 ret = qdev_init(DEVICE(&s->cuda));
137 if (ret < 0) {
138 return ret;
139 }
140 sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
141 memory_region_add_subregion(&s->bar, 0x16000,
142 sysbus_mmio_get_region(sysbus_dev, 0));
143
7b925079
AF
144 macio_bar_setup(s);
145 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar);
146
d8c51b05
AL
147 return 0;
148}
149
14eefd0e
AG
150static int macio_initfn_ide(MacIOState *s, MACIOIDEState *ide, qemu_irq irq0,
151 qemu_irq irq1, int dmaid)
152{
153 SysBusDevice *sysbus_dev;
154
155 sysbus_dev = SYS_BUS_DEVICE(ide);
156 sysbus_connect_irq(sysbus_dev, 0, irq0);
157 sysbus_connect_irq(sysbus_dev, 1, irq1);
158 macio_ide_register_dma(ide, s->dbdma, dmaid);
159 return qdev_init(DEVICE(ide));
160}
161
d037834a
AF
162static int macio_oldworld_initfn(PCIDevice *d)
163{
164 MacIOState *s = MACIO(d);
95ed3b7c
AF
165 OldWorldMacIOState *os = OLDWORLD_MACIO(d);
166 SysBusDevice *sysbus_dev;
14eefd0e
AG
167 int i;
168 int cur_irq = 0;
d037834a
AF
169 int ret = macio_common_initfn(d);
170 if (ret < 0) {
171 return ret;
172 }
173
45fa67fb 174 sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
14eefd0e 175 sysbus_connect_irq(sysbus_dev, 0, os->irqs[cur_irq++]);
45fa67fb 176
95ed3b7c
AF
177 ret = qdev_init(DEVICE(&os->nvram));
178 if (ret < 0) {
179 return ret;
180 }
181 sysbus_dev = SYS_BUS_DEVICE(&os->nvram);
182 memory_region_add_subregion(&s->bar, 0x60000,
183 sysbus_mmio_get_region(sysbus_dev, 0));
184 pmac_format_nvram_partition(&os->nvram, os->nvram.size);
185
d037834a
AF
186 if (s->pic_mem) {
187 /* Heathrow PIC */
188 memory_region_add_subregion(&s->bar, 0x00000, s->pic_mem);
189 }
190
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AG
191 /* IDE buses */
192 for (i = 0; i < ARRAY_SIZE(os->ide); i++) {
193 qemu_irq irq0 = os->irqs[cur_irq++];
194 qemu_irq irq1 = os->irqs[cur_irq++];
195
196 ret = macio_initfn_ide(s, &os->ide[i], irq0, irq1, 0x16 + (i * 4));
197 if (ret < 0) {
198 return ret;
199 }
07a7484e
AF
200 }
201
d037834a
AF
202 return 0;
203}
204
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AG
205static void macio_init_ide(MacIOState *s, MACIOIDEState *ide, int index)
206{
207 gchar *name;
208
209 object_initialize(ide, TYPE_MACIO_IDE);
210 qdev_set_parent_bus(DEVICE(ide), sysbus_get_default());
211 memory_region_add_subregion(&s->bar, 0x1f000 + ((index + 1) * 0x1000),
212 &ide->mem);
213 name = g_strdup_printf("ide[%i]", index);
214 object_property_add_child(OBJECT(s), name, OBJECT(ide), NULL);
215 g_free(name);
216}
217
95ed3b7c
AF
218static void macio_oldworld_init(Object *obj)
219{
07a7484e 220 MacIOState *s = MACIO(obj);
95ed3b7c
AF
221 OldWorldMacIOState *os = OLDWORLD_MACIO(obj);
222 DeviceState *dev;
14eefd0e 223 int i;
95ed3b7c 224
07a7484e
AF
225 qdev_init_gpio_out(DEVICE(obj), os->irqs, ARRAY_SIZE(os->irqs));
226
95ed3b7c
AF
227 object_initialize(&os->nvram, TYPE_MACIO_NVRAM);
228 dev = DEVICE(&os->nvram);
229 qdev_prop_set_uint32(dev, "size", 0x2000);
230 qdev_prop_set_uint32(dev, "it_shift", 4);
07a7484e 231
14eefd0e
AG
232 for (i = 0; i < 2; i++) {
233 macio_init_ide(s, &os->ide[i], i);
234 }
95ed3b7c
AF
235}
236
a0f9fdfd
AG
237static void timer_write(void *opaque, hwaddr addr, uint64_t value,
238 unsigned size)
239{
240}
241
242static uint64_t timer_read(void *opaque, hwaddr addr, unsigned size)
243{
244 uint32_t value = 0;
245
246 switch (addr) {
247 case 0x38:
bc72ad67 248 value = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
a0f9fdfd
AG
249 break;
250 case 0x3c:
bc72ad67 251 value = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) >> 32;
a0f9fdfd
AG
252 break;
253 }
254
255 return value;
256}
257
258static const MemoryRegionOps timer_ops = {
259 .read = timer_read,
260 .write = timer_write,
261 .endianness = DEVICE_NATIVE_ENDIAN,
262};
263
d037834a
AF
264static int macio_newworld_initfn(PCIDevice *d)
265{
266 MacIOState *s = MACIO(d);
07a7484e
AF
267 NewWorldMacIOState *ns = NEWWORLD_MACIO(d);
268 SysBusDevice *sysbus_dev;
a0f9fdfd 269 MemoryRegion *timer_memory = g_new(MemoryRegion, 1);
14eefd0e
AG
270 int i;
271 int cur_irq = 0;
d037834a
AF
272 int ret = macio_common_initfn(d);
273 if (ret < 0) {
274 return ret;
275 }
276
45fa67fb 277 sysbus_dev = SYS_BUS_DEVICE(&s->cuda);
14eefd0e 278 sysbus_connect_irq(sysbus_dev, 0, ns->irqs[cur_irq++]);
45fa67fb 279
d037834a
AF
280 if (s->pic_mem) {
281 /* OpenPIC */
282 memory_region_add_subregion(&s->bar, 0x40000, s->pic_mem);
283 }
284
14eefd0e
AG
285 /* IDE buses */
286 for (i = 0; i < ARRAY_SIZE(ns->ide); i++) {
287 qemu_irq irq0 = ns->irqs[cur_irq++];
288 qemu_irq irq1 = ns->irqs[cur_irq++];
07a7484e 289
14eefd0e
AG
290 ret = macio_initfn_ide(s, &ns->ide[i], irq0, irq1, 0x16 + (i * 4));
291 if (ret < 0) {
292 return ret;
293 }
07a7484e
AF
294 }
295
a0f9fdfd
AG
296 /* Timer */
297 memory_region_init_io(timer_memory, OBJECT(s), &timer_ops, NULL, "timer",
298 0x1000);
299 memory_region_add_subregion(&s->bar, 0x15000, timer_memory);
300
d037834a
AF
301 return 0;
302}
303
07a7484e
AF
304static void macio_newworld_init(Object *obj)
305{
306 MacIOState *s = MACIO(obj);
307 NewWorldMacIOState *ns = NEWWORLD_MACIO(obj);
308 int i;
07a7484e
AF
309
310 qdev_init_gpio_out(DEVICE(obj), ns->irqs, ARRAY_SIZE(ns->irqs));
311
312 for (i = 0; i < 2; i++) {
14eefd0e 313 macio_init_ide(s, &ns->ide[i], i);
07a7484e
AF
314 }
315}
316
fcf1bbab
AF
317static void macio_instance_init(Object *obj)
318{
319 MacIOState *s = MACIO(obj);
07a7484e 320 MemoryRegion *dbdma_mem;
fcf1bbab 321
2c9b15ca 322 memory_region_init(&s->bar, NULL, "macio", 0x80000);
07a7484e 323
45fa67fb
AF
324 object_initialize(&s->cuda, TYPE_CUDA);
325 qdev_set_parent_bus(DEVICE(&s->cuda), sysbus_get_default());
326 object_property_add_child(obj, "cuda", OBJECT(&s->cuda), NULL);
327
07a7484e
AF
328 s->dbdma = DBDMA_init(&dbdma_mem);
329 memory_region_add_subregion(&s->bar, 0x08000, dbdma_mem);
fcf1bbab
AF
330}
331
d037834a
AF
332static void macio_oldworld_class_init(ObjectClass *oc, void *data)
333{
334 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc);
335
336 pdc->init = macio_oldworld_initfn;
337 pdc->device_id = PCI_DEVICE_ID_APPLE_343S1201;
338}
339
340static void macio_newworld_class_init(ObjectClass *oc, void *data)
341{
342 PCIDeviceClass *pdc = PCI_DEVICE_CLASS(oc);
343
344 pdc->init = macio_newworld_initfn;
345 pdc->device_id = PCI_DEVICE_ID_APPLE_UNI_N_KEYL;
346}
347
40021f08
AL
348static void macio_class_init(ObjectClass *klass, void *data)
349{
350 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
351
40021f08
AL
352 k->vendor_id = PCI_VENDOR_ID_APPLE;
353 k->class_id = PCI_CLASS_OTHERS << 8;
354}
355
d037834a
AF
356static const TypeInfo macio_oldworld_type_info = {
357 .name = TYPE_OLDWORLD_MACIO,
358 .parent = TYPE_MACIO,
95ed3b7c
AF
359 .instance_size = sizeof(OldWorldMacIOState),
360 .instance_init = macio_oldworld_init,
d037834a
AF
361 .class_init = macio_oldworld_class_init,
362};
363
364static const TypeInfo macio_newworld_type_info = {
365 .name = TYPE_NEWWORLD_MACIO,
366 .parent = TYPE_MACIO,
07a7484e
AF
367 .instance_size = sizeof(NewWorldMacIOState),
368 .instance_init = macio_newworld_init,
d037834a
AF
369 .class_init = macio_newworld_class_init,
370};
371
fcf1bbab
AF
372static const TypeInfo macio_type_info = {
373 .name = TYPE_MACIO,
39bffca2
AL
374 .parent = TYPE_PCI_DEVICE,
375 .instance_size = sizeof(MacIOState),
fcf1bbab 376 .instance_init = macio_instance_init,
d037834a 377 .abstract = true,
39bffca2 378 .class_init = macio_class_init,
d8c51b05
AL
379};
380
83f7d43a 381static void macio_register_types(void)
d8c51b05 382{
fcf1bbab 383 type_register_static(&macio_type_info);
d037834a
AF
384 type_register_static(&macio_oldworld_type_info);
385 type_register_static(&macio_newworld_type_info);
d8c51b05
AL
386}
387
83f7d43a 388type_init(macio_register_types)
d8c51b05 389
d037834a 390void macio_init(PCIDevice *d,
07a7484e 391 MemoryRegion *pic_mem,
d037834a 392 MemoryRegion *escc_mem)
3cbee15b 393{
d037834a 394 MacIOState *macio_state = MACIO(d);
3cbee15b 395
23c5e4ca 396 macio_state->pic_mem = pic_mem;
23c5e4ca 397 macio_state->escc_mem = escc_mem;
3cbee15b
JM
398 /* Note: this code is strongly inspirated from the corresponding code
399 in PearPC */
deb54399 400
7b925079 401 qdev_init_nofail(DEVICE(d));
3cbee15b 402}