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added PCI bus - added IRQ support for PowerPC bridges - suppressed PREP PCI bios...
[qemu.git] / hw / pci.c
CommitLineData
69b91039
FB		 1/*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#include "vl.h"
25
26//#define DEBUG_PCI
27
0ac32c83
FB		 28#define PCI_VENDOR_ID 0x00 /* 16 bits */
29#define PCI_DEVICE_ID 0x02 /* 16 bits */
30#define PCI_COMMAND 0x04 /* 16 bits */
31#define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
32#define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
33#define PCI_CLASS_DEVICE 0x0a /* Device class */
34#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
35#define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
36#define PCI_MIN_GNT 0x3e /* 8 bits */
37#define PCI_MAX_LAT 0x3f /* 8 bits */
38
39/* just used for simpler irq handling. */
40#define PCI_DEVICES_MAX 64
41#define PCI_IRQ_WORDS ((PCI_DEVICES_MAX + 31) / 32)
42
30468f78
FB		 43struct PCIBus {
44 int bus_num;
45 int devfn_min;
46 void (*set_irq)(PCIDevice *pci_dev, int irq_num, int level);
47 uint32_t config_reg; /* XXX: suppress */
48 openpic_t *openpic; /* XXX: suppress */
49 PCIDevice *devices[256];
50};
69b91039 51
69b91039 52target_phys_addr_t pci_mem_base;
0ac32c83
FB		 53static int pci_irq_index;
54static uint32_t pci_irq_levels[4][PCI_IRQ_WORDS];
30468f78
FB		 55static PCIBus *first_bus;
56
57static PCIBus *pci_register_bus(void)
58{
59 PCIBus *bus;
60 bus = qemu_mallocz(sizeof(PCIBus));
61 first_bus = bus;
62 return bus;
63}
69b91039
FB		 64
65/* -1 for devfn means auto assign */
30468f78
FB		 66PCIDevice *pci_register_device(PCIBus *bus, const char *name,
67 int instance_size, int devfn,
69b91039
FB		 68 PCIConfigReadFunc *config_read,
69 PCIConfigWriteFunc *config_write)
70{
30468f78 71 PCIDevice *pci_dev;
69b91039 72
0ac32c83
FB		 73 if (pci_irq_index >= PCI_DEVICES_MAX)
74 return NULL;
75
69b91039 76 if (devfn < 0) {
30468f78
FB		 77 for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
78 if (!bus->devices[devfn])
69b91039
FB		 79 goto found;
80 }
81 return NULL;
82 found: ;
83 }
84 pci_dev = qemu_mallocz(instance_size);
85 if (!pci_dev)
86 return NULL;
30468f78 87 pci_dev->bus = bus;
69b91039
FB		 88 pci_dev->devfn = devfn;
89 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
0ac32c83
FB		 90
91 if (!config_read)
92 config_read = pci_default_read_config;
93 if (!config_write)
94 config_write = pci_default_write_config;
69b91039
FB		 95 pci_dev->config_read = config_read;
96 pci_dev->config_write = config_write;
0ac32c83 97 pci_dev->irq_index = pci_irq_index++;
30468f78 98 bus->devices[devfn] = pci_dev;
69b91039
FB		 99 return pci_dev;
100}
101
102void pci_register_io_region(PCIDevice *pci_dev, int region_num,
103 uint32_t size, int type,
104 PCIMapIORegionFunc *map_func)
105{
106 PCIIORegion *r;
107
8a8696a3 108 if ((unsigned int)region_num >= PCI_NUM_REGIONS)
69b91039
FB		 109 return;
110 r = &pci_dev->io_regions[region_num];
111 r->addr = -1;
112 r->size = size;
113 r->type = type;
114 r->map_func = map_func;
115}
116
0ac32c83 117static void pci_addr_writel(void* opaque, uint32_t addr, uint32_t val)
69b91039 118{
30468f78 119 PCIBus *s = opaque;
69b91039
FB		 120 s->config_reg = val;
121}
122
0ac32c83 123static uint32_t pci_addr_readl(void* opaque, uint32_t addr)
69b91039 124{
30468f78 125 PCIBus *s = opaque;
69b91039
FB		 126 return s->config_reg;
127}
128
0ac32c83
FB		 129static void pci_update_mappings(PCIDevice *d)
130{
131 PCIIORegion *r;
132 int cmd, i;
8a8696a3 133 uint32_t last_addr, new_addr, config_ofs;
0ac32c83
FB		 134
135 cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
8a8696a3 136 for(i = 0; i < PCI_NUM_REGIONS; i++) {
0ac32c83 137 r = &d->io_regions[i];
8a8696a3
FB		 138 if (i == PCI_ROM_SLOT) {
139 config_ofs = 0x30;
140 } else {
141 config_ofs = 0x10 + i * 4;
142 }
0ac32c83
FB		 143 if (r->size != 0) {
144 if (r->type & PCI_ADDRESS_SPACE_IO) {
145 if (cmd & PCI_COMMAND_IO) {
146 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
8a8696a3 147 config_ofs));
0ac32c83
FB		 148 new_addr = new_addr & ~(r->size - 1);
149 last_addr = new_addr + r->size - 1;
150 /* NOTE: we have only 64K ioports on PC */
151 if (last_addr <= new_addr || new_addr == 0 ||
152 last_addr >= 0x10000) {
153 new_addr = -1;
154 }
155 } else {
156 new_addr = -1;
157 }
158 } else {
159 if (cmd & PCI_COMMAND_MEMORY) {
160 new_addr = le32_to_cpu(*(uint32_t *)(d->config +
8a8696a3
FB		 161 config_ofs));
162 /* the ROM slot has a specific enable bit */
163 if (i == PCI_ROM_SLOT && !(new_addr & 1))
164 goto no_mem_map;
0ac32c83
FB		 165 new_addr = new_addr & ~(r->size - 1);
166 last_addr = new_addr + r->size - 1;
167 /* NOTE: we do not support wrapping */
168 /* XXX: as we cannot support really dynamic
169 mappings, we handle specific values as invalid
170 mappings. */
171 if (last_addr <= new_addr || new_addr == 0 ||
172 last_addr == -1) {
173 new_addr = -1;
174 }
175 } else {
8a8696a3 176 no_mem_map:
0ac32c83
FB		 177 new_addr = -1;
178 }
179 }
180 /* now do the real mapping */
181 if (new_addr != r->addr) {
182 if (r->addr != -1) {
183 if (r->type & PCI_ADDRESS_SPACE_IO) {
184 int class;
185 /* NOTE: specific hack for IDE in PC case:
186 only one byte must be mapped. */
187 class = d->config[0x0a] | (d->config[0x0b] << 8);
188 if (class == 0x0101 && r->size == 4) {
189 isa_unassign_ioport(r->addr + 2, 1);
190 } else {
191 isa_unassign_ioport(r->addr, r->size);
192 }
193 } else {
194 cpu_register_physical_memory(r->addr + pci_mem_base,
195 r->size,
196 IO_MEM_UNASSIGNED);
197 }
198 }
199 r->addr = new_addr;
200 if (r->addr != -1) {
201 r->map_func(d, i, r->addr, r->size, r->type);
202 }
203 }
204 }
205 }
206}
207
208uint32_t pci_default_read_config(PCIDevice *d,
209 uint32_t address, int len)
69b91039 210{
0ac32c83
FB		 211 uint32_t val;
212 switch(len) {
213 case 1:
214 val = d->config[address];
215 break;
216 case 2:
217 val = le16_to_cpu(*(uint16_t *)(d->config + address));
218 break;
219 default:
220 case 4:
221 val = le32_to_cpu(*(uint32_t *)(d->config + address));
222 break;
223 }
224 return val;
225}
226
227void pci_default_write_config(PCIDevice *d,
228 uint32_t address, uint32_t val, int len)
229{
230 int can_write, i;
7bf5be70 231 uint32_t end, addr;
0ac32c83 232
8a8696a3
FB		 233 if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
234 (address >= 0x30 && address < 0x34))) {
0ac32c83
FB		 235 PCIIORegion *r;
236 int reg;
237
8a8696a3
FB		 238 if ( address >= 0x30 ) {
239 reg = PCI_ROM_SLOT;
240 }else{
241 reg = (address - 0x10) >> 2;
242 }
0ac32c83
FB		 243 r = &d->io_regions[reg];
244 if (r->size == 0)
245 goto default_config;
246 /* compute the stored value */
8a8696a3
FB		 247 if (reg == PCI_ROM_SLOT) {
248 /* keep ROM enable bit */
249 val &= (~(r->size - 1)) | 1;
250 } else {
251 val &= ~(r->size - 1);
252 val |= r->type;
253 }
254 *(uint32_t *)(d->config + address) = cpu_to_le32(val);
0ac32c83 255 pci_update_mappings(d);
69b91039 256 return;
0ac32c83
FB		 257 }
258 default_config:
259 /* not efficient, but simple */
7bf5be70 260 addr = address;
0ac32c83
FB		 261 for(i = 0; i < len; i++) {
262 /* default read/write accesses */
1f62d938 263 switch(d->config[0x0e]) {
0ac32c83 264 case 0x00:
1f62d938
FB		 265 case 0x80:
266 switch(addr) {
267 case 0x00:
268 case 0x01:
269 case 0x02:
270 case 0x03:
271 case 0x08:
272 case 0x09:
273 case 0x0a:
274 case 0x0b:
275 case 0x0e:
276 case 0x10 ... 0x27: /* base */
277 case 0x30 ... 0x33: /* rom */
278 case 0x3d:
279 can_write = 0;
280 break;
281 default:
282 can_write = 1;
283 break;
284 }
0ac32c83
FB		 285 break;
286 default:
1f62d938
FB		 287 case 0x01:
288 switch(addr) {
289 case 0x00:
290 case 0x01:
291 case 0x02:
292 case 0x03:
293 case 0x08:
294 case 0x09:
295 case 0x0a:
296 case 0x0b:
297 case 0x0e:
298 case 0x38 ... 0x3b: /* rom */
299 case 0x3d:
300 can_write = 0;
301 break;
302 default:
303 can_write = 1;
304 break;
305 }
0ac32c83
FB		 306 break;
307 }
308 if (can_write) {
7bf5be70 309 d->config[addr] = val;
0ac32c83 310 }
7bf5be70 311 addr++;
0ac32c83
FB		 312 val >>= 8;
313 }
314
315 end = address + len;
316 if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
317 /* if the command register is modified, we must modify the mappings */
318 pci_update_mappings(d);
69b91039
FB		 319 }
320}
321
322static void pci_data_write(void *opaque, uint32_t addr,
323 uint32_t val, int len)
324{
30468f78
FB		 325 PCIBus *s = opaque;
326 PCIDevice *pci_dev;
327 int config_addr, bus_num;
69b91039
FB		 328
329#if defined(DEBUG_PCI) && 0
330 printf("pci_data_write: addr=%08x val=%08x len=%d\n",
331 s->config_reg, val, len);
332#endif
333 if (!(s->config_reg & (1 << 31))) {
334 return;
335 }
336 if ((s->config_reg & 0x3) != 0) {
337 return;
338 }
30468f78
FB		 339 bus_num = (s->config_reg >> 16) & 0xff;
340 if (bus_num != 0)
69b91039 341 return;
30468f78 342 pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
69b91039
FB		 343 if (!pci_dev)
344 return;
345 config_addr = (s->config_reg & 0xfc) | (addr & 3);
69b91039
FB		 346#if defined(DEBUG_PCI)
347 printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
348 pci_dev->name, config_addr, val, len);
349#endif
0ac32c83 350 pci_dev->config_write(pci_dev, config_addr, val, len);
69b91039
FB		 351}
352
353static uint32_t pci_data_read(void *opaque, uint32_t addr,
354 int len)
355{
30468f78
FB		 356 PCIBus *s = opaque;
357 PCIDevice *pci_dev;
358 int config_addr, bus_num;
69b91039
FB		 359 uint32_t val;
360
361 if (!(s->config_reg & (1 << 31)))
362 goto fail;
363 if ((s->config_reg & 0x3) != 0)
364 goto fail;
30468f78
FB		 365 bus_num = (s->config_reg >> 16) & 0xff;
366 if (bus_num != 0)
69b91039 367 goto fail;
30468f78 368 pci_dev = s->devices[(s->config_reg >> 8) & 0xff];
69b91039
FB		 369 if (!pci_dev) {
370 fail:
63ce9e0a
FB		 371 switch(len) {
372 case 1:
373 val = 0xff;
374 break;
375 case 2:
376 val = 0xffff;
377 break;
378 default:
379 case 4:
380 val = 0xffffffff;
381 break;
382 }
69b91039
FB		 383 goto the_end;
384 }
385 config_addr = (s->config_reg & 0xfc) | (addr & 3);
386 val = pci_dev->config_read(pci_dev, config_addr, len);
387#if defined(DEBUG_PCI)
388 printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
389 pci_dev->name, config_addr, val, len);
390#endif
391 the_end:
392#if defined(DEBUG_PCI) && 0
393 printf("pci_data_read: addr=%08x val=%08x len=%d\n",
394 s->config_reg, val, len);
395#endif
396 return val;
397}
398
399static void pci_data_writeb(void* opaque, uint32_t addr, uint32_t val)
400{
401 pci_data_write(opaque, addr, val, 1);
402}
403
404static void pci_data_writew(void* opaque, uint32_t addr, uint32_t val)
405{
406 pci_data_write(opaque, addr, val, 2);
407}
408
409static void pci_data_writel(void* opaque, uint32_t addr, uint32_t val)
410{
411 pci_data_write(opaque, addr, val, 4);
412}
413
414static uint32_t pci_data_readb(void* opaque, uint32_t addr)
415{
416 return pci_data_read(opaque, addr, 1);
417}
418
419static uint32_t pci_data_readw(void* opaque, uint32_t addr)
420{
421 return pci_data_read(opaque, addr, 2);
422}
423
424static uint32_t pci_data_readl(void* opaque, uint32_t addr)
425{
426 return pci_data_read(opaque, addr, 4);
427}
428
429/* i440FX PCI bridge */
430
30468f78
FB		 431static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level);
432
433PCIBus *i440fx_init(void)
69b91039 434{
30468f78 435 PCIBus *s;
69b91039
FB		 436 PCIDevice *d;
437
30468f78
FB		 438 s = pci_register_bus();
439 s->set_irq = piix3_set_irq;
440
0ac32c83
FB		 441 register_ioport_write(0xcf8, 4, 4, pci_addr_writel, s);
442 register_ioport_read(0xcf8, 4, 4, pci_addr_readl, s);
69b91039
FB		 443
444 register_ioport_write(0xcfc, 4, 1, pci_data_writeb, s);
445 register_ioport_write(0xcfc, 4, 2, pci_data_writew, s);
446 register_ioport_write(0xcfc, 4, 4, pci_data_writel, s);
447 register_ioport_read(0xcfc, 4, 1, pci_data_readb, s);
448 register_ioport_read(0xcfc, 4, 2, pci_data_readw, s);
449 register_ioport_read(0xcfc, 4, 4, pci_data_readl, s);
450
30468f78 451 d = pci_register_device(s, "i440FX", sizeof(PCIDevice), 0,
0ac32c83 452 NULL, NULL);
69b91039
FB		 453
454 d->config[0x00] = 0x86; // vendor_id
455 d->config[0x01] = 0x80;
456 d->config[0x02] = 0x37; // device_id
457 d->config[0x03] = 0x12;
458 d->config[0x08] = 0x02; // revision
358c6407 459 d->config[0x0a] = 0x00; // class_sub = host2pci
69b91039 460 d->config[0x0b] = 0x06; // class_base = PCI_bridge
358c6407 461 d->config[0x0e] = 0x00; // header_type
30468f78 462 return s;
69b91039
FB		 463}
464
0ac32c83
FB		 465/* PIIX3 PCI to ISA bridge */
466
467typedef struct PIIX3State {
468 PCIDevice dev;
469} PIIX3State;
470
471PIIX3State *piix3_state;
472
30468f78
FB		 473/* return the global irq number corresponding to a given device irq
474 pin. We could also use the bus number to have a more precise
475 mapping. */
476static inline int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
477{
478 int slot_addend;
479 slot_addend = (pci_dev->devfn >> 3);
480 return (irq_num + slot_addend) & 3;
481}
482
483static void piix3_set_irq(PCIDevice *pci_dev, int irq_num, int level)
484{
485 int irq_index, shift, pic_irq, pic_level;
486 uint32_t *p;
487
488 irq_num = pci_slot_get_pirq(pci_dev, irq_num);
489 irq_index = pci_dev->irq_index;
490 p = &pci_irq_levels[irq_num][irq_index >> 5];
491 shift = (irq_index & 0x1f);
492 *p = (*p & ~(1 << shift)) | (level << shift);
493
494 /* now we change the pic irq level according to the piix irq mappings */
495 pic_irq = piix3_state->dev.config[0x60 + irq_num];
496 if (pic_irq < 16) {
497 /* the pic level is the logical OR of all the PCI irqs mapped
498 to it */
499 pic_level = 0;
500#if (PCI_IRQ_WORDS == 2)
501 pic_level = ((pci_irq_levels[irq_num][0] |
502 pci_irq_levels[irq_num][1]) != 0);
503#else
504 {
505 int i;
506 pic_level = 0;
507 for(i = 0; i < PCI_IRQ_WORDS; i++) {
508 if (pci_irq_levels[irq_num][i]) {
509 pic_level = 1;
510 break;
511 }
512 }
513 }
514#endif
515 pic_set_irq(pic_irq, pic_level);
516 }
517}
518
0ac32c83
FB		 519static void piix3_reset(PIIX3State *d)
520{
521 uint8_t *pci_conf = d->dev.config;
522
523 pci_conf[0x04] = 0x07; // master, memory and I/O
524 pci_conf[0x05] = 0x00;
525 pci_conf[0x06] = 0x00;
526 pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
527 pci_conf[0x4c] = 0x4d;
528 pci_conf[0x4e] = 0x03;
529 pci_conf[0x4f] = 0x00;
530 pci_conf[0x60] = 0x80;
531 pci_conf[0x69] = 0x02;
532 pci_conf[0x70] = 0x80;
533 pci_conf[0x76] = 0x0c;
534 pci_conf[0x77] = 0x0c;
535 pci_conf[0x78] = 0x02;
536 pci_conf[0x79] = 0x00;
537 pci_conf[0x80] = 0x00;
538 pci_conf[0x82] = 0x00;
539 pci_conf[0xa0] = 0x08;
540 pci_conf[0xa0] = 0x08;
541 pci_conf[0xa2] = 0x00;
542 pci_conf[0xa3] = 0x00;
543 pci_conf[0xa4] = 0x00;
544 pci_conf[0xa5] = 0x00;
545 pci_conf[0xa6] = 0x00;
546 pci_conf[0xa7] = 0x00;
547 pci_conf[0xa8] = 0x0f;
548 pci_conf[0xaa] = 0x00;
549 pci_conf[0xab] = 0x00;
550 pci_conf[0xac] = 0x00;
551 pci_conf[0xae] = 0x00;
552}
553
30468f78 554void piix3_init(PCIBus *bus)
0ac32c83
FB		 555{
556 PIIX3State *d;
557 uint8_t *pci_conf;
558
30468f78
FB		 559 d = (PIIX3State *)pci_register_device(bus, "PIIX3", sizeof(PIIX3State),
560 -1, NULL, NULL);
0ac32c83
FB		 561 piix3_state = d;
562 pci_conf = d->dev.config;
563
564 pci_conf[0x00] = 0x86; // Intel
565 pci_conf[0x01] = 0x80;
566 pci_conf[0x02] = 0x00; // 82371SB PIIX3 PCI-to-ISA bridge (Step A1)
567 pci_conf[0x03] = 0x70;
568 pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA
569 pci_conf[0x0b] = 0x06; // class_base = PCI_bridge
570 pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic
571
572 piix3_reset(d);
573}
574
77d4bc34
FB		 575/* PREP pci init */
576
30468f78 577static inline void set_config(PCIBus *s, target_phys_addr_t addr)
77d4bc34
FB		 578{
579 int devfn, i;
580
581 for(i = 0; i < 11; i++) {
582 if ((addr & (1 << (11 + i))) != 0)
583 break;
584 }
585 devfn = ((addr >> 8) & 7) | (i << 3);
586 s->config_reg = 0x80000000 | (addr & 0xfc) | (devfn << 8);
587}
588
8a8696a3 589static void PPC_PCIIO_writeb (void *opaque, target_phys_addr_t addr, uint32_t val)
77d4bc34 590{
30468f78 591 PCIBus *s = opaque;
77d4bc34
FB		 592 set_config(s, addr);
593 pci_data_write(s, addr, val, 1);
594}
595
8a8696a3 596static void PPC_PCIIO_writew (void *opaque, target_phys_addr_t addr, uint32_t val)
77d4bc34 597{
30468f78 598 PCIBus *s = opaque;
77d4bc34
FB		 599 set_config(s, addr);
600#ifdef TARGET_WORDS_BIGENDIAN
601 val = bswap16(val);
602#endif
603 pci_data_write(s, addr, val, 2);
604}
605
8a8696a3 606static void PPC_PCIIO_writel (void *opaque, target_phys_addr_t addr, uint32_t val)
77d4bc34 607{
30468f78 608 PCIBus *s = opaque;
77d4bc34
FB		 609 set_config(s, addr);
610#ifdef TARGET_WORDS_BIGENDIAN
611 val = bswap32(val);
612#endif
613 pci_data_write(s, addr, val, 4);
614}
615
8a8696a3 616static uint32_t PPC_PCIIO_readb (void *opaque, target_phys_addr_t addr)
77d4bc34 617{
30468f78 618 PCIBus *s = opaque;
77d4bc34
FB		 619 uint32_t val;
620 set_config(s, addr);
621 val = pci_data_read(s, addr, 1);
622 return val;
623}
624
8a8696a3 625static uint32_t PPC_PCIIO_readw (void *opaque, target_phys_addr_t addr)
77d4bc34 626{
30468f78 627 PCIBus *s = opaque;
77d4bc34
FB		 628 uint32_t val;
629 set_config(s, addr);
630 val = pci_data_read(s, addr, 2);
631#ifdef TARGET_WORDS_BIGENDIAN
632 val = bswap16(val);
633#endif
634 return val;
635}
636
8a8696a3 637static uint32_t PPC_PCIIO_readl (void *opaque, target_phys_addr_t addr)
77d4bc34 638{
30468f78 639 PCIBus *s = opaque;
77d4bc34
FB		 640 uint32_t val;
641 set_config(s, addr);
642 val = pci_data_read(s, addr, 4);
643#ifdef TARGET_WORDS_BIGENDIAN
644 val = bswap32(val);
645#endif
646 return val;
647}
648
649static CPUWriteMemoryFunc *PPC_PCIIO_write[] = {
650 &PPC_PCIIO_writeb,
651 &PPC_PCIIO_writew,
652 &PPC_PCIIO_writel,
653};
654
655static CPUReadMemoryFunc *PPC_PCIIO_read[] = {
656 &PPC_PCIIO_readb,
657 &PPC_PCIIO_readw,
658 &PPC_PCIIO_readl,
659};
660
30468f78
FB		 661static void prep_set_irq(PCIDevice *d, int irq_num, int level)
662{
663 /* XXX: we do not simulate the hardware - we rely on the BIOS to
664 set correctly for irq line field */
665 pic_set_irq(d->config[PCI_INTERRUPT_LINE], level);
666}
667
668PCIBus *pci_prep_init(void)
77d4bc34 669{
30468f78 670 PCIBus *s;
77d4bc34
FB		 671 PCIDevice *d;
672 int PPC_io_memory;
673
30468f78
FB		 674 s = pci_register_bus();
675 s->set_irq = prep_set_irq;
676
8a8696a3
FB		 677 PPC_io_memory = cpu_register_io_memory(0, PPC_PCIIO_read,
678 PPC_PCIIO_write, s);
77d4bc34
FB		 679 cpu_register_physical_memory(0x80800000, 0x00400000, PPC_io_memory);
680
30468f78 681 d = pci_register_device(s, "PREP PCI Bridge", sizeof(PCIDevice), 0,
77d4bc34
FB		 682 NULL, NULL);
683
684 /* XXX: put correct IDs */
685 d->config[0x00] = 0x11; // vendor_id
686 d->config[0x01] = 0x10;
687 d->config[0x02] = 0x26; // device_id
688 d->config[0x03] = 0x00;
689 d->config[0x08] = 0x02; // revision
690 d->config[0x0a] = 0x04; // class_sub = pci2pci
691 d->config[0x0b] = 0x06; // class_base = PCI_bridge
692 d->config[0x0e] = 0x01; // header_type
30468f78 693 return s;
77d4bc34
FB		 694}
695
696
697/* pmac pci init */
698
30468f78 699#if 0
f2aa58c6
FB		 700/* Grackle PCI host */
701static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
702 uint32_t val)
77d4bc34 703{
30468f78 704 PCIBus *s = opaque;
77d4bc34
FB		 705#ifdef TARGET_WORDS_BIGENDIAN
706 val = bswap32(val);
707#endif
708 s->config_reg = val;
709}
710
f2aa58c6 711static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
77d4bc34 712{
30468f78 713 PCIBus *s = opaque;
77d4bc34
FB		 714 uint32_t val;
715
716 val = s->config_reg;
717#ifdef TARGET_WORDS_BIGENDIAN
718 val = bswap32(val);
719#endif
720 return val;
721}
722
f2aa58c6
FB		 723static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
724 &pci_grackle_config_writel,
725 &pci_grackle_config_writel,
726 &pci_grackle_config_writel,
77d4bc34
FB		 727};
728
f2aa58c6
FB		 729static CPUReadMemoryFunc *pci_grackle_config_read[] = {
730 &pci_grackle_config_readl,
731 &pci_grackle_config_readl,
732 &pci_grackle_config_readl,
77d4bc34
FB		 733};
734
f2aa58c6
FB		 735static void pci_grackle_writeb (void *opaque, target_phys_addr_t addr,
736 uint32_t val)
77d4bc34 737{
30468f78 738 PCIBus *s = opaque;
77d4bc34
FB		 739 pci_data_write(s, addr, val, 1);
740}
741
f2aa58c6
FB		 742static void pci_grackle_writew (void *opaque, target_phys_addr_t addr,
743 uint32_t val)
77d4bc34 744{
30468f78 745 PCIBus *s = opaque;
77d4bc34
FB		 746#ifdef TARGET_WORDS_BIGENDIAN
747 val = bswap16(val);
748#endif
749 pci_data_write(s, addr, val, 2);
750}
751
f2aa58c6
FB		 752static void pci_grackle_writel (void *opaque, target_phys_addr_t addr,
753 uint32_t val)
77d4bc34 754{
30468f78 755 PCIBus *s = opaque;
77d4bc34
FB		 756#ifdef TARGET_WORDS_BIGENDIAN
757 val = bswap32(val);
758#endif
759 pci_data_write(s, addr, val, 4);
760}
761
f2aa58c6 762static uint32_t pci_grackle_readb (void *opaque, target_phys_addr_t addr)
77d4bc34 763{
30468f78 764 PCIBus *s = opaque;
77d4bc34
FB		 765 uint32_t val;
766 val = pci_data_read(s, addr, 1);
767 return val;
768}
769
f2aa58c6 770static uint32_t pci_grackle_readw (void *opaque, target_phys_addr_t addr)
77d4bc34 771{
30468f78 772 PCIBus *s = opaque;
77d4bc34
FB		 773 uint32_t val;
774 val = pci_data_read(s, addr, 2);
775#ifdef TARGET_WORDS_BIGENDIAN
776 val = bswap16(val);
777#endif
778 return val;
779}
780
f2aa58c6
FB		 781static uint32_t pci_grackle_readl (void *opaque, target_phys_addr_t addr)
782{
30468f78 783 PCIBus *s = opaque;
f2aa58c6
FB		 784 uint32_t val;
785
786 val = pci_data_read(s, addr, 4);
787#ifdef TARGET_WORDS_BIGENDIAN
788 val = bswap32(val);
789#endif
790 return val;
791}
792
793static CPUWriteMemoryFunc *pci_grackle_write[] = {
794 &pci_grackle_writeb,
795 &pci_grackle_writew,
796 &pci_grackle_writel,
797};
798
799static CPUReadMemoryFunc *pci_grackle_read[] = {
800 &pci_grackle_readb,
801 &pci_grackle_readw,
802 &pci_grackle_readl,
803};
30468f78 804#endif
f2aa58c6
FB		 805
806/* Uninorth PCI host (for all Mac99 and newer machines */
807static void pci_unin_main_config_writel (void *opaque, target_phys_addr_t addr,
808 uint32_t val)
809{
30468f78 810 PCIBus *s = opaque;
f2aa58c6
FB		 811 int i;
812
813#ifdef TARGET_WORDS_BIGENDIAN
814 val = bswap32(val);
815#endif
816
817 for (i = 11; i < 32; i++) {
818 if ((val & (1 << i)) != 0)
819 break;
820 }
821#if 0
822 s->config_reg = 0x80000000 | (1 << 16) | (val & 0x7FC) | (i << 11);
823#else
824 s->config_reg = 0x80000000 | (0 << 16) | (val & 0x7FC) | (i << 11);
825#endif
826}
827
828static uint32_t pci_unin_main_config_readl (void *opaque,
829 target_phys_addr_t addr)
830{
30468f78 831 PCIBus *s = opaque;
f2aa58c6
FB		 832 uint32_t val;
833 int devfn;
834
835 devfn = (s->config_reg >> 8) & 0xFF;
836 val = (1 << (devfn >> 3)) | ((devfn & 0x07) << 8) | (s->config_reg & 0xFC);
837#ifdef TARGET_WORDS_BIGENDIAN
838 val = bswap32(val);
839#endif
840
841 return val;
842}
843
844static CPUWriteMemoryFunc *pci_unin_main_config_write[] = {
845 &pci_unin_main_config_writel,
846 &pci_unin_main_config_writel,
847 &pci_unin_main_config_writel,
848};
849
850static CPUReadMemoryFunc *pci_unin_main_config_read[] = {
851 &pci_unin_main_config_readl,
852 &pci_unin_main_config_readl,
853 &pci_unin_main_config_readl,
854};
855
856static void pci_unin_main_writeb (void *opaque, target_phys_addr_t addr,
857 uint32_t val)
858{
30468f78 859 PCIBus *s = opaque;
f2aa58c6
FB		 860 pci_data_write(s, addr & 7, val, 1);
861}
862
863static void pci_unin_main_writew (void *opaque, target_phys_addr_t addr,
864 uint32_t val)
865{
30468f78 866 PCIBus *s = opaque;
f2aa58c6
FB		 867#ifdef TARGET_WORDS_BIGENDIAN
868 val = bswap16(val);
869#endif
870 pci_data_write(s, addr & 7, val, 2);
871}
872
873static void pci_unin_main_writel (void *opaque, target_phys_addr_t addr,
874 uint32_t val)
875{
30468f78 876 PCIBus *s = opaque;
f2aa58c6
FB		 877#ifdef TARGET_WORDS_BIGENDIAN
878 val = bswap32(val);
879#endif
880 pci_data_write(s, addr & 7, val, 4);
881}
882
883static uint32_t pci_unin_main_readb (void *opaque, target_phys_addr_t addr)
884{
30468f78 885 PCIBus *s = opaque;
f2aa58c6
FB		 886 uint32_t val;
887
888 val = pci_data_read(s, addr & 7, 1);
889
890 return val;
891}
892
893static uint32_t pci_unin_main_readw (void *opaque, target_phys_addr_t addr)
894{
30468f78 895 PCIBus *s = opaque;
f2aa58c6
FB		 896 uint32_t val;
897
898 val = pci_data_read(s, addr & 7, 2);
899#ifdef TARGET_WORDS_BIGENDIAN
900 val = bswap16(val);
901#endif
902
903 return val;
904}
905
906static uint32_t pci_unin_main_readl (void *opaque, target_phys_addr_t addr)
77d4bc34 907{
30468f78 908 PCIBus *s = opaque;
77d4bc34
FB		 909 uint32_t val;
910
911 val = pci_data_read(s, addr, 4);
912#ifdef TARGET_WORDS_BIGENDIAN
913 val = bswap32(val);
914#endif
f2aa58c6
FB		 915
916 return val;
917}
918
919static CPUWriteMemoryFunc *pci_unin_main_write[] = {
920 &pci_unin_main_writeb,
921 &pci_unin_main_writew,
922 &pci_unin_main_writel,
923};
924
925static CPUReadMemoryFunc *pci_unin_main_read[] = {
926 &pci_unin_main_readb,
927 &pci_unin_main_readw,
928 &pci_unin_main_readl,
929};
930
30468f78
FB		 931#if 0
932
f2aa58c6
FB		 933static void pci_unin_config_writel (void *opaque, target_phys_addr_t addr,
934 uint32_t val)
935{
30468f78 936 PCIBus *s = opaque;
f2aa58c6
FB		 937
938#ifdef TARGET_WORDS_BIGENDIAN
939 val = bswap32(val);
940#endif
941 s->config_reg = 0x80000000 | (val & ~0x00000001);
942}
943
944static uint32_t pci_unin_config_readl (void *opaque,
945 target_phys_addr_t addr)
946{
30468f78 947 PCIBus *s = opaque;
f2aa58c6
FB		 948 uint32_t val;
949
950 val = (s->config_reg | 0x00000001) & ~0x80000000;
951#ifdef TARGET_WORDS_BIGENDIAN
952 val = bswap32(val);
953#endif
954
955 return val;
956}
957
958static CPUWriteMemoryFunc *pci_unin_config_write[] = {
959 &pci_unin_config_writel,
960 &pci_unin_config_writel,
961 &pci_unin_config_writel,
962};
963
964static CPUReadMemoryFunc *pci_unin_config_read[] = {
965 &pci_unin_config_readl,
966 &pci_unin_config_readl,
967 &pci_unin_config_readl,
968};
969
970static void pci_unin_writeb (void *opaque, target_phys_addr_t addr,
971 uint32_t val)
972{
30468f78 973 PCIBus *s = opaque;
f2aa58c6
FB		 974 pci_data_write(s, addr & 3, val, 1);
975}
976
977static void pci_unin_writew (void *opaque, target_phys_addr_t addr,
978 uint32_t val)
979{
30468f78 980 PCIBus *s = opaque;
f2aa58c6
FB		 981#ifdef TARGET_WORDS_BIGENDIAN
982 val = bswap16(val);
983#endif
984 pci_data_write(s, addr & 3, val, 2);
985}
986
987static void pci_unin_writel (void *opaque, target_phys_addr_t addr,
988 uint32_t val)
989{
30468f78 990 PCIBus *s = opaque;
f2aa58c6
FB		 991#ifdef TARGET_WORDS_BIGENDIAN
992 val = bswap32(val);
993#endif
994 pci_data_write(s, addr & 3, val, 4);
995}
996
997static uint32_t pci_unin_readb (void *opaque, target_phys_addr_t addr)
998{
30468f78 999 PCIBus *s = opaque;
f2aa58c6
FB		 1000 uint32_t val;
1001
1002 val = pci_data_read(s, addr & 3, 1);
1003
1004 return val;
1005}
1006
1007static uint32_t pci_unin_readw (void *opaque, target_phys_addr_t addr)
1008{
30468f78 1009 PCIBus *s = opaque;
f2aa58c6
FB		 1010 uint32_t val;
1011
1012 val = pci_data_read(s, addr & 3, 2);
1013#ifdef TARGET_WORDS_BIGENDIAN
1014 val = bswap16(val);
1015#endif
1016
1017 return val;
1018}
1019
1020static uint32_t pci_unin_readl (void *opaque, target_phys_addr_t addr)
1021{
30468f78 1022 PCIBus *s = opaque;
f2aa58c6
FB		 1023 uint32_t val;
1024
1025 val = pci_data_read(s, addr & 3, 4);
1026#ifdef TARGET_WORDS_BIGENDIAN
1027 val = bswap32(val);
1028#endif
1029
77d4bc34
FB		 1030 return val;
1031}
1032
f2aa58c6
FB		 1033static CPUWriteMemoryFunc *pci_unin_write[] = {
1034 &pci_unin_writeb,
1035 &pci_unin_writew,
1036 &pci_unin_writel,
77d4bc34
FB		 1037};
1038
f2aa58c6
FB		 1039static CPUReadMemoryFunc *pci_unin_read[] = {
1040 &pci_unin_readb,
1041 &pci_unin_readw,
1042 &pci_unin_readl,
77d4bc34 1043};
30468f78
FB		 1044#endif
1045
1046static void pmac_set_irq(PCIDevice *d, int irq_num, int level)
1047{
1048 openpic_t *openpic;
1049 /* XXX: we do not simulate the hardware - we rely on the BIOS to
1050 set correctly for irq line field */
1051 openpic = d->bus->openpic;
1052#ifdef TARGET_PPC
1053 if (openpic)
1054 openpic_set_irq(openpic, d->config[PCI_INTERRUPT_LINE], level);
1055#endif
1056}
1057
1058void pci_pmac_set_openpic(PCIBus *bus, openpic_t *openpic)
1059{
1060 bus->openpic = openpic;
1061}
77d4bc34 1062
30468f78 1063PCIBus *pci_pmac_init(void)
77d4bc34 1064{
30468f78 1065 PCIBus *s;
77d4bc34
FB		 1066 PCIDevice *d;
1067 int pci_mem_config, pci_mem_data;
1068
f2aa58c6
FB		 1069 /* Use values found on a real PowerMac */
1070 /* Uninorth main bus */
30468f78
FB		 1071 s = pci_register_bus();
1072 s->set_irq = pmac_set_irq;
1073
f2aa58c6
FB		 1074 pci_mem_config = cpu_register_io_memory(0, pci_unin_main_config_read,
1075 pci_unin_main_config_write, s);
1076 pci_mem_data = cpu_register_io_memory(0, pci_unin_main_read,
1077 pci_unin_main_write, s);
1078 cpu_register_physical_memory(0xf2800000, 0x1000, pci_mem_config);
1079 cpu_register_physical_memory(0xf2c00000, 0x1000, pci_mem_data);
30468f78
FB		 1080 s->devfn_min = 11 << 3;
1081 d = pci_register_device(s, "Uni-north main", sizeof(PCIDevice),
1082 11 << 3, NULL, NULL);
f2aa58c6
FB		 1083 d->config[0x00] = 0x6b; // vendor_id : Apple
1084 d->config[0x01] = 0x10;
1085 d->config[0x02] = 0x1F; // device_id
1086 d->config[0x03] = 0x00;
1087 d->config[0x08] = 0x00; // revision
1088 d->config[0x0A] = 0x00; // class_sub = pci host
1089 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1090 d->config[0x0C] = 0x08; // cache_line_size
1091 d->config[0x0D] = 0x10; // latency_timer
1092 d->config[0x0E] = 0x00; // header_type
1093 d->config[0x34] = 0x00; // capabilities_pointer
1094
1095#if 0 // XXX: not activated as PPC BIOS doesn't handle mutiple buses properly
1096 /* pci-to-pci bridge */
1097 d = pci_register_device("Uni-north bridge", sizeof(PCIDevice), 0, 13 << 3,
1098 NULL, NULL);
1099 d->config[0x00] = 0x11; // vendor_id : TI
1100 d->config[0x01] = 0x10;
1101 d->config[0x02] = 0x26; // device_id
1102 d->config[0x03] = 0x00;
1103 d->config[0x08] = 0x05; // revision
1104 d->config[0x0A] = 0x04; // class_sub = pci2pci
1105 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1106 d->config[0x0C] = 0x08; // cache_line_size
1107 d->config[0x0D] = 0x20; // latency_timer
1108 d->config[0x0E] = 0x01; // header_type
1109
1110 d->config[0x18] = 0x01; // primary_bus
1111 d->config[0x19] = 0x02; // secondary_bus
1112 d->config[0x1A] = 0x02; // subordinate_bus
1113 d->config[0x1B] = 0x20; // secondary_latency_timer
1114 d->config[0x1C] = 0x11; // io_base
1115 d->config[0x1D] = 0x01; // io_limit
1116 d->config[0x20] = 0x00; // memory_base
1117 d->config[0x21] = 0x80;
1118 d->config[0x22] = 0x00; // memory_limit
1119 d->config[0x23] = 0x80;
1120 d->config[0x24] = 0x01; // prefetchable_memory_base
1121 d->config[0x25] = 0x80;
1122 d->config[0x26] = 0xF1; // prefectchable_memory_limit
1123 d->config[0x27] = 0x7F;
1124 // d->config[0x34] = 0xdc // capabilities_pointer
1125#endif
1126#if 0 // XXX: not needed for now
1127 /* Uninorth AGP bus */
1128 s = &pci_bridge[1];
1129 pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1130 pci_unin_config_write, s);
1131 pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
1132 pci_unin_write, s);
1133 cpu_register_physical_memory(0xf0800000, 0x1000, pci_mem_config);
1134 cpu_register_physical_memory(0xf0c00000, 0x1000, pci_mem_data);
1135
1136 d = pci_register_device("Uni-north AGP", sizeof(PCIDevice), 0, 11 << 3,
1137 NULL, NULL);
1138 d->config[0x00] = 0x6b; // vendor_id : Apple
1139 d->config[0x01] = 0x10;
1140 d->config[0x02] = 0x20; // device_id
1141 d->config[0x03] = 0x00;
1142 d->config[0x08] = 0x00; // revision
1143 d->config[0x0A] = 0x00; // class_sub = pci host
1144 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1145 d->config[0x0C] = 0x08; // cache_line_size
1146 d->config[0x0D] = 0x10; // latency_timer
1147 d->config[0x0E] = 0x00; // header_type
1148 // d->config[0x34] = 0x80; // capabilities_pointer
1149#endif
77d4bc34 1150
f2aa58c6
FB		 1151#if 0 // XXX: not needed for now
1152 /* Uninorth internal bus */
1153 s = &pci_bridge[2];
1154 pci_mem_config = cpu_register_io_memory(0, pci_unin_config_read,
1155 pci_unin_config_write, s);
1156 pci_mem_data = cpu_register_io_memory(0, pci_unin_read,
1157 pci_unin_write, s);
1158 cpu_register_physical_memory(0xf4800000, 0x1000, pci_mem_config);
1159 cpu_register_physical_memory(0xf4c00000, 0x1000, pci_mem_data);
1160
1161 d = pci_register_device("Uni-north internal", sizeof(PCIDevice),
1162 3, 11 << 3, NULL, NULL);
1163 d->config[0x00] = 0x6b; // vendor_id : Apple
1164 d->config[0x01] = 0x10;
1165 d->config[0x02] = 0x1E; // device_id
1166 d->config[0x03] = 0x00;
1167 d->config[0x08] = 0x00; // revision
1168 d->config[0x0A] = 0x00; // class_sub = pci host
1169 d->config[0x0B] = 0x06; // class_base = PCI_bridge
1170 d->config[0x0C] = 0x08; // cache_line_size
1171 d->config[0x0D] = 0x10; // latency_timer
1172 d->config[0x0E] = 0x00; // header_type
1173 d->config[0x34] = 0x00; // capabilities_pointer
1174#endif
1175
1176#if 0 // Grackle ?
77d4bc34
FB		 1177 /* same values as PearPC - check this */
1178 d->config[0x00] = 0x11; // vendor_id
1179 d->config[0x01] = 0x10;
1180 d->config[0x02] = 0x26; // device_id
1181 d->config[0x03] = 0x00;
1182 d->config[0x08] = 0x02; // revision
1183 d->config[0x0a] = 0x04; // class_sub = pci2pci
1184 d->config[0x0b] = 0x06; // class_base = PCI_bridge
1185 d->config[0x0e] = 0x01; // header_type
1186
1187 d->config[0x18] = 0x0; // primary_bus
1188 d->config[0x19] = 0x1; // secondary_bus
1189 d->config[0x1a] = 0x1; // subordinate_bus
1190 d->config[0x1c] = 0x10; // io_base
1191 d->config[0x1d] = 0x20; // io_limit
1192
1193 d->config[0x20] = 0x80; // memory_base
1194 d->config[0x21] = 0x80;
1195 d->config[0x22] = 0x90; // memory_limit
1196 d->config[0x23] = 0x80;
1197
1198 d->config[0x24] = 0x00; // prefetchable_memory_base
1199 d->config[0x25] = 0x84;
1200 d->config[0x26] = 0x00; // prefetchable_memory_limit
1201 d->config[0x27] = 0x85;
f2aa58c6 1202#endif
30468f78 1203 return s;
77d4bc34
FB		 1204}
1205
0ac32c83
FB		 1206/***********************************************************/
1207/* generic PCI irq support */
1208
0ac32c83 1209/* 0 <= irq_num <= 3. level must be 0 or 1 */
77d4bc34
FB		 1210void pci_set_irq(PCIDevice *pci_dev, int irq_num, int level)
1211{
30468f78
FB		 1212 PCIBus *bus = pci_dev->bus;
1213 bus->set_irq(pci_dev, irq_num, level);
77d4bc34 1214}
0ac32c83
FB		 1215
1216/***********************************************************/
1217/* monitor info on PCI */
1218
1219static void pci_info_device(PCIDevice *d)
1220{
1221 int i, class;
1222 PCIIORegion *r;
1223
1224 printf(" Bus %2d, device %3d, function %d:\n",
30468f78 1225 d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
0ac32c83
FB		 1226 class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
1227 printf(" ");
1228 switch(class) {
1229 case 0x0101:
1230 printf("IDE controller");
1231 break;
1232 case 0x0200:
1233 printf("Ethernet controller");
1234 break;
1235 case 0x0300:
1236 printf("VGA controller");
1237 break;
1238 default:
1239 printf("Class %04x", class);
1240 break;
1241 }
1242 printf(": PCI device %04x:%04x\n",
1243 le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
1244 le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
1245
1246 if (d->config[PCI_INTERRUPT_PIN] != 0) {
1247 printf(" IRQ %d.\n", d->config[PCI_INTERRUPT_LINE]);
1248 }
8a8696a3 1249 for(i = 0;i < PCI_NUM_REGIONS; i++) {
0ac32c83
FB		 1250 r = &d->io_regions[i];
1251 if (r->size != 0) {
1252 printf(" BAR%d: ", i);
1253 if (r->type & PCI_ADDRESS_SPACE_IO) {
1254 printf("I/O at 0x%04x [0x%04x].\n",
1255 r->addr, r->addr + r->size - 1);
1256 } else {
1257 printf("32 bit memory at 0x%08x [0x%08x].\n",
1258 r->addr, r->addr + r->size - 1);
1259 }
1260 }
1261 }
1262}
1263
1264void pci_info(void)
1265{
30468f78
FB		 1266 PCIBus *bus = first_bus;
1267 PCIDevice *d;
1268 int devfn;
0ac32c83 1269
30468f78
FB		 1270 if (bus) {
1271 for(devfn = 0; devfn < 256; devfn++) {
1272 d = bus->devices[devfn];
1273 if (d)
1274 pci_info_device(d);
0ac32c83
FB		 1275 }
1276 }
1277}
1278
1279/***********************************************************/
1280/* XXX: the following should be moved to the PC BIOS */
1281
30468f78 1282static __attribute__((unused)) uint32_t isa_inb(uint32_t addr)
0ac32c83
FB		 1283{
1284 return cpu_inb(cpu_single_env, addr);
1285}
1286
1287static void isa_outb(uint32_t val, uint32_t addr)
1288{
1289 cpu_outb(cpu_single_env, addr, val);
1290}
1291
30468f78 1292static __attribute__((unused)) uint32_t isa_inw(uint32_t addr)
0ac32c83
FB		 1293{
1294 return cpu_inw(cpu_single_env, addr);
1295}
1296
30468f78 1297static __attribute__((unused)) void isa_outw(uint32_t val, uint32_t addr)
0ac32c83
FB		 1298{
1299 cpu_outw(cpu_single_env, addr, val);
1300}
1301
30468f78 1302static __attribute__((unused)) uint32_t isa_inl(uint32_t addr)
0ac32c83
FB		 1303{
1304 return cpu_inl(cpu_single_env, addr);
1305}
1306
30468f78 1307static __attribute__((unused)) void isa_outl(uint32_t val, uint32_t addr)
0ac32c83
FB		 1308{
1309 cpu_outl(cpu_single_env, addr, val);
1310}
1311
1312static void pci_config_writel(PCIDevice *d, uint32_t addr, uint32_t val)
1313{
30468f78
FB		 1314 PCIBus *s = d->bus;
1315 s->config_reg = 0x80000000 | (s->bus_num << 16) |
0ac32c83
FB		 1316 (d->devfn << 8) | addr;
1317 pci_data_write(s, 0, val, 4);
1318}
1319
1320static void pci_config_writew(PCIDevice *d, uint32_t addr, uint32_t val)
1321{
30468f78
FB		 1322 PCIBus *s = d->bus;
1323 s->config_reg = 0x80000000 | (s->bus_num << 16) |
0ac32c83
FB		 1324 (d->devfn << 8) | (addr & ~3);
1325 pci_data_write(s, addr & 3, val, 2);
1326}
1327
1328static void pci_config_writeb(PCIDevice *d, uint32_t addr, uint32_t val)
1329{
30468f78
FB		 1330 PCIBus *s = d->bus;
1331 s->config_reg = 0x80000000 | (s->bus_num << 16) |
0ac32c83
FB		 1332 (d->devfn << 8) | (addr & ~3);
1333 pci_data_write(s, addr & 3, val, 1);
1334}
1335
30468f78 1336static __attribute__((unused)) uint32_t pci_config_readl(PCIDevice *d, uint32_t addr)
0ac32c83 1337{
30468f78
FB		 1338 PCIBus *s = d->bus;
1339 s->config_reg = 0x80000000 | (s->bus_num << 16) |
0ac32c83
FB		 1340 (d->devfn << 8) | addr;
1341 return pci_data_read(s, 0, 4);
1342}
1343
1344static uint32_t pci_config_readw(PCIDevice *d, uint32_t addr)
1345{
30468f78
FB		 1346 PCIBus *s = d->bus;
1347 s->config_reg = 0x80000000 | (s->bus_num << 16) |
0ac32c83
FB		 1348 (d->devfn << 8) | (addr & ~3);
1349 return pci_data_read(s, addr & 3, 2);
1350}
1351
1352static uint32_t pci_config_readb(PCIDevice *d, uint32_t addr)
1353{
30468f78
FB		 1354 PCIBus *s = d->bus;
1355 s->config_reg = 0x80000000 | (s->bus_num << 16) |
0ac32c83
FB		 1356 (d->devfn << 8) | (addr & ~3);
1357 return pci_data_read(s, addr & 3, 1);
1358}
69b91039
FB		 1359
1360static uint32_t pci_bios_io_addr;
1361static uint32_t pci_bios_mem_addr;
0ac32c83
FB		 1362/* host irqs corresponding to PCI irqs A-D */
1363static uint8_t pci_irqs[4] = { 11, 9, 11, 9 };
69b91039
FB		 1364
1365static void pci_set_io_region_addr(PCIDevice *d, int region_num, uint32_t addr)
1366{
69b91039 1367 PCIIORegion *r;
0ac32c83 1368 uint16_t cmd;
8a8696a3
FB		 1369 uint32_t ofs;
1370
1371 if ( region_num == PCI_ROM_SLOT ) {
1372 ofs = 0x30;
1373 }else{
1374 ofs = 0x10 + region_num * 4;
1375 }
69b91039 1376
8a8696a3 1377 pci_config_writel(d, ofs, addr);
69b91039
FB		 1378 r = &d->io_regions[region_num];
1379
1380 /* enable memory mappings */
0ac32c83 1381 cmd = pci_config_readw(d, PCI_COMMAND);
8a8696a3
FB		 1382 if ( region_num == PCI_ROM_SLOT )
1383 cmd |= 2;
1384 else if (r->type & PCI_ADDRESS_SPACE_IO)
0ac32c83 1385 cmd |= 1;
69b91039 1386 else
0ac32c83
FB		 1387 cmd |= 2;
1388 pci_config_writew(d, PCI_COMMAND, cmd);
69b91039
FB		 1389}
1390
69b91039
FB		 1391static void pci_bios_init_device(PCIDevice *d)
1392{
1393 int class;
1394 PCIIORegion *r;
1395 uint32_t *paddr;
63ce9e0a 1396 int i, pin, pic_irq, vendor_id, device_id;
69b91039 1397
63ce9e0a 1398 class = pci_config_readw(d, PCI_CLASS_DEVICE);
1f62d938
FB		 1399 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1400 device_id = pci_config_readw(d, PCI_DEVICE_ID);
69b91039
FB		 1401 switch(class) {
1402 case 0x0101:
63ce9e0a
FB		 1403 if (vendor_id == 0x8086 && device_id == 0x7010) {
1404 /* PIIX3 IDE */
1405 pci_config_writew(d, PCI_COMMAND, PCI_COMMAND_IO);
1406 pci_config_writew(d, 0x40, 0x8000); // enable IDE0
7f647cf6 1407 pci_config_writew(d, 0x42, 0x8000); // enable IDE1
63ce9e0a
FB		 1408 } else {
1409 /* IDE: we map it as in ISA mode */
1410 pci_set_io_region_addr(d, 0, 0x1f0);
1411 pci_set_io_region_addr(d, 1, 0x3f4);
1412 pci_set_io_region_addr(d, 2, 0x170);
1413 pci_set_io_region_addr(d, 3, 0x374);
1414 }
69b91039 1415 break;
0ac32c83 1416 case 0x0300:
4c7634bc
FB		 1417 if (vendor_id != 0x1234)
1418 goto default_map;
0ac32c83
FB		 1419 /* VGA: map frame buffer to default Bochs VBE address */
1420 pci_set_io_region_addr(d, 0, 0xE0000000);
1421 break;
f2aa58c6
FB		 1422 case 0x0800:
1423 /* PIC */
1424 vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
1425 device_id = pci_config_readw(d, PCI_DEVICE_ID);
1426 if (vendor_id == 0x1014) {
1427 /* IBM */
1428 if (device_id == 0x0046 || device_id == 0xFFFF) {
1429 /* MPIC & MPIC2 */
1430 pci_set_io_region_addr(d, 0, 0x80800000 + 0x00040000);
1431 }
1432 }
1433 break;
1f62d938 1434 case 0xff00:
f2aa58c6
FB		 1435 if (vendor_id == 0x0106b &&
1436 (device_id == 0x0017 || device_id == 0x0022)) {
1f62d938
FB		 1437 /* macio bridge */
1438 pci_set_io_region_addr(d, 0, 0x80800000);
1439 }
1440 break;
69b91039 1441 default:
4c7634bc 1442 default_map:
69b91039 1443 /* default memory mappings */
8a8696a3 1444 for(i = 0; i < PCI_NUM_REGIONS; i++) {
69b91039
FB		 1445 r = &d->io_regions[i];
1446 if (r->size) {
1447 if (r->type & PCI_ADDRESS_SPACE_IO)
1448 paddr = &pci_bios_io_addr;
1449 else
1450 paddr = &pci_bios_mem_addr;
1451 *paddr = (*paddr + r->size - 1) & ~(r->size - 1);
1452 pci_set_io_region_addr(d, i, *paddr);
1453 *paddr += r->size;
1454 }
1455 }
1456 break;
1457 }
0ac32c83
FB		 1458
1459 /* map the interrupt */
1460 pin = pci_config_readb(d, PCI_INTERRUPT_PIN);
1461 if (pin != 0) {
1462 pin = pci_slot_get_pirq(d, pin - 1);
1463 pic_irq = pci_irqs[pin];
1464 pci_config_writeb(d, PCI_INTERRUPT_LINE, pic_irq);
1465 }
69b91039
FB		 1466}
1467
1468/*
1469 * This function initializes the PCI devices as a normal PCI BIOS
1470 * would do. It is provided just in case the BIOS has no support for
1471 * PCI.
1472 */
1473void pci_bios_init(void)
1474{
30468f78
FB		 1475 PCIBus *bus;
1476 PCIDevice *d;
1477 int devfn, i, irq;
0ac32c83 1478 uint8_t elcr[2];
69b91039
FB		 1479
1480 pci_bios_io_addr = 0xc000;
1481 pci_bios_mem_addr = 0xf0000000;
1482
0ac32c83
FB		 1483 /* activate IRQ mappings */
1484 elcr[0] = 0x00;
1485 elcr[1] = 0x00;
1486 for(i = 0; i < 4; i++) {
1487 irq = pci_irqs[i];
1488 /* set to trigger level */
1489 elcr[irq >> 3] |= (1 << (irq & 7));
1490 /* activate irq remapping in PIIX */
1491 pci_config_writeb((PCIDevice *)piix3_state, 0x60 + i, irq);
1492 }
1493 isa_outb(elcr[0], 0x4d0);
1494 isa_outb(elcr[1], 0x4d1);
1495
30468f78
FB		 1496 bus = first_bus;
1497 if (bus) {
1498 for(devfn = 0; devfn < 256; devfn++) {
1499 d = bus->devices[devfn];
1500 if (d)
1501 pci_bios_init_device(d);
77d4bc34
FB		 1502 }
1503 }
1504}
Qemu copy for testing