[qemu.git] / hw / pxa2xx_timer.c

/*
 * Intel XScale PXA255/270 OS Timers.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Copyright (c) 2006 Thorsten Zitterell
 *
 * This code is licensed under the GPL.
 */

#include "hw.h"
#include "qemu-timer.h"
#include "sysemu.h"
#include "pxa.h"
#include "sysbus.h"

#define OSMR0	0x00
#define OSMR1	0x04
#define OSMR2	0x08
#define OSMR3	0x0c
#define OSMR4	0x80
#define OSMR5	0x84
#define OSMR6	0x88
#define OSMR7	0x8c
#define OSMR8	0x90
#define OSMR9	0x94
#define OSMR10	0x98
#define OSMR11	0x9c
#define OSCR	0x10	/* OS Timer Count */
#define OSCR4	0x40
#define OSCR5	0x44
#define OSCR6	0x48
#define OSCR7	0x4c
#define OSCR8	0x50
#define OSCR9	0x54
#define OSCR10	0x58
#define OSCR11	0x5c
#define OSSR	0x14	/* Timer status register */
#define OWER	0x18
#define OIER	0x1c	/* Interrupt enable register  3-0 to E3-E0 */
#define OMCR4	0xc0	/* OS Match Control registers */
#define OMCR5	0xc4
#define OMCR6	0xc8
#define OMCR7	0xcc
#define OMCR8	0xd0
#define OMCR9	0xd4
#define OMCR10	0xd8
#define OMCR11	0xdc
#define OSNR	0x20

#define PXA25X_FREQ	3686400	/* 3.6864 MHz */
#define PXA27X_FREQ	3250000	/* 3.25 MHz */

static int pxa2xx_timer4_freq[8] = {
    [0] = 0,
    [1] = 32768,
    [2] = 1000,
    [3] = 1,
    [4] = 1000000,
    /* [5] is the "Externally supplied clock".  Assign if necessary.  */
    [5 ... 7] = 0,
};

typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;

typedef struct {
    uint32_t value;
    qemu_irq irq;
    QEMUTimer *qtimer;
    int num;
    PXA2xxTimerInfo *info;
} PXA2xxTimer0;

typedef struct {
    PXA2xxTimer0 tm;
    int32_t oldclock;
    int32_t clock;
    uint64_t lastload;
    uint32_t freq;
    uint32_t control;
} PXA2xxTimer4;

struct PXA2xxTimerInfo {
    SysBusDevice busdev;
    uint32_t flags;

    int32_t clock;
    int32_t oldclock;
    uint64_t lastload;
    uint32_t freq;
    PXA2xxTimer0 timer[4];
    uint32_t events;
    uint32_t irq_enabled;
    uint32_t reset3;
    uint32_t snapshot;

    qemu_irq irq4;
    PXA2xxTimer4 tm4[8];
};

#define PXA2XX_TIMER_HAVE_TM4	0

static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
{
    return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
}

static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int i;
    uint32_t now_vm;
    uint64_t new_qemu;

    now_vm = s->clock +
            muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec());

    for (i = 0; i < 4; i ++) {
        new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
                        get_ticks_per_sec(), s->freq);
        qemu_mod_timer(s->timer[i].qtimer, new_qemu);
    }
}

static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    uint32_t now_vm;
    uint64_t new_qemu;
    static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
    int counter;

    if (s->tm4[n].control & (1 << 7))
        counter = n;
    else
        counter = counters[n];

    if (!s->tm4[counter].freq) {
        qemu_del_timer(s->tm4[n].tm.qtimer);
        return;
    }

    now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
                    s->tm4[counter].lastload,
                    s->tm4[counter].freq, get_ticks_per_sec());

    new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
                    get_ticks_per_sec(), s->tm4[counter].freq);
    qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
}

static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int tm = 0;

    switch (offset) {
    case OSMR3:  tm ++;
    case OSMR2:  tm ++;
    case OSMR1:  tm ++;
    case OSMR0:
        return s->timer[tm].value;
    case OSMR11: tm ++;
    case OSMR10: tm ++;
    case OSMR9:  tm ++;
    case OSMR8:  tm ++;
    case OSMR7:  tm ++;
    case OSMR6:  tm ++;
    case OSMR5:  tm ++;
    case OSMR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        return s->tm4[tm].tm.value;
    case OSCR:
        return s->clock + muldiv64(qemu_get_clock_ns(vm_clock) -
                        s->lastload, s->freq, get_ticks_per_sec());
    case OSCR11: tm ++;
    case OSCR10: tm ++;
    case OSCR9:  tm ++;
    case OSCR8:  tm ++;
    case OSCR7:  tm ++;
    case OSCR6:  tm ++;
    case OSCR5:  tm ++;
    case OSCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;

        if ((tm == 9 - 4 || tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
            if (s->tm4[tm - 1].freq)
                s->snapshot = s->tm4[tm - 1].clock + muldiv64(
                                qemu_get_clock_ns(vm_clock) -
                                s->tm4[tm - 1].lastload,
                                s->tm4[tm - 1].freq, get_ticks_per_sec());
            else
                s->snapshot = s->tm4[tm - 1].clock;
        }

        if (!s->tm4[tm].freq)
            return s->tm4[tm].clock;
        return s->tm4[tm].clock + muldiv64(qemu_get_clock_ns(vm_clock) -
                        s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
    case OIER:
        return s->irq_enabled;
    case OSSR:	/* Status register */
        return s->events;
    case OWER:
        return s->reset3;
    case OMCR11: tm ++;
    case OMCR10: tm ++;
    case OMCR9:  tm ++;
    case OMCR8:  tm ++;
    case OMCR7:  tm ++;
    case OMCR6:  tm ++;
    case OMCR5:  tm ++;
    case OMCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        return s->tm4[tm].control;
    case OSNR:
        return s->snapshot;
    default:
    badreg:
        hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
    }

    return 0;
}

static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
                uint32_t value)
{
    int i, tm = 0;
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;

    switch (offset) {
    case OSMR3:  tm ++;
    case OSMR2:  tm ++;
    case OSMR1:  tm ++;
    case OSMR0:
        s->timer[tm].value = value;
        pxa2xx_timer_update(s, qemu_get_clock_ns(vm_clock));
        break;
    case OSMR11: tm ++;
    case OSMR10: tm ++;
    case OSMR9:  tm ++;
    case OSMR8:  tm ++;
    case OSMR7:  tm ++;
    case OSMR6:  tm ++;
    case OSMR5:  tm ++;
    case OSMR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].tm.value = value;
        pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
        break;
    case OSCR:
        s->oldclock = s->clock;
        s->lastload = qemu_get_clock_ns(vm_clock);
        s->clock = value;
        pxa2xx_timer_update(s, s->lastload);
        break;
    case OSCR11: tm ++;
    case OSCR10: tm ++;
    case OSCR9:  tm ++;
    case OSCR8:  tm ++;
    case OSCR7:  tm ++;
    case OSCR6:  tm ++;
    case OSCR5:  tm ++;
    case OSCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].oldclock = s->tm4[tm].clock;
        s->tm4[tm].lastload = qemu_get_clock_ns(vm_clock);
        s->tm4[tm].clock = value;
        pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
        break;
    case OIER:
        s->irq_enabled = value & 0xfff;
        break;
    case OSSR:	/* Status register */
        value &= s->events;
        s->events &= ~value;
        for (i = 0; i < 4; i ++, value >>= 1)
            if (value & 1)
                qemu_irq_lower(s->timer[i].irq);
        if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
            qemu_irq_lower(s->irq4);
        break;
    case OWER:	/* XXX: Reset on OSMR3 match? */
        s->reset3 = value;
        break;
    case OMCR7:  tm ++;
    case OMCR6:  tm ++;
    case OMCR5:  tm ++;
    case OMCR4:
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].control = value & 0x0ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || tm == 0)
            s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
        }
        break;
    case OMCR11: tm ++;
    case OMCR10: tm ++;
    case OMCR9:  tm ++;
    case OMCR8:  tm += 4;
        if (!pxa2xx_timer_has_tm4(s))
            goto badreg;
        s->tm4[tm].control = value & 0x3ff;
        /* XXX Stop if running (shouldn't happen) */
        if ((value & (1 << 7)) || !(tm & 1))
            s->tm4[tm].freq =
                    pxa2xx_timer4_freq[(value & (1 << 8)) ?  0 : (value & 7)];
        else {
            s->tm4[tm].freq = 0;
            pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
        }
        break;
    default:
    badreg:
        hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
    }
}

static CPUReadMemoryFunc * const pxa2xx_timer_readfn[] = {
    pxa2xx_timer_read,
    pxa2xx_timer_read,
    pxa2xx_timer_read,
};

static CPUWriteMemoryFunc * const pxa2xx_timer_writefn[] = {
    pxa2xx_timer_write,
    pxa2xx_timer_write,
    pxa2xx_timer_write,
};

static void pxa2xx_timer_tick(void *opaque)
{
    PXA2xxTimer0 *t = (PXA2xxTimer0 *) opaque;
    PXA2xxTimerInfo *i = t->info;

    if (i->irq_enabled & (1 << t->num)) {
        i->events |= 1 << t->num;
        qemu_irq_raise(t->irq);
    }

    if (t->num == 3)
        if (i->reset3 & 1) {
            i->reset3 = 0;
            qemu_system_reset_request();
        }
}

static void pxa2xx_timer_tick4(void *opaque)
{
    PXA2xxTimer4 *t = (PXA2xxTimer4 *) opaque;
    PXA2xxTimerInfo *i = (PXA2xxTimerInfo *) t->tm.info;

    pxa2xx_timer_tick(&t->tm);
    if (t->control & (1 << 3))
        t->clock = 0;
    if (t->control & (1 << 6))
        pxa2xx_timer_update4(i, qemu_get_clock_ns(vm_clock), t->tm.num - 4);
    if (i->events & 0xff0)
        qemu_irq_raise(i->irq4);
}

static int pxa25x_timer_post_load(void *opaque, int version_id)
{
    PXA2xxTimerInfo *s = (PXA2xxTimerInfo *) opaque;
    int64_t now;
    int i;

    now = qemu_get_clock_ns(vm_clock);
    pxa2xx_timer_update(s, now);

    if (pxa2xx_timer_has_tm4(s))
        for (i = 0; i < 8; i ++)
            pxa2xx_timer_update4(s, now, i);

    return 0;
}

static int pxa2xx_timer_init(SysBusDevice *dev)
{
    int i;
    int iomemtype;
    PXA2xxTimerInfo *s;

    s = FROM_SYSBUS(PXA2xxTimerInfo, dev);
    s->irq_enabled = 0;
    s->oldclock = 0;
    s->clock = 0;
    s->lastload = qemu_get_clock_ns(vm_clock);
    s->reset3 = 0;

    for (i = 0; i < 4; i ++) {
        s->timer[i].value = 0;
        sysbus_init_irq(dev, &s->timer[i].irq);
        s->timer[i].info = s;
        s->timer[i].num = i;
        s->timer[i].qtimer = qemu_new_timer_ns(vm_clock,
                        pxa2xx_timer_tick, &s->timer[i]);
    }
    if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
        sysbus_init_irq(dev, &s->irq4);

        for (i = 0; i < 8; i ++) {
            s->tm4[i].tm.value = 0;
            s->tm4[i].tm.info = s;
            s->tm4[i].tm.num = i + 4;
            s->tm4[i].freq = 0;
            s->tm4[i].control = 0x0;
            s->tm4[i].tm.qtimer = qemu_new_timer_ns(vm_clock,
                        pxa2xx_timer_tick4, &s->tm4[i]);
        }
    }

    iomemtype = cpu_register_io_memory(pxa2xx_timer_readfn,
                    pxa2xx_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, 0x00001000, iomemtype);

    return 0;
}

static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
    .name = "pxa2xx_timer0",
    .version_id = 2,
    .minimum_version_id = 2,
    .minimum_version_id_old = 2,
    .fields = (VMStateField[]) {
        VMSTATE_UINT32(value, PXA2xxTimer0),
        VMSTATE_END_OF_LIST(),
    },
};

static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
    .name = "pxa2xx_timer4",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .fields = (VMStateField[]) {
        VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
                        vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
        VMSTATE_INT32(oldclock, PXA2xxTimer4),
        VMSTATE_INT32(clock, PXA2xxTimer4),
        VMSTATE_UINT64(lastload, PXA2xxTimer4),
        VMSTATE_UINT32(freq, PXA2xxTimer4),
        VMSTATE_UINT32(control, PXA2xxTimer4),
        VMSTATE_END_OF_LIST(),
    },
};

static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
{
    return pxa2xx_timer_has_tm4(opaque);
}

static const VMStateDescription vmstate_pxa2xx_timer_regs = {
    .name = "pxa2xx_timer",
    .version_id = 1,
    .minimum_version_id = 1,
    .minimum_version_id_old = 1,
    .post_load = pxa25x_timer_post_load,
    .fields = (VMStateField[]) {
        VMSTATE_INT32(clock, PXA2xxTimerInfo),
        VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
        VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
        VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
                        vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
        VMSTATE_UINT32(events, PXA2xxTimerInfo),
        VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
        VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
        VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
        VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
                        pxa2xx_timer_has_tm4_test, 0,
                        vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
        VMSTATE_END_OF_LIST(),
    }
};

static SysBusDeviceInfo pxa25x_timer_dev_info = {
    .init       = pxa2xx_timer_init,
    .qdev.name  = "pxa25x-timer",
    .qdev.desc  = "PXA25x timer",
    .qdev.size  = sizeof(PXA2xxTimerInfo),
    .qdev.vmsd  = &vmstate_pxa2xx_timer_regs,
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
        DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
                        PXA2XX_TIMER_HAVE_TM4, false),
        DEFINE_PROP_END_OF_LIST(),
    },
};

static SysBusDeviceInfo pxa27x_timer_dev_info = {
    .init       = pxa2xx_timer_init,
    .qdev.name  = "pxa27x-timer",
    .qdev.desc  = "PXA27x timer",
    .qdev.size  = sizeof(PXA2xxTimerInfo),
    .qdev.vmsd  = &vmstate_pxa2xx_timer_regs,
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
        DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
                        PXA2XX_TIMER_HAVE_TM4, true),
        DEFINE_PROP_END_OF_LIST(),
    },
};

static void pxa2xx_timer_register(void)
{
    sysbus_register_withprop(&pxa25x_timer_dev_info);
    sysbus_register_withprop(&pxa27x_timer_dev_info);
};
device_init(pxa2xx_timer_register);
Commit	Line	Data
a171fe39 AZ	1	/*
	2	* Intel XScale PXA255/270 OS Timers.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Copyright (c) 2006 Thorsten Zitterell
	6	*
8e31bf38	7	* This code is licensed under the GPL.
a171fe39 AZ	8	*/
a171fe39 AZ	9
87ecb68b PB	10	#include "hw.h"
	11	#include "qemu-timer.h"
	12	#include "sysemu.h"
	13	#include "pxa.h"
797e9542	14	#include "sysbus.h"
a171fe39 AZ	15
	16	#define OSMR0 0x00
	17	#define OSMR1 0x04
	18	#define OSMR2 0x08
	19	#define OSMR3 0x0c
	20	#define OSMR4 0x80
	21	#define OSMR5 0x84
	22	#define OSMR6 0x88
	23	#define OSMR7 0x8c
	24	#define OSMR8 0x90
	25	#define OSMR9 0x94
	26	#define OSMR10 0x98
	27	#define OSMR11 0x9c
	28	#define OSCR 0x10 /* OS Timer Count */
	29	#define OSCR4 0x40
	30	#define OSCR5 0x44
	31	#define OSCR6 0x48
	32	#define OSCR7 0x4c
	33	#define OSCR8 0x50
	34	#define OSCR9 0x54
	35	#define OSCR10 0x58
	36	#define OSCR11 0x5c
	37	#define OSSR 0x14 /* Timer status register */
	38	#define OWER 0x18
	39	#define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
	40	#define OMCR4 0xc0 /* OS Match Control registers */
	41	#define OMCR5 0xc4
	42	#define OMCR6 0xc8
	43	#define OMCR7 0xcc
	44	#define OMCR8 0xd0
	45	#define OMCR9 0xd4
	46	#define OMCR10 0xd8
	47	#define OMCR11 0xdc
	48	#define OSNR 0x20
	49
	50	#define PXA25X_FREQ 3686400 /* 3.6864 MHz */
	51	#define PXA27X_FREQ 3250000 /* 3.25 MHz */
	52
	53	static int pxa2xx_timer4_freq[8] = {
	54	[0] = 0,
	55	[1] = 32768,
	56	[2] = 1000,
	57	[3] = 1,
	58	[4] = 1000000,
	59	/* [5] is the "Externally supplied clock". Assign if necessary. */
	60	[5 ... 7] = 0,
	61	};
	62
797e9542 DES	63	typedef struct PXA2xxTimerInfo PXA2xxTimerInfo;
797e9542 DES	64
bc24a225	65	typedef struct {
a171fe39	66	uint32_t value;
5251d196	67	qemu_irq irq;
a171fe39 AZ	68	QEMUTimer *qtimer;
a171fe39 AZ	69	int num;
797e9542	70	PXA2xxTimerInfo *info;
bc24a225	71	} PXA2xxTimer0;
a171fe39	72
bc24a225 PB	73	typedef struct {
bc24a225 PB	74	PXA2xxTimer0 tm;
a171fe39 AZ	75	int32_t oldclock;
	76	int32_t clock;
	77	uint64_t lastload;
	78	uint32_t freq;
	79	uint32_t control;
bc24a225	80	} PXA2xxTimer4;
a171fe39	81
797e9542 DES	82	struct PXA2xxTimerInfo {
	83	SysBusDevice busdev;
	84	uint32_t flags;
	85
a171fe39 AZ	86	int32_t clock;
	87	int32_t oldclock;
	88	uint64_t lastload;
	89	uint32_t freq;
bc24a225	90	PXA2xxTimer0 timer[4];
a171fe39 AZ	91	uint32_t events;
	92	uint32_t irq_enabled;
	93	uint32_t reset3;
a171fe39	94	uint32_t snapshot;
797e9542	95
4ff927cc	96	qemu_irq irq4;
797e9542	97	PXA2xxTimer4 tm4[8];
797e9542 DES	98	};
	99
	100	#define PXA2XX_TIMER_HAVE_TM4 0
	101
	102	static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo *s)
	103	{
	104	return s->flags & (1 << PXA2XX_TIMER_HAVE_TM4);
	105	}
a171fe39 AZ	106
	107	static void pxa2xx_timer_update(void *opaque, uint64_t now_qemu)
	108	{
d353eb43	109	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	110	int i;
	111	uint32_t now_vm;
	112	uint64_t new_qemu;
	113
	114	now_vm = s->clock +
6ee093c9	115	muldiv64(now_qemu - s->lastload, s->freq, get_ticks_per_sec());
a171fe39 AZ	116
	117	for (i = 0; i < 4; i ++) {
	118	new_qemu = now_qemu + muldiv64((uint32_t) (s->timer[i].value - now_vm),
6ee093c9	119	get_ticks_per_sec(), s->freq);
a171fe39 AZ	120	qemu_mod_timer(s->timer[i].qtimer, new_qemu);
	121	}
	122	}
	123
	124	static void pxa2xx_timer_update4(void *opaque, uint64_t now_qemu, int n)
	125	{
d353eb43	126	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	127	uint32_t now_vm;
	128	uint64_t new_qemu;
	129	static const int counters[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
	130	int counter;
	131
	132	if (s->tm4[n].control & (1 << 7))
	133	counter = n;
	134	else
	135	counter = counters[n];
	136
	137	if (!s->tm4[counter].freq) {
3f582262	138	qemu_del_timer(s->tm4[n].tm.qtimer);
a171fe39 AZ	139	return;
	140	}
	141
	142	now_vm = s->tm4[counter].clock + muldiv64(now_qemu -
	143	s->tm4[counter].lastload,
6ee093c9	144	s->tm4[counter].freq, get_ticks_per_sec());
a171fe39	145
3bdd58a4	146	new_qemu = now_qemu + muldiv64((uint32_t) (s->tm4[n].tm.value - now_vm),
6ee093c9	147	get_ticks_per_sec(), s->tm4[counter].freq);
3f582262	148	qemu_mod_timer(s->tm4[n].tm.qtimer, new_qemu);
a171fe39 AZ	149	}
a171fe39 AZ	150
c227f099	151	static uint32_t pxa2xx_timer_read(void *opaque, target_phys_addr_t offset)
a171fe39	152	{
d353eb43	153	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39 AZ	154	int tm = 0;
a171fe39 AZ	155
a171fe39 AZ	156	switch (offset) {
	157	case OSMR3: tm ++;
	158	case OSMR2: tm ++;
	159	case OSMR1: tm ++;
	160	case OSMR0:
	161	return s->timer[tm].value;
	162	case OSMR11: tm ++;
	163	case OSMR10: tm ++;
	164	case OSMR9: tm ++;
	165	case OSMR8: tm ++;
	166	case OSMR7: tm ++;
	167	case OSMR6: tm ++;
	168	case OSMR5: tm ++;
	169	case OSMR4:
797e9542	170	if (!pxa2xx_timer_has_tm4(s))
a171fe39	171	goto badreg;
3bdd58a4	172	return s->tm4[tm].tm.value;
a171fe39	173	case OSCR:
74475455	174	return s->clock + muldiv64(qemu_get_clock_ns(vm_clock) -
6ee093c9	175	s->lastload, s->freq, get_ticks_per_sec());
a171fe39 AZ	176	case OSCR11: tm ++;
	177	case OSCR10: tm ++;
	178	case OSCR9: tm ++;
	179	case OSCR8: tm ++;
	180	case OSCR7: tm ++;
	181	case OSCR6: tm ++;
	182	case OSCR5: tm ++;
	183	case OSCR4:
797e9542	184	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	185	goto badreg;
	186
	187	if ((tm == 9 - 4 \|\| tm == 11 - 4) && (s->tm4[tm].control & (1 << 9))) {
	188	if (s->tm4[tm - 1].freq)
	189	s->snapshot = s->tm4[tm - 1].clock + muldiv64(
74475455	190	qemu_get_clock_ns(vm_clock) -
a171fe39	191	s->tm4[tm - 1].lastload,
6ee093c9	192	s->tm4[tm - 1].freq, get_ticks_per_sec());
a171fe39 AZ	193	else
	194	s->snapshot = s->tm4[tm - 1].clock;
	195	}
	196
	197	if (!s->tm4[tm].freq)
	198	return s->tm4[tm].clock;
74475455	199	return s->tm4[tm].clock + muldiv64(qemu_get_clock_ns(vm_clock) -
6ee093c9	200	s->tm4[tm].lastload, s->tm4[tm].freq, get_ticks_per_sec());
a171fe39 AZ	201	case OIER:
	202	return s->irq_enabled;
	203	case OSSR: /* Status register */
	204	return s->events;
	205	case OWER:
	206	return s->reset3;
	207	case OMCR11: tm ++;
	208	case OMCR10: tm ++;
	209	case OMCR9: tm ++;
	210	case OMCR8: tm ++;
	211	case OMCR7: tm ++;
	212	case OMCR6: tm ++;
	213	case OMCR5: tm ++;
	214	case OMCR4:
797e9542	215	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	216	goto badreg;
	217	return s->tm4[tm].control;
	218	case OSNR:
	219	return s->snapshot;
	220	default:
	221	badreg:
2ac71179	222	hw_error("pxa2xx_timer_read: Bad offset " REG_FMT "\n", offset);
a171fe39 AZ	223	}
	224
	225	return 0;
	226	}
	227
c227f099	228	static void pxa2xx_timer_write(void *opaque, target_phys_addr_t offset,
a171fe39 AZ	229	uint32_t value)
	230	{
	231	int i, tm = 0;
d353eb43	232	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
a171fe39	233
a171fe39 AZ	234	switch (offset) {
	235	case OSMR3: tm ++;
	236	case OSMR2: tm ++;
	237	case OSMR1: tm ++;
	238	case OSMR0:
	239	s->timer[tm].value = value;
74475455	240	pxa2xx_timer_update(s, qemu_get_clock_ns(vm_clock));
a171fe39 AZ	241	break;
	242	case OSMR11: tm ++;
	243	case OSMR10: tm ++;
	244	case OSMR9: tm ++;
	245	case OSMR8: tm ++;
	246	case OSMR7: tm ++;
	247	case OSMR6: tm ++;
	248	case OSMR5: tm ++;
	249	case OSMR4:
797e9542	250	if (!pxa2xx_timer_has_tm4(s))
a171fe39	251	goto badreg;
3bdd58a4	252	s->tm4[tm].tm.value = value;
74475455	253	pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
a171fe39 AZ	254	break;
	255	case OSCR:
	256	s->oldclock = s->clock;
74475455	257	s->lastload = qemu_get_clock_ns(vm_clock);
a171fe39 AZ	258	s->clock = value;
	259	pxa2xx_timer_update(s, s->lastload);
	260	break;
	261	case OSCR11: tm ++;
	262	case OSCR10: tm ++;
	263	case OSCR9: tm ++;
	264	case OSCR8: tm ++;
	265	case OSCR7: tm ++;
	266	case OSCR6: tm ++;
	267	case OSCR5: tm ++;
	268	case OSCR4:
797e9542	269	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	270	goto badreg;
a171fe39 AZ	271	s->tm4[tm].oldclock = s->tm4[tm].clock;
74475455	272	s->tm4[tm].lastload = qemu_get_clock_ns(vm_clock);
a171fe39 AZ	273	s->tm4[tm].clock = value;
	274	pxa2xx_timer_update4(s, s->tm4[tm].lastload, tm);
	275	break;
	276	case OIER:
	277	s->irq_enabled = value & 0xfff;
	278	break;
	279	case OSSR: /* Status register */
8034ce7d	280	value &= s->events;
a171fe39	281	s->events &= ~value;
8034ce7d AZ	282	for (i = 0; i < 4; i ++, value >>= 1)
8034ce7d AZ	283	if (value & 1)
5251d196	284	qemu_irq_lower(s->timer[i].irq);
8034ce7d AZ	285	if (pxa2xx_timer_has_tm4(s) && !(s->events & 0xff0) && value)
8034ce7d AZ	286	qemu_irq_lower(s->irq4);
a171fe39 AZ	287	break;
	288	case OWER: /* XXX: Reset on OSMR3 match? */
	289	s->reset3 = value;
	290	break;
	291	case OMCR7: tm ++;
	292	case OMCR6: tm ++;
	293	case OMCR5: tm ++;
	294	case OMCR4:
797e9542	295	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	296	goto badreg;
	297	s->tm4[tm].control = value & 0x0ff;
	298	/* XXX Stop if running (shouldn't happen) */
	299	if ((value & (1 << 7)) \|\| tm == 0)
	300	s->tm4[tm].freq = pxa2xx_timer4_freq[value & 7];
	301	else {
	302	s->tm4[tm].freq = 0;
74475455	303	pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
a171fe39 AZ	304	}
	305	break;
	306	case OMCR11: tm ++;
	307	case OMCR10: tm ++;
	308	case OMCR9: tm ++;
	309	case OMCR8: tm += 4;
797e9542	310	if (!pxa2xx_timer_has_tm4(s))
a171fe39 AZ	311	goto badreg;
	312	s->tm4[tm].control = value & 0x3ff;
	313	/* XXX Stop if running (shouldn't happen) */
	314	if ((value & (1 << 7)) \|\| !(tm & 1))
	315	s->tm4[tm].freq =
	316	pxa2xx_timer4_freq[(value & (1 << 8)) ? 0 : (value & 7)];
	317	else {
	318	s->tm4[tm].freq = 0;
74475455	319	pxa2xx_timer_update4(s, qemu_get_clock_ns(vm_clock), tm);
a171fe39 AZ	320	}
	321	break;
	322	default:
	323	badreg:
2ac71179	324	hw_error("pxa2xx_timer_write: Bad offset " REG_FMT "\n", offset);
a171fe39 AZ	325	}
	326	}
	327
d60efc6b	328	static CPUReadMemoryFunc * const pxa2xx_timer_readfn[] = {
a171fe39 AZ	329	pxa2xx_timer_read,
	330	pxa2xx_timer_read,
	331	pxa2xx_timer_read,
	332	};
	333
d60efc6b	334	static CPUWriteMemoryFunc * const pxa2xx_timer_writefn[] = {
a171fe39 AZ	335	pxa2xx_timer_write,
	336	pxa2xx_timer_write,
	337	pxa2xx_timer_write,
	338	};
	339
	340	static void pxa2xx_timer_tick(void *opaque)
	341	{
bc24a225	342	PXA2xxTimer0 t = (PXA2xxTimer0 ) opaque;
797e9542	343	PXA2xxTimerInfo *i = t->info;
a171fe39 AZ	344
a171fe39 AZ	345	if (i->irq_enabled & (1 << t->num)) {
a171fe39	346	i->events \|= 1 << t->num;
5251d196	347	qemu_irq_raise(t->irq);
a171fe39 AZ	348	}
	349
	350	if (t->num == 3)
	351	if (i->reset3 & 1) {
	352	i->reset3 = 0;
3f582262	353	qemu_system_reset_request();
a171fe39 AZ	354	}
	355	}
	356
	357	static void pxa2xx_timer_tick4(void *opaque)
	358	{
bc24a225	359	PXA2xxTimer4 t = (PXA2xxTimer4 ) opaque;
d353eb43	360	PXA2xxTimerInfo i = (PXA2xxTimerInfo ) t->tm.info;
a171fe39	361
3bdd58a4	362	pxa2xx_timer_tick(&t->tm);
a171fe39 AZ	363	if (t->control & (1 << 3))
	364	t->clock = 0;
	365	if (t->control & (1 << 6))
74475455	366	pxa2xx_timer_update4(i, qemu_get_clock_ns(vm_clock), t->tm.num - 4);
4ff927cc DES	367	if (i->events & 0xff0)
4ff927cc DES	368	qemu_irq_raise(i->irq4);
a171fe39 AZ	369	}
a171fe39 AZ	370
797e9542	371	static int pxa25x_timer_post_load(void *opaque, int version_id)
aa941b94	372	{
d353eb43	373	PXA2xxTimerInfo s = (PXA2xxTimerInfo ) opaque;
aa941b94 AZ	374	int64_t now;
	375	int i;
	376
74475455	377	now = qemu_get_clock_ns(vm_clock);
aa941b94 AZ	378	pxa2xx_timer_update(s, now);
aa941b94 AZ	379
797e9542 DES	380	if (pxa2xx_timer_has_tm4(s))
797e9542 DES	381	for (i = 0; i < 8; i ++)
aa941b94	382	pxa2xx_timer_update4(s, now, i);
aa941b94 AZ	383
	384	return 0;
	385	}
	386
797e9542	387	static int pxa2xx_timer_init(SysBusDevice *dev)
a171fe39 AZ	388	{
	389	int i;
	390	int iomemtype;
d353eb43	391	PXA2xxTimerInfo *s;
a171fe39	392
797e9542	393	s = FROM_SYSBUS(PXA2xxTimerInfo, dev);
a171fe39 AZ	394	s->irq_enabled = 0;
	395	s->oldclock = 0;
	396	s->clock = 0;
74475455	397	s->lastload = qemu_get_clock_ns(vm_clock);
a171fe39	398	s->reset3 = 0;
a171fe39 AZ	399
	400	for (i = 0; i < 4; i ++) {
	401	s->timer[i].value = 0;
5251d196	402	sysbus_init_irq(dev, &s->timer[i].irq);
a171fe39 AZ	403	s->timer[i].info = s;
a171fe39 AZ	404	s->timer[i].num = i;
74475455	405	s->timer[i].qtimer = qemu_new_timer_ns(vm_clock,
a171fe39 AZ	406	pxa2xx_timer_tick, &s->timer[i]);
a171fe39 AZ	407	}
797e9542	408	if (s->flags & (1 << PXA2XX_TIMER_HAVE_TM4)) {
4ff927cc	409	sysbus_init_irq(dev, &s->irq4);
797e9542 DES	410
	411	for (i = 0; i < 8; i ++) {
	412	s->tm4[i].tm.value = 0;
	413	s->tm4[i].tm.info = s;
	414	s->tm4[i].tm.num = i + 4;
797e9542 DES	415	s->tm4[i].freq = 0;
797e9542 DES	416	s->tm4[i].control = 0x0;
74475455	417	s->tm4[i].tm.qtimer = qemu_new_timer_ns(vm_clock,
797e9542 DES	418	pxa2xx_timer_tick4, &s->tm4[i]);
	419	}
	420	}
a171fe39	421
1eed09cb	422	iomemtype = cpu_register_io_memory(pxa2xx_timer_readfn,
2507c12a	423	pxa2xx_timer_writefn, s, DEVICE_NATIVE_ENDIAN);
797e9542	424	sysbus_init_mmio(dev, 0x00001000, iomemtype);
aa941b94	425
797e9542	426	return 0;
a171fe39 AZ	427	}
a171fe39 AZ	428
797e9542 DES	429	static const VMStateDescription vmstate_pxa2xx_timer0_regs = {
797e9542 DES	430	.name = "pxa2xx_timer0",
8034ce7d AZ	431	.version_id = 2,
	432	.minimum_version_id = 2,
	433	.minimum_version_id_old = 2,
797e9542 DES	434	.fields = (VMStateField[]) {
797e9542 DES	435	VMSTATE_UINT32(value, PXA2xxTimer0),
797e9542 DES	436	VMSTATE_END_OF_LIST(),
	437	},
	438	};
	439
	440	static const VMStateDescription vmstate_pxa2xx_timer4_regs = {
	441	.name = "pxa2xx_timer4",
	442	.version_id = 1,
	443	.minimum_version_id = 1,
	444	.minimum_version_id_old = 1,
	445	.fields = (VMStateField[]) {
	446	VMSTATE_STRUCT(tm, PXA2xxTimer4, 1,
	447	vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
	448	VMSTATE_INT32(oldclock, PXA2xxTimer4),
	449	VMSTATE_INT32(clock, PXA2xxTimer4),
	450	VMSTATE_UINT64(lastload, PXA2xxTimer4),
	451	VMSTATE_UINT32(freq, PXA2xxTimer4),
	452	VMSTATE_UINT32(control, PXA2xxTimer4),
	453	VMSTATE_END_OF_LIST(),
	454	},
	455	};
	456
	457	static bool pxa2xx_timer_has_tm4_test(void *opaque, int version_id)
a171fe39	458	{
797e9542	459	return pxa2xx_timer_has_tm4(opaque);
a171fe39 AZ	460	}
a171fe39 AZ	461
797e9542 DES	462	static const VMStateDescription vmstate_pxa2xx_timer_regs = {
	463	.name = "pxa2xx_timer",
	464	.version_id = 1,
	465	.minimum_version_id = 1,
	466	.minimum_version_id_old = 1,
	467	.post_load = pxa25x_timer_post_load,
	468	.fields = (VMStateField[]) {
	469	VMSTATE_INT32(clock, PXA2xxTimerInfo),
	470	VMSTATE_INT32(oldclock, PXA2xxTimerInfo),
	471	VMSTATE_UINT64(lastload, PXA2xxTimerInfo),
	472	VMSTATE_STRUCT_ARRAY(timer, PXA2xxTimerInfo, 4, 1,
	473	vmstate_pxa2xx_timer0_regs, PXA2xxTimer0),
	474	VMSTATE_UINT32(events, PXA2xxTimerInfo),
	475	VMSTATE_UINT32(irq_enabled, PXA2xxTimerInfo),
	476	VMSTATE_UINT32(reset3, PXA2xxTimerInfo),
	477	VMSTATE_UINT32(snapshot, PXA2xxTimerInfo),
	478	VMSTATE_STRUCT_ARRAY_TEST(tm4, PXA2xxTimerInfo, 8,
	479	pxa2xx_timer_has_tm4_test, 0,
	480	vmstate_pxa2xx_timer4_regs, PXA2xxTimer4),
	481	VMSTATE_END_OF_LIST(),
a171fe39	482	}
797e9542 DES	483	};
	484
	485	static SysBusDeviceInfo pxa25x_timer_dev_info = {
	486	.init = pxa2xx_timer_init,
	487	.qdev.name = "pxa25x-timer",
	488	.qdev.desc = "PXA25x timer",
	489	.qdev.size = sizeof(PXA2xxTimerInfo),
	490	.qdev.vmsd = &vmstate_pxa2xx_timer_regs,
	491	.qdev.props = (Property[]) {
	492	DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ),
	493	DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
	494	PXA2XX_TIMER_HAVE_TM4, false),
	495	DEFINE_PROP_END_OF_LIST(),
	496	},
	497	};
	498
	499	static SysBusDeviceInfo pxa27x_timer_dev_info = {
	500	.init = pxa2xx_timer_init,
	501	.qdev.name = "pxa27x-timer",
	502	.qdev.desc = "PXA27x timer",
	503	.qdev.size = sizeof(PXA2xxTimerInfo),
	504	.qdev.vmsd = &vmstate_pxa2xx_timer_regs,
	505	.qdev.props = (Property[]) {
	506	DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA27X_FREQ),
	507	DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags,
	508	PXA2XX_TIMER_HAVE_TM4, true),
	509	DEFINE_PROP_END_OF_LIST(),
	510	},
	511	};
	512
	513	static void pxa2xx_timer_register(void)
	514	{
	515	sysbus_register_withprop(&pxa25x_timer_dev_info);
	516	sysbus_register_withprop(&pxa27x_timer_dev_info);
	517	};
	518	device_init(pxa2xx_timer_register);