[qemu.git] / hw / r2d.c

/*
 * Renesas SH7751R R2D-PLUS emulation
 *
 * Copyright (c) 2007 Magnus Damm
 * Copyright (c) 2008 Paul Mundt
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "hw.h"
#include "sh.h"
#include "devices.h"
#include "sysemu/sysemu.h"
#include "boards.h"
#include "pci/pci.h"
#include "net/net.h"
#include "sh7750_regs.h"
#include "ide.h"
#include "loader.h"
#include "usb.h"
#include "flash.h"
#include "sysemu/blockdev.h"
#include "exec/address-spaces.h"

#define FLASH_BASE 0x00000000
#define FLASH_SIZE 0x02000000

#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
#define SDRAM_SIZE 0x04000000

#define SM501_VRAM_SIZE 0x800000

#define BOOT_PARAMS_OFFSET 0x0010000
/* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
#define LINUX_LOAD_OFFSET  0x0800000
#define INITRD_LOAD_OFFSET 0x1800000

#define PA_IRLMSK	0x00
#define PA_POWOFF	0x30
#define PA_VERREG	0x32
#define PA_OUTPORT	0x36

typedef struct {
    uint16_t bcr;
    uint16_t irlmsk;
    uint16_t irlmon;
    uint16_t cfctl;
    uint16_t cfpow;
    uint16_t dispctl;
    uint16_t sdmpow;
    uint16_t rtcce;
    uint16_t pcicd;
    uint16_t voyagerrts;
    uint16_t cfrst;
    uint16_t admrts;
    uint16_t extrst;
    uint16_t cfcdintclr;
    uint16_t keyctlclr;
    uint16_t pad0;
    uint16_t pad1;
    uint16_t verreg;
    uint16_t inport;
    uint16_t outport;
    uint16_t bverreg;

/* output pin */
    qemu_irq irl;
    MemoryRegion iomem;
} r2d_fpga_t;

enum r2d_fpga_irq {
    PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
    SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
    NR_IRQS
};

static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
    [CF_IDE]	= {  1, 1<<9 },
    [CF_CD]	= {  2, 1<<8 },
    [PCI_INTA]	= {  9, 1<<14 },
    [PCI_INTB]	= { 10, 1<<13 },
    [PCI_INTC]	= {  3, 1<<12 },
    [PCI_INTD]	= {  0, 1<<11 },
    [SM501]	= {  4, 1<<10 },
    [KEY]	= {  5, 1<<6 },
    [RTC_A]	= {  6, 1<<5 },
    [RTC_T]	= {  7, 1<<4 },
    [SDCARD]	= {  8, 1<<7 },
    [EXT]	= { 11, 1<<0 },
    [TP]	= { 12, 1<<15 },
};

static void update_irl(r2d_fpga_t *fpga)
{
    int i, irl = 15;
    for (i = 0; i < NR_IRQS; i++)
        if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
            if (irqtab[i].irl < irl)
                irl = irqtab[i].irl;
    qemu_set_irq(fpga->irl, irl ^ 15);
}

static void r2d_fpga_irq_set(void *opaque, int n, int level)
{
    r2d_fpga_t *fpga = opaque;
    if (level)
        fpga->irlmon |= irqtab[n].msk;
    else
        fpga->irlmon &= ~irqtab[n].msk;
    update_irl(fpga);
}

static uint32_t r2d_fpga_read(void *opaque, hwaddr addr)
{
    r2d_fpga_t *s = opaque;

    switch (addr) {
    case PA_IRLMSK:
        return s->irlmsk;
    case PA_OUTPORT:
	return s->outport;
    case PA_POWOFF:
	return 0x00;
    case PA_VERREG:
	return 0x10;
    }

    return 0;
}

static void
r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value)
{
    r2d_fpga_t *s = opaque;

    switch (addr) {
    case PA_IRLMSK:
        s->irlmsk = value;
        update_irl(s);
	break;
    case PA_OUTPORT:
	s->outport = value;
	break;
    case PA_POWOFF:
        if (value & 1) {
            qemu_system_shutdown_request();
        }
        break;
    case PA_VERREG:
	/* Discard writes */
	break;
    }
}

static const MemoryRegionOps r2d_fpga_ops = {
    .old_mmio = {
        .read = { r2d_fpga_read, r2d_fpga_read, NULL, },
        .write = { r2d_fpga_write, r2d_fpga_write, NULL, },
    },
    .endianness = DEVICE_NATIVE_ENDIAN,
};

static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem,
                               hwaddr base, qemu_irq irl)
{
    r2d_fpga_t *s;

    s = g_malloc0(sizeof(r2d_fpga_t));

    s->irl = irl;

    memory_region_init_io(&s->iomem, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
    memory_region_add_subregion(sysmem, base, &s->iomem);
    return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
}

typedef struct ResetData {
    SuperHCPU *cpu;
    uint32_t vector;
} ResetData;

static void main_cpu_reset(void *opaque)
{
    ResetData *s = (ResetData *)opaque;
    CPUSH4State *env = &s->cpu->env;

    cpu_reset(CPU(s->cpu));
    env->pc = s->vector;
}

static struct QEMU_PACKED
{
    int mount_root_rdonly;
    int ramdisk_flags;
    int orig_root_dev;
    int loader_type;
    int initrd_start;
    int initrd_size;

    char pad[232];

    char kernel_cmdline[256];
} boot_params;

static void r2d_init(QEMUMachineInitArgs *args)
{
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    const char *kernel_cmdline = args->kernel_cmdline;
    const char *initrd_filename = args->initrd_filename;
    SuperHCPU *cpu;
    CPUSH4State *env;
    ResetData *reset_info;
    struct SH7750State *s;
    MemoryRegion *sdram = g_new(MemoryRegion, 1);
    qemu_irq *irq;
    DriveInfo *dinfo;
    int i;
    DeviceState *dev;
    SysBusDevice *busdev;
    MemoryRegion *address_space_mem = get_system_memory();

    if (cpu_model == NULL) {
        cpu_model = "SH7751R";
    }

    cpu = cpu_sh4_init(cpu_model);
    if (cpu == NULL) {
        fprintf(stderr, "Unable to find CPU definition\n");
        exit(1);
    }
    env = &cpu->env;

    reset_info = g_malloc0(sizeof(ResetData));
    reset_info->cpu = cpu;
    reset_info->vector = env->pc;
    qemu_register_reset(main_cpu_reset, reset_info);

    /* Allocate memory space */
    memory_region_init_ram(sdram, "r2d.sdram", SDRAM_SIZE);
    vmstate_register_ram_global(sdram);
    memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
    /* Register peripherals */
    s = sh7750_init(env, address_space_mem);
    irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));

    dev = qdev_create(NULL, "sh_pci");
    busdev = sysbus_from_qdev(dev);
    qdev_init_nofail(dev);
    sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
    sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
    sysbus_connect_irq(busdev, 0, irq[PCI_INTA]);
    sysbus_connect_irq(busdev, 1, irq[PCI_INTB]);
    sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
    sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);

    sm501_init(address_space_mem, 0x10000000, SM501_VRAM_SIZE,
               irq[SM501], serial_hds[2]);

    /* onboard CF (True IDE mode, Master only). */
    dinfo = drive_get(IF_IDE, 0, 0);
    mmio_ide_init(0x14001000, 0x1400080c, address_space_mem, irq[CF_IDE], 1,
                  dinfo, NULL);

    /* onboard flash memory */
    dinfo = drive_get(IF_PFLASH, 0, 0);
    pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE,
                          dinfo ? dinfo->bdrv : NULL, (16 * 1024),
                          FLASH_SIZE >> 16,
                          1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
                          0x555, 0x2aa, 0);

    /* NIC: rtl8139 on-board, and 2 slots. */
    for (i = 0; i < nb_nics; i++)
        pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL);

    /* USB keyboard */
    usbdevice_create("keyboard");

    /* Todo: register on board registers */
    memset(&boot_params, 0, sizeof(boot_params));

    if (kernel_filename) {
        int kernel_size;

        kernel_size = load_image_targphys(kernel_filename,
                                          SDRAM_BASE + LINUX_LOAD_OFFSET,
                                          INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
        if (kernel_size < 0) {
          fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
          exit(1);
        }

        /* initialization which should be done by firmware */
        stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
        stw_phys(SH7750_BCR2, 3<<(3*2)); /* cs3 32bit */
        reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) | 0xa0000000; /* Start from P2 area */
    }

    if (initrd_filename) {
        int initrd_size;

        initrd_size = load_image_targphys(initrd_filename,
                                          SDRAM_BASE + INITRD_LOAD_OFFSET,
                                          SDRAM_SIZE - INITRD_LOAD_OFFSET);

        if (initrd_size < 0) {
          fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
          exit(1);
        }

        /* initialization which should be done by firmware */
        boot_params.loader_type = 1;
        boot_params.initrd_start = INITRD_LOAD_OFFSET;
        boot_params.initrd_size = initrd_size;
    }

    if (kernel_cmdline) {
        /* I see no evidence that this .kernel_cmdline buffer requires
           NUL-termination, so using strncpy should be ok. */
        strncpy(boot_params.kernel_cmdline, kernel_cmdline,
                sizeof(boot_params.kernel_cmdline));
    }

    rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
                       SDRAM_BASE + BOOT_PARAMS_OFFSET);
}

static QEMUMachine r2d_machine = {
    .name = "r2d",
    .desc = "r2d-plus board",
    .init = r2d_init,
};

static void r2d_machine_init(void)
{
    qemu_register_machine(&r2d_machine);
}

machine_init(r2d_machine_init);
Commit	Line	Data
0d78f544 TS	1	/*
	2	* Renesas SH7751R R2D-PLUS emulation
	3	*
	4	* Copyright (c) 2007 Magnus Damm
b319feb7	5	* Copyright (c) 2008 Paul Mundt
0d78f544 TS	6	*
	7	* Permission is hereby granted, free of charge, to any person obtaining a copy
	8	* of this software and associated documentation files (the "Software"), to deal
	9	* in the Software without restriction, including without limitation the rights
	10	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	11	* copies of the Software, and to permit persons to whom the Software is
	12	* furnished to do so, subject to the following conditions:
	13	*
	14	* The above copyright notice and this permission notice shall be included in
	15	* all copies or substantial portions of the Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	22	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	23	* THE SOFTWARE.
	24	*/
	25
cf154394	26	#include "sysbus.h"
87ecb68b PB	27	#include "hw.h"
87ecb68b PB	28	#include "sh.h"
ffd39257	29	#include "devices.h"
9c17d615	30	#include "sysemu/sysemu.h"
87ecb68b	31	#include "boards.h"
a2cb15b0	32	#include "pci/pci.h"
1422e32d	33	#include "net/net.h"
c2f01775	34	#include "sh7750_regs.h"
3d2bf4a1	35	#include "ide.h"
ca20cf32	36	#include "loader.h"
9caa3ec1	37	#include "usb.h"
56839a19	38	#include "flash.h"
9c17d615	39	#include "sysemu/blockdev.h"
022c62cb	40	#include "exec/address-spaces.h"
56839a19 AJ	41
	42	#define FLASH_BASE 0x00000000
	43	#define FLASH_SIZE 0x02000000
0d78f544 TS	44
	45	#define SDRAM_BASE 0x0c000000 /* Physical location of SDRAM: Area 3 */
	46	#define SDRAM_SIZE 0x04000000
	47
ffd39257 BS	48	#define SM501_VRAM_SIZE 0x800000
ffd39257 BS	49
73f19035	50	#define BOOT_PARAMS_OFFSET 0x0010000
e8afa065	51	/* CONFIG_BOOT_LINK_OFFSET of Linux kernel */
73f19035 AJ	52	#define LINUX_LOAD_OFFSET 0x0800000
73f19035 AJ	53	#define INITRD_LOAD_OFFSET 0x1800000
e8afa065	54
d47ede60	55	#define PA_IRLMSK 0x00
b319feb7 AJ	56	#define PA_POWOFF 0x30
	57	#define PA_VERREG 0x32
	58	#define PA_OUTPORT 0x36
	59
	60	typedef struct {
b319feb7	61	uint16_t bcr;
d47ede60	62	uint16_t irlmsk;
b319feb7 AJ	63	uint16_t irlmon;
	64	uint16_t cfctl;
	65	uint16_t cfpow;
	66	uint16_t dispctl;
	67	uint16_t sdmpow;
	68	uint16_t rtcce;
	69	uint16_t pcicd;
	70	uint16_t voyagerrts;
	71	uint16_t cfrst;
	72	uint16_t admrts;
	73	uint16_t extrst;
	74	uint16_t cfcdintclr;
	75	uint16_t keyctlclr;
	76	uint16_t pad0;
	77	uint16_t pad1;
b319feb7 AJ	78	uint16_t verreg;
	79	uint16_t inport;
	80	uint16_t outport;
	81	uint16_t bverreg;
d47ede60 AZ	82
	83	/* output pin */
	84	qemu_irq irl;
5dea2efb	85	MemoryRegion iomem;
c227f099	86	} r2d_fpga_t;
b319feb7	87
d47ede60 AZ	88	enum r2d_fpga_irq {
	89	PCI_INTD, CF_IDE, CF_CD, PCI_INTC, SM501, KEY, RTC_A, RTC_T,
	90	SDCARD, PCI_INTA, PCI_INTB, EXT, TP,
	91	NR_IRQS
	92	};
	93
	94	static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
	95	[CF_IDE] = { 1, 1<<9 },
	96	[CF_CD] = { 2, 1<<8 },
	97	[PCI_INTA] = { 9, 1<<14 },
	98	[PCI_INTB] = { 10, 1<<13 },
	99	[PCI_INTC] = { 3, 1<<12 },
	100	[PCI_INTD] = { 0, 1<<11 },
	101	[SM501] = { 4, 1<<10 },
	102	[KEY] = { 5, 1<<6 },
	103	[RTC_A] = { 6, 1<<5 },
	104	[RTC_T] = { 7, 1<<4 },
	105	[SDCARD] = { 8, 1<<7 },
	106	[EXT] = { 11, 1<<0 },
	107	[TP] = { 12, 1<<15 },
	108	};
	109
c227f099	110	static void update_irl(r2d_fpga_t *fpga)
d47ede60 AZ	111	{
	112	int i, irl = 15;
	113	for (i = 0; i < NR_IRQS; i++)
	114	if (fpga->irlmon & fpga->irlmsk & irqtab[i].msk)
	115	if (irqtab[i].irl < irl)
	116	irl = irqtab[i].irl;
	117	qemu_set_irq(fpga->irl, irl ^ 15);
	118	}
	119
	120	static void r2d_fpga_irq_set(void *opaque, int n, int level)
	121	{
c227f099	122	r2d_fpga_t *fpga = opaque;
d47ede60 AZ	123	if (level)
	124	fpga->irlmon \|= irqtab[n].msk;
	125	else
	126	fpga->irlmon &= ~irqtab[n].msk;
	127	update_irl(fpga);
	128	}
	129
a8170e5e	130	static uint32_t r2d_fpga_read(void *opaque, hwaddr addr)
b319feb7	131	{
c227f099	132	r2d_fpga_t *s = opaque;
b319feb7	133
b319feb7	134	switch (addr) {
d47ede60 AZ	135	case PA_IRLMSK:
d47ede60 AZ	136	return s->irlmsk;
b319feb7 AJ	137	case PA_OUTPORT:
	138	return s->outport;
	139	case PA_POWOFF:
37cc0b44	140	return 0x00;
b319feb7 AJ	141	case PA_VERREG:
	142	return 0x10;
	143	}
	144
	145	return 0;
	146	}
	147
	148	static void
a8170e5e	149	r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value)
b319feb7	150	{
c227f099	151	r2d_fpga_t *s = opaque;
b319feb7	152
b319feb7	153	switch (addr) {
d47ede60 AZ	154	case PA_IRLMSK:
	155	s->irlmsk = value;
	156	update_irl(s);
	157	break;
b319feb7 AJ	158	case PA_OUTPORT:
	159	s->outport = value;
	160	break;
	161	case PA_POWOFF:
37cc0b44 AJ	162	if (value & 1) {
	163	qemu_system_shutdown_request();
	164	}
	165	break;
b319feb7 AJ	166	case PA_VERREG:
	167	/* Discard writes */
	168	break;
	169	}
	170	}
	171
5dea2efb AK	172	static const MemoryRegionOps r2d_fpga_ops = {
	173	.old_mmio = {
	174	.read = { r2d_fpga_read, r2d_fpga_read, NULL, },
	175	.write = { r2d_fpga_write, r2d_fpga_write, NULL, },
	176	},
	177	.endianness = DEVICE_NATIVE_ENDIAN,
b319feb7 AJ	178	};
b319feb7 AJ	179
5dea2efb	180	static qemu_irq r2d_fpga_init(MemoryRegion sysmem,
a8170e5e	181	hwaddr base, qemu_irq irl)
b319feb7	182	{
c227f099	183	r2d_fpga_t *s;
b319feb7	184
7267c094	185	s = g_malloc0(sizeof(r2d_fpga_t));
d47ede60 AZ	186
d47ede60 AZ	187	s->irl = irl;
b319feb7	188
5dea2efb AK	189	memory_region_init_io(&s->iomem, &r2d_fpga_ops, s, "r2d-fpga", 0x40);
5dea2efb AK	190	memory_region_add_subregion(sysmem, base, &s->iomem);
d47ede60	191	return qemu_allocate_irqs(r2d_fpga_irq_set, s, NR_IRQS);
b319feb7 AJ	192	}
b319feb7 AJ	193
4f6493ff	194	typedef struct ResetData {
868bac81	195	SuperHCPU *cpu;
4f6493ff AJ	196	uint32_t vector;
	197	} ResetData;
	198
	199	static void main_cpu_reset(void *opaque)
	200	{
	201	ResetData s = (ResetData )opaque;
868bac81	202	CPUSH4State *env = &s->cpu->env;
4f6493ff	203
868bac81	204	cpu_reset(CPU(s->cpu));
4f6493ff AJ	205	env->pc = s->vector;
	206	}
	207
541dc0d4	208	static struct QEMU_PACKED
73f19035 AJ	209	{
	210	int mount_root_rdonly;
	211	int ramdisk_flags;
	212	int orig_root_dev;
	213	int loader_type;
	214	int initrd_start;
	215	int initrd_size;
	216
	217	char pad[232];
	218
	219	char kernel_cmdline[256];
	220	} boot_params;
	221
5f072e1f	222	static void r2d_init(QEMUMachineInitArgs *args)
0d78f544	223	{
5f072e1f EH	224	const char *cpu_model = args->cpu_model;
	225	const char *kernel_filename = args->kernel_filename;
	226	const char *kernel_cmdline = args->kernel_cmdline;
	227	const char *initrd_filename = args->initrd_filename;
fd2f410b	228	SuperHCPU *cpu;
0b7ade1d	229	CPUSH4State *env;
4f6493ff	230	ResetData *reset_info;
0d78f544	231	struct SH7750State *s;
5dea2efb	232	MemoryRegion *sdram = g_new(MemoryRegion, 1);
d47ede60	233	qemu_irq *irq;
751c6a17	234	DriveInfo *dinfo;
c2f01775	235	int i;
8c106233 BC	236	DeviceState *dev;
8c106233 BC	237	SysBusDevice *busdev;
27a9d2ea	238	MemoryRegion *address_space_mem = get_system_memory();
0d78f544	239
fd2f410b	240	if (cpu_model == NULL) {
0fd3ca30	241	cpu_model = "SH7751R";
fd2f410b	242	}
aaed909a	243
fd2f410b AF	244	cpu = cpu_sh4_init(cpu_model);
fd2f410b AF	245	if (cpu == NULL) {
aaed909a FB	246	fprintf(stderr, "Unable to find CPU definition\n");
	247	exit(1);
	248	}
fd2f410b AF	249	env = &cpu->env;
fd2f410b AF	250
7267c094	251	reset_info = g_malloc0(sizeof(ResetData));
868bac81	252	reset_info->cpu = cpu;
4f6493ff AJ	253	reset_info->vector = env->pc;
4f6493ff AJ	254	qemu_register_reset(main_cpu_reset, reset_info);
0d78f544 TS	255
0d78f544 TS	256	/* Allocate memory space */
c5705a77 AK	257	memory_region_init_ram(sdram, "r2d.sdram", SDRAM_SIZE);
c5705a77 AK	258	vmstate_register_ram_global(sdram);
5dea2efb	259	memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram);
0d78f544	260	/* Register peripherals */
382863e2	261	s = sh7750_init(env, address_space_mem);
5dea2efb	262	irq = r2d_fpga_init(address_space_mem, 0x04000000, sh7750_irl(s));
8c106233 BC	263
	264	dev = qdev_create(NULL, "sh_pci");
	265	busdev = sysbus_from_qdev(dev);
	266	qdev_init_nofail(dev);
	267	sysbus_mmio_map(busdev, 0, P4ADDR(0x1e200000));
	268	sysbus_mmio_map(busdev, 1, A7ADDR(0x1e200000));
	269	sysbus_connect_irq(busdev, 0, irq[PCI_INTA]);
	270	sysbus_connect_irq(busdev, 1, irq[PCI_INTB]);
	271	sysbus_connect_irq(busdev, 2, irq[PCI_INTC]);
	272	sysbus_connect_irq(busdev, 3, irq[PCI_INTD]);
d47ede60	273
27a9d2ea RH	274	sm501_init(address_space_mem, 0x10000000, SM501_VRAM_SIZE,
27a9d2ea RH	275	irq[SM501], serial_hds[2]);
a4a771c0 AZ	276
a4a771c0 AZ	277	/* onboard CF (True IDE mode, Master only). */
612b2bd0	278	dinfo = drive_get(IF_IDE, 0, 0);
9d7f1b9a	279	mmio_ide_init(0x14001000, 0x1400080c, address_space_mem, irq[CF_IDE], 1,
612b2bd0	280	dinfo, NULL);
a4a771c0	281
56839a19	282	/* onboard flash memory */
45e7e4bc	283	dinfo = drive_get(IF_PFLASH, 0, 0);
cfe5f011	284	pflash_cfi02_register(0x0, NULL, "r2d.flash", FLASH_SIZE,
612b2bd0 AJ	285	dinfo ? dinfo->bdrv : NULL, (16 * 1024),
	286	FLASH_SIZE >> 16,
	287	1, 4, 0x0000, 0x0000, 0x0000, 0x0000,
01e0451a	288	0x555, 0x2aa, 0);
56839a19	289
c2f01775	290	/* NIC: rtl8139 on-board, and 2 slots. */
ab2da564	291	for (i = 0; i < nb_nics; i++)
07caea31	292	pci_nic_init_nofail(&nd_table[i], "rtl8139", i==0 ? "2" : NULL);
c2f01775	293
9caa3ec1 AJ	294	/* USB keyboard */
	295	usbdevice_create("keyboard");
	296
0d78f544	297	/* Todo: register on board registers */
73f19035 AJ	298	memset(&boot_params, 0, sizeof(boot_params));
73f19035 AJ	299
e8afa065	300	if (kernel_filename) {
73f19035 AJ	301	int kernel_size;
	302
	303	kernel_size = load_image_targphys(kernel_filename,
	304	SDRAM_BASE + LINUX_LOAD_OFFSET,
	305	INITRD_LOAD_OFFSET - LINUX_LOAD_OFFSET);
	306	if (kernel_size < 0) {
	307	fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
	308	exit(1);
	309	}
	310
	311	/* initialization which should be done by firmware */
	312	stl_phys(SH7750_BCR1, 1<<3); /* cs3 SDRAM */
	313	stw_phys(SH7750_BCR2, 3<<(32)); / cs3 32bit */
4f6493ff	314	reset_info->vector = (SDRAM_BASE + LINUX_LOAD_OFFSET) \| 0xa0000000; /* Start from P2 area */
0d78f544	315	}
73f19035 AJ	316
	317	if (initrd_filename) {
	318	int initrd_size;
	319
	320	initrd_size = load_image_targphys(initrd_filename,
	321	SDRAM_BASE + INITRD_LOAD_OFFSET,
	322	SDRAM_SIZE - INITRD_LOAD_OFFSET);
	323
	324	if (initrd_size < 0) {
	325	fprintf(stderr, "qemu: could not load initrd '%s'\n", initrd_filename);
	326	exit(1);
	327	}
	328
	329	/* initialization which should be done by firmware */
	330	boot_params.loader_type = 1;
	331	boot_params.initrd_start = INITRD_LOAD_OFFSET;
	332	boot_params.initrd_size = initrd_size;
	333	}
	334
	335	if (kernel_cmdline) {
9310b9be JM	336	/* I see no evidence that this .kernel_cmdline buffer requires
9310b9be JM	337	NUL-termination, so using strncpy should be ok. */
73f19035 AJ	338	strncpy(boot_params.kernel_cmdline, kernel_cmdline,
	339	sizeof(boot_params.kernel_cmdline));
	340	}
	341
	342	rom_add_blob_fixed("boot_params", &boot_params, sizeof(boot_params),
	343	SDRAM_BASE + BOOT_PARAMS_OFFSET);
0d78f544 TS	344	}
0d78f544 TS	345
f80f9ec9	346	static QEMUMachine r2d_machine = {
4b32e168 AL	347	.name = "r2d",
	348	.desc = "r2d-plus board",
	349	.init = r2d_init,
0d78f544	350	};
f80f9ec9 AL	351
	352	static void r2d_machine_init(void)
	353	{
	354	qemu_register_machine(&r2d_machine);
	355	}
	356
	357	machine_init(r2d_machine_init);