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a41b2ff2
PB		 1/**
2 * QEMU RTL8139 emulation
5fafdf24 3 *
a41b2ff2 4 * Copyright (c) 2006 Igor Kovalenko
5fafdf24 5 *
a41b2ff2
PB		 6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
5fafdf24 23
a41b2ff2
PB		 24 * Modifications:
25 * 2006-Jan-28 Mark Malakanov : TSAD and CSCR implementation (for Windows driver)
5fafdf24 26 *
6cadb320
FB		 27 * 2006-Apr-28 Juergen Lock : EEPROM emulation changes for FreeBSD driver
28 * HW revision ID changes for FreeBSD driver
5fafdf24 29 *
6cadb320
FB		 30 * 2006-Jul-01 Igor Kovalenko : Implemented loopback mode for FreeBSD driver
31 * Corrected packet transfer reassembly routine for 8139C+ mode
32 * Rearranged debugging print statements
33 * Implemented PCI timer interrupt (disabled by default)
34 * Implemented Tally Counters, increased VM load/save version
35 * Implemented IP/TCP/UDP checksum task offloading
718da2b9
FB		 36 *
37 * 2006-Jul-04 Igor Kovalenko : Implemented TCP segmentation offloading
38 * Fixed MTU=1500 for produced ethernet frames
39 *
40 * 2006-Jul-09 Igor Kovalenko : Fixed TCP header length calculation while processing
41 * segmentation offloading
42 * Removed slirp.h dependency
43 * Added rx/tx buffer reset when enabling rx/tx operation
05447803
FZ		 44 *
45 * 2010-Feb-04 Frediano Ziglio: Rewrote timer support using QEMU timer only
46 * when strictly needed (required for for
47 * Darwin)
bf6b87a8 48 * 2011-Mar-22 Benjamin Poirier: Implemented VLAN offloading
a41b2ff2
PB		 49 */
50
2c406b8f
BP		 51/* For crc32 */
52#include <zlib.h>
53
87ecb68b 54#include "hw.h"
a2cb15b0 55#include "pci/pci.h"
9c17d615 56#include "sysemu/dma.h"
1de7afc9 57#include "qemu/timer.h"
1422e32d 58#include "net/net.h"
254111ec 59#include "loader.h"
9c17d615 60#include "sysemu/sysemu.h"
1de7afc9 61#include "qemu/iov.h"
a41b2ff2 62
a41b2ff2
PB		 63/* debug RTL8139 card */
64//#define DEBUG_RTL8139 1
65
6cadb320
FB		 66#define PCI_FREQUENCY 33000000L
67
a41b2ff2
PB		 68#define SET_MASKED(input, mask, curr) \
69 ( ( (input) & ~(mask) ) | ( (curr) & (mask) ) )
70
71/* arg % size for size which is a power of 2 */
72#define MOD2(input, size) \
73 ( ( input ) & ( size - 1 ) )
74
18dabfd1
BP		 75#define ETHER_ADDR_LEN 6
76#define ETHER_TYPE_LEN 2
77#define ETH_HLEN (ETHER_ADDR_LEN * 2 + ETHER_TYPE_LEN)
78#define ETH_P_IP 0x0800 /* Internet Protocol packet */
79#define ETH_P_8021Q 0x8100 /* 802.1Q VLAN Extended Header */
80#define ETH_MTU 1500
81
82#define VLAN_TCI_LEN 2
83#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
84
6cadb320 85#if defined (DEBUG_RTL8139)
7cdeb319
BP		 86# define DPRINTF(fmt, ...) \
87 do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
6cadb320 88#else
c6a0487b 89static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
ec48c774
BP		 90{
91 return 0;
92}
6cadb320
FB		 93#endif
94
a41b2ff2
PB		 95/* Symbolic offsets to registers. */
96enum RTL8139_registers {
97 MAC0 = 0, /* Ethernet hardware address. */
98 MAR0 = 8, /* Multicast filter. */
6cadb320
FB		 99 TxStatus0 = 0x10,/* Transmit status (Four 32bit registers). C mode only */
100 /* Dump Tally Conter control register(64bit). C+ mode only */
101 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
a41b2ff2
PB		 102 RxBuf = 0x30,
103 ChipCmd = 0x37,
104 RxBufPtr = 0x38,
105 RxBufAddr = 0x3A,
106 IntrMask = 0x3C,
107 IntrStatus = 0x3E,
108 TxConfig = 0x40,
109 RxConfig = 0x44,
110 Timer = 0x48, /* A general-purpose counter. */
111 RxMissed = 0x4C, /* 24 bits valid, write clears. */
112 Cfg9346 = 0x50,
113 Config0 = 0x51,
114 Config1 = 0x52,
115 FlashReg = 0x54,
116 MediaStatus = 0x58,
117 Config3 = 0x59,
118 Config4 = 0x5A, /* absent on RTL-8139A */
119 HltClk = 0x5B,
120 MultiIntr = 0x5C,
121 PCIRevisionID = 0x5E,
122 TxSummary = 0x60, /* TSAD register. Transmit Status of All Descriptors*/
123 BasicModeCtrl = 0x62,
124 BasicModeStatus = 0x64,
125 NWayAdvert = 0x66,
126 NWayLPAR = 0x68,
127 NWayExpansion = 0x6A,
128 /* Undocumented registers, but required for proper operation. */
129 FIFOTMS = 0x70, /* FIFO Control and test. */
130 CSCR = 0x74, /* Chip Status and Configuration Register. */
131 PARA78 = 0x78,
132 PARA7c = 0x7c, /* Magic transceiver parameter register. */
133 Config5 = 0xD8, /* absent on RTL-8139A */
134 /* C+ mode */
135 TxPoll = 0xD9, /* Tell chip to check Tx descriptors for work */
136 RxMaxSize = 0xDA, /* Max size of an Rx packet (8169 only) */
137 CpCmd = 0xE0, /* C+ Command register (C+ mode only) */
138 IntrMitigate = 0xE2, /* rx/tx interrupt mitigation control */
139 RxRingAddrLO = 0xE4, /* 64-bit start addr of Rx ring */
140 RxRingAddrHI = 0xE8, /* 64-bit start addr of Rx ring */
141 TxThresh = 0xEC, /* Early Tx threshold */
142};
143
144enum ClearBitMasks {
145 MultiIntrClear = 0xF000,
146 ChipCmdClear = 0xE2,
147 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
148};
149
150enum ChipCmdBits {
151 CmdReset = 0x10,
152 CmdRxEnb = 0x08,
153 CmdTxEnb = 0x04,
154 RxBufEmpty = 0x01,
155};
156
157/* C+ mode */
158enum CplusCmdBits {
6cadb320
FB		 159 CPlusRxVLAN = 0x0040, /* enable receive VLAN detagging */
160 CPlusRxChkSum = 0x0020, /* enable receive checksum offloading */
161 CPlusRxEnb = 0x0002,
162 CPlusTxEnb = 0x0001,
a41b2ff2
PB		 163};
164
165/* Interrupt register bits, using my own meaningful names. */
166enum IntrStatusBits {
167 PCIErr = 0x8000,
168 PCSTimeout = 0x4000,
169 RxFIFOOver = 0x40,
9e12c5af 170 RxUnderrun = 0x20, /* Packet Underrun / Link Change */
a41b2ff2
PB		 171 RxOverflow = 0x10,
172 TxErr = 0x08,
173 TxOK = 0x04,
174 RxErr = 0x02,
175 RxOK = 0x01,
176
177 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
178};
179
180enum TxStatusBits {
181 TxHostOwns = 0x2000,
182 TxUnderrun = 0x4000,
183 TxStatOK = 0x8000,
184 TxOutOfWindow = 0x20000000,
185 TxAborted = 0x40000000,
186 TxCarrierLost = 0x80000000,
187};
188enum RxStatusBits {
189 RxMulticast = 0x8000,
190 RxPhysical = 0x4000,
191 RxBroadcast = 0x2000,
192 RxBadSymbol = 0x0020,
193 RxRunt = 0x0010,
194 RxTooLong = 0x0008,
195 RxCRCErr = 0x0004,
196 RxBadAlign = 0x0002,
197 RxStatusOK = 0x0001,
198};
199
200/* Bits in RxConfig. */
201enum rx_mode_bits {
202 AcceptErr = 0x20,
203 AcceptRunt = 0x10,
204 AcceptBroadcast = 0x08,
205 AcceptMulticast = 0x04,
206 AcceptMyPhys = 0x02,
207 AcceptAllPhys = 0x01,
208};
209
210/* Bits in TxConfig. */
211enum tx_config_bits {
212
213 /* Interframe Gap Time. Only TxIFG96 doesn't violate IEEE 802.3 */
214 TxIFGShift = 24,
215 TxIFG84 = (0 << TxIFGShift), /* 8.4us / 840ns (10 / 100Mbps) */
216 TxIFG88 = (1 << TxIFGShift), /* 8.8us / 880ns (10 / 100Mbps) */
217 TxIFG92 = (2 << TxIFGShift), /* 9.2us / 920ns (10 / 100Mbps) */
218 TxIFG96 = (3 << TxIFGShift), /* 9.6us / 960ns (10 / 100Mbps) */
219
220 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
221 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
222 TxClearAbt = (1 << 0), /* Clear abort (WO) */
223 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
224 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
225
226 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
227};
228
229
230/* Transmit Status of All Descriptors (TSAD) Register */
231enum TSAD_bits {
232 TSAD_TOK3 = 1<<15, // TOK bit of Descriptor 3
233 TSAD_TOK2 = 1<<14, // TOK bit of Descriptor 2
234 TSAD_TOK1 = 1<<13, // TOK bit of Descriptor 1
235 TSAD_TOK0 = 1<<12, // TOK bit of Descriptor 0
236 TSAD_TUN3 = 1<<11, // TUN bit of Descriptor 3
237 TSAD_TUN2 = 1<<10, // TUN bit of Descriptor 2
238 TSAD_TUN1 = 1<<9, // TUN bit of Descriptor 1
239 TSAD_TUN0 = 1<<8, // TUN bit of Descriptor 0
240 TSAD_TABT3 = 1<<07, // TABT bit of Descriptor 3
241 TSAD_TABT2 = 1<<06, // TABT bit of Descriptor 2
242 TSAD_TABT1 = 1<<05, // TABT bit of Descriptor 1
243 TSAD_TABT0 = 1<<04, // TABT bit of Descriptor 0
244 TSAD_OWN3 = 1<<03, // OWN bit of Descriptor 3
245 TSAD_OWN2 = 1<<02, // OWN bit of Descriptor 2
246 TSAD_OWN1 = 1<<01, // OWN bit of Descriptor 1
247 TSAD_OWN0 = 1<<00, // OWN bit of Descriptor 0
248};
249
250
251/* Bits in Config1 */
252enum Config1Bits {
253 Cfg1_PM_Enable = 0x01,
254 Cfg1_VPD_Enable = 0x02,
255 Cfg1_PIO = 0x04,
256 Cfg1_MMIO = 0x08,
257 LWAKE = 0x10, /* not on 8139, 8139A */
258 Cfg1_Driver_Load = 0x20,
259 Cfg1_LED0 = 0x40,
260 Cfg1_LED1 = 0x80,
261 SLEEP = (1 << 1), /* only on 8139, 8139A */
262 PWRDN = (1 << 0), /* only on 8139, 8139A */
263};
264
265/* Bits in Config3 */
266enum Config3Bits {
267 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
268 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
269 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
270 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
271 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
272 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
273 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
274 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
275};
276
277/* Bits in Config4 */
278enum Config4Bits {
279 LWPTN = (1 << 2), /* not on 8139, 8139A */
280};
281
282/* Bits in Config5 */
283enum Config5Bits {
284 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
285 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
286 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
287 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
288 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
289 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
290 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
291};
292
293enum RxConfigBits {
294 /* rx fifo threshold */
295 RxCfgFIFOShift = 13,
296 RxCfgFIFONone = (7 << RxCfgFIFOShift),
297
298 /* Max DMA burst */
299 RxCfgDMAShift = 8,
300 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
301
302 /* rx ring buffer length */
303 RxCfgRcv8K = 0,
304 RxCfgRcv16K = (1 << 11),
305 RxCfgRcv32K = (1 << 12),
306 RxCfgRcv64K = (1 << 11) | (1 << 12),
307
308 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
309 RxNoWrap = (1 << 7),
310};
311
312/* Twister tuning parameters from RealTek.
313 Completely undocumented, but required to tune bad links on some boards. */
314/*
315enum CSCRBits {
316 CSCR_LinkOKBit = 0x0400,
317 CSCR_LinkChangeBit = 0x0800,
318 CSCR_LinkStatusBits = 0x0f000,
319 CSCR_LinkDownOffCmd = 0x003c0,
320 CSCR_LinkDownCmd = 0x0f3c0,
321*/
322enum CSCRBits {
5fafdf24 323 CSCR_Testfun = 1<<15, /* 1 = Auto-neg speeds up internal timer, WO, def 0 */
a41b2ff2
PB		 324 CSCR_LD = 1<<9, /* Active low TPI link disable signal. When low, TPI still transmits link pulses and TPI stays in good link state. def 1*/
325 CSCR_HEART_BIT = 1<<8, /* 1 = HEART BEAT enable, 0 = HEART BEAT disable. HEART BEAT function is only valid in 10Mbps mode. def 1*/
326 CSCR_JBEN = 1<<7, /* 1 = enable jabber function. 0 = disable jabber function, def 1*/
5fafdf24 327 CSCR_F_LINK_100 = 1<<6, /* Used to login force good link in 100Mbps for diagnostic purposes. 1 = DISABLE, 0 = ENABLE. def 1*/
a41b2ff2
PB		 328 CSCR_F_Connect = 1<<5, /* Assertion of this bit forces the disconnect function to be bypassed. def 0*/
329 CSCR_Con_status = 1<<3, /* This bit indicates the status of the connection. 1 = valid connected link detected; 0 = disconnected link detected. RO def 0*/
330 CSCR_Con_status_En = 1<<2, /* Assertion of this bit configures LED1 pin to indicate connection status. def 0*/
331 CSCR_PASS_SCR = 1<<0, /* Bypass Scramble, def 0*/
332};
333
334enum Cfg9346Bits {
eb46c5ed
JW		 335 Cfg9346_Normal = 0x00,
336 Cfg9346_Autoload = 0x40,
337 Cfg9346_Programming = 0x80,
338 Cfg9346_ConfigWrite = 0xC0,
a41b2ff2
PB		 339};
340
341typedef enum {
342 CH_8139 = 0,
343 CH_8139_K,
344 CH_8139A,
345 CH_8139A_G,
346 CH_8139B,
347 CH_8130,
348 CH_8139C,
349 CH_8100,
350 CH_8100B_8139D,
351 CH_8101,
c227f099 352} chip_t;
a41b2ff2
PB		 353
354enum chip_flags {
355 HasHltClk = (1 << 0),
356 HasLWake = (1 << 1),
357};
358
359#define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
360 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
361#define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
362
6cadb320
FB		 363#define RTL8139_PCI_REVID_8139 0x10
364#define RTL8139_PCI_REVID_8139CPLUS 0x20
365
366#define RTL8139_PCI_REVID RTL8139_PCI_REVID_8139CPLUS
367
a41b2ff2
PB		 368/* Size is 64 * 16bit words */
369#define EEPROM_9346_ADDR_BITS 6
370#define EEPROM_9346_SIZE (1 << EEPROM_9346_ADDR_BITS)
371#define EEPROM_9346_ADDR_MASK (EEPROM_9346_SIZE - 1)
372
373enum Chip9346Operation
374{
375 Chip9346_op_mask = 0xc0, /* 10 zzzzzz */
376 Chip9346_op_read = 0x80, /* 10 AAAAAA */
377 Chip9346_op_write = 0x40, /* 01 AAAAAA D(15)..D(0) */
378 Chip9346_op_ext_mask = 0xf0, /* 11 zzzzzz */
379 Chip9346_op_write_enable = 0x30, /* 00 11zzzz */
380 Chip9346_op_write_all = 0x10, /* 00 01zzzz */
381 Chip9346_op_write_disable = 0x00, /* 00 00zzzz */
382};
383
384enum Chip9346Mode
385{
386 Chip9346_none = 0,
387 Chip9346_enter_command_mode,
388 Chip9346_read_command,
389 Chip9346_data_read, /* from output register */
390 Chip9346_data_write, /* to input register, then to contents at specified address */
391 Chip9346_data_write_all, /* to input register, then filling contents */
392};
393
394typedef struct EEprom9346
395{
396 uint16_t contents[EEPROM_9346_SIZE];
397 int mode;
398 uint32_t tick;
399 uint8_t address;
400 uint16_t input;
401 uint16_t output;
402
403 uint8_t eecs;
404 uint8_t eesk;
405 uint8_t eedi;
406 uint8_t eedo;
407} EEprom9346;
408
6cadb320
FB		 409typedef struct RTL8139TallyCounters
410{
411 /* Tally counters */
412 uint64_t TxOk;
413 uint64_t RxOk;
414 uint64_t TxERR;
415 uint32_t RxERR;
416 uint16_t MissPkt;
417 uint16_t FAE;
418 uint32_t Tx1Col;
419 uint32_t TxMCol;
420 uint64_t RxOkPhy;
421 uint64_t RxOkBrd;
422 uint32_t RxOkMul;
423 uint16_t TxAbt;
424 uint16_t TxUndrn;
425} RTL8139TallyCounters;
426
427/* Clears all tally counters */
428static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
429
a41b2ff2 430typedef struct RTL8139State {
efd6dd45 431 PCIDevice dev;
a41b2ff2
PB		 432 uint8_t phys[8]; /* mac address */
433 uint8_t mult[8]; /* multicast mask array */
434
6cadb320 435 uint32_t TxStatus[4]; /* TxStatus0 in C mode*/ /* also DTCCR[0] and DTCCR[1] in C+ mode */
a41b2ff2
PB		 436 uint32_t TxAddr[4]; /* TxAddr0 */
437 uint32_t RxBuf; /* Receive buffer */
438 uint32_t RxBufferSize;/* internal variable, receive ring buffer size in C mode */
439 uint32_t RxBufPtr;
440 uint32_t RxBufAddr;
441
442 uint16_t IntrStatus;
443 uint16_t IntrMask;
444
445 uint32_t TxConfig;
446 uint32_t RxConfig;
447 uint32_t RxMissed;
448
449 uint16_t CSCR;
450
451 uint8_t Cfg9346;
452 uint8_t Config0;
453 uint8_t Config1;
454 uint8_t Config3;
455 uint8_t Config4;
456 uint8_t Config5;
457
458 uint8_t clock_enabled;
459 uint8_t bChipCmdState;
460
461 uint16_t MultiIntr;
462
463 uint16_t BasicModeCtrl;
464 uint16_t BasicModeStatus;
465 uint16_t NWayAdvert;
466 uint16_t NWayLPAR;
467 uint16_t NWayExpansion;
468
469 uint16_t CpCmd;
470 uint8_t TxThresh;
471
1673ad51 472 NICState *nic;
254111ec 473 NICConf conf;
a41b2ff2
PB		 474
475 /* C ring mode */
476 uint32_t currTxDesc;
477
478 /* C+ mode */
2c3891ab
AL		 479 uint32_t cplus_enabled;
480
a41b2ff2
PB		 481 uint32_t currCPlusRxDesc;
482 uint32_t currCPlusTxDesc;
483
484 uint32_t RxRingAddrLO;
485 uint32_t RxRingAddrHI;
486
487 EEprom9346 eeprom;
6cadb320
FB		 488
489 uint32_t TCTR;
490 uint32_t TimerInt;
491 int64_t TCTR_base;
492
493 /* Tally counters */
494 RTL8139TallyCounters tally_counters;
495
496 /* Non-persistent data */
497 uint8_t *cplus_txbuffer;
498 int cplus_txbuffer_len;
499 int cplus_txbuffer_offset;
500
501 /* PCI interrupt timer */
502 QEMUTimer *timer;
05447803 503 int64_t TimerExpire;
6cadb320 504
bd80f3fc
AK		 505 MemoryRegion bar_io;
506 MemoryRegion bar_mem;
507
c574ba5a
AW		 508 /* Support migration to/from old versions */
509 int rtl8139_mmio_io_addr_dummy;
a41b2ff2
PB		 510} RTL8139State;
511
3ada003a
EGM		 512/* Writes tally counters to memory via DMA */
513static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr);
514
05447803
FZ		 515static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time);
516
9596ebb7 517static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
a41b2ff2 518{
7cdeb319 519 DPRINTF("eeprom command 0x%02x\n", command);
a41b2ff2
PB		 520
521 switch (command & Chip9346_op_mask)
522 {
523 case Chip9346_op_read:
524 {
525 eeprom->address = command & EEPROM_9346_ADDR_MASK;
526 eeprom->output = eeprom->contents[eeprom->address];
527 eeprom->eedo = 0;
528 eeprom->tick = 0;
529 eeprom->mode = Chip9346_data_read;
7cdeb319
BP		 530 DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
531 eeprom->address, eeprom->output);
a41b2ff2
PB		 532 }
533 break;
534
535 case Chip9346_op_write:
536 {
537 eeprom->address = command & EEPROM_9346_ADDR_MASK;
538 eeprom->input = 0;
539 eeprom->tick = 0;
540 eeprom->mode = Chip9346_none; /* Chip9346_data_write */
7cdeb319
BP		 541 DPRINTF("eeprom begin write to address 0x%02x\n",
542 eeprom->address);
a41b2ff2
PB		 543 }
544 break;
545 default:
546 eeprom->mode = Chip9346_none;
547 switch (command & Chip9346_op_ext_mask)
548 {
549 case Chip9346_op_write_enable:
7cdeb319 550 DPRINTF("eeprom write enabled\n");
a41b2ff2
PB		 551 break;
552 case Chip9346_op_write_all:
7cdeb319 553 DPRINTF("eeprom begin write all\n");
a41b2ff2
PB		 554 break;
555 case Chip9346_op_write_disable:
7cdeb319 556 DPRINTF("eeprom write disabled\n");
a41b2ff2
PB		 557 break;
558 }
559 break;
560 }
561}
562
9596ebb7 563static void prom9346_shift_clock(EEprom9346 *eeprom)
a41b2ff2
PB		 564{
565 int bit = eeprom->eedi?1:0;
566
567 ++ eeprom->tick;
568
7cdeb319
BP		 569 DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
570 eeprom->eedo);
a41b2ff2
PB		 571
572 switch (eeprom->mode)
573 {
574 case Chip9346_enter_command_mode:
575 if (bit)
576 {
577 eeprom->mode = Chip9346_read_command;
578 eeprom->tick = 0;
579 eeprom->input = 0;
7cdeb319 580 DPRINTF("eeprom: +++ synchronized, begin command read\n");
a41b2ff2
PB		 581 }
582 break;
583
584 case Chip9346_read_command:
585 eeprom->input = (eeprom->input << 1) | (bit & 1);
586 if (eeprom->tick == 8)
587 {
588 prom9346_decode_command(eeprom, eeprom->input & 0xff);
589 }
590 break;
591
592 case Chip9346_data_read:
593 eeprom->eedo = (eeprom->output & 0x8000)?1:0;
594 eeprom->output <<= 1;
595 if (eeprom->tick == 16)
596 {
6cadb320
FB		 597#if 1
598 // the FreeBSD drivers (rl and re) don't explicitly toggle
599 // CS between reads (or does setting Cfg9346 to 0 count too?),
600 // so we need to enter wait-for-command state here
601 eeprom->mode = Chip9346_enter_command_mode;
602 eeprom->input = 0;
603 eeprom->tick = 0;
604
7cdeb319 605 DPRINTF("eeprom: +++ end of read, awaiting next command\n");
6cadb320
FB		 606#else
607 // original behaviour
a41b2ff2
PB		 608 ++eeprom->address;
609 eeprom->address &= EEPROM_9346_ADDR_MASK;
610 eeprom->output = eeprom->contents[eeprom->address];
611 eeprom->tick = 0;
612
7cdeb319
BP		 613 DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
614 eeprom->address, eeprom->output);
a41b2ff2
PB		 615#endif
616 }
617 break;
618
619 case Chip9346_data_write:
620 eeprom->input = (eeprom->input << 1) | (bit & 1);
621 if (eeprom->tick == 16)
622 {
7cdeb319
BP		 623 DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
624 eeprom->address, eeprom->input);
6cadb320 625
a41b2ff2
PB		 626 eeprom->contents[eeprom->address] = eeprom->input;
627 eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
628 eeprom->tick = 0;
629 eeprom->input = 0;
630 }
631 break;
632
633 case Chip9346_data_write_all:
634 eeprom->input = (eeprom->input << 1) | (bit & 1);
635 if (eeprom->tick == 16)
636 {
637 int i;
638 for (i = 0; i < EEPROM_9346_SIZE; i++)
639 {
640 eeprom->contents[i] = eeprom->input;
641 }
7cdeb319 642 DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
6cadb320 643
a41b2ff2
PB		 644 eeprom->mode = Chip9346_enter_command_mode;
645 eeprom->tick = 0;
646 eeprom->input = 0;
647 }
648 break;
649
650 default:
651 break;
652 }
653}
654
9596ebb7 655static int prom9346_get_wire(RTL8139State *s)
a41b2ff2
PB		 656{
657 EEprom9346 *eeprom = &s->eeprom;
658 if (!eeprom->eecs)
659 return 0;
660
661 return eeprom->eedo;
662}
663
9596ebb7
PB		 664/* FIXME: This should be merged into/replaced by eeprom93xx.c. */
665static void prom9346_set_wire(RTL8139State *s, int eecs, int eesk, int eedi)
a41b2ff2
PB		 666{
667 EEprom9346 *eeprom = &s->eeprom;
668 uint8_t old_eecs = eeprom->eecs;
669 uint8_t old_eesk = eeprom->eesk;
670
671 eeprom->eecs = eecs;
672 eeprom->eesk = eesk;
673 eeprom->eedi = eedi;
674
7cdeb319
BP		 675 DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
676 eeprom->eesk, eeprom->eedi, eeprom->eedo);
a41b2ff2
PB		 677
678 if (!old_eecs && eecs)
679 {
680 /* Synchronize start */
681 eeprom->tick = 0;
682 eeprom->input = 0;
683 eeprom->output = 0;
684 eeprom->mode = Chip9346_enter_command_mode;
685
7cdeb319 686 DPRINTF("=== eeprom: begin access, enter command mode\n");
a41b2ff2
PB		 687 }
688
689 if (!eecs)
690 {
7cdeb319 691 DPRINTF("=== eeprom: end access\n");
a41b2ff2
PB		 692 return;
693 }
694
695 if (!old_eesk && eesk)
696 {
697 /* SK front rules */
698 prom9346_shift_clock(eeprom);
699 }
700}
701
702static void rtl8139_update_irq(RTL8139State *s)
703{
704 int isr;
705 isr = (s->IntrStatus & s->IntrMask) & 0xffff;
6cadb320 706
7cdeb319
BP		 707 DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
708 s->IntrMask);
6cadb320 709
efd6dd45 710 qemu_set_irq(s->dev.irq[0], (isr != 0));
a41b2ff2
PB		 711}
712
a41b2ff2
PB		 713static int rtl8139_RxWrap(RTL8139State *s)
714{
715 /* wrapping enabled; assume 1.5k more buffer space if size < 65536 */
716 return (s->RxConfig & (1 << 7));
717}
718
719static int rtl8139_receiver_enabled(RTL8139State *s)
720{
721 return s->bChipCmdState & CmdRxEnb;
722}
723
724static int rtl8139_transmitter_enabled(RTL8139State *s)
725{
726 return s->bChipCmdState & CmdTxEnb;
727}
728
729static int rtl8139_cp_receiver_enabled(RTL8139State *s)
730{
731 return s->CpCmd & CPlusRxEnb;
732}
733
734static int rtl8139_cp_transmitter_enabled(RTL8139State *s)
735{
736 return s->CpCmd & CPlusTxEnb;
737}
738
739static void rtl8139_write_buffer(RTL8139State *s, const void *buf, int size)
740{
741 if (s->RxBufAddr + size > s->RxBufferSize)
742 {
743 int wrapped = MOD2(s->RxBufAddr + size, s->RxBufferSize);
744
745 /* write packet data */
ccf1d14a 746 if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
a41b2ff2 747 {
7cdeb319 748 DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
a41b2ff2
PB		 749
750 if (size > wrapped)
751 {
3ada003a
EGM		 752 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
753 buf, size-wrapped);
a41b2ff2
PB		 754 }
755
756 /* reset buffer pointer */
757 s->RxBufAddr = 0;
758
3ada003a
EGM		 759 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr,
760 buf + (size-wrapped), wrapped);
a41b2ff2
PB		 761
762 s->RxBufAddr = wrapped;
763
764 return;
765 }
766 }
767
768 /* non-wrapping path or overwrapping enabled */
3ada003a 769 pci_dma_write(&s->dev, s->RxBuf + s->RxBufAddr, buf, size);
a41b2ff2
PB		 770
771 s->RxBufAddr += size;
772}
773
774#define MIN_BUF_SIZE 60
3ada003a 775static inline dma_addr_t rtl8139_addr64(uint32_t low, uint32_t high)
a41b2ff2 776{
4be403c8 777 return low | ((uint64_t)high << 32);
a41b2ff2
PB		 778}
779
fcce6fd2
JW		 780/* Workaround for buggy guest driver such as linux who allocates rx
781 * rings after the receiver were enabled. */
782static bool rtl8139_cp_rx_valid(RTL8139State *s)
783{
784 return !(s->RxRingAddrLO == 0 && s->RxRingAddrHI == 0);
785}
786
4e68f7a0 787static int rtl8139_can_receive(NetClientState *nc)
a41b2ff2 788{
1673ad51 789 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
a41b2ff2
PB		 790 int avail;
791
aa1f17c1 792 /* Receive (drop) packets if card is disabled. */
a41b2ff2
PB		 793 if (!s->clock_enabled)
794 return 1;
795 if (!rtl8139_receiver_enabled(s))
796 return 1;
797
fcce6fd2 798 if (rtl8139_cp_receiver_enabled(s) && rtl8139_cp_rx_valid(s)) {
a41b2ff2
PB		 799 /* ??? Flow control not implemented in c+ mode.
800 This is a hack to work around slirp deficiencies anyway. */
801 return 1;
802 } else {
803 avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr,
804 s->RxBufferSize);
fee9d348 805 return (avail == 0 || avail >= 1514 || (s->IntrMask & RxOverflow));
a41b2ff2
PB		 806 }
807}
808
4e68f7a0 809static ssize_t rtl8139_do_receive(NetClientState *nc, const uint8_t *buf, size_t size_, int do_interrupt)
a41b2ff2 810{
1673ad51 811 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
18dabfd1 812 /* size is the length of the buffer passed to the driver */
4f1c942b 813 int size = size_;
18dabfd1 814 const uint8_t *dot1q_buf = NULL;
a41b2ff2
PB		 815
816 uint32_t packet_header = 0;
817
18dabfd1 818 uint8_t buf1[MIN_BUF_SIZE + VLAN_HLEN];
5fafdf24 819 static const uint8_t broadcast_macaddr[6] =
a41b2ff2
PB		 820 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
821
7cdeb319 822 DPRINTF(">>> received len=%d\n", size);
a41b2ff2
PB		 823
824 /* test if board clock is stopped */
825 if (!s->clock_enabled)
826 {
7cdeb319 827 DPRINTF("stopped ==========================\n");
4f1c942b 828 return -1;
a41b2ff2
PB		 829 }
830
831 /* first check if receiver is enabled */
832
833 if (!rtl8139_receiver_enabled(s))
834 {
7cdeb319 835 DPRINTF("receiver disabled ================\n");
4f1c942b 836 return -1;
a41b2ff2
PB		 837 }
838
839 /* XXX: check this */
840 if (s->RxConfig & AcceptAllPhys) {
841 /* promiscuous: receive all */
7cdeb319 842 DPRINTF(">>> packet received in promiscuous mode\n");
a41b2ff2
PB		 843
844 } else {
845 if (!memcmp(buf, broadcast_macaddr, 6)) {
846 /* broadcast address */
847 if (!(s->RxConfig & AcceptBroadcast))
848 {
7cdeb319 849 DPRINTF(">>> broadcast packet rejected\n");
6cadb320
FB		 850
851 /* update tally counter */
852 ++s->tally_counters.RxERR;
853
4f1c942b 854 return size;
a41b2ff2
PB		 855 }
856
857 packet_header |= RxBroadcast;
858
7cdeb319 859 DPRINTF(">>> broadcast packet received\n");
6cadb320
FB		 860
861 /* update tally counter */
862 ++s->tally_counters.RxOkBrd;
863
a41b2ff2
PB		 864 } else if (buf[0] & 0x01) {
865 /* multicast */
866 if (!(s->RxConfig & AcceptMulticast))
867 {
7cdeb319 868 DPRINTF(">>> multicast packet rejected\n");
6cadb320
FB		 869
870 /* update tally counter */
871 ++s->tally_counters.RxERR;
872
4f1c942b 873 return size;
a41b2ff2
PB		 874 }
875
876 int mcast_idx = compute_mcast_idx(buf);
877
878 if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
879 {
7cdeb319 880 DPRINTF(">>> multicast address mismatch\n");
6cadb320
FB		 881
882 /* update tally counter */
883 ++s->tally_counters.RxERR;
884
4f1c942b 885 return size;
a41b2ff2
PB		 886 }
887
888 packet_header |= RxMulticast;
889
7cdeb319 890 DPRINTF(">>> multicast packet received\n");
6cadb320
FB		 891
892 /* update tally counter */
893 ++s->tally_counters.RxOkMul;
894
a41b2ff2 895 } else if (s->phys[0] == buf[0] &&
3b46e624
TS		 896 s->phys[1] == buf[1] &&
897 s->phys[2] == buf[2] &&
898 s->phys[3] == buf[3] &&
899 s->phys[4] == buf[4] &&
a41b2ff2
PB		 900 s->phys[5] == buf[5]) {
901 /* match */
902 if (!(s->RxConfig & AcceptMyPhys))
903 {
7cdeb319 904 DPRINTF(">>> rejecting physical address matching packet\n");
6cadb320
FB		 905
906 /* update tally counter */
907 ++s->tally_counters.RxERR;
908
4f1c942b 909 return size;
a41b2ff2
PB		 910 }
911
912 packet_header |= RxPhysical;
913
7cdeb319 914 DPRINTF(">>> physical address matching packet received\n");
6cadb320
FB		 915
916 /* update tally counter */
917 ++s->tally_counters.RxOkPhy;
a41b2ff2
PB		 918
919 } else {
920
7cdeb319 921 DPRINTF(">>> unknown packet\n");
6cadb320
FB		 922
923 /* update tally counter */
924 ++s->tally_counters.RxERR;
925
4f1c942b 926 return size;
a41b2ff2
PB		 927 }
928 }
929
18dabfd1
BP		 930 /* if too small buffer, then expand it
931 * Include some tailroom in case a vlan tag is later removed. */
932 if (size < MIN_BUF_SIZE + VLAN_HLEN) {
a41b2ff2 933 memcpy(buf1, buf, size);
18dabfd1 934 memset(buf1 + size, 0, MIN_BUF_SIZE + VLAN_HLEN - size);
a41b2ff2 935 buf = buf1;
18dabfd1
BP		 936 if (size < MIN_BUF_SIZE) {
937 size = MIN_BUF_SIZE;
938 }
a41b2ff2
PB		 939 }
940
941 if (rtl8139_cp_receiver_enabled(s))
942 {
fcce6fd2
JW		 943 if (!rtl8139_cp_rx_valid(s)) {
944 return size;
945 }
946
7cdeb319 947 DPRINTF("in C+ Rx mode ================\n");
a41b2ff2
PB		 948
949 /* begin C+ receiver mode */
950
951/* w0 ownership flag */
952#define CP_RX_OWN (1<<31)
953/* w0 end of ring flag */
954#define CP_RX_EOR (1<<30)
955/* w0 bits 0...12 : buffer size */
956#define CP_RX_BUFFER_SIZE_MASK ((1<<13) - 1)
957/* w1 tag available flag */
958#define CP_RX_TAVA (1<<16)
959/* w1 bits 0...15 : VLAN tag */
960#define CP_RX_VLAN_TAG_MASK ((1<<16) - 1)
961/* w2 low 32bit of Rx buffer ptr */
962/* w3 high 32bit of Rx buffer ptr */
963
964 int descriptor = s->currCPlusRxDesc;
3ada003a 965 dma_addr_t cplus_rx_ring_desc;
a41b2ff2
PB		 966
967 cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
968 cplus_rx_ring_desc += 16 * descriptor;
969
7cdeb319 970 DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
3ada003a 971 "%08x %08x = "DMA_ADDR_FMT"\n", descriptor, s->RxRingAddrHI,
7cdeb319 972 s->RxRingAddrLO, cplus_rx_ring_desc);
a41b2ff2
PB		 973
974 uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
975
a6a29eea 976 pci_dma_read(&s->dev, cplus_rx_ring_desc, &val, 4);
a41b2ff2 977 rxdw0 = le32_to_cpu(val);
a6a29eea 978 pci_dma_read(&s->dev, cplus_rx_ring_desc+4, &val, 4);
a41b2ff2 979 rxdw1 = le32_to_cpu(val);
a6a29eea 980 pci_dma_read(&s->dev, cplus_rx_ring_desc+8, &val, 4);
a41b2ff2 981 rxbufLO = le32_to_cpu(val);
a6a29eea 982 pci_dma_read(&s->dev, cplus_rx_ring_desc+12, &val, 4);
a41b2ff2
PB		 983 rxbufHI = le32_to_cpu(val);
984
7cdeb319
BP		 985 DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
986 descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
a41b2ff2
PB		 987
988 if (!(rxdw0 & CP_RX_OWN))
989 {
7cdeb319
BP		 990 DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
991 descriptor);
6cadb320 992
a41b2ff2
PB		 993 s->IntrStatus |= RxOverflow;
994 ++s->RxMissed;
6cadb320
FB		 995
996 /* update tally counter */
997 ++s->tally_counters.RxERR;
998 ++s->tally_counters.MissPkt;
999
a41b2ff2 1000 rtl8139_update_irq(s);
4f1c942b 1001 return size_;
a41b2ff2
PB		 1002 }
1003
1004 uint32_t rx_space = rxdw0 & CP_RX_BUFFER_SIZE_MASK;
1005
18dabfd1
BP		 1006 /* write VLAN info to descriptor variables. */
1007 if (s->CpCmd & CPlusRxVLAN && be16_to_cpup((uint16_t *)
1008 &buf[ETHER_ADDR_LEN * 2]) == ETH_P_8021Q) {
1009 dot1q_buf = &buf[ETHER_ADDR_LEN * 2];
1010 size -= VLAN_HLEN;
1011 /* if too small buffer, use the tailroom added duing expansion */
1012 if (size < MIN_BUF_SIZE) {
1013 size = MIN_BUF_SIZE;
1014 }
1015
1016 rxdw1 &= ~CP_RX_VLAN_TAG_MASK;
1017 /* BE + ~le_to_cpu()~ + cpu_to_le() = BE */
1018 rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
1019 &dot1q_buf[ETHER_TYPE_LEN]);
1020
7cdeb319
BP		 1021 DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
1022 be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
18dabfd1
BP		 1023 } else {
1024 /* reset VLAN tag flag */
1025 rxdw1 &= ~CP_RX_TAVA;
1026 }
1027
6cadb320
FB		 1028 /* TODO: scatter the packet over available receive ring descriptors space */
1029
a41b2ff2
PB		 1030 if (size+4 > rx_space)
1031 {
7cdeb319
BP		 1032 DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
1033 descriptor, rx_space, size);
6cadb320 1034
a41b2ff2
PB		 1035 s->IntrStatus |= RxOverflow;
1036 ++s->RxMissed;
6cadb320
FB		 1037
1038 /* update tally counter */
1039 ++s->tally_counters.RxERR;
1040 ++s->tally_counters.MissPkt;
1041
a41b2ff2 1042 rtl8139_update_irq(s);
4f1c942b 1043 return size_;
a41b2ff2
PB		 1044 }
1045
3ada003a 1046 dma_addr_t rx_addr = rtl8139_addr64(rxbufLO, rxbufHI);
a41b2ff2
PB		 1047
1048 /* receive/copy to target memory */
18dabfd1 1049 if (dot1q_buf) {
3ada003a
EGM		 1050 pci_dma_write(&s->dev, rx_addr, buf, 2 * ETHER_ADDR_LEN);
1051 pci_dma_write(&s->dev, rx_addr + 2 * ETHER_ADDR_LEN,
1052 buf + 2 * ETHER_ADDR_LEN + VLAN_HLEN,
1053 size - 2 * ETHER_ADDR_LEN);
18dabfd1 1054 } else {
3ada003a 1055 pci_dma_write(&s->dev, rx_addr, buf, size);
18dabfd1 1056 }
a41b2ff2 1057
6cadb320
FB		 1058 if (s->CpCmd & CPlusRxChkSum)
1059 {
1060 /* do some packet checksumming */
1061 }
1062
a41b2ff2 1063 /* write checksum */
18dabfd1 1064 val = cpu_to_le32(crc32(0, buf, size_));
3ada003a 1065 pci_dma_write(&s->dev, rx_addr+size, (uint8_t *)&val, 4);
a41b2ff2
PB		 1066
1067/* first segment of received packet flag */
1068#define CP_RX_STATUS_FS (1<<29)
1069/* last segment of received packet flag */
1070#define CP_RX_STATUS_LS (1<<28)
1071/* multicast packet flag */
1072#define CP_RX_STATUS_MAR (1<<26)
1073/* physical-matching packet flag */
1074#define CP_RX_STATUS_PAM (1<<25)
1075/* broadcast packet flag */
1076#define CP_RX_STATUS_BAR (1<<24)
1077/* runt packet flag */
1078#define CP_RX_STATUS_RUNT (1<<19)
1079/* crc error flag */
1080#define CP_RX_STATUS_CRC (1<<18)
1081/* IP checksum error flag */
1082#define CP_RX_STATUS_IPF (1<<15)
1083/* UDP checksum error flag */
1084#define CP_RX_STATUS_UDPF (1<<14)
1085/* TCP checksum error flag */
1086#define CP_RX_STATUS_TCPF (1<<13)
1087
1088 /* transfer ownership to target */
1089 rxdw0 &= ~CP_RX_OWN;
1090
1091 /* set first segment bit */
1092 rxdw0 |= CP_RX_STATUS_FS;
1093
1094 /* set last segment bit */
1095 rxdw0 |= CP_RX_STATUS_LS;
1096
1097 /* set received packet type flags */
1098 if (packet_header & RxBroadcast)
1099 rxdw0 |= CP_RX_STATUS_BAR;
1100 if (packet_header & RxMulticast)
1101 rxdw0 |= CP_RX_STATUS_MAR;
1102 if (packet_header & RxPhysical)
1103 rxdw0 |= CP_RX_STATUS_PAM;
1104
1105 /* set received size */
1106 rxdw0 &= ~CP_RX_BUFFER_SIZE_MASK;
1107 rxdw0 |= (size+4);
1108
a41b2ff2
PB		 1109 /* update ring data */
1110 val = cpu_to_le32(rxdw0);
3ada003a 1111 pci_dma_write(&s->dev, cplus_rx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1112 val = cpu_to_le32(rxdw1);
3ada003a 1113 pci_dma_write(&s->dev, cplus_rx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1114
6cadb320
FB		 1115 /* update tally counter */
1116 ++s->tally_counters.RxOk;
1117
a41b2ff2
PB		 1118 /* seek to next Rx descriptor */
1119 if (rxdw0 & CP_RX_EOR)
1120 {
1121 s->currCPlusRxDesc = 0;
1122 }
1123 else
1124 {
1125 ++s->currCPlusRxDesc;
1126 }
1127
7cdeb319 1128 DPRINTF("done C+ Rx mode ----------------\n");
a41b2ff2
PB		 1129
1130 }
1131 else
1132 {
7cdeb319 1133 DPRINTF("in ring Rx mode ================\n");
6cadb320 1134
a41b2ff2
PB		 1135 /* begin ring receiver mode */
1136 int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
1137
1138 /* if receiver buffer is empty then avail == 0 */
1139
1140 if (avail != 0 && size + 8 >= avail)
1141 {
7cdeb319
BP		 1142 DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
1143 "read 0x%04x === available 0x%04x need 0x%04x\n",
1144 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
6cadb320 1145
a41b2ff2
PB		 1146 s->IntrStatus |= RxOverflow;
1147 ++s->RxMissed;
1148 rtl8139_update_irq(s);
4f1c942b 1149 return size_;
a41b2ff2
PB		 1150 }
1151
1152 packet_header |= RxStatusOK;
1153
1154 packet_header |= (((size+4) << 16) & 0xffff0000);
1155
1156 /* write header */
1157 uint32_t val = cpu_to_le32(packet_header);
1158
1159 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1160
1161 rtl8139_write_buffer(s, buf, size);
1162
1163 /* write checksum */
ccf1d14a 1164 val = cpu_to_le32(crc32(0, buf, size));
a41b2ff2
PB		 1165 rtl8139_write_buffer(s, (uint8_t *)&val, 4);
1166
1167 /* correct buffer write pointer */
1168 s->RxBufAddr = MOD2((s->RxBufAddr + 3) & ~0x3, s->RxBufferSize);
1169
1170 /* now we can signal we have received something */
1171
7cdeb319
BP		 1172 DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
1173 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 1174 }
1175
1176 s->IntrStatus |= RxOK;
6cadb320
FB		 1177
1178 if (do_interrupt)
1179 {
1180 rtl8139_update_irq(s);
1181 }
4f1c942b
MM		 1182
1183 return size_;
6cadb320
FB		 1184}
1185
4e68f7a0 1186static ssize_t rtl8139_receive(NetClientState *nc, const uint8_t *buf, size_t size)
6cadb320 1187{
1673ad51 1188 return rtl8139_do_receive(nc, buf, size, 1);
a41b2ff2
PB		 1189}
1190
1191static void rtl8139_reset_rxring(RTL8139State *s, uint32_t bufferSize)
1192{
1193 s->RxBufferSize = bufferSize;
1194 s->RxBufPtr = 0;
1195 s->RxBufAddr = 0;
1196}
1197
7f23f812 1198static void rtl8139_reset(DeviceState *d)
a41b2ff2 1199{
7f23f812 1200 RTL8139State *s = container_of(d, RTL8139State, dev.qdev);
a41b2ff2
PB		 1201 int i;
1202
1203 /* restore MAC address */
254111ec 1204 memcpy(s->phys, s->conf.macaddr.a, 6);
a41b2ff2
PB		 1205
1206 /* reset interrupt mask */
1207 s->IntrStatus = 0;
1208 s->IntrMask = 0;
1209
1210 rtl8139_update_irq(s);
1211
a41b2ff2
PB		 1212 /* mark all status registers as owned by host */
1213 for (i = 0; i < 4; ++i)
1214 {
1215 s->TxStatus[i] = TxHostOwns;
1216 }
1217
1218 s->currTxDesc = 0;
1219 s->currCPlusRxDesc = 0;
1220 s->currCPlusTxDesc = 0;
1221
1222 s->RxRingAddrLO = 0;
1223 s->RxRingAddrHI = 0;
1224
1225 s->RxBuf = 0;
1226
1227 rtl8139_reset_rxring(s, 8192);
1228
1229 /* ACK the reset */
1230 s->TxConfig = 0;
1231
1232#if 0
1233// s->TxConfig |= HW_REVID(1, 0, 0, 0, 0, 0, 0); // RTL-8139 HasHltClk
1234 s->clock_enabled = 0;
1235#else
6cadb320 1236 s->TxConfig |= HW_REVID(1, 1, 1, 0, 1, 1, 0); // RTL-8139C+ HasLWake
a41b2ff2
PB		 1237 s->clock_enabled = 1;
1238#endif
1239
1240 s->bChipCmdState = CmdReset; /* RxBufEmpty bit is calculated on read from ChipCmd */;
1241
1242 /* set initial state data */
1243 s->Config0 = 0x0; /* No boot ROM */
1244 s->Config1 = 0xC; /* IO mapped and MEM mapped registers available */
1245 s->Config3 = 0x1; /* fast back-to-back compatible */
1246 s->Config5 = 0x0;
1247
5fafdf24 1248 s->CSCR = CSCR_F_LINK_100 | CSCR_HEART_BIT | CSCR_LD;
a41b2ff2
PB		 1249
1250 s->CpCmd = 0x0; /* reset C+ mode */
2c3891ab
AL		 1251 s->cplus_enabled = 0;
1252
a41b2ff2
PB		 1253
1254// s->BasicModeCtrl = 0x3100; // 100Mbps, full duplex, autonegotiation
1255// s->BasicModeCtrl = 0x2100; // 100Mbps, full duplex
1256 s->BasicModeCtrl = 0x1000; // autonegotiation
1257
1258 s->BasicModeStatus = 0x7809;
1259 //s->BasicModeStatus |= 0x0040; /* UTP medium */
1260 s->BasicModeStatus |= 0x0020; /* autonegotiation completed */
1261 s->BasicModeStatus |= 0x0004; /* link is up */
1262
1263 s->NWayAdvert = 0x05e1; /* all modes, full duplex */
1264 s->NWayLPAR = 0x05e1; /* all modes, full duplex */
1265 s->NWayExpansion = 0x0001; /* autonegotiation supported */
6cadb320
FB		 1266
1267 /* also reset timer and disable timer interrupt */
1268 s->TCTR = 0;
1269 s->TimerInt = 0;
1270 s->TCTR_base = 0;
1271
1272 /* reset tally counters */
1273 RTL8139TallyCounters_clear(&s->tally_counters);
1274}
1275
b1d8e52e 1276static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters)
6cadb320
FB		 1277{
1278 counters->TxOk = 0;
1279 counters->RxOk = 0;
1280 counters->TxERR = 0;
1281 counters->RxERR = 0;
1282 counters->MissPkt = 0;
1283 counters->FAE = 0;
1284 counters->Tx1Col = 0;
1285 counters->TxMCol = 0;
1286 counters->RxOkPhy = 0;
1287 counters->RxOkBrd = 0;
1288 counters->RxOkMul = 0;
1289 counters->TxAbt = 0;
1290 counters->TxUndrn = 0;
1291}
1292
3ada003a 1293static void RTL8139TallyCounters_dma_write(RTL8139State *s, dma_addr_t tc_addr)
6cadb320 1294{
3ada003a 1295 RTL8139TallyCounters *tally_counters = &s->tally_counters;
6cadb320
FB		 1296 uint16_t val16;
1297 uint32_t val32;
1298 uint64_t val64;
1299
1300 val64 = cpu_to_le64(tally_counters->TxOk);
3ada003a 1301 pci_dma_write(&s->dev, tc_addr + 0, (uint8_t *)&val64, 8);
6cadb320
FB		 1302
1303 val64 = cpu_to_le64(tally_counters->RxOk);
3ada003a 1304 pci_dma_write(&s->dev, tc_addr + 8, (uint8_t *)&val64, 8);
6cadb320
FB		 1305
1306 val64 = cpu_to_le64(tally_counters->TxERR);
3ada003a 1307 pci_dma_write(&s->dev, tc_addr + 16, (uint8_t *)&val64, 8);
6cadb320
FB		 1308
1309 val32 = cpu_to_le32(tally_counters->RxERR);
3ada003a 1310 pci_dma_write(&s->dev, tc_addr + 24, (uint8_t *)&val32, 4);
6cadb320
FB		 1311
1312 val16 = cpu_to_le16(tally_counters->MissPkt);
3ada003a 1313 pci_dma_write(&s->dev, tc_addr + 28, (uint8_t *)&val16, 2);
6cadb320
FB		 1314
1315 val16 = cpu_to_le16(tally_counters->FAE);
3ada003a 1316 pci_dma_write(&s->dev, tc_addr + 30, (uint8_t *)&val16, 2);
6cadb320
FB		 1317
1318 val32 = cpu_to_le32(tally_counters->Tx1Col);
3ada003a 1319 pci_dma_write(&s->dev, tc_addr + 32, (uint8_t *)&val32, 4);
6cadb320
FB		 1320
1321 val32 = cpu_to_le32(tally_counters->TxMCol);
3ada003a 1322 pci_dma_write(&s->dev, tc_addr + 36, (uint8_t *)&val32, 4);
6cadb320
FB		 1323
1324 val64 = cpu_to_le64(tally_counters->RxOkPhy);
3ada003a 1325 pci_dma_write(&s->dev, tc_addr + 40, (uint8_t *)&val64, 8);
6cadb320
FB		 1326
1327 val64 = cpu_to_le64(tally_counters->RxOkBrd);
3ada003a 1328 pci_dma_write(&s->dev, tc_addr + 48, (uint8_t *)&val64, 8);
6cadb320
FB		 1329
1330 val32 = cpu_to_le32(tally_counters->RxOkMul);
3ada003a 1331 pci_dma_write(&s->dev, tc_addr + 56, (uint8_t *)&val32, 4);
6cadb320
FB		 1332
1333 val16 = cpu_to_le16(tally_counters->TxAbt);
3ada003a 1334 pci_dma_write(&s->dev, tc_addr + 60, (uint8_t *)&val16, 2);
6cadb320
FB		 1335
1336 val16 = cpu_to_le16(tally_counters->TxUndrn);
3ada003a 1337 pci_dma_write(&s->dev, tc_addr + 62, (uint8_t *)&val16, 2);
6cadb320
FB		 1338}
1339
1340/* Loads values of tally counters from VM state file */
9d29cdea
JQ		 1341
1342static const VMStateDescription vmstate_tally_counters = {
1343 .name = "tally_counters",
1344 .version_id = 1,
1345 .minimum_version_id = 1,
1346 .minimum_version_id_old = 1,
1347 .fields = (VMStateField []) {
1348 VMSTATE_UINT64(TxOk, RTL8139TallyCounters),
1349 VMSTATE_UINT64(RxOk, RTL8139TallyCounters),
1350 VMSTATE_UINT64(TxERR, RTL8139TallyCounters),
1351 VMSTATE_UINT32(RxERR, RTL8139TallyCounters),
1352 VMSTATE_UINT16(MissPkt, RTL8139TallyCounters),
1353 VMSTATE_UINT16(FAE, RTL8139TallyCounters),
1354 VMSTATE_UINT32(Tx1Col, RTL8139TallyCounters),
1355 VMSTATE_UINT32(TxMCol, RTL8139TallyCounters),
1356 VMSTATE_UINT64(RxOkPhy, RTL8139TallyCounters),
1357 VMSTATE_UINT64(RxOkBrd, RTL8139TallyCounters),
1358 VMSTATE_UINT16(TxAbt, RTL8139TallyCounters),
1359 VMSTATE_UINT16(TxUndrn, RTL8139TallyCounters),
1360 VMSTATE_END_OF_LIST()
1361 }
1362};
a41b2ff2
PB		 1363
1364static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
1365{
1366 val &= 0xff;
1367
7cdeb319 1368 DPRINTF("ChipCmd write val=0x%08x\n", val);
a41b2ff2
PB		 1369
1370 if (val & CmdReset)
1371 {
7cdeb319 1372 DPRINTF("ChipCmd reset\n");
7f23f812 1373 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1374 }
1375 if (val & CmdRxEnb)
1376 {
7cdeb319 1377 DPRINTF("ChipCmd enable receiver\n");
718da2b9
FB		 1378
1379 s->currCPlusRxDesc = 0;
a41b2ff2
PB		 1380 }
1381 if (val & CmdTxEnb)
1382 {
7cdeb319 1383 DPRINTF("ChipCmd enable transmitter\n");
718da2b9
FB		 1384
1385 s->currCPlusTxDesc = 0;
a41b2ff2
PB		 1386 }
1387
ebabb67a 1388 /* mask unwritable bits */
a41b2ff2
PB		 1389 val = SET_MASKED(val, 0xe3, s->bChipCmdState);
1390
1391 /* Deassert reset pin before next read */
1392 val &= ~CmdReset;
1393
1394 s->bChipCmdState = val;
1395}
1396
1397static int rtl8139_RxBufferEmpty(RTL8139State *s)
1398{
1399 int unread = MOD2(s->RxBufferSize + s->RxBufAddr - s->RxBufPtr, s->RxBufferSize);
1400
1401 if (unread != 0)
1402 {
7cdeb319 1403 DPRINTF("receiver buffer data available 0x%04x\n", unread);
a41b2ff2
PB		 1404 return 0;
1405 }
1406
7cdeb319 1407 DPRINTF("receiver buffer is empty\n");
a41b2ff2
PB		 1408
1409 return 1;
1410}
1411
1412static uint32_t rtl8139_ChipCmd_read(RTL8139State *s)
1413{
1414 uint32_t ret = s->bChipCmdState;
1415
1416 if (rtl8139_RxBufferEmpty(s))
1417 ret |= RxBufEmpty;
1418
7cdeb319 1419 DPRINTF("ChipCmd read val=0x%04x\n", ret);
a41b2ff2
PB		 1420
1421 return ret;
1422}
1423
1424static void rtl8139_CpCmd_write(RTL8139State *s, uint32_t val)
1425{
1426 val &= 0xffff;
1427
7cdeb319 1428 DPRINTF("C+ command register write(w) val=0x%04x\n", val);
a41b2ff2 1429
2c3891ab
AL		 1430 s->cplus_enabled = 1;
1431
ebabb67a 1432 /* mask unwritable bits */
a41b2ff2
PB		 1433 val = SET_MASKED(val, 0xff84, s->CpCmd);
1434
1435 s->CpCmd = val;
1436}
1437
1438static uint32_t rtl8139_CpCmd_read(RTL8139State *s)
1439{
1440 uint32_t ret = s->CpCmd;
1441
7cdeb319 1442 DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
6cadb320
FB		 1443
1444 return ret;
1445}
1446
1447static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
1448{
7cdeb319 1449 DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
6cadb320
FB		 1450}
1451
1452static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
1453{
1454 uint32_t ret = 0;
1455
7cdeb319 1456 DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1457
1458 return ret;
1459}
1460
ebabb67a 1461static int rtl8139_config_writable(RTL8139State *s)
a41b2ff2 1462{
eb46c5ed 1463 if ((s->Cfg9346 & Chip9346_op_mask) == Cfg9346_ConfigWrite)
a41b2ff2
PB		 1464 {
1465 return 1;
1466 }
1467
7cdeb319 1468 DPRINTF("Configuration registers are write-protected\n");
a41b2ff2
PB		 1469
1470 return 0;
1471}
1472
1473static void rtl8139_BasicModeCtrl_write(RTL8139State *s, uint32_t val)
1474{
1475 val &= 0xffff;
1476
7cdeb319 1477 DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
a41b2ff2 1478
ebabb67a 1479 /* mask unwritable bits */
e3d7e843 1480 uint32_t mask = 0x4cff;
a41b2ff2 1481
ebabb67a 1482 if (1 || !rtl8139_config_writable(s))
a41b2ff2
PB		 1483 {
1484 /* Speed setting and autonegotiation enable bits are read-only */
1485 mask |= 0x3000;
1486 /* Duplex mode setting is read-only */
1487 mask |= 0x0100;
1488 }
1489
1490 val = SET_MASKED(val, mask, s->BasicModeCtrl);
1491
1492 s->BasicModeCtrl = val;
1493}
1494
1495static uint32_t rtl8139_BasicModeCtrl_read(RTL8139State *s)
1496{
1497 uint32_t ret = s->BasicModeCtrl;
1498
7cdeb319 1499 DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1500
1501 return ret;
1502}
1503
1504static void rtl8139_BasicModeStatus_write(RTL8139State *s, uint32_t val)
1505{
1506 val &= 0xffff;
1507
7cdeb319 1508 DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
a41b2ff2 1509
ebabb67a 1510 /* mask unwritable bits */
a41b2ff2
PB		 1511 val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
1512
1513 s->BasicModeStatus = val;
1514}
1515
1516static uint32_t rtl8139_BasicModeStatus_read(RTL8139State *s)
1517{
1518 uint32_t ret = s->BasicModeStatus;
1519
7cdeb319 1520 DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 1521
1522 return ret;
1523}
1524
1525static void rtl8139_Cfg9346_write(RTL8139State *s, uint32_t val)
1526{
1527 val &= 0xff;
1528
7cdeb319 1529 DPRINTF("Cfg9346 write val=0x%02x\n", val);
a41b2ff2 1530
ebabb67a 1531 /* mask unwritable bits */
a41b2ff2
PB		 1532 val = SET_MASKED(val, 0x31, s->Cfg9346);
1533
1534 uint32_t opmode = val & 0xc0;
1535 uint32_t eeprom_val = val & 0xf;
1536
1537 if (opmode == 0x80) {
1538 /* eeprom access */
1539 int eecs = (eeprom_val & 0x08)?1:0;
1540 int eesk = (eeprom_val & 0x04)?1:0;
1541 int eedi = (eeprom_val & 0x02)?1:0;
1542 prom9346_set_wire(s, eecs, eesk, eedi);
1543 } else if (opmode == 0x40) {
1544 /* Reset. */
1545 val = 0;
7f23f812 1546 rtl8139_reset(&s->dev.qdev);
a41b2ff2
PB		 1547 }
1548
1549 s->Cfg9346 = val;
1550}
1551
1552static uint32_t rtl8139_Cfg9346_read(RTL8139State *s)
1553{
1554 uint32_t ret = s->Cfg9346;
1555
1556 uint32_t opmode = ret & 0xc0;
1557
1558 if (opmode == 0x80)
1559 {
1560 /* eeprom access */
1561 int eedo = prom9346_get_wire(s);
1562 if (eedo)
1563 {
1564 ret |= 0x01;
1565 }
1566 else
1567 {
1568 ret &= ~0x01;
1569 }
1570 }
1571
7cdeb319 1572 DPRINTF("Cfg9346 read val=0x%02x\n", ret);
a41b2ff2
PB		 1573
1574 return ret;
1575}
1576
1577static void rtl8139_Config0_write(RTL8139State *s, uint32_t val)
1578{
1579 val &= 0xff;
1580
7cdeb319 1581 DPRINTF("Config0 write val=0x%02x\n", val);
a41b2ff2 1582
ebabb67a 1583 if (!rtl8139_config_writable(s)) {
a41b2ff2 1584 return;
ebabb67a 1585 }
a41b2ff2 1586
ebabb67a 1587 /* mask unwritable bits */
a41b2ff2
PB		 1588 val = SET_MASKED(val, 0xf8, s->Config0);
1589
1590 s->Config0 = val;
1591}
1592
1593static uint32_t rtl8139_Config0_read(RTL8139State *s)
1594{
1595 uint32_t ret = s->Config0;
1596
7cdeb319 1597 DPRINTF("Config0 read val=0x%02x\n", ret);
a41b2ff2
PB		 1598
1599 return ret;
1600}
1601
1602static void rtl8139_Config1_write(RTL8139State *s, uint32_t val)
1603{
1604 val &= 0xff;
1605
7cdeb319 1606 DPRINTF("Config1 write val=0x%02x\n", val);
a41b2ff2 1607
ebabb67a 1608 if (!rtl8139_config_writable(s)) {
a41b2ff2 1609 return;
ebabb67a 1610 }
a41b2ff2 1611
ebabb67a 1612 /* mask unwritable bits */
a41b2ff2
PB		 1613 val = SET_MASKED(val, 0xC, s->Config1);
1614
1615 s->Config1 = val;
1616}
1617
1618static uint32_t rtl8139_Config1_read(RTL8139State *s)
1619{
1620 uint32_t ret = s->Config1;
1621
7cdeb319 1622 DPRINTF("Config1 read val=0x%02x\n", ret);
a41b2ff2
PB		 1623
1624 return ret;
1625}
1626
1627static void rtl8139_Config3_write(RTL8139State *s, uint32_t val)
1628{
1629 val &= 0xff;
1630
7cdeb319 1631 DPRINTF("Config3 write val=0x%02x\n", val);
a41b2ff2 1632
ebabb67a 1633 if (!rtl8139_config_writable(s)) {
a41b2ff2 1634 return;
ebabb67a 1635 }
a41b2ff2 1636
ebabb67a 1637 /* mask unwritable bits */
a41b2ff2
PB		 1638 val = SET_MASKED(val, 0x8F, s->Config3);
1639
1640 s->Config3 = val;
1641}
1642
1643static uint32_t rtl8139_Config3_read(RTL8139State *s)
1644{
1645 uint32_t ret = s->Config3;
1646
7cdeb319 1647 DPRINTF("Config3 read val=0x%02x\n", ret);
a41b2ff2
PB		 1648
1649 return ret;
1650}
1651
1652static void rtl8139_Config4_write(RTL8139State *s, uint32_t val)
1653{
1654 val &= 0xff;
1655
7cdeb319 1656 DPRINTF("Config4 write val=0x%02x\n", val);
a41b2ff2 1657
ebabb67a 1658 if (!rtl8139_config_writable(s)) {
a41b2ff2 1659 return;
ebabb67a 1660 }
a41b2ff2 1661
ebabb67a 1662 /* mask unwritable bits */
a41b2ff2
PB		 1663 val = SET_MASKED(val, 0x0a, s->Config4);
1664
1665 s->Config4 = val;
1666}
1667
1668static uint32_t rtl8139_Config4_read(RTL8139State *s)
1669{
1670 uint32_t ret = s->Config4;
1671
7cdeb319 1672 DPRINTF("Config4 read val=0x%02x\n", ret);
a41b2ff2
PB		 1673
1674 return ret;
1675}
1676
1677static void rtl8139_Config5_write(RTL8139State *s, uint32_t val)
1678{
1679 val &= 0xff;
1680
7cdeb319 1681 DPRINTF("Config5 write val=0x%02x\n", val);
a41b2ff2 1682
ebabb67a 1683 /* mask unwritable bits */
a41b2ff2
PB		 1684 val = SET_MASKED(val, 0x80, s->Config5);
1685
1686 s->Config5 = val;
1687}
1688
1689static uint32_t rtl8139_Config5_read(RTL8139State *s)
1690{
1691 uint32_t ret = s->Config5;
1692
7cdeb319 1693 DPRINTF("Config5 read val=0x%02x\n", ret);
a41b2ff2
PB		 1694
1695 return ret;
1696}
1697
1698static void rtl8139_TxConfig_write(RTL8139State *s, uint32_t val)
1699{
1700 if (!rtl8139_transmitter_enabled(s))
1701 {
7cdeb319 1702 DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1703 return;
1704 }
1705
7cdeb319 1706 DPRINTF("TxConfig write val=0x%08x\n", val);
a41b2ff2
PB		 1707
1708 val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
1709
1710 s->TxConfig = val;
1711}
1712
1713static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
1714{
7cdeb319 1715 DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
6cadb320
FB		 1716
1717 uint32_t tc = s->TxConfig;
1718 tc &= 0xFFFFFF00;
1719 tc |= (val & 0x000000FF);
1720 rtl8139_TxConfig_write(s, tc);
a41b2ff2
PB		 1721}
1722
1723static uint32_t rtl8139_TxConfig_read(RTL8139State *s)
1724{
1725 uint32_t ret = s->TxConfig;
1726
7cdeb319 1727 DPRINTF("TxConfig read val=0x%04x\n", ret);
a41b2ff2
PB		 1728
1729 return ret;
1730}
1731
1732static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
1733{
7cdeb319 1734 DPRINTF("RxConfig write val=0x%08x\n", val);
a41b2ff2 1735
ebabb67a 1736 /* mask unwritable bits */
a41b2ff2
PB		 1737 val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
1738
1739 s->RxConfig = val;
1740
1741 /* reset buffer size and read/write pointers */
1742 rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
1743
7cdeb319 1744 DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
a41b2ff2
PB		 1745}
1746
1747static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
1748{
1749 uint32_t ret = s->RxConfig;
1750
7cdeb319 1751 DPRINTF("RxConfig read val=0x%08x\n", ret);
a41b2ff2
PB		 1752
1753 return ret;
1754}
1755
bf6b87a8
BP		 1756static void rtl8139_transfer_frame(RTL8139State *s, uint8_t *buf, int size,
1757 int do_interrupt, const uint8_t *dot1q_buf)
718da2b9 1758{
bf6b87a8
BP		 1759 struct iovec *iov = NULL;
1760
718da2b9
FB		 1761 if (!size)
1762 {
7cdeb319 1763 DPRINTF("+++ empty ethernet frame\n");
718da2b9
FB		 1764 return;
1765 }
1766
bf6b87a8
BP		 1767 if (dot1q_buf && size >= ETHER_ADDR_LEN * 2) {
1768 iov = (struct iovec[3]) {
1769 { .iov_base = buf, .iov_len = ETHER_ADDR_LEN * 2 },
1770 { .iov_base = (void *) dot1q_buf, .iov_len = VLAN_HLEN },
1771 { .iov_base = buf + ETHER_ADDR_LEN * 2,
1772 .iov_len = size - ETHER_ADDR_LEN * 2 },
1773 };
1774 }
1775
718da2b9
FB		 1776 if (TxLoopBack == (s->TxConfig & TxLoopBack))
1777 {
bf6b87a8
BP		 1778 size_t buf2_size;
1779 uint8_t *buf2;
1780
1781 if (iov) {
1782 buf2_size = iov_size(iov, 3);
7267c094 1783 buf2 = g_malloc(buf2_size);
dcf6f5e1 1784 iov_to_buf(iov, 3, 0, buf2, buf2_size);
bf6b87a8
BP		 1785 buf = buf2;
1786 }
1787
7cdeb319 1788 DPRINTF("+++ transmit loopback mode\n");
1673ad51 1789 rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
bf6b87a8
BP		 1790
1791 if (iov) {
7267c094 1792 g_free(buf2);
bf6b87a8 1793 }
718da2b9
FB		 1794 }
1795 else
1796 {
bf6b87a8
BP		 1797 if (iov) {
1798 qemu_sendv_packet(&s->nic->nc, iov, 3);
1799 } else {
1800 qemu_send_packet(&s->nic->nc, buf, size);
1801 }
718da2b9
FB		 1802 }
1803}
1804
a41b2ff2
PB		 1805static int rtl8139_transmit_one(RTL8139State *s, int descriptor)
1806{
1807 if (!rtl8139_transmitter_enabled(s))
1808 {
7cdeb319
BP		 1809 DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
1810 "disabled\n", descriptor);
a41b2ff2
PB		 1811 return 0;
1812 }
1813
1814 if (s->TxStatus[descriptor] & TxHostOwns)
1815 {
7cdeb319
BP		 1816 DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
1817 "(%08x)\n", descriptor, s->TxStatus[descriptor]);
a41b2ff2
PB		 1818 return 0;
1819 }
1820
7cdeb319 1821 DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
a41b2ff2
PB		 1822
1823 int txsize = s->TxStatus[descriptor] & 0x1fff;
1824 uint8_t txbuffer[0x2000];
1825
7cdeb319
BP		 1826 DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
1827 txsize, s->TxAddr[descriptor]);
a41b2ff2 1828
3ada003a 1829 pci_dma_read(&s->dev, s->TxAddr[descriptor], txbuffer, txsize);
a41b2ff2
PB		 1830
1831 /* Mark descriptor as transferred */
1832 s->TxStatus[descriptor] |= TxHostOwns;
1833 s->TxStatus[descriptor] |= TxStatOK;
1834
bf6b87a8 1835 rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
6cadb320 1836
7cdeb319
BP		 1837 DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
1838 descriptor);
a41b2ff2
PB		 1839
1840 /* update interrupt */
1841 s->IntrStatus |= TxOK;
1842 rtl8139_update_irq(s);
1843
1844 return 1;
1845}
1846
718da2b9
FB		 1847/* structures and macros for task offloading */
1848typedef struct ip_header
1849{
1850 uint8_t ip_ver_len; /* version and header length */
1851 uint8_t ip_tos; /* type of service */
1852 uint16_t ip_len; /* total length */
1853 uint16_t ip_id; /* identification */
1854 uint16_t ip_off; /* fragment offset field */
1855 uint8_t ip_ttl; /* time to live */
1856 uint8_t ip_p; /* protocol */
1857 uint16_t ip_sum; /* checksum */
1858 uint32_t ip_src,ip_dst; /* source and dest address */
1859} ip_header;
1860
1861#define IP_HEADER_VERSION_4 4
1862#define IP_HEADER_VERSION(ip) ((ip->ip_ver_len >> 4)&0xf)
1863#define IP_HEADER_LENGTH(ip) (((ip->ip_ver_len)&0xf) << 2)
1864
1865typedef struct tcp_header
1866{
1867 uint16_t th_sport; /* source port */
1868 uint16_t th_dport; /* destination port */
1869 uint32_t th_seq; /* sequence number */
1870 uint32_t th_ack; /* acknowledgement number */
1871 uint16_t th_offset_flags; /* data offset, reserved 6 bits, TCP protocol flags */
1872 uint16_t th_win; /* window */
1873 uint16_t th_sum; /* checksum */
1874 uint16_t th_urp; /* urgent pointer */
1875} tcp_header;
1876
1877typedef struct udp_header
1878{
1879 uint16_t uh_sport; /* source port */
1880 uint16_t uh_dport; /* destination port */
1881 uint16_t uh_ulen; /* udp length */
1882 uint16_t uh_sum; /* udp checksum */
1883} udp_header;
1884
1885typedef struct ip_pseudo_header
1886{
1887 uint32_t ip_src;
1888 uint32_t ip_dst;
1889 uint8_t zeros;
1890 uint8_t ip_proto;
1891 uint16_t ip_payload;
1892} ip_pseudo_header;
1893
1894#define IP_PROTO_TCP 6
1895#define IP_PROTO_UDP 17
1896
1897#define TCP_HEADER_DATA_OFFSET(tcp) (((be16_to_cpu(tcp->th_offset_flags) >> 12)&0xf) << 2)
1898#define TCP_FLAGS_ONLY(flags) ((flags)&0x3f)
1899#define TCP_HEADER_FLAGS(tcp) TCP_FLAGS_ONLY(be16_to_cpu(tcp->th_offset_flags))
1900
1901#define TCP_HEADER_CLEAR_FLAGS(tcp, off) ((tcp)->th_offset_flags &= cpu_to_be16(~TCP_FLAGS_ONLY(off)))
1902
1903#define TCP_FLAG_FIN 0x01
1904#define TCP_FLAG_PUSH 0x08
1905
1906/* produces ones' complement sum of data */
1907static uint16_t ones_complement_sum(uint8_t *data, size_t len)
1908{
1909 uint32_t result = 0;
1910
1911 for (; len > 1; data+=2, len-=2)
1912 {
1913 result += *(uint16_t*)data;
1914 }
1915
1916 /* add the remainder byte */
1917 if (len)
1918 {
1919 uint8_t odd[2] = {*data, 0};
1920 result += *(uint16_t*)odd;
1921 }
1922
1923 while (result>>16)
1924 result = (result & 0xffff) + (result >> 16);
1925
1926 return result;
1927}
1928
1929static uint16_t ip_checksum(void *data, size_t len)
1930{
1931 return ~ones_complement_sum((uint8_t*)data, len);
1932}
1933
a41b2ff2
PB		 1934static int rtl8139_cplus_transmit_one(RTL8139State *s)
1935{
1936 if (!rtl8139_transmitter_enabled(s))
1937 {
7cdeb319 1938 DPRINTF("+++ C+ mode: transmitter disabled\n");
a41b2ff2
PB		 1939 return 0;
1940 }
1941
1942 if (!rtl8139_cp_transmitter_enabled(s))
1943 {
7cdeb319 1944 DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
a41b2ff2
PB		 1945 return 0 ;
1946 }
1947
1948 int descriptor = s->currCPlusTxDesc;
1949
3ada003a 1950 dma_addr_t cplus_tx_ring_desc = rtl8139_addr64(s->TxAddr[0], s->TxAddr[1]);
a41b2ff2
PB		 1951
1952 /* Normal priority ring */
1953 cplus_tx_ring_desc += 16 * descriptor;
1954
7cdeb319 1955 DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
4abf12f4 1956 "%08x %08x = 0x"DMA_ADDR_FMT"\n", descriptor, s->TxAddr[1],
7cdeb319 1957 s->TxAddr[0], cplus_tx_ring_desc);
a41b2ff2
PB		 1958
1959 uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
1960
3ada003a 1961 pci_dma_read(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 1962 txdw0 = le32_to_cpu(val);
3ada003a 1963 pci_dma_read(&s->dev, cplus_tx_ring_desc+4, (uint8_t *)&val, 4);
a41b2ff2 1964 txdw1 = le32_to_cpu(val);
3ada003a 1965 pci_dma_read(&s->dev, cplus_tx_ring_desc+8, (uint8_t *)&val, 4);
a41b2ff2 1966 txbufLO = le32_to_cpu(val);
3ada003a 1967 pci_dma_read(&s->dev, cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
a41b2ff2
PB		 1968 txbufHI = le32_to_cpu(val);
1969
7cdeb319
BP		 1970 DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
1971 txdw0, txdw1, txbufLO, txbufHI);
a41b2ff2
PB		 1972
1973/* w0 ownership flag */
1974#define CP_TX_OWN (1<<31)
1975/* w0 end of ring flag */
1976#define CP_TX_EOR (1<<30)
1977/* first segment of received packet flag */
1978#define CP_TX_FS (1<<29)
1979/* last segment of received packet flag */
1980#define CP_TX_LS (1<<28)
1981/* large send packet flag */
1982#define CP_TX_LGSEN (1<<27)
718da2b9
FB		 1983/* large send MSS mask, bits 16...25 */
1984#define CP_TC_LGSEN_MSS_MASK ((1 << 12) - 1)
1985
a41b2ff2
PB		 1986/* IP checksum offload flag */
1987#define CP_TX_IPCS (1<<18)
1988/* UDP checksum offload flag */
1989#define CP_TX_UDPCS (1<<17)
1990/* TCP checksum offload flag */
1991#define CP_TX_TCPCS (1<<16)
1992
1993/* w0 bits 0...15 : buffer size */
1994#define CP_TX_BUFFER_SIZE (1<<16)
1995#define CP_TX_BUFFER_SIZE_MASK (CP_TX_BUFFER_SIZE - 1)
bf6b87a8
BP		 1996/* w1 add tag flag */
1997#define CP_TX_TAGC (1<<17)
1998/* w1 bits 0...15 : VLAN tag (big endian) */
a41b2ff2
PB		 1999#define CP_TX_VLAN_TAG_MASK ((1<<16) - 1)
2000/* w2 low 32bit of Rx buffer ptr */
2001/* w3 high 32bit of Rx buffer ptr */
2002
2003/* set after transmission */
2004/* FIFO underrun flag */
2005#define CP_TX_STATUS_UNF (1<<25)
2006/* transmit error summary flag, valid if set any of three below */
2007#define CP_TX_STATUS_TES (1<<23)
2008/* out-of-window collision flag */
2009#define CP_TX_STATUS_OWC (1<<22)
2010/* link failure flag */
2011#define CP_TX_STATUS_LNKF (1<<21)
2012/* excessive collisions flag */
2013#define CP_TX_STATUS_EXC (1<<20)
2014
2015 if (!(txdw0 & CP_TX_OWN))
2016 {
7cdeb319 2017 DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
a41b2ff2
PB		 2018 return 0 ;
2019 }
2020
7cdeb319 2021 DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
6cadb320
FB		 2022
2023 if (txdw0 & CP_TX_FS)
2024 {
7cdeb319
BP		 2025 DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
2026 "descriptor\n", descriptor);
6cadb320
FB		 2027
2028 /* reset internal buffer offset */
2029 s->cplus_txbuffer_offset = 0;
2030 }
a41b2ff2
PB		 2031
2032 int txsize = txdw0 & CP_TX_BUFFER_SIZE_MASK;
3ada003a 2033 dma_addr_t tx_addr = rtl8139_addr64(txbufLO, txbufHI);
a41b2ff2 2034
6cadb320
FB		 2035 /* make sure we have enough space to assemble the packet */
2036 if (!s->cplus_txbuffer)
2037 {
2038 s->cplus_txbuffer_len = CP_TX_BUFFER_SIZE;
7267c094 2039 s->cplus_txbuffer = g_malloc(s->cplus_txbuffer_len);
6cadb320 2040 s->cplus_txbuffer_offset = 0;
718da2b9 2041
7cdeb319
BP		 2042 DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
2043 s->cplus_txbuffer_len);
6cadb320
FB		 2044 }
2045
cde31a0e 2046 if (s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
6cadb320 2047 {
cde31a0e
JW		 2048 /* The spec didn't tell the maximum size, stick to CP_TX_BUFFER_SIZE */
2049 txsize = s->cplus_txbuffer_len - s->cplus_txbuffer_offset;
2050 DPRINTF("+++ C+ mode transmission buffer overrun, truncated descriptor"
2051 "length to %d\n", txsize);
6cadb320
FB		 2052 }
2053
2054 if (!s->cplus_txbuffer)
2055 {
2056 /* out of memory */
a41b2ff2 2057
7cdeb319
BP		 2058 DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
2059 s->cplus_txbuffer_len);
6cadb320
FB		 2060
2061 /* update tally counter */
2062 ++s->tally_counters.TxERR;
2063 ++s->tally_counters.TxAbt;
2064
2065 return 0;
2066 }
2067
2068 /* append more data to the packet */
2069
7cdeb319 2070 DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
3ada003a
EGM		 2071 DMA_ADDR_FMT" to offset %d\n", txsize, tx_addr,
2072 s->cplus_txbuffer_offset);
6cadb320 2073
3ada003a
EGM		 2074 pci_dma_read(&s->dev, tx_addr,
2075 s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
6cadb320
FB		 2076 s->cplus_txbuffer_offset += txsize;
2077
2078 /* seek to next Rx descriptor */
2079 if (txdw0 & CP_TX_EOR)
2080 {
2081 s->currCPlusTxDesc = 0;
2082 }
2083 else
2084 {
2085 ++s->currCPlusTxDesc;
2086 if (s->currCPlusTxDesc >= 64)
2087 s->currCPlusTxDesc = 0;
2088 }
a41b2ff2
PB		 2089
2090 /* transfer ownership to target */
2091 txdw0 &= ~CP_RX_OWN;
2092
2093 /* reset error indicator bits */
2094 txdw0 &= ~CP_TX_STATUS_UNF;
2095 txdw0 &= ~CP_TX_STATUS_TES;
2096 txdw0 &= ~CP_TX_STATUS_OWC;
2097 txdw0 &= ~CP_TX_STATUS_LNKF;
2098 txdw0 &= ~CP_TX_STATUS_EXC;
2099
2100 /* update ring data */
2101 val = cpu_to_le32(txdw0);
3ada003a 2102 pci_dma_write(&s->dev, cplus_tx_ring_desc, (uint8_t *)&val, 4);
a41b2ff2 2103
6cadb320
FB		 2104 /* Now decide if descriptor being processed is holding the last segment of packet */
2105 if (txdw0 & CP_TX_LS)
a41b2ff2 2106 {
bf6b87a8
BP		 2107 uint8_t dot1q_buffer_space[VLAN_HLEN];
2108 uint16_t *dot1q_buffer;
2109
7cdeb319
BP		 2110 DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
2111 descriptor);
6cadb320
FB		 2112
2113 /* can transfer fully assembled packet */
2114
2115 uint8_t *saved_buffer = s->cplus_txbuffer;
2116 int saved_size = s->cplus_txbuffer_offset;
2117 int saved_buffer_len = s->cplus_txbuffer_len;
2118
bf6b87a8
BP		 2119 /* create vlan tag */
2120 if (txdw1 & CP_TX_TAGC) {
2121 /* the vlan tag is in BE byte order in the descriptor
2122 * BE + le_to_cpu() + ~swap()~ = cpu */
7cdeb319
BP		 2123 DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
2124 bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
bf6b87a8
BP		 2125
2126 dot1q_buffer = (uint16_t *) dot1q_buffer_space;
2127 dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
2128 /* BE + le_to_cpu() + ~cpu_to_le()~ = BE */
2129 dot1q_buffer[1] = cpu_to_le16(txdw1 & CP_TX_VLAN_TAG_MASK);
2130 } else {
2131 dot1q_buffer = NULL;
2132 }
2133
6cadb320
FB		 2134 /* reset the card space to protect from recursive call */
2135 s->cplus_txbuffer = NULL;
2136 s->cplus_txbuffer_offset = 0;
2137 s->cplus_txbuffer_len = 0;
2138
718da2b9 2139 if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
6cadb320 2140 {
7cdeb319 2141 DPRINTF("+++ C+ mode offloaded task checksum\n");
6cadb320 2142
6cadb320 2143 /* ip packet header */
660f11be 2144 ip_header *ip = NULL;
6cadb320 2145 int hlen = 0;
718da2b9
FB		 2146 uint8_t ip_protocol = 0;
2147 uint16_t ip_data_len = 0;
6cadb320 2148
660f11be 2149 uint8_t *eth_payload_data = NULL;
718da2b9 2150 size_t eth_payload_len = 0;
6cadb320 2151
718da2b9 2152 int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
6cadb320
FB		 2153 if (proto == ETH_P_IP)
2154 {
7cdeb319 2155 DPRINTF("+++ C+ mode has IP packet\n");
6cadb320
FB		 2156
2157 /* not aligned */
718da2b9
FB		 2158 eth_payload_data = saved_buffer + ETH_HLEN;
2159 eth_payload_len = saved_size - ETH_HLEN;
6cadb320 2160
718da2b9 2161 ip = (ip_header*)eth_payload_data;
6cadb320 2162
718da2b9 2163 if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
7cdeb319
BP		 2164 DPRINTF("+++ C+ mode packet has bad IP version %d "
2165 "expected %d\n", IP_HEADER_VERSION(ip),
2166 IP_HEADER_VERSION_4);
6cadb320
FB		 2167 ip = NULL;
2168 } else {
718da2b9
FB		 2169 hlen = IP_HEADER_LENGTH(ip);
2170 ip_protocol = ip->ip_p;
2171 ip_data_len = be16_to_cpu(ip->ip_len) - hlen;
6cadb320
FB		 2172 }
2173 }
2174
2175 if (ip)
2176 {
2177 if (txdw0 & CP_TX_IPCS)
2178 {
7cdeb319 2179 DPRINTF("+++ C+ mode need IP checksum\n");
6cadb320 2180
718da2b9 2181 if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
6cadb320
FB		 2182 /* bad packet header len */
2183 /* or packet too short */
2184 }
2185 else
2186 {
2187 ip->ip_sum = 0;
718da2b9 2188 ip->ip_sum = ip_checksum(ip, hlen);
7cdeb319
BP		 2189 DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
2190 hlen, ip->ip_sum);
6cadb320
FB		 2191 }
2192 }
2193
718da2b9 2194 if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
6cadb320 2195 {
718da2b9 2196 int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
ec48c774 2197
7cdeb319
BP		 2198 DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
2199 "frame data %d specified MSS=%d\n", ETH_MTU,
2200 ip_data_len, saved_size - ETH_HLEN, large_send_mss);
6cadb320 2201
718da2b9
FB		 2202 int tcp_send_offset = 0;
2203 int send_count = 0;
6cadb320
FB		 2204
2205 /* maximum IP header length is 60 bytes */
2206 uint8_t saved_ip_header[60];
6cadb320 2207
718da2b9
FB		 2208 /* save IP header template; data area is used in tcp checksum calculation */
2209 memcpy(saved_ip_header, eth_payload_data, hlen);
2210
2211 /* a placeholder for checksum calculation routine in tcp case */
2212 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2213 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
2214
2215 /* pointer to TCP header */
2216 tcp_header *p_tcp_hdr = (tcp_header*)(eth_payload_data + hlen);
2217
2218 int tcp_hlen = TCP_HEADER_DATA_OFFSET(p_tcp_hdr);
2219
2220 /* ETH_MTU = ip header len + tcp header len + payload */
2221 int tcp_data_len = ip_data_len - tcp_hlen;
2222 int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
2223
7cdeb319
BP		 2224 DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
2225 "data len %d TCP chunk size %d\n", ip_data_len,
2226 tcp_hlen, tcp_data_len, tcp_chunk_size);
718da2b9
FB		 2227
2228 /* note the cycle below overwrites IP header data,
2229 but restores it from saved_ip_header before sending packet */
2230
2231 int is_last_frame = 0;
2232
2233 for (tcp_send_offset = 0; tcp_send_offset < tcp_data_len; tcp_send_offset += tcp_chunk_size)
2234 {
2235 uint16_t chunk_size = tcp_chunk_size;
2236
2237 /* check if this is the last frame */
2238 if (tcp_send_offset + tcp_chunk_size >= tcp_data_len)
2239 {
2240 is_last_frame = 1;
2241 chunk_size = tcp_data_len - tcp_send_offset;
2242 }
2243
7cdeb319
BP		 2244 DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
2245 be32_to_cpu(p_tcp_hdr->th_seq));
718da2b9
FB		 2246
2247 /* add 4 TCP pseudoheader fields */
2248 /* copy IP source and destination fields */
2249 memcpy(data_to_checksum, saved_ip_header + 12, 8);
2250
7cdeb319
BP		 2251 DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
2252 "packet with %d bytes data\n", tcp_hlen +
2253 chunk_size);
718da2b9
FB		 2254
2255 if (tcp_send_offset)
2256 {
2257 memcpy((uint8_t*)p_tcp_hdr + tcp_hlen, (uint8_t*)p_tcp_hdr + tcp_hlen + tcp_send_offset, chunk_size);
2258 }
2259
2260 /* keep PUSH and FIN flags only for the last frame */
2261 if (!is_last_frame)
2262 {
2263 TCP_HEADER_CLEAR_FLAGS(p_tcp_hdr, TCP_FLAG_PUSH|TCP_FLAG_FIN);
2264 }
6cadb320 2265
718da2b9
FB		 2266 /* recalculate TCP checksum */
2267 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2268 p_tcpip_hdr->zeros = 0;
2269 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2270 p_tcpip_hdr->ip_payload = cpu_to_be16(tcp_hlen + chunk_size);
2271
2272 p_tcp_hdr->th_sum = 0;
2273
2274 int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
7cdeb319
BP		 2275 DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
2276 tcp_checksum);
718da2b9
FB		 2277
2278 p_tcp_hdr->th_sum = tcp_checksum;
2279
2280 /* restore IP header */
2281 memcpy(eth_payload_data, saved_ip_header, hlen);
2282
2283 /* set IP data length and recalculate IP checksum */
2284 ip->ip_len = cpu_to_be16(hlen + tcp_hlen + chunk_size);
2285
2286 /* increment IP id for subsequent frames */
2287 ip->ip_id = cpu_to_be16(tcp_send_offset/tcp_chunk_size + be16_to_cpu(ip->ip_id));
2288
2289 ip->ip_sum = 0;
2290 ip->ip_sum = ip_checksum(eth_payload_data, hlen);
7cdeb319
BP		 2291 DPRINTF("+++ C+ mode TSO IP header len=%d "
2292 "checksum=%04x\n", hlen, ip->ip_sum);
718da2b9
FB		 2293
2294 int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
7cdeb319
BP		 2295 DPRINTF("+++ C+ mode TSO transferring packet size "
2296 "%d\n", tso_send_size);
bf6b87a8
BP		 2297 rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
2298 0, (uint8_t *) dot1q_buffer);
718da2b9
FB		 2299
2300 /* add transferred count to TCP sequence number */
2301 p_tcp_hdr->th_seq = cpu_to_be32(chunk_size + be32_to_cpu(p_tcp_hdr->th_seq));
2302 ++send_count;
2303 }
2304
2305 /* Stop sending this frame */
2306 saved_size = 0;
2307 }
2308 else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
2309 {
7cdeb319 2310 DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
718da2b9
FB		 2311
2312 /* maximum IP header length is 60 bytes */
2313 uint8_t saved_ip_header[60];
2314 memcpy(saved_ip_header, eth_payload_data, hlen);
2315
2316 uint8_t *data_to_checksum = eth_payload_data + hlen - 12;
2317 // size_t data_to_checksum_len = eth_payload_len - hlen + 12;
6cadb320
FB		 2318
2319 /* add 4 TCP pseudoheader fields */
2320 /* copy IP source and destination fields */
718da2b9 2321 memcpy(data_to_checksum, saved_ip_header + 12, 8);
6cadb320 2322
718da2b9 2323 if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
6cadb320 2324 {
7cdeb319
BP		 2325 DPRINTF("+++ C+ mode calculating TCP checksum for "
2326 "packet with %d bytes data\n", ip_data_len);
6cadb320 2327
718da2b9
FB		 2328 ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
2329 p_tcpip_hdr->zeros = 0;
2330 p_tcpip_hdr->ip_proto = IP_PROTO_TCP;
2331 p_tcpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2332
718da2b9 2333 tcp_header* p_tcp_hdr = (tcp_header *) (data_to_checksum+12);
6cadb320
FB		 2334
2335 p_tcp_hdr->th_sum = 0;
2336
718da2b9 2337 int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2338 DPRINTF("+++ C+ mode TCP checksum %04x\n",
2339 tcp_checksum);
6cadb320
FB		 2340
2341 p_tcp_hdr->th_sum = tcp_checksum;
2342 }
718da2b9 2343 else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
6cadb320 2344 {
7cdeb319
BP		 2345 DPRINTF("+++ C+ mode calculating UDP checksum for "
2346 "packet with %d bytes data\n", ip_data_len);
6cadb320 2347
718da2b9
FB		 2348 ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
2349 p_udpip_hdr->zeros = 0;
2350 p_udpip_hdr->ip_proto = IP_PROTO_UDP;
2351 p_udpip_hdr->ip_payload = cpu_to_be16(ip_data_len);
6cadb320 2352
718da2b9 2353 udp_header *p_udp_hdr = (udp_header *) (data_to_checksum+12);
6cadb320 2354
6cadb320
FB		 2355 p_udp_hdr->uh_sum = 0;
2356
718da2b9 2357 int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
7cdeb319
BP		 2358 DPRINTF("+++ C+ mode UDP checksum %04x\n",
2359 udp_checksum);
6cadb320 2360
6cadb320
FB		 2361 p_udp_hdr->uh_sum = udp_checksum;
2362 }
2363
2364 /* restore IP header */
718da2b9 2365 memcpy(eth_payload_data, saved_ip_header, hlen);
6cadb320
FB		 2366 }
2367 }
2368 }
2369
2370 /* update tally counter */
2371 ++s->tally_counters.TxOk;
2372
7cdeb319 2373 DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
6cadb320 2374
bf6b87a8
BP		 2375 rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
2376 (uint8_t *) dot1q_buffer);
6cadb320
FB		 2377
2378 /* restore card space if there was no recursion and reset offset */
2379 if (!s->cplus_txbuffer)
2380 {
2381 s->cplus_txbuffer = saved_buffer;
2382 s->cplus_txbuffer_len = saved_buffer_len;
2383 s->cplus_txbuffer_offset = 0;
2384 }
2385 else
2386 {
7267c094 2387 g_free(saved_buffer);
6cadb320 2388 }
a41b2ff2
PB		 2389 }
2390 else
2391 {
7cdeb319 2392 DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
a41b2ff2
PB		 2393 }
2394
a41b2ff2
PB		 2395 return 1;
2396}
2397
2398static void rtl8139_cplus_transmit(RTL8139State *s)
2399{
2400 int txcount = 0;
2401
2402 while (rtl8139_cplus_transmit_one(s))
2403 {
2404 ++txcount;
2405 }
2406
2407 /* Mark transfer completed */
2408 if (!txcount)
2409 {
7cdeb319
BP		 2410 DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
2411 s->currCPlusTxDesc);
a41b2ff2
PB		 2412 }
2413 else
2414 {
2415 /* update interrupt status */
2416 s->IntrStatus |= TxOK;
2417 rtl8139_update_irq(s);
2418 }
2419}
2420
2421static void rtl8139_transmit(RTL8139State *s)
2422{
2423 int descriptor = s->currTxDesc, txcount = 0;
2424
2425 /*while*/
2426 if (rtl8139_transmit_one(s, descriptor))
2427 {
2428 ++s->currTxDesc;
2429 s->currTxDesc %= 4;
2430 ++txcount;
2431 }
2432
2433 /* Mark transfer completed */
2434 if (!txcount)
2435 {
7cdeb319
BP		 2436 DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
2437 s->currTxDesc);
a41b2ff2
PB		 2438 }
2439}
2440
2441static void rtl8139_TxStatus_write(RTL8139State *s, uint32_t txRegOffset, uint32_t val)
2442{
2443
2444 int descriptor = txRegOffset/4;
6cadb320
FB		 2445
2446 /* handle C+ transmit mode register configuration */
2447
2c3891ab 2448 if (s->cplus_enabled)
6cadb320 2449 {
7cdeb319
BP		 2450 DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
2451 "descriptor=%d\n", txRegOffset, val, descriptor);
6cadb320
FB		 2452
2453 /* handle Dump Tally Counters command */
2454 s->TxStatus[descriptor] = val;
2455
2456 if (descriptor == 0 && (val & 0x8))
2457 {
a8170e5e 2458 hwaddr tc_addr = rtl8139_addr64(s->TxStatus[0] & ~0x3f, s->TxStatus[1]);
6cadb320
FB		 2459
2460 /* dump tally counters to specified memory location */
3ada003a 2461 RTL8139TallyCounters_dma_write(s, tc_addr);
6cadb320
FB		 2462
2463 /* mark dump completed */
2464 s->TxStatus[0] &= ~0x8;
2465 }
2466
2467 return;
2468 }
2469
7cdeb319
BP		 2470 DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
2471 txRegOffset, val, descriptor);
a41b2ff2
PB		 2472
2473 /* mask only reserved bits */
2474 val &= ~0xff00c000; /* these bits are reset on write */
2475 val = SET_MASKED(val, 0x00c00000, s->TxStatus[descriptor]);
2476
2477 s->TxStatus[descriptor] = val;
2478
2479 /* attempt to start transmission */
2480 rtl8139_transmit(s);
2481}
2482
3e48dd4a
SH		 2483static uint32_t rtl8139_TxStatus_TxAddr_read(RTL8139State *s, uint32_t regs[],
2484 uint32_t base, uint8_t addr,
2485 int size)
a41b2ff2 2486{
3e48dd4a 2487 uint32_t reg = (addr - base) / 4;
afe0a595
JW		 2488 uint32_t offset = addr & 0x3;
2489 uint32_t ret = 0;
2490
2491 if (addr & (size - 1)) {
3e48dd4a
SH		 2492 DPRINTF("not implemented read for TxStatus/TxAddr "
2493 "addr=0x%x size=0x%x\n", addr, size);
afe0a595
JW		 2494 return ret;
2495 }
a41b2ff2 2496
afe0a595
JW		 2497 switch (size) {
2498 case 1: /* fall through */
2499 case 2: /* fall through */
2500 case 4:
bdc62e62 2501 ret = (regs[reg] >> offset * 8) & (((uint64_t)1 << (size * 8)) - 1);
3e48dd4a
SH		 2502 DPRINTF("TxStatus/TxAddr[%d] read addr=0x%x size=0x%x val=0x%08x\n",
2503 reg, addr, size, ret);
afe0a595
JW		 2504 break;
2505 default:
3e48dd4a 2506 DPRINTF("unsupported size 0x%x of TxStatus/TxAddr reading\n", size);
afe0a595
JW		 2507 break;
2508 }
a41b2ff2
PB		 2509
2510 return ret;
2511}
2512
2513static uint16_t rtl8139_TSAD_read(RTL8139State *s)
2514{
2515 uint16_t ret = 0;
2516
2517 /* Simulate TSAD, it is read only anyway */
2518
2519 ret = ((s->TxStatus[3] & TxStatOK )?TSAD_TOK3:0)
2520 |((s->TxStatus[2] & TxStatOK )?TSAD_TOK2:0)
2521 |((s->TxStatus[1] & TxStatOK )?TSAD_TOK1:0)
2522 |((s->TxStatus[0] & TxStatOK )?TSAD_TOK0:0)
2523
2524 |((s->TxStatus[3] & TxUnderrun)?TSAD_TUN3:0)
2525 |((s->TxStatus[2] & TxUnderrun)?TSAD_TUN2:0)
2526 |((s->TxStatus[1] & TxUnderrun)?TSAD_TUN1:0)
2527 |((s->TxStatus[0] & TxUnderrun)?TSAD_TUN0:0)
3b46e624 2528
a41b2ff2
PB		 2529 |((s->TxStatus[3] & TxAborted )?TSAD_TABT3:0)
2530 |((s->TxStatus[2] & TxAborted )?TSAD_TABT2:0)
2531 |((s->TxStatus[1] & TxAborted )?TSAD_TABT1:0)
2532 |((s->TxStatus[0] & TxAborted )?TSAD_TABT0:0)
3b46e624 2533
a41b2ff2
PB		 2534 |((s->TxStatus[3] & TxHostOwns )?TSAD_OWN3:0)
2535 |((s->TxStatus[2] & TxHostOwns )?TSAD_OWN2:0)
2536 |((s->TxStatus[1] & TxHostOwns )?TSAD_OWN1:0)
2537 |((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
3b46e624 2538
a41b2ff2 2539
7cdeb319 2540 DPRINTF("TSAD read val=0x%04x\n", ret);
a41b2ff2
PB		 2541
2542 return ret;
2543}
2544
2545static uint16_t rtl8139_CSCR_read(RTL8139State *s)
2546{
2547 uint16_t ret = s->CSCR;
2548
7cdeb319 2549 DPRINTF("CSCR read val=0x%04x\n", ret);
a41b2ff2
PB		 2550
2551 return ret;
2552}
2553
2554static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
2555{
7cdeb319 2556 DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
a41b2ff2 2557
290a0933 2558 s->TxAddr[txAddrOffset/4] = val;
a41b2ff2
PB		 2559}
2560
2561static uint32_t rtl8139_TxAddr_read(RTL8139State *s, uint32_t txAddrOffset)
2562{
290a0933 2563 uint32_t ret = s->TxAddr[txAddrOffset/4];
a41b2ff2 2564
7cdeb319 2565 DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
a41b2ff2
PB		 2566
2567 return ret;
2568}
2569
2570static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
2571{
7cdeb319 2572 DPRINTF("RxBufPtr write val=0x%04x\n", val);
a41b2ff2
PB		 2573
2574 /* this value is off by 16 */
2575 s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
2576
7cdeb319
BP		 2577 DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
2578 s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
a41b2ff2
PB		 2579}
2580
2581static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
2582{
2583 /* this value is off by 16 */
2584 uint32_t ret = s->RxBufPtr - 0x10;
2585
7cdeb319 2586 DPRINTF("RxBufPtr read val=0x%04x\n", ret);
6cadb320
FB		 2587
2588 return ret;
2589}
2590
2591static uint32_t rtl8139_RxBufAddr_read(RTL8139State *s)
2592{
2593 /* this value is NOT off by 16 */
2594 uint32_t ret = s->RxBufAddr;
2595
7cdeb319 2596 DPRINTF("RxBufAddr read val=0x%04x\n", ret);
a41b2ff2
PB		 2597
2598 return ret;
2599}
2600
2601static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
2602{
7cdeb319 2603 DPRINTF("RxBuf write val=0x%08x\n", val);
a41b2ff2
PB		 2604
2605 s->RxBuf = val;
2606
2607 /* may need to reset rxring here */
2608}
2609
2610static uint32_t rtl8139_RxBuf_read(RTL8139State *s)
2611{
2612 uint32_t ret = s->RxBuf;
2613
7cdeb319 2614 DPRINTF("RxBuf read val=0x%08x\n", ret);
a41b2ff2
PB		 2615
2616 return ret;
2617}
2618
2619static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
2620{
7cdeb319 2621 DPRINTF("IntrMask write(w) val=0x%04x\n", val);
a41b2ff2 2622
ebabb67a 2623 /* mask unwritable bits */
a41b2ff2
PB		 2624 val = SET_MASKED(val, 0x1e00, s->IntrMask);
2625
2626 s->IntrMask = val;
2627
74475455 2628 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2629 rtl8139_update_irq(s);
05447803 2630
a41b2ff2
PB		 2631}
2632
2633static uint32_t rtl8139_IntrMask_read(RTL8139State *s)
2634{
2635 uint32_t ret = s->IntrMask;
2636
7cdeb319 2637 DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2638
2639 return ret;
2640}
2641
2642static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
2643{
7cdeb319 2644 DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2645
2646#if 0
2647
2648 /* writing to ISR has no effect */
2649
2650 return;
2651
2652#else
2653 uint16_t newStatus = s->IntrStatus & ~val;
2654
ebabb67a 2655 /* mask unwritable bits */
a41b2ff2
PB		 2656 newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
2657
2658 /* writing 1 to interrupt status register bit clears it */
2659 s->IntrStatus = 0;
2660 rtl8139_update_irq(s);
2661
2662 s->IntrStatus = newStatus;
05447803
FZ		 2663 /*
2664 * Computing if we miss an interrupt here is not that correct but
2665 * considered that we should have had already an interrupt
2666 * and probably emulated is slower is better to assume this resetting was
26404edc 2667 * done before testing on previous rtl8139_update_irq lead to IRQ losing
05447803 2668 */
74475455 2669 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
a41b2ff2 2670 rtl8139_update_irq(s);
05447803 2671
a41b2ff2
PB		 2672#endif
2673}
2674
2675static uint32_t rtl8139_IntrStatus_read(RTL8139State *s)
2676{
74475455 2677 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2678
a41b2ff2
PB		 2679 uint32_t ret = s->IntrStatus;
2680
7cdeb319 2681 DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2682
2683#if 0
2684
2685 /* reading ISR clears all interrupts */
2686 s->IntrStatus = 0;
2687
2688 rtl8139_update_irq(s);
2689
2690#endif
2691
2692 return ret;
2693}
2694
2695static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
2696{
7cdeb319 2697 DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
a41b2ff2 2698
ebabb67a 2699 /* mask unwritable bits */
a41b2ff2
PB		 2700 val = SET_MASKED(val, 0xf000, s->MultiIntr);
2701
2702 s->MultiIntr = val;
2703}
2704
2705static uint32_t rtl8139_MultiIntr_read(RTL8139State *s)
2706{
2707 uint32_t ret = s->MultiIntr;
2708
7cdeb319 2709 DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 2710
2711 return ret;
2712}
2713
2714static void rtl8139_io_writeb(void *opaque, uint8_t addr, uint32_t val)
2715{
2716 RTL8139State *s = opaque;
2717
a41b2ff2
PB		 2718 switch (addr)
2719 {
2720 case MAC0 ... MAC0+5:
2721 s->phys[addr - MAC0] = val;
2722 break;
2723 case MAC0+6 ... MAC0+7:
2724 /* reserved */
2725 break;
2726 case MAR0 ... MAR0+7:
2727 s->mult[addr - MAR0] = val;
2728 break;
2729 case ChipCmd:
2730 rtl8139_ChipCmd_write(s, val);
2731 break;
2732 case Cfg9346:
2733 rtl8139_Cfg9346_write(s, val);
2734 break;
2735 case TxConfig: /* windows driver sometimes writes using byte-lenth call */
2736 rtl8139_TxConfig_writeb(s, val);
2737 break;
2738 case Config0:
2739 rtl8139_Config0_write(s, val);
2740 break;
2741 case Config1:
2742 rtl8139_Config1_write(s, val);
2743 break;
2744 case Config3:
2745 rtl8139_Config3_write(s, val);
2746 break;
2747 case Config4:
2748 rtl8139_Config4_write(s, val);
2749 break;
2750 case Config5:
2751 rtl8139_Config5_write(s, val);
2752 break;
2753 case MediaStatus:
2754 /* ignore */
7cdeb319
BP		 2755 DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
2756 val);
a41b2ff2
PB		 2757 break;
2758
2759 case HltClk:
7cdeb319 2760 DPRINTF("HltClk write val=0x%08x\n", val);
a41b2ff2
PB		 2761 if (val == 'R')
2762 {
2763 s->clock_enabled = 1;
2764 }
2765 else if (val == 'H')
2766 {
2767 s->clock_enabled = 0;
2768 }
2769 break;
2770
2771 case TxThresh:
7cdeb319 2772 DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2773 s->TxThresh = val;
2774 break;
2775
2776 case TxPoll:
7cdeb319 2777 DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
a41b2ff2
PB		 2778 if (val & (1 << 7))
2779 {
7cdeb319
BP		 2780 DPRINTF("C+ TxPoll high priority transmission (not "
2781 "implemented)\n");
a41b2ff2
PB		 2782 //rtl8139_cplus_transmit(s);
2783 }
2784 if (val & (1 << 6))
2785 {
7cdeb319 2786 DPRINTF("C+ TxPoll normal priority transmission\n");
a41b2ff2
PB		 2787 rtl8139_cplus_transmit(s);
2788 }
2789
2790 break;
2791
2792 default:
7cdeb319
BP		 2793 DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
2794 val);
a41b2ff2
PB		 2795 break;
2796 }
2797}
2798
2799static void rtl8139_io_writew(void *opaque, uint8_t addr, uint32_t val)
2800{
2801 RTL8139State *s = opaque;
2802
a41b2ff2
PB		 2803 switch (addr)
2804 {
2805 case IntrMask:
2806 rtl8139_IntrMask_write(s, val);
2807 break;
2808
2809 case IntrStatus:
2810 rtl8139_IntrStatus_write(s, val);
2811 break;
2812
2813 case MultiIntr:
2814 rtl8139_MultiIntr_write(s, val);
2815 break;
2816
2817 case RxBufPtr:
2818 rtl8139_RxBufPtr_write(s, val);
2819 break;
2820
2821 case BasicModeCtrl:
2822 rtl8139_BasicModeCtrl_write(s, val);
2823 break;
2824 case BasicModeStatus:
2825 rtl8139_BasicModeStatus_write(s, val);
2826 break;
2827 case NWayAdvert:
7cdeb319 2828 DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2829 s->NWayAdvert = val;
2830 break;
2831 case NWayLPAR:
7cdeb319 2832 DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2833 break;
2834 case NWayExpansion:
7cdeb319 2835 DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
a41b2ff2
PB		 2836 s->NWayExpansion = val;
2837 break;
2838
2839 case CpCmd:
2840 rtl8139_CpCmd_write(s, val);
2841 break;
2842
6cadb320
FB		 2843 case IntrMitigate:
2844 rtl8139_IntrMitigate_write(s, val);
2845 break;
2846
a41b2ff2 2847 default:
7cdeb319
BP		 2848 DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
2849 addr, val);
a41b2ff2 2850
a41b2ff2
PB		 2851 rtl8139_io_writeb(opaque, addr, val & 0xff);
2852 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
a41b2ff2
PB		 2853 break;
2854 }
2855}
2856
05447803
FZ		 2857static void rtl8139_set_next_tctr_time(RTL8139State *s, int64_t current_time)
2858{
2859 int64_t pci_time, next_time;
2860 uint32_t low_pci;
2861
7cdeb319 2862 DPRINTF("entered rtl8139_set_next_tctr_time\n");
05447803
FZ		 2863
2864 if (s->TimerExpire && current_time >= s->TimerExpire) {
2865 s->IntrStatus |= PCSTimeout;
2866 rtl8139_update_irq(s);
2867 }
2868
2869 /* Set QEMU timer only if needed that is
2870 * - TimerInt <> 0 (we have a timer)
2871 * - mask = 1 (we want an interrupt timer)
2872 * - irq = 0 (irq is not already active)
2873 * If any of above change we need to compute timer again
2874 * Also we must check if timer is passed without QEMU timer
2875 */
2876 s->TimerExpire = 0;
2877 if (!s->TimerInt) {
2878 return;
2879 }
2880
2881 pci_time = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
2882 get_ticks_per_sec());
2883 low_pci = pci_time & 0xffffffff;
2884 pci_time = pci_time - low_pci + s->TimerInt;
2885 if (low_pci >= s->TimerInt) {
2886 pci_time += 0x100000000LL;
2887 }
2888 next_time = s->TCTR_base + muldiv64(pci_time, get_ticks_per_sec(),
2889 PCI_FREQUENCY);
2890 s->TimerExpire = next_time;
2891
2892 if ((s->IntrMask & PCSTimeout) != 0 && (s->IntrStatus & PCSTimeout) == 0) {
2893 qemu_mod_timer(s->timer, next_time);
2894 }
2895}
2896
a41b2ff2
PB		 2897static void rtl8139_io_writel(void *opaque, uint8_t addr, uint32_t val)
2898{
2899 RTL8139State *s = opaque;
2900
a41b2ff2
PB		 2901 switch (addr)
2902 {
2903 case RxMissed:
7cdeb319 2904 DPRINTF("RxMissed clearing on write\n");
a41b2ff2
PB		 2905 s->RxMissed = 0;
2906 break;
2907
2908 case TxConfig:
2909 rtl8139_TxConfig_write(s, val);
2910 break;
2911
2912 case RxConfig:
2913 rtl8139_RxConfig_write(s, val);
2914 break;
2915
2916 case TxStatus0 ... TxStatus0+4*4-1:
2917 rtl8139_TxStatus_write(s, addr-TxStatus0, val);
2918 break;
2919
2920 case TxAddr0 ... TxAddr0+4*4-1:
2921 rtl8139_TxAddr_write(s, addr-TxAddr0, val);
2922 break;
2923
2924 case RxBuf:
2925 rtl8139_RxBuf_write(s, val);
2926 break;
2927
2928 case RxRingAddrLO:
7cdeb319 2929 DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
a41b2ff2
PB		 2930 s->RxRingAddrLO = val;
2931 break;
2932
2933 case RxRingAddrHI:
7cdeb319 2934 DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
a41b2ff2
PB		 2935 s->RxRingAddrHI = val;
2936 break;
2937
6cadb320 2938 case Timer:
7cdeb319 2939 DPRINTF("TCTR Timer reset on write\n");
74475455 2940 s->TCTR_base = qemu_get_clock_ns(vm_clock);
05447803 2941 rtl8139_set_next_tctr_time(s, s->TCTR_base);
6cadb320
FB		 2942 break;
2943
2944 case FlashReg:
7cdeb319 2945 DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
05447803
FZ		 2946 if (s->TimerInt != val) {
2947 s->TimerInt = val;
74475455 2948 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
05447803 2949 }
6cadb320
FB		 2950 break;
2951
a41b2ff2 2952 default:
7cdeb319
BP		 2953 DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
2954 addr, val);
a41b2ff2
PB		 2955 rtl8139_io_writeb(opaque, addr, val & 0xff);
2956 rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
2957 rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
2958 rtl8139_io_writeb(opaque, addr + 3, (val >> 24) & 0xff);
a41b2ff2
PB		 2959 break;
2960 }
2961}
2962
2963static uint32_t rtl8139_io_readb(void *opaque, uint8_t addr)
2964{
2965 RTL8139State *s = opaque;
2966 int ret;
2967
a41b2ff2
PB		 2968 switch (addr)
2969 {
2970 case MAC0 ... MAC0+5:
2971 ret = s->phys[addr - MAC0];
2972 break;
2973 case MAC0+6 ... MAC0+7:
2974 ret = 0;
2975 break;
2976 case MAR0 ... MAR0+7:
2977 ret = s->mult[addr - MAR0];
2978 break;
afe0a595 2979 case TxStatus0 ... TxStatus0+4*4-1:
3e48dd4a
SH		 2980 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
2981 addr, 1);
afe0a595 2982 break;
a41b2ff2
PB		 2983 case ChipCmd:
2984 ret = rtl8139_ChipCmd_read(s);
2985 break;
2986 case Cfg9346:
2987 ret = rtl8139_Cfg9346_read(s);
2988 break;
2989 case Config0:
2990 ret = rtl8139_Config0_read(s);
2991 break;
2992 case Config1:
2993 ret = rtl8139_Config1_read(s);
2994 break;
2995 case Config3:
2996 ret = rtl8139_Config3_read(s);
2997 break;
2998 case Config4:
2999 ret = rtl8139_Config4_read(s);
3000 break;
3001 case Config5:
3002 ret = rtl8139_Config5_read(s);
3003 break;
3004
3005 case MediaStatus:
9e12c5af
JW		 3006 /* The LinkDown bit of MediaStatus is inverse with link status */
3007 ret = 0xd0 | (~s->BasicModeStatus & 0x04);
7cdeb319 3008 DPRINTF("MediaStatus read 0x%x\n", ret);
a41b2ff2
PB		 3009 break;
3010
3011 case HltClk:
3012 ret = s->clock_enabled;
7cdeb319 3013 DPRINTF("HltClk read 0x%x\n", ret);
a41b2ff2
PB		 3014 break;
3015
3016 case PCIRevisionID:
6cadb320 3017 ret = RTL8139_PCI_REVID;
7cdeb319 3018 DPRINTF("PCI Revision ID read 0x%x\n", ret);
a41b2ff2
PB		 3019 break;
3020
3021 case TxThresh:
3022 ret = s->TxThresh;
7cdeb319 3023 DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3024 break;
3025
3026 case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
3027 ret = s->TxConfig >> 24;
7cdeb319 3028 DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
a41b2ff2
PB		 3029 break;
3030
3031 default:
7cdeb319 3032 DPRINTF("not implemented read(b) addr=0x%x\n", addr);
a41b2ff2
PB		 3033 ret = 0;
3034 break;
3035 }
3036
3037 return ret;
3038}
3039
3040static uint32_t rtl8139_io_readw(void *opaque, uint8_t addr)
3041{
3042 RTL8139State *s = opaque;
3043 uint32_t ret;
3044
a41b2ff2
PB		 3045 switch (addr)
3046 {
afe0a595 3047 case TxAddr0 ... TxAddr0+4*4-1:
3e48dd4a 3048 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxAddr, TxAddr0, addr, 2);
afe0a595 3049 break;
a41b2ff2
PB		 3050 case IntrMask:
3051 ret = rtl8139_IntrMask_read(s);
3052 break;
3053
3054 case IntrStatus:
3055 ret = rtl8139_IntrStatus_read(s);
3056 break;
3057
3058 case MultiIntr:
3059 ret = rtl8139_MultiIntr_read(s);
3060 break;
3061
3062 case RxBufPtr:
3063 ret = rtl8139_RxBufPtr_read(s);
3064 break;
3065
6cadb320
FB		 3066 case RxBufAddr:
3067 ret = rtl8139_RxBufAddr_read(s);
3068 break;
3069
a41b2ff2
PB		 3070 case BasicModeCtrl:
3071 ret = rtl8139_BasicModeCtrl_read(s);
3072 break;
3073 case BasicModeStatus:
3074 ret = rtl8139_BasicModeStatus_read(s);
3075 break;
3076 case NWayAdvert:
3077 ret = s->NWayAdvert;
7cdeb319 3078 DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3079 break;
3080 case NWayLPAR:
3081 ret = s->NWayLPAR;
7cdeb319 3082 DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3083 break;
3084 case NWayExpansion:
3085 ret = s->NWayExpansion;
7cdeb319 3086 DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
a41b2ff2
PB		 3087 break;
3088
3089 case CpCmd:
3090 ret = rtl8139_CpCmd_read(s);
3091 break;
3092
6cadb320
FB		 3093 case IntrMitigate:
3094 ret = rtl8139_IntrMitigate_read(s);
3095 break;
3096
a41b2ff2
PB		 3097 case TxSummary:
3098 ret = rtl8139_TSAD_read(s);
3099 break;
3100
3101 case CSCR:
3102 ret = rtl8139_CSCR_read(s);
3103 break;
3104
3105 default:
7cdeb319 3106 DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
a41b2ff2 3107
a41b2ff2
PB		 3108 ret = rtl8139_io_readb(opaque, addr);
3109 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
a41b2ff2 3110
7cdeb319 3111 DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
a41b2ff2
PB		 3112 break;
3113 }
3114
3115 return ret;
3116}
3117
3118static uint32_t rtl8139_io_readl(void *opaque, uint8_t addr)
3119{
3120 RTL8139State *s = opaque;
3121 uint32_t ret;
3122
a41b2ff2
PB		 3123 switch (addr)
3124 {
3125 case RxMissed:
3126 ret = s->RxMissed;
3127
7cdeb319 3128 DPRINTF("RxMissed read val=0x%08x\n", ret);
a41b2ff2
PB		 3129 break;
3130
3131 case TxConfig:
3132 ret = rtl8139_TxConfig_read(s);
3133 break;
3134
3135 case RxConfig:
3136 ret = rtl8139_RxConfig_read(s);
3137 break;
3138
3139 case TxStatus0 ... TxStatus0+4*4-1:
3e48dd4a
SH		 3140 ret = rtl8139_TxStatus_TxAddr_read(s, s->TxStatus, TxStatus0,
3141 addr, 4);
a41b2ff2
PB		 3142 break;
3143
3144 case TxAddr0 ... TxAddr0+4*4-1:
3145 ret = rtl8139_TxAddr_read(s, addr-TxAddr0);
3146 break;
3147
3148 case RxBuf:
3149 ret = rtl8139_RxBuf_read(s);
3150 break;
3151
3152 case RxRingAddrLO:
3153 ret = s->RxRingAddrLO;
7cdeb319 3154 DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
a41b2ff2
PB		 3155 break;
3156
3157 case RxRingAddrHI:
3158 ret = s->RxRingAddrHI;
7cdeb319 3159 DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
6cadb320
FB		 3160 break;
3161
3162 case Timer:
74475455 3163 ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
05447803 3164 PCI_FREQUENCY, get_ticks_per_sec());
7cdeb319 3165 DPRINTF("TCTR Timer read val=0x%08x\n", ret);
6cadb320
FB		 3166 break;
3167
3168 case FlashReg:
3169 ret = s->TimerInt;
7cdeb319 3170 DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
a41b2ff2
PB		 3171 break;
3172
3173 default:
7cdeb319 3174 DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
a41b2ff2 3175
a41b2ff2
PB		 3176 ret = rtl8139_io_readb(opaque, addr);
3177 ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
3178 ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
3179 ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
a41b2ff2 3180
7cdeb319 3181 DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
a41b2ff2
PB		 3182 break;
3183 }
3184
3185 return ret;
3186}
3187
3188/* */
3189
a8170e5e 3190static void rtl8139_mmio_writeb(void *opaque, hwaddr addr, uint32_t val)
a41b2ff2
PB		 3191{
3192 rtl8139_io_writeb(opaque, addr & 0xFF, val);
3193}
3194
a8170e5e 3195static void rtl8139_mmio_writew(void *opaque, hwaddr addr, uint32_t val)
a41b2ff2
PB		 3196{
3197 rtl8139_io_writew(opaque, addr & 0xFF, val);
3198}
3199
a8170e5e 3200static void rtl8139_mmio_writel(void *opaque, hwaddr addr, uint32_t val)
a41b2ff2
PB		 3201{
3202 rtl8139_io_writel(opaque, addr & 0xFF, val);
3203}
3204
a8170e5e 3205static uint32_t rtl8139_mmio_readb(void *opaque, hwaddr addr)
a41b2ff2
PB		 3206{
3207 return rtl8139_io_readb(opaque, addr & 0xFF);
3208}
3209
a8170e5e 3210static uint32_t rtl8139_mmio_readw(void *opaque, hwaddr addr)
a41b2ff2 3211{
5fedc612 3212 uint32_t val = rtl8139_io_readw(opaque, addr & 0xFF);
5fedc612 3213 return val;
a41b2ff2
PB		 3214}
3215
a8170e5e 3216static uint32_t rtl8139_mmio_readl(void *opaque, hwaddr addr)
a41b2ff2 3217{
5fedc612 3218 uint32_t val = rtl8139_io_readl(opaque, addr & 0xFF);
5fedc612 3219 return val;
a41b2ff2
PB		 3220}
3221
060110c3 3222static int rtl8139_post_load(void *opaque, int version_id)
a41b2ff2 3223{
6597ebbb 3224 RTL8139State* s = opaque;
74475455 3225 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
060110c3 3226 if (version_id < 4) {
2c3891ab
AL		 3227 s->cplus_enabled = s->CpCmd != 0;
3228 }
3229
9e12c5af
JW		 3230 /* nc.link_down can't be migrated, so infer link_down according
3231 * to link status bit in BasicModeStatus */
3232 s->nic->nc.link_down = (s->BasicModeStatus & 0x04) == 0;
3233
a41b2ff2
PB		 3234 return 0;
3235}
3236
c574ba5a
AW		 3237static bool rtl8139_hotplug_ready_needed(void *opaque)
3238{
3239 return qdev_machine_modified();
3240}
3241
3242static const VMStateDescription vmstate_rtl8139_hotplug_ready ={
3243 .name = "rtl8139/hotplug_ready",
3244 .version_id = 1,
3245 .minimum_version_id = 1,
3246 .minimum_version_id_old = 1,
3247 .fields = (VMStateField []) {
3248 VMSTATE_END_OF_LIST()
3249 }
3250};
3251
05447803
FZ		 3252static void rtl8139_pre_save(void *opaque)
3253{
3254 RTL8139State* s = opaque;
74475455 3255 int64_t current_time = qemu_get_clock_ns(vm_clock);
05447803
FZ		 3256
3257 /* set IntrStatus correctly */
3258 rtl8139_set_next_tctr_time(s, current_time);
3259 s->TCTR = muldiv64(current_time - s->TCTR_base, PCI_FREQUENCY,
3260 get_ticks_per_sec());
bd80f3fc 3261 s->rtl8139_mmio_io_addr_dummy = 0;
05447803
FZ		 3262}
3263
060110c3
JQ		 3264static const VMStateDescription vmstate_rtl8139 = {
3265 .name = "rtl8139",
3266 .version_id = 4,
3267 .minimum_version_id = 3,
3268 .minimum_version_id_old = 3,
3269 .post_load = rtl8139_post_load,
05447803 3270 .pre_save = rtl8139_pre_save,
060110c3
JQ		 3271 .fields = (VMStateField []) {
3272 VMSTATE_PCI_DEVICE(dev, RTL8139State),
3273 VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
3274 VMSTATE_BUFFER(mult, RTL8139State),
3275 VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
3276 VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
3277
3278 VMSTATE_UINT32(RxBuf, RTL8139State),
3279 VMSTATE_UINT32(RxBufferSize, RTL8139State),
3280 VMSTATE_UINT32(RxBufPtr, RTL8139State),
3281 VMSTATE_UINT32(RxBufAddr, RTL8139State),
3282
3283 VMSTATE_UINT16(IntrStatus, RTL8139State),
3284 VMSTATE_UINT16(IntrMask, RTL8139State),
3285
3286 VMSTATE_UINT32(TxConfig, RTL8139State),
3287 VMSTATE_UINT32(RxConfig, RTL8139State),
3288 VMSTATE_UINT32(RxMissed, RTL8139State),
3289 VMSTATE_UINT16(CSCR, RTL8139State),
3290
3291 VMSTATE_UINT8(Cfg9346, RTL8139State),
3292 VMSTATE_UINT8(Config0, RTL8139State),
3293 VMSTATE_UINT8(Config1, RTL8139State),
3294 VMSTATE_UINT8(Config3, RTL8139State),
3295 VMSTATE_UINT8(Config4, RTL8139State),
3296 VMSTATE_UINT8(Config5, RTL8139State),
3297
3298 VMSTATE_UINT8(clock_enabled, RTL8139State),
3299 VMSTATE_UINT8(bChipCmdState, RTL8139State),
3300
3301 VMSTATE_UINT16(MultiIntr, RTL8139State),
3302
3303 VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
3304 VMSTATE_UINT16(BasicModeStatus, RTL8139State),
3305 VMSTATE_UINT16(NWayAdvert, RTL8139State),
3306 VMSTATE_UINT16(NWayLPAR, RTL8139State),
3307 VMSTATE_UINT16(NWayExpansion, RTL8139State),
3308
3309 VMSTATE_UINT16(CpCmd, RTL8139State),
3310 VMSTATE_UINT8(TxThresh, RTL8139State),
3311
3312 VMSTATE_UNUSED(4),
3313 VMSTATE_MACADDR(conf.macaddr, RTL8139State),
c574ba5a 3314 VMSTATE_INT32(rtl8139_mmio_io_addr_dummy, RTL8139State),
060110c3
JQ		 3315
3316 VMSTATE_UINT32(currTxDesc, RTL8139State),
3317 VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
3318 VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
3319 VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
3320 VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
3321
3322 VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
3323 VMSTATE_INT32(eeprom.mode, RTL8139State),
3324 VMSTATE_UINT32(eeprom.tick, RTL8139State),
3325 VMSTATE_UINT8(eeprom.address, RTL8139State),
3326 VMSTATE_UINT16(eeprom.input, RTL8139State),
3327 VMSTATE_UINT16(eeprom.output, RTL8139State),
3328
3329 VMSTATE_UINT8(eeprom.eecs, RTL8139State),
3330 VMSTATE_UINT8(eeprom.eesk, RTL8139State),
3331 VMSTATE_UINT8(eeprom.eedi, RTL8139State),
3332 VMSTATE_UINT8(eeprom.eedo, RTL8139State),
3333
3334 VMSTATE_UINT32(TCTR, RTL8139State),
3335 VMSTATE_UINT32(TimerInt, RTL8139State),
3336 VMSTATE_INT64(TCTR_base, RTL8139State),
3337
3338 VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
3339 vmstate_tally_counters, RTL8139TallyCounters),
3340
3341 VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
3342 VMSTATE_END_OF_LIST()
c574ba5a
AW		 3343 },
3344 .subsections = (VMStateSubsection []) {
3345 {
3346 .vmsd = &vmstate_rtl8139_hotplug_ready,
3347 .needed = rtl8139_hotplug_ready_needed,
3348 }, {
3349 /* empty */
3350 }
060110c3
JQ		 3351 }
3352};
3353
a41b2ff2
PB		 3354/***********************************************************/
3355/* PCI RTL8139 definitions */
3356
1bebb0ad
AG		 3357static void rtl8139_ioport_write(void *opaque, hwaddr addr,
3358 uint64_t val, unsigned size)
3359{
3360 switch (size) {
3361 case 1:
3362 rtl8139_io_writeb(opaque, addr, val);
3363 break;
3364 case 2:
3365 rtl8139_io_writew(opaque, addr, val);
3366 break;
3367 case 4:
3368 rtl8139_io_writel(opaque, addr, val);
3369 break;
3370 }
3371}
3372
3373static uint64_t rtl8139_ioport_read(void *opaque, hwaddr addr,
3374 unsigned size)
3375{
3376 switch (size) {
3377 case 1:
3378 return rtl8139_io_readb(opaque, addr);
3379 case 2:
3380 return rtl8139_io_readw(opaque, addr);
3381 case 4:
3382 return rtl8139_io_readl(opaque, addr);
3383 }
3384
3385 return -1;
3386}
a41b2ff2 3387
bd80f3fc 3388static const MemoryRegionOps rtl8139_io_ops = {
1bebb0ad
AG		 3389 .read = rtl8139_ioport_read,
3390 .write = rtl8139_ioport_write,
3391 .impl = {
3392 .min_access_size = 1,
3393 .max_access_size = 4,
3394 },
bd80f3fc 3395 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3396};
3397
bd80f3fc
AK		 3398static const MemoryRegionOps rtl8139_mmio_ops = {
3399 .old_mmio = {
3400 .read = {
3401 rtl8139_mmio_readb,
3402 rtl8139_mmio_readw,
3403 rtl8139_mmio_readl,
3404 },
3405 .write = {
3406 rtl8139_mmio_writeb,
3407 rtl8139_mmio_writew,
3408 rtl8139_mmio_writel,
3409 },
3410 },
3411 .endianness = DEVICE_LITTLE_ENDIAN,
a41b2ff2
PB		 3412};
3413
6cadb320
FB		 3414static void rtl8139_timer(void *opaque)
3415{
3416 RTL8139State *s = opaque;
3417
6cadb320
FB		 3418 if (!s->clock_enabled)
3419 {
7cdeb319 3420 DPRINTF(">>> timer: clock is not running\n");
6cadb320
FB		 3421 return;
3422 }
3423
05447803
FZ		 3424 s->IntrStatus |= PCSTimeout;
3425 rtl8139_update_irq(s);
74475455 3426 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
6cadb320 3427}
6cadb320 3428
4e68f7a0 3429static void rtl8139_cleanup(NetClientState *nc)
b946a153 3430{
1673ad51 3431 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
b946a153 3432
1673ad51 3433 s->nic = NULL;
254111ec
GH		 3434}
3435
f90c2bcd 3436static void pci_rtl8139_uninit(PCIDevice *dev)
254111ec
GH		 3437{
3438 RTL8139State *s = DO_UPCAST(RTL8139State, dev, dev);
3439
bd80f3fc
AK		 3440 memory_region_destroy(&s->bar_io);
3441 memory_region_destroy(&s->bar_mem);
b946a153 3442 if (s->cplus_txbuffer) {
7267c094 3443 g_free(s->cplus_txbuffer);
b946a153
AL		 3444 s->cplus_txbuffer = NULL;
3445 }
b946a153
AL		 3446 qemu_del_timer(s->timer);
3447 qemu_free_timer(s->timer);
b20c6b9e 3448 qemu_del_net_client(&s->nic->nc);
b946a153
AL		 3449}
3450
9e12c5af
JW		 3451static void rtl8139_set_link_status(NetClientState *nc)
3452{
3453 RTL8139State *s = DO_UPCAST(NICState, nc, nc)->opaque;
3454
3455 if (nc->link_down) {
3456 s->BasicModeStatus &= ~0x04;
3457 } else {
3458 s->BasicModeStatus |= 0x04;
3459 }
3460
3461 s->IntrStatus |= RxUnderrun;
3462 rtl8139_update_irq(s);
3463}
3464
1673ad51 3465static NetClientInfo net_rtl8139_info = {
2be64a68 3466 .type = NET_CLIENT_OPTIONS_KIND_NIC,
1673ad51
MM		 3467 .size = sizeof(NICState),
3468 .can_receive = rtl8139_can_receive,
3469 .receive = rtl8139_receive,
3470 .cleanup = rtl8139_cleanup,
9e12c5af 3471 .link_status_changed = rtl8139_set_link_status,
1673ad51
MM		 3472};
3473
81a322d4 3474static int pci_rtl8139_init(PCIDevice *dev)
a41b2ff2 3475{
efd6dd45 3476 RTL8139State * s = DO_UPCAST(RTL8139State, dev, dev);
a41b2ff2 3477 uint8_t *pci_conf;
3b46e624 3478
efd6dd45 3479 pci_conf = s->dev.config;
817e0b6f 3480 pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin A */
0b5b3547
MT		 3481 /* TODO: start of capability list, but no capability
3482 * list bit in status register, and offset 0xdc seems unused. */
3483 pci_conf[PCI_CAPABILITY_LIST] = 0xdc;
a41b2ff2 3484
bd80f3fc
AK		 3485 memory_region_init_io(&s->bar_io, &rtl8139_io_ops, s, "rtl8139", 0x100);
3486 memory_region_init_io(&s->bar_mem, &rtl8139_mmio_ops, s, "rtl8139", 0x100);
e824b2cc
AK		 3487 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->bar_io);
3488 pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar_mem);
a41b2ff2 3489
254111ec 3490 qemu_macaddr_default_if_unset(&s->conf.macaddr);
c1699988 3491
7165448a
WD		 3492 /* prepare eeprom */
3493 s->eeprom.contents[0] = 0x8129;
3494#if 1
3495 /* PCI vendor and device ID should be mirrored here */
3496 s->eeprom.contents[1] = PCI_VENDOR_ID_REALTEK;
3497 s->eeprom.contents[2] = PCI_DEVICE_ID_REALTEK_8139;
3498#endif
3499 s->eeprom.contents[7] = s->conf.macaddr.a[0] | s->conf.macaddr.a[1] << 8;
3500 s->eeprom.contents[8] = s->conf.macaddr.a[2] | s->conf.macaddr.a[3] << 8;
3501 s->eeprom.contents[9] = s->conf.macaddr.a[4] | s->conf.macaddr.a[5] << 8;
3502
1673ad51 3503 s->nic = qemu_new_nic(&net_rtl8139_info, &s->conf,
f79f2bfc 3504 object_get_typename(OBJECT(dev)), dev->qdev.id, s);
1673ad51 3505 qemu_format_nic_info_str(&s->nic->nc, s->conf.macaddr.a);
6cadb320
FB		 3506
3507 s->cplus_txbuffer = NULL;
3508 s->cplus_txbuffer_len = 0;
3509 s->cplus_txbuffer_offset = 0;
3b46e624 3510
05447803 3511 s->TimerExpire = 0;
74475455
PB		 3512 s->timer = qemu_new_timer_ns(vm_clock, rtl8139_timer, s);
3513 rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
1ca4d09a
GN		 3514
3515 add_boot_device_path(s->conf.bootindex, &dev->qdev, "/ethernet-phy@0");
3516
81a322d4 3517 return 0;
a41b2ff2 3518}
9d07d757 3519
40021f08
AL		 3520static Property rtl8139_properties[] = {
3521 DEFINE_NIC_PROPERTIES(RTL8139State, conf),
3522 DEFINE_PROP_END_OF_LIST(),
3523};
3524
3525static void rtl8139_class_init(ObjectClass *klass, void *data)
3526{
39bffca2 3527 DeviceClass *dc = DEVICE_CLASS(klass);
40021f08
AL		 3528 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3529
3530 k->init = pci_rtl8139_init;
3531 k->exit = pci_rtl8139_uninit;
3532 k->romfile = "pxe-rtl8139.rom";
3533 k->vendor_id = PCI_VENDOR_ID_REALTEK;
3534 k->device_id = PCI_DEVICE_ID_REALTEK_8139;
3535 k->revision = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
3536 k->class_id = PCI_CLASS_NETWORK_ETHERNET;
39bffca2
AL		 3537 dc->reset = rtl8139_reset;
3538 dc->vmsd = &vmstate_rtl8139;
3539 dc->props = rtl8139_properties;
40021f08
AL		 3540}
3541
39bffca2
AL		 3542static TypeInfo rtl8139_info = {
3543 .name = "rtl8139",
3544 .parent = TYPE_PCI_DEVICE,
3545 .instance_size = sizeof(RTL8139State),
3546 .class_init = rtl8139_class_init,
0aab0d3a
GH		 3547};
3548
83f7d43a 3549static void rtl8139_register_types(void)
9d07d757 3550{
39bffca2 3551 type_register_static(&rtl8139_info);
9d07d757
PB		 3552}
3553
83f7d43a 3554type_init(rtl8139_register_types)
Qemu copy for testing