[qemu.git] / hw / xilinx_timer.c

/*
 * QEMU model of the Xilinx timer block.
 *
 * Copyright (c) 2009 Edgar E. Iglesias.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */

#include "sysbus.h"
#include "qemu-timer.h"

#define D(x)

#define R_TCSR     0
#define R_TLR      1
#define R_TCR      2
#define R_MAX      4

#define TCSR_MDT        (1<<0)
#define TCSR_UDT        (1<<1)
#define TCSR_GENT       (1<<2)
#define TCSR_CAPT       (1<<3)
#define TCSR_ARHT       (1<<4)
#define TCSR_LOAD       (1<<5)
#define TCSR_ENIT       (1<<6)
#define TCSR_ENT        (1<<7)
#define TCSR_TINT       (1<<8)
#define TCSR_PWMA       (1<<9)
#define TCSR_ENALL      (1<<10)

struct xlx_timer
{
    QEMUBH *bh;
    ptimer_state *ptimer;
    void *parent;
    int nr; /* for debug.  */

    unsigned long timer_div;

    uint32_t regs[R_MAX];
};

struct timerblock
{
    SysBusDevice busdev;
    qemu_irq irq;
    uint32_t nr_timers;
    uint32_t freq_hz;
    struct xlx_timer *timers;
};

static inline unsigned int timer_from_addr(target_phys_addr_t addr)
{
    /* Timers get a 4x32bit control reg area each.  */
    return addr >> 2;
}

static void timer_update_irq(struct timerblock *t)
{
    unsigned int i, irq = 0;
    uint32_t csr;

    for (i = 0; i < t->nr_timers; i++) {
        csr = t->timers[i].regs[R_TCSR];
        irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
    }

    /* All timers within the same slave share a single IRQ line.  */
    qemu_set_irq(t->irq, !!irq);
}

static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
{
    struct timerblock *t = opaque;
    struct xlx_timer *xt;
    uint32_t r = 0;
    unsigned int timer;

    addr >>= 2;
    timer = timer_from_addr(addr);
    xt = &t->timers[timer];
    /* Further decoding to address a specific timers reg.  */
    addr &= 0x3;
    switch (addr)
    {
        case R_TCR:
                r = ptimer_get_count(xt->ptimer);
                if (!(xt->regs[R_TCSR] & TCSR_UDT))
                    r = ~r;
                D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
                         timer, r, xt->regs[R_TCSR] & TCSR_UDT));
            break;
        default:
            if (addr < ARRAY_SIZE(xt->regs))
                r = xt->regs[addr];
            break;

    }
    D(printf("%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
    return r;
}

static void timer_enable(struct xlx_timer *xt)
{
    uint64_t count;

    D(printf("%s timer=%d down=%d\n", __func__,
              xt->nr, xt->regs[R_TCSR] & TCSR_UDT));

    ptimer_stop(xt->ptimer);

    if (xt->regs[R_TCSR] & TCSR_UDT)
        count = xt->regs[R_TLR];
    else
        count = ~0 - xt->regs[R_TLR];
    ptimer_set_count(xt->ptimer, count);
    ptimer_run(xt->ptimer, 1);
}

static void
timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
    struct timerblock *t = opaque;
    struct xlx_timer *xt;
    unsigned int timer;

    addr >>= 2;
    timer = timer_from_addr(addr);
    xt = &t->timers[timer];
    D(printf("%s addr=%x val=%x (timer=%d off=%d)\n",
             __func__, addr * 4, value, timer, addr & 3));
    /* Further decoding to address a specific timers reg.  */
    addr &= 3;
    switch (addr) 
    {
        case R_TCSR:
            if (value & TCSR_TINT)
                value &= ~TCSR_TINT;

            xt->regs[addr] = value;
            if (value & TCSR_ENT)
                timer_enable(xt);
            break;
 
        default:
            if (addr < ARRAY_SIZE(xt->regs))
                xt->regs[addr] = value;
            break;
    }
    timer_update_irq(t);
}

static CPUReadMemoryFunc * const timer_read[] = {
    NULL, NULL,
    &timer_readl,
};

static CPUWriteMemoryFunc * const timer_write[] = {
    NULL, NULL,
    &timer_writel,
};

static void timer_hit(void *opaque)
{
    struct xlx_timer *xt = opaque;
    struct timerblock *t = xt->parent;
    D(printf("%s %d\n", __func__, timer));
    xt->regs[R_TCSR] |= TCSR_TINT;

    if (xt->regs[R_TCSR] & TCSR_ARHT)
        timer_enable(xt);
    timer_update_irq(t);
}

static int xilinx_timer_init(SysBusDevice *dev)
{
    struct timerblock *t = FROM_SYSBUS(typeof (*t), dev);
    unsigned int i;
    int timer_regs;

    /* All timers share a single irq line.  */
    sysbus_init_irq(dev, &t->irq);

    /* Init all the ptimers.  */
    t->timers = qemu_mallocz(sizeof t->timers[0] * t->nr_timers);
    for (i = 0; i < t->nr_timers; i++) {
        struct xlx_timer *xt = &t->timers[i];

        xt->parent = t;
        xt->nr = i;
        xt->bh = qemu_bh_new(timer_hit, xt);
        xt->ptimer = ptimer_init(xt->bh);
        ptimer_set_freq(xt->ptimer, t->freq_hz);
    }

    timer_regs = cpu_register_io_memory(timer_read, timer_write, t,
                                        DEVICE_NATIVE_ENDIAN);
    sysbus_init_mmio(dev, R_MAX * 4 * t->nr_timers, timer_regs);
    return 0;
}

static SysBusDeviceInfo xilinx_timer_info = {
    .init = xilinx_timer_init,
    .qdev.name  = "xilinx,timer",
    .qdev.size  = sizeof(struct timerblock),
    .qdev.props = (Property[]) {
        DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz,   0),
        DEFINE_PROP_UINT32("nr-timers", struct timerblock, nr_timers, 0),
        DEFINE_PROP_END_OF_LIST(),
    }
};

static void xilinx_timer_register(void)
{
    sysbus_register_withprop(&xilinx_timer_info);
}

device_init(xilinx_timer_register)
Commit	Line	Data
388f60b1 EI	1	/*
	2	* QEMU model of the Xilinx timer block.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias.
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24
	25	#include "sysbus.h"
388f60b1 EI	26	#include "qemu-timer.h"
	27
	28	#define D(x)
	29
	30	#define R_TCSR 0
	31	#define R_TLR 1
	32	#define R_TCR 2
	33	#define R_MAX 4
	34
	35	#define TCSR_MDT (1<<0)
	36	#define TCSR_UDT (1<<1)
	37	#define TCSR_GENT (1<<2)
	38	#define TCSR_CAPT (1<<3)
	39	#define TCSR_ARHT (1<<4)
	40	#define TCSR_LOAD (1<<5)
	41	#define TCSR_ENIT (1<<6)
	42	#define TCSR_ENT (1<<7)
	43	#define TCSR_TINT (1<<8)
	44	#define TCSR_PWMA (1<<9)
	45	#define TCSR_ENALL (1<<10)
	46
	47	struct xlx_timer
	48	{
	49	QEMUBH *bh;
	50	ptimer_state *ptimer;
	51	void *parent;
	52	int nr; /* for debug. */
	53
	54	unsigned long timer_div;
	55
	56	uint32_t regs[R_MAX];
	57	};
	58
	59	struct timerblock
	60	{
	61	SysBusDevice busdev;
	62	qemu_irq irq;
ee6847d1 GH	63	uint32_t nr_timers;
ee6847d1 GH	64	uint32_t freq_hz;
388f60b1 EI	65	struct xlx_timer *timers;
	66	};
	67
c227f099	68	static inline unsigned int timer_from_addr(target_phys_addr_t addr)
388f60b1 EI	69	{
	70	/* Timers get a 4x32bit control reg area each. */
	71	return addr >> 2;
	72	}
	73
	74	static void timer_update_irq(struct timerblock *t)
	75	{
	76	unsigned int i, irq = 0;
	77	uint32_t csr;
	78
	79	for (i = 0; i < t->nr_timers; i++) {
	80	csr = t->timers[i].regs[R_TCSR];
	81	irq \|= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
	82	}
	83
	84	/* All timers within the same slave share a single IRQ line. */
	85	qemu_set_irq(t->irq, !!irq);
	86	}
	87
c227f099	88	static uint32_t timer_readl (void *opaque, target_phys_addr_t addr)
388f60b1 EI	89	{
	90	struct timerblock *t = opaque;
	91	struct xlx_timer *xt;
	92	uint32_t r = 0;
	93	unsigned int timer;
	94
	95	addr >>= 2;
	96	timer = timer_from_addr(addr);
	97	xt = &t->timers[timer];
	98	/* Further decoding to address a specific timers reg. */
	99	addr &= 0x3;
	100	switch (addr)
	101	{
	102	case R_TCR:
	103	r = ptimer_get_count(xt->ptimer);
	104	if (!(xt->regs[R_TCSR] & TCSR_UDT))
	105	r = ~r;
	106	D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
	107	timer, r, xt->regs[R_TCSR] & TCSR_UDT));
	108	break;
	109	default:
	110	if (addr < ARRAY_SIZE(xt->regs))
	111	r = xt->regs[addr];
	112	break;
	113
	114	}
	115	D(printf("%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
	116	return r;
	117	}
	118
	119	static void timer_enable(struct xlx_timer *xt)
	120	{
	121	uint64_t count;
	122
	123	D(printf("%s timer=%d down=%d\n", __func__,
	124	xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
	125
	126	ptimer_stop(xt->ptimer);
	127
	128	if (xt->regs[R_TCSR] & TCSR_UDT)
	129	count = xt->regs[R_TLR];
	130	else
	131	count = ~0 - xt->regs[R_TLR];
	132	ptimer_set_count(xt->ptimer, count);
	133	ptimer_run(xt->ptimer, 1);
	134	}
	135
	136	static void
c227f099	137	timer_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
388f60b1 EI	138	{
	139	struct timerblock *t = opaque;
	140	struct xlx_timer *xt;
	141	unsigned int timer;
	142
	143	addr >>= 2;
	144	timer = timer_from_addr(addr);
	145	xt = &t->timers[timer];
	146	D(printf("%s addr=%x val=%x (timer=%d off=%d)\n",
	147	__func__, addr * 4, value, timer, addr & 3));
	148	/* Further decoding to address a specific timers reg. */
	149	addr &= 3;
	150	switch (addr)
	151	{
	152	case R_TCSR:
	153	if (value & TCSR_TINT)
	154	value &= ~TCSR_TINT;
	155
	156	xt->regs[addr] = value;
	157	if (value & TCSR_ENT)
	158	timer_enable(xt);
	159	break;
	160
	161	default:
	162	if (addr < ARRAY_SIZE(xt->regs))
	163	xt->regs[addr] = value;
	164	break;
	165	}
	166	timer_update_irq(t);
	167	}
	168
d60efc6b	169	static CPUReadMemoryFunc * const timer_read[] = {
388f60b1 EI	170	NULL, NULL,
	171	&timer_readl,
	172	};
	173
d60efc6b	174	static CPUWriteMemoryFunc * const timer_write[] = {
388f60b1 EI	175	NULL, NULL,
	176	&timer_writel,
	177	};
	178
	179	static void timer_hit(void *opaque)
	180	{
	181	struct xlx_timer *xt = opaque;
	182	struct timerblock *t = xt->parent;
	183	D(printf("%s %d\n", __func__, timer));
	184	xt->regs[R_TCSR] \|= TCSR_TINT;
	185
	186	if (xt->regs[R_TCSR] & TCSR_ARHT)
	187	timer_enable(xt);
	188	timer_update_irq(t);
	189	}
	190
81a322d4	191	static int xilinx_timer_init(SysBusDevice *dev)
388f60b1 EI	192	{
	193	struct timerblock t = FROM_SYSBUS(typeof (t), dev);
	194	unsigned int i;
ee6847d1	195	int timer_regs;
388f60b1 EI	196
	197	/* All timers share a single irq line. */
	198	sysbus_init_irq(dev, &t->irq);
	199
	200	/* Init all the ptimers. */
388f60b1 EI	201	t->timers = qemu_mallocz(sizeof t->timers[0] * t->nr_timers);
	202	for (i = 0; i < t->nr_timers; i++) {
	203	struct xlx_timer *xt = &t->timers[i];
	204
	205	xt->parent = t;
	206	xt->nr = i;
	207	xt->bh = qemu_bh_new(timer_hit, xt);
	208	xt->ptimer = ptimer_init(xt->bh);
ee6847d1	209	ptimer_set_freq(xt->ptimer, t->freq_hz);
388f60b1 EI	210	}
388f60b1 EI	211
2507c12a AG	212	timer_regs = cpu_register_io_memory(timer_read, timer_write, t,
2507c12a AG	213	DEVICE_NATIVE_ENDIAN);
388f60b1	214	sysbus_init_mmio(dev, R_MAX * 4 * t->nr_timers, timer_regs);
81a322d4	215	return 0;
388f60b1 EI	216	}
388f60b1 EI	217
ee6847d1 GH	218	static SysBusDeviceInfo xilinx_timer_info = {
	219	.init = xilinx_timer_init,
	220	.qdev.name = "xilinx,timer",
	221	.qdev.size = sizeof(struct timerblock),
	222	.qdev.props = (Property[]) {
ea2b7271 GH	223	DEFINE_PROP_UINT32("frequency", struct timerblock, freq_hz, 0),
	224	DEFINE_PROP_UINT32("nr-timers", struct timerblock, nr_timers, 0),
	225	DEFINE_PROP_END_OF_LIST(),
ee6847d1 GH	226	}
	227	};
	228
388f60b1 EI	229	static void xilinx_timer_register(void)
388f60b1 EI	230	{
ee6847d1	231	sysbus_register_withprop(&xilinx_timer_info);
388f60b1 EI	232	}
	233
	234	device_init(xilinx_timer_register)