[qemu.git] / include / hw / arm / pxa.h

/*
 * Intel XScale PXA255/270 processor support.
 *
 * Copyright (c) 2006 Openedhand Ltd.
 * Written by Andrzej Zaborowski <balrog@zabor.org>
 *
 * This code is licensed under the GNU GPL v2.
 */
#ifndef PXA_H
# define PXA_H			"pxa.h"

#include "exec/memory.h"

/* Interrupt numbers */
# define PXA2XX_PIC_SSP3	0
# define PXA2XX_PIC_USBH2	2
# define PXA2XX_PIC_USBH1	3
# define PXA2XX_PIC_KEYPAD	4
# define PXA2XX_PIC_PWRI2C	6
# define PXA25X_PIC_HWUART	7
# define PXA27X_PIC_OST_4_11	7
# define PXA2XX_PIC_GPIO_0	8
# define PXA2XX_PIC_GPIO_1	9
# define PXA2XX_PIC_GPIO_X	10
# define PXA2XX_PIC_I2S 	13
# define PXA26X_PIC_ASSP	15
# define PXA25X_PIC_NSSP	16
# define PXA27X_PIC_SSP2	16
# define PXA2XX_PIC_LCD		17
# define PXA2XX_PIC_I2C		18
# define PXA2XX_PIC_ICP		19
# define PXA2XX_PIC_STUART	20
# define PXA2XX_PIC_BTUART	21
# define PXA2XX_PIC_FFUART	22
# define PXA2XX_PIC_MMC		23
# define PXA2XX_PIC_SSP		24
# define PXA2XX_PIC_DMA		25
# define PXA2XX_PIC_OST_0	26
# define PXA2XX_PIC_RTC1HZ	30
# define PXA2XX_PIC_RTCALARM	31

/* DMA requests */
# define PXA2XX_RX_RQ_I2S	2
# define PXA2XX_TX_RQ_I2S	3
# define PXA2XX_RX_RQ_BTUART	4
# define PXA2XX_TX_RQ_BTUART	5
# define PXA2XX_RX_RQ_FFUART	6
# define PXA2XX_TX_RQ_FFUART	7
# define PXA2XX_RX_RQ_SSP1	13
# define PXA2XX_TX_RQ_SSP1	14
# define PXA2XX_RX_RQ_SSP2	15
# define PXA2XX_TX_RQ_SSP2	16
# define PXA2XX_RX_RQ_ICP	17
# define PXA2XX_TX_RQ_ICP	18
# define PXA2XX_RX_RQ_STUART	19
# define PXA2XX_TX_RQ_STUART	20
# define PXA2XX_RX_RQ_MMCI	21
# define PXA2XX_TX_RQ_MMCI	22
# define PXA2XX_USB_RQ(x)	((x) + 24)
# define PXA2XX_RX_RQ_SSP3	66
# define PXA2XX_TX_RQ_SSP3	67

# define PXA2XX_SDRAM_BASE	0xa0000000
# define PXA2XX_INTERNAL_BASE	0x5c000000
# define PXA2XX_INTERNAL_SIZE	0x40000

/* pxa2xx_pic.c */
DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu);

/* pxa2xx_gpio.c */
DeviceState *pxa2xx_gpio_init(hwaddr base,
                              ARMCPU *cpu, DeviceState *pic, int lines);
void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);

/* pxa2xx_dma.c */
DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq);
DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq);

/* pxa2xx_lcd.c */
typedef struct PXA2xxLCDState PXA2xxLCDState;
PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
                hwaddr base, qemu_irq irq);
void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
void pxa2xx_lcdc_oritentation(void *opaque, int angle);

/* pxa2xx_mmci.c */
typedef struct PXA2xxMMCIState PXA2xxMMCIState;
PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
                hwaddr base,
                BlockDriverState *bd, qemu_irq irq,
                qemu_irq rx_dma, qemu_irq tx_dma);
void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
                qemu_irq coverswitch);

/* pxa2xx_pcmcia.c */
typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
                                      hwaddr base);
int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
int pxa2xx_pcmcia_detach(void *opaque);
void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);

/* pxa2xx_keypad.c */
struct  keymap {
    int column;
    int row;
};
typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
                                      hwaddr base,
                                      qemu_irq irq);
void pxa27x_register_keypad(PXA2xxKeyPadState *kp, struct keymap *map,
                int size);

/* pxa2xx.c */
typedef struct PXA2xxI2CState PXA2xxI2CState;
PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
                qemu_irq irq, uint32_t page_size);
i2c_bus *pxa2xx_i2c_bus(PXA2xxI2CState *s);

typedef struct PXA2xxI2SState PXA2xxI2SState;
typedef struct PXA2xxFIrState PXA2xxFIrState;

typedef struct {
    ARMCPU *cpu;
    DeviceState *pic;
    qemu_irq reset;
    MemoryRegion sdram;
    MemoryRegion internal;
    MemoryRegion cm_iomem;
    MemoryRegion mm_iomem;
    MemoryRegion pm_iomem;
    DeviceState *dma;
    DeviceState *gpio;
    PXA2xxLCDState *lcd;
    SSIBus **ssp;
    PXA2xxI2CState *i2c[2];
    PXA2xxMMCIState *mmc;
    PXA2xxPCMCIAState *pcmcia[2];
    PXA2xxI2SState *i2s;
    PXA2xxFIrState *fir;
    PXA2xxKeyPadState *kp;

    /* Power management */
    hwaddr pm_base;
    uint32_t pm_regs[0x40];

    /* Clock management */
    hwaddr cm_base;
    uint32_t cm_regs[4];
    uint32_t clkcfg;

    /* Memory management */
    hwaddr mm_base;
    uint32_t mm_regs[0x1a];

    /* Performance monitoring */
    uint32_t pmnc;
} PXA2xxState;

struct PXA2xxI2SState {
    MemoryRegion iomem;
    qemu_irq irq;
    qemu_irq rx_dma;
    qemu_irq tx_dma;
    void (*data_req)(void *, int, int);

    uint32_t control[2];
    uint32_t status;
    uint32_t mask;
    uint32_t clk;

    int enable;
    int rx_len;
    int tx_len;
    void (*codec_out)(void *, uint32_t);
    uint32_t (*codec_in)(void *);
    void *opaque;

    int fifo_len;
    uint32_t fifo[16];
};

# define PA_FMT			"0x%08lx"
# define REG_FMT		"0x" TARGET_FMT_plx

PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
                         const char *revision);
PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size);

#endif	/* PXA_H */
Commit	Line	Data
c1713132 AZ	1	/*
	2	* Intel XScale PXA255/270 processor support.
	3	*
	4	* Copyright (c) 2006 Openedhand Ltd.
	5	* Written by Andrzej Zaborowski <balrog@zabor.org>
	6	*
8e31bf38	7	* This code is licensed under the GNU GPL v2.
c1713132 AZ	8	*/
	9	#ifndef PXA_H
	10	# define PXA_H "pxa.h"
	11
022c62cb	12	#include "exec/memory.h"
a6dc4c2d	13
c1713132 AZ	14	/* Interrupt numbers */
	15	# define PXA2XX_PIC_SSP3 0
	16	# define PXA2XX_PIC_USBH2 2
	17	# define PXA2XX_PIC_USBH1 3
31b87f2e	18	# define PXA2XX_PIC_KEYPAD 4
c1713132 AZ	19	# define PXA2XX_PIC_PWRI2C 6
	20	# define PXA25X_PIC_HWUART 7
	21	# define PXA27X_PIC_OST_4_11 7
	22	# define PXA2XX_PIC_GPIO_0 8
	23	# define PXA2XX_PIC_GPIO_1 9
	24	# define PXA2XX_PIC_GPIO_X 10
	25	# define PXA2XX_PIC_I2S 13
	26	# define PXA26X_PIC_ASSP 15
	27	# define PXA25X_PIC_NSSP 16
	28	# define PXA27X_PIC_SSP2 16
	29	# define PXA2XX_PIC_LCD 17
	30	# define PXA2XX_PIC_I2C 18
	31	# define PXA2XX_PIC_ICP 19
	32	# define PXA2XX_PIC_STUART 20
	33	# define PXA2XX_PIC_BTUART 21
	34	# define PXA2XX_PIC_FFUART 22
	35	# define PXA2XX_PIC_MMC 23
	36	# define PXA2XX_PIC_SSP 24
	37	# define PXA2XX_PIC_DMA 25
	38	# define PXA2XX_PIC_OST_0 26
	39	# define PXA2XX_PIC_RTC1HZ 30
	40	# define PXA2XX_PIC_RTCALARM 31
	41
	42	/* DMA requests */
	43	# define PXA2XX_RX_RQ_I2S 2
	44	# define PXA2XX_TX_RQ_I2S 3
	45	# define PXA2XX_RX_RQ_BTUART 4
	46	# define PXA2XX_TX_RQ_BTUART 5
	47	# define PXA2XX_RX_RQ_FFUART 6
	48	# define PXA2XX_TX_RQ_FFUART 7
	49	# define PXA2XX_RX_RQ_SSP1 13
	50	# define PXA2XX_TX_RQ_SSP1 14
	51	# define PXA2XX_RX_RQ_SSP2 15
	52	# define PXA2XX_TX_RQ_SSP2 16
	53	# define PXA2XX_RX_RQ_ICP 17
	54	# define PXA2XX_TX_RQ_ICP 18
	55	# define PXA2XX_RX_RQ_STUART 19
	56	# define PXA2XX_TX_RQ_STUART 20
	57	# define PXA2XX_RX_RQ_MMCI 21
	58	# define PXA2XX_TX_RQ_MMCI 22
	59	# define PXA2XX_USB_RQ(x) ((x) + 24)
	60	# define PXA2XX_RX_RQ_SSP3 66
	61	# define PXA2XX_TX_RQ_SSP3 67
	62
d95b2f8d AZ	63	# define PXA2XX_SDRAM_BASE 0xa0000000
d95b2f8d AZ	64	# define PXA2XX_INTERNAL_BASE 0x5c000000
a07dec22	65	# define PXA2XX_INTERNAL_SIZE 0x40000
c1713132 AZ	66
c1713132 AZ	67	/* pxa2xx_pic.c */
a8170e5e	68	DeviceState pxa2xx_pic_init(hwaddr base, ARMCPU cpu);
c1713132 AZ	69
c1713132 AZ	70	/* pxa2xx_gpio.c */
a8170e5e	71	DeviceState *pxa2xx_gpio_init(hwaddr base,
55e5c285	72	ARMCPU cpu, DeviceState pic, int lines);
0bb53337	73	void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
c1713132 AZ	74
c1713132 AZ	75	/* pxa2xx_dma.c */
a8170e5e AK	76	DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq);
a8170e5e AK	77	DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq);
c1713132	78
a171fe39	79	/* pxa2xx_lcd.c */
bc24a225	80	typedef struct PXA2xxLCDState PXA2xxLCDState;
5a6fdd91	81	PXA2xxLCDState pxa2xx_lcdc_init(MemoryRegion sysmem,
a8170e5e	82	hwaddr base, qemu_irq irq);
bc24a225	83	void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
a171fe39 AZ	84	void pxa2xx_lcdc_oritentation(void *opaque, int angle);
	85
	86	/* pxa2xx_mmci.c */
bc24a225	87	typedef struct PXA2xxMMCIState PXA2xxMMCIState;
2bf90458	88	PXA2xxMMCIState pxa2xx_mmci_init(MemoryRegion sysmem,
a8170e5e	89	hwaddr base,
2115c019 AZ	90	BlockDriverState *bd, qemu_irq irq,
2115c019 AZ	91	qemu_irq rx_dma, qemu_irq tx_dma);
bc24a225	92	void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
02ce600c	93	qemu_irq coverswitch);
a171fe39 AZ	94
a171fe39 AZ	95	/* pxa2xx_pcmcia.c */
bc24a225	96	typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
354a8c06	97	PXA2xxPCMCIAState pxa2xx_pcmcia_init(MemoryRegion sysmem,
a8170e5e	98	hwaddr base);
bc24a225	99	int pxa2xx_pcmcia_attach(void opaque, PCMCIACardState card);
853ca11d	100	int pxa2xx_pcmcia_detach(void *opaque);
a171fe39 AZ	101	void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
a171fe39 AZ	102
31b87f2e AZ	103	/* pxa2xx_keypad.c */
	104	struct keymap {
	105	int column;
	106	int row;
	107	};
bc24a225	108	typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
6cd816b8	109	PXA2xxKeyPadState pxa27x_keypad_init(MemoryRegion sysmem,
a8170e5e	110	hwaddr base,
6cd816b8	111	qemu_irq irq);
bc24a225	112	void pxa27x_register_keypad(PXA2xxKeyPadState kp, struct keymap map,
31b87f2e AZ	113	int size);
31b87f2e AZ	114
c1713132	115	/* pxa2xx.c */
bc24a225	116	typedef struct PXA2xxI2CState PXA2xxI2CState;
a8170e5e	117	PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
2a163929	118	qemu_irq irq, uint32_t page_size);
bc24a225	119	i2c_bus pxa2xx_i2c_bus(PXA2xxI2CState s);
3f582262	120
bc24a225 PB	121	typedef struct PXA2xxI2SState PXA2xxI2SState;
bc24a225 PB	122	typedef struct PXA2xxFIrState PXA2xxFIrState;
c1713132	123
bc24a225	124	typedef struct {
43824588	125	ARMCPU *cpu;
e1f8c729	126	DeviceState *pic;
38641a52	127	qemu_irq reset;
adfc39ea AK	128	MemoryRegion sdram;
	129	MemoryRegion internal;
	130	MemoryRegion cm_iomem;
	131	MemoryRegion mm_iomem;
	132	MemoryRegion pm_iomem;
2115c019	133	DeviceState *dma;
0bb53337	134	DeviceState *gpio;
bc24a225	135	PXA2xxLCDState *lcd;
a984a69e	136	SSIBus **ssp;
bc24a225 PB	137	PXA2xxI2CState *i2c[2];
	138	PXA2xxMMCIState *mmc;
	139	PXA2xxPCMCIAState *pcmcia[2];
	140	PXA2xxI2SState *i2s;
	141	PXA2xxFIrState *fir;
	142	PXA2xxKeyPadState *kp;
c1713132 AZ	143
c1713132 AZ	144	/* Power management */
a8170e5e	145	hwaddr pm_base;
c1713132 AZ	146	uint32_t pm_regs[0x40];
	147
	148	/* Clock management */
a8170e5e	149	hwaddr cm_base;
c1713132 AZ	150	uint32_t cm_regs[4];
	151	uint32_t clkcfg;
	152
	153	/* Memory management */
a8170e5e	154	hwaddr mm_base;
c1713132 AZ	155	uint32_t mm_regs[0x1a];
	156
	157	/* Performance monitoring */
	158	uint32_t pmnc;
bc24a225	159	} PXA2xxState;
c1713132	160
bc24a225	161	struct PXA2xxI2SState {
9c843933	162	MemoryRegion iomem;
c1713132	163	qemu_irq irq;
2115c019 AZ	164	qemu_irq rx_dma;
2115c019 AZ	165	qemu_irq tx_dma;
c1713132 AZ	166	void (data_req)(void , int, int);
	167
	168	uint32_t control[2];
	169	uint32_t status;
	170	uint32_t mask;
	171	uint32_t clk;
	172
	173	int enable;
	174	int rx_len;
	175	int tx_len;
	176	void (codec_out)(void , uint32_t);
	177	uint32_t (codec_in)(void );
	178	void *opaque;
	179
	180	int fifo_len;
	181	uint32_t fifo[16];
	182	};
	183
	184	# define PA_FMT "0x%08lx"
444ce241	185	# define REG_FMT "0x" TARGET_FMT_plx
c1713132	186
a6dc4c2d RH	187	PXA2xxState pxa270_init(MemoryRegion address_space, unsigned int sdram_size,
	188	const char *revision);
	189	PXA2xxState pxa255_init(MemoryRegion address_space, unsigned int sdram_size);
c1713132	190
c1713132	191	#endif /* PXA_H */