[qemu.git] / ioport.c

/*
 * QEMU System Emulator
 *
 * Copyright (c) 2003-2008 Fabrice Bellard
 *
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included in
 * all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
 * THE SOFTWARE.
 */
/*
 * splitted out ioport related stuffs from vl.c.
 */

#include "ioport.h"
#include "trace.h"

/***********************************************************/
/* IO Port */

//#define DEBUG_UNUSED_IOPORT
//#define DEBUG_IOPORT

#ifdef DEBUG_UNUSED_IOPORT
#  define LOG_UNUSED_IOPORT(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
#else
#  define LOG_UNUSED_IOPORT(fmt, ...) do{ } while (0)
#endif

#ifdef DEBUG_IOPORT
#  define LOG_IOPORT(...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__)
#else
#  define LOG_IOPORT(...) do { } while (0)
#endif

/* XXX: use a two level table to limit memory usage */

static void *ioport_opaque[MAX_IOPORTS];
static IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
static IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];

static IOPortReadFunc default_ioport_readb, default_ioport_readw, default_ioport_readl;
static IOPortWriteFunc default_ioport_writeb, default_ioport_writew, default_ioport_writel;

static uint32_t ioport_read(int index, uint32_t address)
{
    static IOPortReadFunc * const default_func[3] = {
        default_ioport_readb,
        default_ioport_readw,
        default_ioport_readl
    };
    IOPortReadFunc *func = ioport_read_table[index][address];
    if (!func)
        func = default_func[index];
    return func(ioport_opaque[address], address);
}

static void ioport_write(int index, uint32_t address, uint32_t data)
{
    static IOPortWriteFunc * const default_func[3] = {
        default_ioport_writeb,
        default_ioport_writew,
        default_ioport_writel
    };
    IOPortWriteFunc *func = ioport_write_table[index][address];
    if (!func)
        func = default_func[index];
    func(ioport_opaque[address], address, data);
}

static uint32_t default_ioport_readb(void *opaque, uint32_t address)
{
    LOG_UNUSED_IOPORT("unused inb: port=0x%04"PRIx32"\n", address);
    return 0xff;
}

static void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data)
{
    LOG_UNUSED_IOPORT("unused outb: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
                      address, data);
}

/* default is to make two byte accesses */
static uint32_t default_ioport_readw(void *opaque, uint32_t address)
{
    uint32_t data;
    data = ioport_read(0, address);
    address = (address + 1) & IOPORTS_MASK;
    data |= ioport_read(0, address) << 8;
    return data;
}

static void default_ioport_writew(void *opaque, uint32_t address, uint32_t data)
{
    ioport_write(0, address, data & 0xff);
    address = (address + 1) & IOPORTS_MASK;
    ioport_write(0, address, (data >> 8) & 0xff);
}

static uint32_t default_ioport_readl(void *opaque, uint32_t address)
{
    LOG_UNUSED_IOPORT("unused inl: port=0x%04"PRIx32"\n", address);
    return 0xffffffff;
}

static void default_ioport_writel(void *opaque, uint32_t address, uint32_t data)
{
    LOG_UNUSED_IOPORT("unused outl: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
                      address, data);
}

static int ioport_bsize(int size, int *bsize)
{
    if (size == 1) {
        *bsize = 0;
    } else if (size == 2) {
        *bsize = 1;
    } else if (size == 4) {
        *bsize = 2;
    } else {
        return -1;
    }
    return 0;
}

/* size is the word size in byte */
int register_ioport_read(pio_addr_t start, int length, int size,
                         IOPortReadFunc *func, void *opaque)
{
    int i, bsize;

    if (ioport_bsize(size, &bsize)) {
        hw_error("register_ioport_read: invalid size");
        return -1;
    }
    for(i = start; i < start + length; i += size) {
        ioport_read_table[bsize][i] = func;
        if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
            hw_error("register_ioport_read: invalid opaque for address 0x%x",
                     i);
        ioport_opaque[i] = opaque;
    }
    return 0;
}

/* size is the word size in byte */
int register_ioport_write(pio_addr_t start, int length, int size,
                          IOPortWriteFunc *func, void *opaque)
{
    int i, bsize;

    if (ioport_bsize(size, &bsize)) {
        hw_error("register_ioport_write: invalid size");
        return -1;
    }
    for(i = start; i < start + length; i += size) {
        ioport_write_table[bsize][i] = func;
        if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
            hw_error("register_ioport_write: invalid opaque for address 0x%x",
                     i);
        ioport_opaque[i] = opaque;
    }
    return 0;
}

static uint32_t ioport_readb_thunk(void *opaque, uint32_t addr)
{
    IORange *ioport = opaque;
    uint64_t data;

    ioport->ops->read(ioport, addr - ioport->base, 1, &data);
    return data;
}

static uint32_t ioport_readw_thunk(void *opaque, uint32_t addr)
{
    IORange *ioport = opaque;
    uint64_t data;

    ioport->ops->read(ioport, addr - ioport->base, 2, &data);
    return data;
}

static uint32_t ioport_readl_thunk(void *opaque, uint32_t addr)
{
    IORange *ioport = opaque;
    uint64_t data;

    ioport->ops->read(ioport, addr - ioport->base, 4, &data);
    return data;
}

static void ioport_writeb_thunk(void *opaque, uint32_t addr, uint32_t data)
{
    IORange *ioport = opaque;

    ioport->ops->write(ioport, addr - ioport->base, 1, data);
}

static void ioport_writew_thunk(void *opaque, uint32_t addr, uint32_t data)
{
    IORange *ioport = opaque;

    ioport->ops->write(ioport, addr - ioport->base, 2, data);
}

static void ioport_writel_thunk(void *opaque, uint32_t addr, uint32_t data)
{
    IORange *ioport = opaque;

    ioport->ops->write(ioport, addr - ioport->base, 4, data);
}

void ioport_register(IORange *ioport)
{
    register_ioport_read(ioport->base, ioport->len, 1,
                         ioport_readb_thunk, ioport);
    register_ioport_read(ioport->base, ioport->len, 2,
                         ioport_readw_thunk, ioport);
    register_ioport_read(ioport->base, ioport->len, 4,
                         ioport_readl_thunk, ioport);
    register_ioport_write(ioport->base, ioport->len, 1,
                          ioport_writeb_thunk, ioport);
    register_ioport_write(ioport->base, ioport->len, 2,
                          ioport_writew_thunk, ioport);
    register_ioport_write(ioport->base, ioport->len, 4,
                          ioport_writel_thunk, ioport);
}

void isa_unassign_ioport(pio_addr_t start, int length)
{
    int i;

    for(i = start; i < start + length; i++) {
        ioport_read_table[0][i] = NULL;
        ioport_read_table[1][i] = NULL;
        ioport_read_table[2][i] = NULL;

        ioport_write_table[0][i] = NULL;
        ioport_write_table[1][i] = NULL;
        ioport_write_table[2][i] = NULL;

        ioport_opaque[i] = NULL;
    }
}

bool isa_is_ioport_assigned(pio_addr_t start)
{
    return (ioport_read_table[0][start] || ioport_write_table[0][start] ||
	    ioport_read_table[1][start] || ioport_write_table[1][start] ||
	    ioport_read_table[2][start] || ioport_write_table[2][start]);
}

/***********************************************************/

void cpu_outb(pio_addr_t addr, uint8_t val)
{
    LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
    trace_cpu_out(addr, val);
    ioport_write(0, addr, val);
}

void cpu_outw(pio_addr_t addr, uint16_t val)
{
    LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
    trace_cpu_out(addr, val);
    ioport_write(1, addr, val);
}

void cpu_outl(pio_addr_t addr, uint32_t val)
{
    LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
    trace_cpu_out(addr, val);
    ioport_write(2, addr, val);
}

uint8_t cpu_inb(pio_addr_t addr)
{
    uint8_t val;
    val = ioport_read(0, addr);
    trace_cpu_in(addr, val);
    LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
    return val;
}

uint16_t cpu_inw(pio_addr_t addr)
{
    uint16_t val;
    val = ioport_read(1, addr);
    trace_cpu_in(addr, val);
    LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
    return val;
}

uint32_t cpu_inl(pio_addr_t addr)
{
    uint32_t val;
    val = ioport_read(2, addr);
    trace_cpu_in(addr, val);
    LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
    return val;
}
Commit	Line	Data
32993977 IY	1	/*
	2	* QEMU System Emulator
	3	*
	4	* Copyright (c) 2003-2008 Fabrice Bellard
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a copy
	7	* of this software and associated documentation files (the "Software"), to deal
	8	* in the Software without restriction, including without limitation the rights
	9	* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
	10	* copies of the Software, and to permit persons to whom the Software is
	11	* furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice shall be included in
	14	* all copies or substantial portions of the Software.
	15	*
	16	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	17	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	18	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	19	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	20	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	21	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
	22	* THE SOFTWARE.
	23	*/
	24	/*
	25	* splitted out ioport related stuffs from vl.c.
	26	*/
	27
	28	#include "ioport.h"
bd3c9aa5	29	#include "trace.h"
32993977 IY	30
	31	/***********************************************************/
	32	/* IO Port */
	33
	34	//#define DEBUG_UNUSED_IOPORT
	35	//#define DEBUG_IOPORT
	36
fc7083b5 IY	37	#ifdef DEBUG_UNUSED_IOPORT
	38	# define LOG_UNUSED_IOPORT(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__)
	39	#else
	40	# define LOG_UNUSED_IOPORT(fmt, ...) do{ } while (0)
	41	#endif
	42
32993977 IY	43	#ifdef DEBUG_IOPORT
	44	# define LOG_IOPORT(...) qemu_log_mask(CPU_LOG_IOPORT, ## __VA_ARGS__)
	45	#else
	46	# define LOG_IOPORT(...) do { } while (0)
	47	#endif
	48
	49	/* XXX: use a two level table to limit memory usage */
	50
	51	static void *ioport_opaque[MAX_IOPORTS];
	52	static IOPortReadFunc *ioport_read_table[3][MAX_IOPORTS];
	53	static IOPortWriteFunc *ioport_write_table[3][MAX_IOPORTS];
	54
	55	static IOPortReadFunc default_ioport_readb, default_ioport_readw, default_ioport_readl;
	56	static IOPortWriteFunc default_ioport_writeb, default_ioport_writew, default_ioport_writel;
	57
	58	static uint32_t ioport_read(int index, uint32_t address)
	59	{
1dde6fcc	60	static IOPortReadFunc * const default_func[3] = {
32993977 IY	61	default_ioport_readb,
	62	default_ioport_readw,
	63	default_ioport_readl
	64	};
	65	IOPortReadFunc *func = ioport_read_table[index][address];
	66	if (!func)
	67	func = default_func[index];
	68	return func(ioport_opaque[address], address);
	69	}
	70
	71	static void ioport_write(int index, uint32_t address, uint32_t data)
	72	{
1dde6fcc	73	static IOPortWriteFunc * const default_func[3] = {
32993977 IY	74	default_ioport_writeb,
	75	default_ioport_writew,
	76	default_ioport_writel
	77	};
	78	IOPortWriteFunc *func = ioport_write_table[index][address];
	79	if (!func)
	80	func = default_func[index];
	81	func(ioport_opaque[address], address, data);
	82	}
	83
	84	static uint32_t default_ioport_readb(void *opaque, uint32_t address)
	85	{
fc7083b5	86	LOG_UNUSED_IOPORT("unused inb: port=0x%04"PRIx32"\n", address);
32993977 IY	87	return 0xff;
	88	}
	89
	90	static void default_ioport_writeb(void *opaque, uint32_t address, uint32_t data)
	91	{
fc7083b5 IY	92	LOG_UNUSED_IOPORT("unused outb: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
fc7083b5 IY	93	address, data);
32993977 IY	94	}
	95
	96	/* default is to make two byte accesses */
	97	static uint32_t default_ioport_readw(void *opaque, uint32_t address)
	98	{
	99	uint32_t data;
	100	data = ioport_read(0, address);
d56dd6cf	101	address = (address + 1) & IOPORTS_MASK;
32993977 IY	102	data \|= ioport_read(0, address) << 8;
	103	return data;
	104	}
	105
	106	static void default_ioport_writew(void *opaque, uint32_t address, uint32_t data)
	107	{
	108	ioport_write(0, address, data & 0xff);
d56dd6cf	109	address = (address + 1) & IOPORTS_MASK;
32993977 IY	110	ioport_write(0, address, (data >> 8) & 0xff);
	111	}
	112
	113	static uint32_t default_ioport_readl(void *opaque, uint32_t address)
	114	{
fc7083b5	115	LOG_UNUSED_IOPORT("unused inl: port=0x%04"PRIx32"\n", address);
32993977 IY	116	return 0xffffffff;
	117	}
	118
	119	static void default_ioport_writel(void *opaque, uint32_t address, uint32_t data)
	120	{
fc7083b5 IY	121	LOG_UNUSED_IOPORT("unused outl: port=0x%04"PRIx32" data=0x%02"PRIx32"\n",
fc7083b5 IY	122	address, data);
32993977 IY	123	}
32993977 IY	124
23e0affd IY	125	static int ioport_bsize(int size, int *bsize)
	126	{
	127	if (size == 1) {
	128	*bsize = 0;
	129	} else if (size == 2) {
	130	*bsize = 1;
	131	} else if (size == 4) {
	132	*bsize = 2;
	133	} else {
	134	return -1;
	135	}
	136	return 0;
	137	}
	138
32993977	139	/* size is the word size in byte */
c227f099	140	int register_ioport_read(pio_addr_t start, int length, int size,
32993977 IY	141	IOPortReadFunc func, void opaque)
	142	{
	143	int i, bsize;
	144
23e0affd	145	if (ioport_bsize(size, &bsize)) {
32993977 IY	146	hw_error("register_ioport_read: invalid size");
	147	return -1;
	148	}
	149	for(i = start; i < start + length; i += size) {
	150	ioport_read_table[bsize][i] = func;
	151	if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
f66a99d7 AF	152	hw_error("register_ioport_read: invalid opaque for address 0x%x",
f66a99d7 AF	153	i);
32993977 IY	154	ioport_opaque[i] = opaque;
	155	}
	156	return 0;
	157	}
	158
	159	/* size is the word size in byte */
c227f099	160	int register_ioport_write(pio_addr_t start, int length, int size,
32993977 IY	161	IOPortWriteFunc func, void opaque)
	162	{
	163	int i, bsize;
	164
23e0affd	165	if (ioport_bsize(size, &bsize)) {
32993977 IY	166	hw_error("register_ioport_write: invalid size");
	167	return -1;
	168	}
	169	for(i = start; i < start + length; i += size) {
	170	ioport_write_table[bsize][i] = func;
	171	if (ioport_opaque[i] != NULL && ioport_opaque[i] != opaque)
f66a99d7 AF	172	hw_error("register_ioport_write: invalid opaque for address 0x%x",
f66a99d7 AF	173	i);
32993977 IY	174	ioport_opaque[i] = opaque;
	175	}
	176	return 0;
	177	}
	178
acd1c812 AK	179	static uint32_t ioport_readb_thunk(void *opaque, uint32_t addr)
	180	{
	181	IORange *ioport = opaque;
	182	uint64_t data;
	183
	184	ioport->ops->read(ioport, addr - ioport->base, 1, &data);
	185	return data;
	186	}
	187
	188	static uint32_t ioport_readw_thunk(void *opaque, uint32_t addr)
	189	{
	190	IORange *ioport = opaque;
	191	uint64_t data;
	192
	193	ioport->ops->read(ioport, addr - ioport->base, 2, &data);
	194	return data;
	195	}
	196
	197	static uint32_t ioport_readl_thunk(void *opaque, uint32_t addr)
	198	{
	199	IORange *ioport = opaque;
	200	uint64_t data;
	201
	202	ioport->ops->read(ioport, addr - ioport->base, 4, &data);
	203	return data;
	204	}
	205
	206	static void ioport_writeb_thunk(void *opaque, uint32_t addr, uint32_t data)
	207	{
	208	IORange *ioport = opaque;
	209
	210	ioport->ops->write(ioport, addr - ioport->base, 1, data);
	211	}
	212
	213	static void ioport_writew_thunk(void *opaque, uint32_t addr, uint32_t data)
	214	{
	215	IORange *ioport = opaque;
	216
	217	ioport->ops->write(ioport, addr - ioport->base, 2, data);
	218	}
	219
	220	static void ioport_writel_thunk(void *opaque, uint32_t addr, uint32_t data)
	221	{
	222	IORange *ioport = opaque;
	223
	224	ioport->ops->write(ioport, addr - ioport->base, 4, data);
	225	}
	226
	227	void ioport_register(IORange *ioport)
	228	{
	229	register_ioport_read(ioport->base, ioport->len, 1,
	230	ioport_readb_thunk, ioport);
	231	register_ioport_read(ioport->base, ioport->len, 2,
	232	ioport_readw_thunk, ioport);
	233	register_ioport_read(ioport->base, ioport->len, 4,
	234	ioport_readl_thunk, ioport);
	235	register_ioport_write(ioport->base, ioport->len, 1,
	236	ioport_writeb_thunk, ioport);
	237	register_ioport_write(ioport->base, ioport->len, 2,
	238	ioport_writew_thunk, ioport);
	239	register_ioport_write(ioport->base, ioport->len, 4,
	240	ioport_writel_thunk, ioport);
	241	}
	242
c227f099	243	void isa_unassign_ioport(pio_addr_t start, int length)
32993977 IY	244	{
	245	int i;
	246
	247	for(i = start; i < start + length; i++) {
6141dbfe PB	248	ioport_read_table[0][i] = NULL;
	249	ioport_read_table[1][i] = NULL;
	250	ioport_read_table[2][i] = NULL;
32993977	251
6141dbfe PB	252	ioport_write_table[0][i] = NULL;
	253	ioport_write_table[1][i] = NULL;
	254	ioport_write_table[2][i] = NULL;
32993977 IY	255
	256	ioport_opaque[i] = NULL;
	257	}
	258	}
	259
6141dbfe PB	260	bool isa_is_ioport_assigned(pio_addr_t start)
	261	{
	262	return (ioport_read_table[0][start] \|\| ioport_write_table[0][start] \|\|
	263	ioport_read_table[1][start] \|\| ioport_write_table[1][start] \|\|
	264	ioport_read_table[2][start] \|\| ioport_write_table[2][start]);
	265	}
	266
32993977 IY	267	/***********************************************************/
32993977 IY	268
c227f099	269	void cpu_outb(pio_addr_t addr, uint8_t val)
32993977	270	{
07323531	271	LOG_IOPORT("outb: %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
bd3c9aa5	272	trace_cpu_out(addr, val);
32993977	273	ioport_write(0, addr, val);
32993977 IY	274	}
32993977 IY	275
c227f099	276	void cpu_outw(pio_addr_t addr, uint16_t val)
32993977	277	{
07323531	278	LOG_IOPORT("outw: %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
bd3c9aa5	279	trace_cpu_out(addr, val);
32993977	280	ioport_write(1, addr, val);
32993977 IY	281	}
32993977 IY	282
c227f099	283	void cpu_outl(pio_addr_t addr, uint32_t val)
32993977	284	{
07323531	285	LOG_IOPORT("outl: %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
bd3c9aa5	286	trace_cpu_out(addr, val);
32993977	287	ioport_write(2, addr, val);
32993977 IY	288	}
32993977 IY	289
c227f099	290	uint8_t cpu_inb(pio_addr_t addr)
32993977	291	{
07323531	292	uint8_t val;
32993977	293	val = ioport_read(0, addr);
bd3c9aa5	294	trace_cpu_in(addr, val);
07323531	295	LOG_IOPORT("inb : %04"FMT_pioaddr" %02"PRIx8"\n", addr, val);
32993977 IY	296	return val;
	297	}
	298
c227f099	299	uint16_t cpu_inw(pio_addr_t addr)
32993977	300	{
07323531	301	uint16_t val;
32993977	302	val = ioport_read(1, addr);
bd3c9aa5	303	trace_cpu_in(addr, val);
07323531	304	LOG_IOPORT("inw : %04"FMT_pioaddr" %04"PRIx16"\n", addr, val);
32993977 IY	305	return val;
	306	}
	307
c227f099	308	uint32_t cpu_inl(pio_addr_t addr)
32993977	309	{
07323531	310	uint32_t val;
32993977	311	val = ioport_read(2, addr);
bd3c9aa5	312	trace_cpu_in(addr, val);
07323531	313	LOG_IOPORT("inl : %04"FMT_pioaddr" %08"PRIx32"\n", addr, val);
32993977 IY	314	return val;
32993977 IY	315	}