[qemu.git] / softmmu_template.h

/*
 *  Software MMU support
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
 */
#define DATA_SIZE (1 << SHIFT)

#if DATA_SIZE == 8
#define SUFFIX q
#define USUFFIX q
#define DATA_TYPE uint64_t
#elif DATA_SIZE == 4
#define SUFFIX l
#define USUFFIX l
#define DATA_TYPE uint32_t
#elif DATA_SIZE == 2
#define SUFFIX w
#define USUFFIX uw
#define DATA_TYPE uint16_t
#elif DATA_SIZE == 1
#define SUFFIX b
#define USUFFIX ub
#define DATA_TYPE uint8_t
#else
#error unsupported data size
#endif

#ifdef SOFTMMU_CODE_ACCESS
#define READ_ACCESS_TYPE 2
#define ADDR_READ addr_code
#else
#define READ_ACCESS_TYPE 0
#define ADDR_READ addr_read
#endif

static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                        int mmu_idx,
                                                        void *retaddr);
static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
                                              target_ulong addr,
                                              void *retaddr)
{
    DATA_TYPE res;
    int index;
    index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    env->mem_io_pc = (unsigned long)retaddr;
    if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
            && !can_do_io(env)) {
        cpu_io_recompile(env, retaddr);
    }

    env->mem_io_vaddr = addr;
#if SHIFT <= 2
    res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
    res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
#else
    res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
    res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
#endif
#endif /* SHIFT > 2 */
#ifdef USE_KQEMU
    env->last_io_time = cpu_get_time_fast();
#endif
    return res;
}

/* handle all cases except unaligned access which span two pages */
DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                      int mmu_idx)
{
    DATA_TYPE res;
    int index;
    target_ulong tlb_addr;
    target_phys_addr_t addend;
    void *retaddr;

    /* test if there is match for unaligned or IO access */
    /* XXX: could done more in memory macro in a non portable way */
    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            addend = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(addend, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
            /* slow unaligned access (it spans two pages or IO) */
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
            res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
                                                         mmu_idx, retaddr);
        } else {
            /* unaligned/aligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
#endif
        tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

/* handle all unaligned cases */
static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                        int mmu_idx,
                                                        void *retaddr)
{
    DATA_TYPE res, res1, res2;
    int index, shift;
    target_phys_addr_t addend;
    target_ulong tlb_addr, addr1, addr2;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            addend = env->iotlb[mmu_idx][index];
            res = glue(io_read, SUFFIX)(addend, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* slow unaligned access (it spans two pages) */
            addr1 = addr & ~(DATA_SIZE - 1);
            addr2 = addr1 + DATA_SIZE;
            res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
                                                          mmu_idx, retaddr);
            res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
                                                          mmu_idx, retaddr);
            shift = (addr & (DATA_SIZE - 1)) * 8;
#ifdef TARGET_WORDS_BIGENDIAN
            res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
#else
            res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
#endif
            res = (DATA_TYPE)res;
        } else {
            /* unaligned/aligned access in the same page */
            addend = env->tlb_table[mmu_idx][index].addend;
            res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
        goto redo;
    }
    return res;
}

#ifndef SOFTMMU_CODE_ACCESS

static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr);

static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
                                          DATA_TYPE val,
                                          target_ulong addr,
                                          void *retaddr)
{
    int index;
    index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
    physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
    if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
            && !can_do_io(env)) {
        cpu_io_recompile(env, retaddr);
    }

    env->mem_io_vaddr = addr;
    env->mem_io_pc = (unsigned long)retaddr;
#if SHIFT <= 2
    io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
#else
#ifdef TARGET_WORDS_BIGENDIAN
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
#else
    io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
    io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
#endif
#endif /* SHIFT > 2 */
#ifdef USE_KQEMU
    env->last_io_time = cpu_get_time_fast();
#endif
}

void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                 DATA_TYPE val,
                                                 int mmu_idx)
{
    target_phys_addr_t addend;
    target_ulong tlb_addr;
    void *retaddr;
    int index;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            retaddr = GETPC();
            addend = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(addend, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            retaddr = GETPC();
#ifdef ALIGNED_ONLY
            do_unaligned_access(addr, 1, mmu_idx, retaddr);
#endif
            glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
                                                   mmu_idx, retaddr);
        } else {
            /* aligned/unaligned access in the same page */
#ifdef ALIGNED_ONLY
            if ((addr & (DATA_SIZE - 1)) != 0) {
                retaddr = GETPC();
                do_unaligned_access(addr, 1, mmu_idx, retaddr);
            }
#endif
            addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        retaddr = GETPC();
#ifdef ALIGNED_ONLY
        if ((addr & (DATA_SIZE - 1)) != 0)
            do_unaligned_access(addr, 1, mmu_idx, retaddr);
#endif
        tlb_fill(addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

/* handles all unaligned cases */
static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
                                                   DATA_TYPE val,
                                                   int mmu_idx,
                                                   void *retaddr)
{
    target_phys_addr_t addend;
    target_ulong tlb_addr;
    int index, i;

    index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 redo:
    tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
    if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
        if (tlb_addr & ~TARGET_PAGE_MASK) {
            /* IO access */
            if ((addr & (DATA_SIZE - 1)) != 0)
                goto do_unaligned_access;
            addend = env->iotlb[mmu_idx][index];
            glue(io_write, SUFFIX)(addend, val, addr, retaddr);
        } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
        do_unaligned_access:
            /* XXX: not efficient, but simple */
            /* Note: relies on the fact that tlb_fill() does not remove the
             * previous page from the TLB cache.  */
            for(i = DATA_SIZE - 1; i >= 0; i--) {
#ifdef TARGET_WORDS_BIGENDIAN
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
                                          mmu_idx, retaddr);
#else
                glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
                                          mmu_idx, retaddr);
#endif
            }
        } else {
            /* aligned/unaligned access in the same page */
            addend = env->tlb_table[mmu_idx][index].addend;
            glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
        }
    } else {
        /* the page is not in the TLB : fill it */
        tlb_fill(addr, 1, mmu_idx, retaddr);
        goto redo;
    }
}

#endif /* !defined(SOFTMMU_CODE_ACCESS) */

#undef READ_ACCESS_TYPE
#undef SHIFT
#undef DATA_TYPE
#undef SUFFIX
#undef USUFFIX
#undef DATA_SIZE
#undef ADDR_READ
Commit	Line	Data
b92e5a22 FB	1	/*
b92e5a22 FB	2	* Software MMU support
5fafdf24	3	*
b92e5a22 FB	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, write to the Free Software
fad6cb1a	18	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
b92e5a22 FB	19	*/
	20	#define DATA_SIZE (1 << SHIFT)
	21
	22	#if DATA_SIZE == 8
	23	#define SUFFIX q
61382a50	24	#define USUFFIX q
b92e5a22 FB	25	#define DATA_TYPE uint64_t
	26	#elif DATA_SIZE == 4
	27	#define SUFFIX l
61382a50	28	#define USUFFIX l
b92e5a22 FB	29	#define DATA_TYPE uint32_t
	30	#elif DATA_SIZE == 2
	31	#define SUFFIX w
61382a50	32	#define USUFFIX uw
b92e5a22 FB	33	#define DATA_TYPE uint16_t
	34	#elif DATA_SIZE == 1
	35	#define SUFFIX b
61382a50	36	#define USUFFIX ub
b92e5a22 FB	37	#define DATA_TYPE uint8_t
	38	#else
	39	#error unsupported data size
	40	#endif
	41
b769d8fe FB	42	#ifdef SOFTMMU_CODE_ACCESS
b769d8fe FB	43	#define READ_ACCESS_TYPE 2
84b7b8e7	44	#define ADDR_READ addr_code
b769d8fe FB	45	#else
b769d8fe FB	46	#define READ_ACCESS_TYPE 0
84b7b8e7	47	#define ADDR_READ addr_read
b769d8fe FB	48	#endif
b769d8fe FB	49
5fafdf24	50	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390	51	int mmu_idx,
61382a50	52	void *retaddr);
5fafdf24	53	static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
2e70f6ef PB	54	target_ulong addr,
2e70f6ef PB	55	void *retaddr)
b92e5a22 FB	56	{
	57	DATA_TYPE res;
	58	int index;
0f459d16 PB	59	index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
0f459d16 PB	60	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
2e70f6ef PB	61	env->mem_io_pc = (unsigned long)retaddr;
	62	if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
	63	&& !can_do_io(env)) {
	64	cpu_io_recompile(env, retaddr);
	65	}
b92e5a22	66
db8886d3	67	env->mem_io_vaddr = addr;
b92e5a22	68	#if SHIFT <= 2
a4193c8a	69	res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
b92e5a22 FB	70	#else
b92e5a22 FB	71	#ifdef TARGET_WORDS_BIGENDIAN
a4193c8a FB	72	res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
a4193c8a FB	73	res \|= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
b92e5a22	74	#else
a4193c8a FB	75	res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
a4193c8a FB	76	res \|= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
b92e5a22 FB	77	#endif
b92e5a22 FB	78	#endif /* SHIFT > 2 */
f1c85677 FB	79	#ifdef USE_KQEMU
	80	env->last_io_time = cpu_get_time_fast();
	81	#endif
b92e5a22 FB	82	return res;
	83	}
	84
b92e5a22	85	/* handle all cases except unaligned access which span two pages */
d656469f FB	86	DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
d656469f FB	87	int mmu_idx)
b92e5a22 FB	88	{
b92e5a22 FB	89	DATA_TYPE res;
61382a50	90	int index;
c27004ec	91	target_ulong tlb_addr;
0f459d16	92	target_phys_addr_t addend;
b92e5a22	93	void *retaddr;
3b46e624	94
b92e5a22 FB	95	/* test if there is match for unaligned or IO access */
b92e5a22 FB	96	/* XXX: could done more in memory macro in a non portable way */
b92e5a22 FB	97	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	98	redo:
6ebbf390	99	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	100	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	101	if (tlb_addr & ~TARGET_PAGE_MASK) {
	102	/* IO access */
	103	if ((addr & (DATA_SIZE - 1)) != 0)
	104	goto do_unaligned_access;
2e70f6ef	105	retaddr = GETPC();
0f459d16	106	addend = env->iotlb[mmu_idx][index];
2e70f6ef	107	res = glue(io_read, SUFFIX)(addend, addr, retaddr);
98699967	108	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	109	/* slow unaligned access (it spans two pages or IO) */
b92e5a22 FB	110	do_unaligned_access:
61382a50	111	retaddr = GETPC();
a64d4718	112	#ifdef ALIGNED_ONLY
6ebbf390	113	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	114	#endif
5fafdf24	115	res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
6ebbf390	116	mmu_idx, retaddr);
b92e5a22	117	} else {
a64d4718 FB	118	/* unaligned/aligned access in the same page */
	119	#ifdef ALIGNED_ONLY
	120	if ((addr & (DATA_SIZE - 1)) != 0) {
	121	retaddr = GETPC();
6ebbf390	122	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718 FB	123	}
a64d4718 FB	124	#endif
0f459d16 PB	125	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	126	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
b92e5a22 FB	127	}
	128	} else {
	129	/* the page is not in the TLB : fill it */
61382a50	130	retaddr = GETPC();
a64d4718 FB	131	#ifdef ALIGNED_ONLY
a64d4718 FB	132	if ((addr & (DATA_SIZE - 1)) != 0)
6ebbf390	133	do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718	134	#endif
6ebbf390	135	tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	136	goto redo;
	137	}
	138	return res;
	139	}
	140
	141	/* handle all unaligned cases */
5fafdf24	142	static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390	143	int mmu_idx,
61382a50	144	void *retaddr)
b92e5a22 FB	145	{
b92e5a22 FB	146	DATA_TYPE res, res1, res2;
61382a50	147	int index, shift;
0f459d16	148	target_phys_addr_t addend;
c27004ec	149	target_ulong tlb_addr, addr1, addr2;
b92e5a22	150
b92e5a22 FB	151	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	152	redo:
6ebbf390	153	tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22	154	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	155	if (tlb_addr & ~TARGET_PAGE_MASK) {
	156	/* IO access */
	157	if ((addr & (DATA_SIZE - 1)) != 0)
	158	goto do_unaligned_access;
2e70f6ef	159	retaddr = GETPC();
0f459d16	160	addend = env->iotlb[mmu_idx][index];
2e70f6ef	161	res = glue(io_read, SUFFIX)(addend, addr, retaddr);
98699967	162	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	163	do_unaligned_access:
	164	/* slow unaligned access (it spans two pages) */
	165	addr1 = addr & ~(DATA_SIZE - 1);
	166	addr2 = addr1 + DATA_SIZE;
5fafdf24	167	res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
6ebbf390	168	mmu_idx, retaddr);
5fafdf24	169	res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
6ebbf390	170	mmu_idx, retaddr);
b92e5a22 FB	171	shift = (addr & (DATA_SIZE - 1)) * 8;
	172	#ifdef TARGET_WORDS_BIGENDIAN
	173	res = (res1 << shift) \| (res2 >> ((DATA_SIZE * 8) - shift));
	174	#else
	175	res = (res1 >> shift) \| (res2 << ((DATA_SIZE * 8) - shift));
	176	#endif
6986f88c	177	res = (DATA_TYPE)res;
b92e5a22 FB	178	} else {
b92e5a22 FB	179	/* unaligned/aligned access in the same page */
0f459d16 PB	180	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	181	res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
b92e5a22 FB	182	}
	183	} else {
	184	/* the page is not in the TLB : fill it */
6ebbf390	185	tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
b92e5a22 FB	186	goto redo;
	187	}
	188	return res;
	189	}
	190
b769d8fe FB	191	#ifndef SOFTMMU_CODE_ACCESS
b769d8fe FB	192
5fafdf24 TS	193	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
5fafdf24 TS	194	DATA_TYPE val,
6ebbf390	195	int mmu_idx,
b769d8fe FB	196	void *retaddr);
b769d8fe FB	197
5fafdf24	198	static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
b769d8fe	199	DATA_TYPE val,
0f459d16	200	target_ulong addr,
b769d8fe FB	201	void *retaddr)
	202	{
	203	int index;
0f459d16 PB	204	index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
0f459d16 PB	205	physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
2e70f6ef PB	206	if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
	207	&& !can_do_io(env)) {
	208	cpu_io_recompile(env, retaddr);
	209	}
b769d8fe	210
2e70f6ef PB	211	env->mem_io_vaddr = addr;
2e70f6ef PB	212	env->mem_io_pc = (unsigned long)retaddr;
b769d8fe FB	213	#if SHIFT <= 2
	214	io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
	215	#else
	216	#ifdef TARGET_WORDS_BIGENDIAN
	217	io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
	218	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
	219	#else
	220	io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
	221	io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
	222	#endif
	223	#endif /* SHIFT > 2 */
f1c85677 FB	224	#ifdef USE_KQEMU
	225	env->last_io_time = cpu_get_time_fast();
	226	#endif
b769d8fe	227	}
b92e5a22	228
d656469f FB	229	void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
	230	DATA_TYPE val,
	231	int mmu_idx)
b92e5a22	232	{
0f459d16	233	target_phys_addr_t addend;
c27004ec	234	target_ulong tlb_addr;
b92e5a22	235	void *retaddr;
61382a50	236	int index;
3b46e624	237
b92e5a22 FB	238	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	239	redo:
6ebbf390	240	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	241	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	242	if (tlb_addr & ~TARGET_PAGE_MASK) {
	243	/* IO access */
	244	if ((addr & (DATA_SIZE - 1)) != 0)
	245	goto do_unaligned_access;
d720b93d	246	retaddr = GETPC();
0f459d16 PB	247	addend = env->iotlb[mmu_idx][index];
0f459d16 PB	248	glue(io_write, SUFFIX)(addend, val, addr, retaddr);
98699967	249	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22	250	do_unaligned_access:
61382a50	251	retaddr = GETPC();
a64d4718	252	#ifdef ALIGNED_ONLY
6ebbf390	253	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718	254	#endif
5fafdf24	255	glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
6ebbf390	256	mmu_idx, retaddr);
b92e5a22 FB	257	} else {
b92e5a22 FB	258	/* aligned/unaligned access in the same page */
a64d4718 FB	259	#ifdef ALIGNED_ONLY
	260	if ((addr & (DATA_SIZE - 1)) != 0) {
	261	retaddr = GETPC();
6ebbf390	262	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718 FB	263	}
a64d4718 FB	264	#endif
0f459d16 PB	265	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	266	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
b92e5a22 FB	267	}
	268	} else {
	269	/* the page is not in the TLB : fill it */
61382a50	270	retaddr = GETPC();
a64d4718 FB	271	#ifdef ALIGNED_ONLY
a64d4718 FB	272	if ((addr & (DATA_SIZE - 1)) != 0)
6ebbf390	273	do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718	274	#endif
6ebbf390	275	tlb_fill(addr, 1, mmu_idx, retaddr);
b92e5a22 FB	276	goto redo;
	277	}
	278	}
	279
	280	/* handles all unaligned cases */
5fafdf24	281	static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50	282	DATA_TYPE val,
6ebbf390	283	int mmu_idx,
61382a50	284	void *retaddr)
b92e5a22	285	{
0f459d16	286	target_phys_addr_t addend;
c27004ec	287	target_ulong tlb_addr;
61382a50	288	int index, i;
b92e5a22	289
b92e5a22 FB	290	index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
b92e5a22 FB	291	redo:
6ebbf390	292	tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22	293	if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK \| TLB_INVALID_MASK))) {
b92e5a22 FB	294	if (tlb_addr & ~TARGET_PAGE_MASK) {
	295	/* IO access */
	296	if ((addr & (DATA_SIZE - 1)) != 0)
	297	goto do_unaligned_access;
0f459d16 PB	298	addend = env->iotlb[mmu_idx][index];
0f459d16 PB	299	glue(io_write, SUFFIX)(addend, val, addr, retaddr);
98699967	300	} else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 FB	301	do_unaligned_access:
b92e5a22 FB	302	/* XXX: not efficient, but simple */
6c41b272 AZ	303	/* Note: relies on the fact that tlb_fill() does not remove the
6c41b272 AZ	304	* previous page from the TLB cache. */
7221fa98	305	for(i = DATA_SIZE - 1; i >= 0; i--) {
b92e5a22	306	#ifdef TARGET_WORDS_BIGENDIAN
5fafdf24	307	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
6ebbf390	308	mmu_idx, retaddr);
b92e5a22	309	#else
5fafdf24	310	glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
6ebbf390	311	mmu_idx, retaddr);
b92e5a22 FB	312	#endif
	313	}
	314	} else {
	315	/* aligned/unaligned access in the same page */
0f459d16 PB	316	addend = env->tlb_table[mmu_idx][index].addend;
0f459d16 PB	317	glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
b92e5a22 FB	318	}
	319	} else {
	320	/* the page is not in the TLB : fill it */
6ebbf390	321	tlb_fill(addr, 1, mmu_idx, retaddr);
b92e5a22 FB	322	goto redo;
	323	}
	324	}
	325
b769d8fe FB	326	#endif /* !defined(SOFTMMU_CODE_ACCESS) */
	327
	328	#undef READ_ACCESS_TYPE
b92e5a22 FB	329	#undef SHIFT
	330	#undef DATA_TYPE
	331	#undef SUFFIX
61382a50	332	#undef USUFFIX
b92e5a22	333	#undef DATA_SIZE
84b7b8e7	334	#undef ADDR_READ