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CommitLineData
b92e5a22
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1/*
2 * Software MMU support
5fafdf24 3 *
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4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
8167ee88 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
b92e5a22 18 */
29e922b6
BS
19#include "qemu-timer.h"
20
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21#define DATA_SIZE (1 << SHIFT)
22
23#if DATA_SIZE == 8
24#define SUFFIX q
61382a50 25#define USUFFIX q
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26#define DATA_TYPE uint64_t
27#elif DATA_SIZE == 4
28#define SUFFIX l
61382a50 29#define USUFFIX l
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30#define DATA_TYPE uint32_t
31#elif DATA_SIZE == 2
32#define SUFFIX w
61382a50 33#define USUFFIX uw
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34#define DATA_TYPE uint16_t
35#elif DATA_SIZE == 1
36#define SUFFIX b
61382a50 37#define USUFFIX ub
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38#define DATA_TYPE uint8_t
39#else
40#error unsupported data size
41#endif
42
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43#ifdef SOFTMMU_CODE_ACCESS
44#define READ_ACCESS_TYPE 2
84b7b8e7 45#define ADDR_READ addr_code
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46#else
47#define READ_ACCESS_TYPE 0
84b7b8e7 48#define ADDR_READ addr_read
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49#endif
50
5fafdf24 51static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390 52 int mmu_idx,
61382a50 53 void *retaddr);
c227f099 54static inline DATA_TYPE glue(io_read, SUFFIX)(target_phys_addr_t physaddr,
2e70f6ef
PB
55 target_ulong addr,
56 void *retaddr)
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57{
58 DATA_TYPE res;
59 int index;
0f459d16
PB
60 index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
61 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
2e70f6ef
PB
62 env->mem_io_pc = (unsigned long)retaddr;
63 if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
64 && !can_do_io(env)) {
65 cpu_io_recompile(env, retaddr);
66 }
b92e5a22 67
db8886d3 68 env->mem_io_vaddr = addr;
b92e5a22 69#if SHIFT <= 2
a4193c8a 70 res = io_mem_read[index][SHIFT](io_mem_opaque[index], physaddr);
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71#else
72#ifdef TARGET_WORDS_BIGENDIAN
a4193c8a
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73 res = (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr) << 32;
74 res |= io_mem_read[index][2](io_mem_opaque[index], physaddr + 4);
b92e5a22 75#else
a4193c8a
FB
76 res = io_mem_read[index][2](io_mem_opaque[index], physaddr);
77 res |= (uint64_t)io_mem_read[index][2](io_mem_opaque[index], physaddr + 4) << 32;
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78#endif
79#endif /* SHIFT > 2 */
80 return res;
81}
82
b92e5a22 83/* handle all cases except unaligned access which span two pages */
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84DATA_TYPE REGPARM glue(glue(__ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
85 int mmu_idx)
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86{
87 DATA_TYPE res;
61382a50 88 int index;
c27004ec 89 target_ulong tlb_addr;
355b1943
PB
90 target_phys_addr_t ioaddr;
91 unsigned long addend;
b92e5a22 92 void *retaddr;
3b46e624 93
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94 /* test if there is match for unaligned or IO access */
95 /* XXX: could done more in memory macro in a non portable way */
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96 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
97 redo:
6ebbf390 98 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22 99 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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FB
100 if (tlb_addr & ~TARGET_PAGE_MASK) {
101 /* IO access */
102 if ((addr & (DATA_SIZE - 1)) != 0)
103 goto do_unaligned_access;
2e70f6ef 104 retaddr = GETPC();
355b1943
PB
105 ioaddr = env->iotlb[mmu_idx][index];
106 res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
98699967 107 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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108 /* slow unaligned access (it spans two pages or IO) */
109 do_unaligned_access:
61382a50 110 retaddr = GETPC();
a64d4718 111#ifdef ALIGNED_ONLY
6ebbf390 112 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718 113#endif
5fafdf24 114 res = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr,
6ebbf390 115 mmu_idx, retaddr);
b92e5a22 116 } else {
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117 /* unaligned/aligned access in the same page */
118#ifdef ALIGNED_ONLY
119 if ((addr & (DATA_SIZE - 1)) != 0) {
120 retaddr = GETPC();
6ebbf390 121 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718
FB
122 }
123#endif
0f459d16
PB
124 addend = env->tlb_table[mmu_idx][index].addend;
125 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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126 }
127 } else {
128 /* the page is not in the TLB : fill it */
61382a50 129 retaddr = GETPC();
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130#ifdef ALIGNED_ONLY
131 if ((addr & (DATA_SIZE - 1)) != 0)
6ebbf390 132 do_unaligned_access(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
a64d4718 133#endif
6ebbf390 134 tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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135 goto redo;
136 }
137 return res;
138}
139
140/* handle all unaligned cases */
5fafdf24 141static DATA_TYPE glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(target_ulong addr,
6ebbf390 142 int mmu_idx,
61382a50 143 void *retaddr)
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FB
144{
145 DATA_TYPE res, res1, res2;
61382a50 146 int index, shift;
355b1943
PB
147 target_phys_addr_t ioaddr;
148 unsigned long addend;
c27004ec 149 target_ulong tlb_addr, addr1, addr2;
b92e5a22 150
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FB
151 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
152 redo:
6ebbf390 153 tlb_addr = env->tlb_table[mmu_idx][index].ADDR_READ;
b92e5a22 154 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
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FB
155 if (tlb_addr & ~TARGET_PAGE_MASK) {
156 /* IO access */
157 if ((addr & (DATA_SIZE - 1)) != 0)
158 goto do_unaligned_access;
355b1943
PB
159 ioaddr = env->iotlb[mmu_idx][index];
160 res = glue(io_read, SUFFIX)(ioaddr, addr, retaddr);
98699967 161 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
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FB
162 do_unaligned_access:
163 /* slow unaligned access (it spans two pages) */
164 addr1 = addr & ~(DATA_SIZE - 1);
165 addr2 = addr1 + DATA_SIZE;
5fafdf24 166 res1 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr1,
6ebbf390 167 mmu_idx, retaddr);
5fafdf24 168 res2 = glue(glue(slow_ld, SUFFIX), MMUSUFFIX)(addr2,
6ebbf390 169 mmu_idx, retaddr);
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170 shift = (addr & (DATA_SIZE - 1)) * 8;
171#ifdef TARGET_WORDS_BIGENDIAN
172 res = (res1 << shift) | (res2 >> ((DATA_SIZE * 8) - shift));
173#else
174 res = (res1 >> shift) | (res2 << ((DATA_SIZE * 8) - shift));
175#endif
6986f88c 176 res = (DATA_TYPE)res;
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FB
177 } else {
178 /* unaligned/aligned access in the same page */
0f459d16
PB
179 addend = env->tlb_table[mmu_idx][index].addend;
180 res = glue(glue(ld, USUFFIX), _raw)((uint8_t *)(long)(addr+addend));
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181 }
182 } else {
183 /* the page is not in the TLB : fill it */
6ebbf390 184 tlb_fill(addr, READ_ACCESS_TYPE, mmu_idx, retaddr);
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FB
185 goto redo;
186 }
187 return res;
188}
189
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190#ifndef SOFTMMU_CODE_ACCESS
191
5fafdf24
TS
192static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
193 DATA_TYPE val,
6ebbf390 194 int mmu_idx,
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FB
195 void *retaddr);
196
c227f099 197static inline void glue(io_write, SUFFIX)(target_phys_addr_t physaddr,
b769d8fe 198 DATA_TYPE val,
0f459d16 199 target_ulong addr,
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FB
200 void *retaddr)
201{
202 int index;
0f459d16
PB
203 index = (physaddr >> IO_MEM_SHIFT) & (IO_MEM_NB_ENTRIES - 1);
204 physaddr = (physaddr & TARGET_PAGE_MASK) + addr;
2e70f6ef
PB
205 if (index > (IO_MEM_NOTDIRTY >> IO_MEM_SHIFT)
206 && !can_do_io(env)) {
207 cpu_io_recompile(env, retaddr);
208 }
b769d8fe 209
2e70f6ef
PB
210 env->mem_io_vaddr = addr;
211 env->mem_io_pc = (unsigned long)retaddr;
b769d8fe
FB
212#if SHIFT <= 2
213 io_mem_write[index][SHIFT](io_mem_opaque[index], physaddr, val);
214#else
215#ifdef TARGET_WORDS_BIGENDIAN
216 io_mem_write[index][2](io_mem_opaque[index], physaddr, val >> 32);
217 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val);
218#else
219 io_mem_write[index][2](io_mem_opaque[index], physaddr, val);
220 io_mem_write[index][2](io_mem_opaque[index], physaddr + 4, val >> 32);
221#endif
222#endif /* SHIFT > 2 */
223}
b92e5a22 224
d656469f
FB
225void REGPARM glue(glue(__st, SUFFIX), MMUSUFFIX)(target_ulong addr,
226 DATA_TYPE val,
227 int mmu_idx)
b92e5a22 228{
355b1943
PB
229 target_phys_addr_t ioaddr;
230 unsigned long addend;
c27004ec 231 target_ulong tlb_addr;
b92e5a22 232 void *retaddr;
61382a50 233 int index;
3b46e624 234
b92e5a22
FB
235 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
236 redo:
6ebbf390 237 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22 238 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
b92e5a22
FB
239 if (tlb_addr & ~TARGET_PAGE_MASK) {
240 /* IO access */
241 if ((addr & (DATA_SIZE - 1)) != 0)
242 goto do_unaligned_access;
d720b93d 243 retaddr = GETPC();
355b1943
PB
244 ioaddr = env->iotlb[mmu_idx][index];
245 glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
98699967 246 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22 247 do_unaligned_access:
61382a50 248 retaddr = GETPC();
a64d4718 249#ifdef ALIGNED_ONLY
6ebbf390 250 do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718 251#endif
5fafdf24 252 glue(glue(slow_st, SUFFIX), MMUSUFFIX)(addr, val,
6ebbf390 253 mmu_idx, retaddr);
b92e5a22
FB
254 } else {
255 /* aligned/unaligned access in the same page */
a64d4718
FB
256#ifdef ALIGNED_ONLY
257 if ((addr & (DATA_SIZE - 1)) != 0) {
258 retaddr = GETPC();
6ebbf390 259 do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718
FB
260 }
261#endif
0f459d16
PB
262 addend = env->tlb_table[mmu_idx][index].addend;
263 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
b92e5a22
FB
264 }
265 } else {
266 /* the page is not in the TLB : fill it */
61382a50 267 retaddr = GETPC();
a64d4718
FB
268#ifdef ALIGNED_ONLY
269 if ((addr & (DATA_SIZE - 1)) != 0)
6ebbf390 270 do_unaligned_access(addr, 1, mmu_idx, retaddr);
a64d4718 271#endif
6ebbf390 272 tlb_fill(addr, 1, mmu_idx, retaddr);
b92e5a22
FB
273 goto redo;
274 }
275}
276
277/* handles all unaligned cases */
5fafdf24 278static void glue(glue(slow_st, SUFFIX), MMUSUFFIX)(target_ulong addr,
61382a50 279 DATA_TYPE val,
6ebbf390 280 int mmu_idx,
61382a50 281 void *retaddr)
b92e5a22 282{
355b1943
PB
283 target_phys_addr_t ioaddr;
284 unsigned long addend;
c27004ec 285 target_ulong tlb_addr;
61382a50 286 int index, i;
b92e5a22 287
b92e5a22
FB
288 index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
289 redo:
6ebbf390 290 tlb_addr = env->tlb_table[mmu_idx][index].addr_write;
b92e5a22 291 if ((addr & TARGET_PAGE_MASK) == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) {
b92e5a22
FB
292 if (tlb_addr & ~TARGET_PAGE_MASK) {
293 /* IO access */
294 if ((addr & (DATA_SIZE - 1)) != 0)
295 goto do_unaligned_access;
355b1943
PB
296 ioaddr = env->iotlb[mmu_idx][index];
297 glue(io_write, SUFFIX)(ioaddr, val, addr, retaddr);
98699967 298 } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) {
b92e5a22
FB
299 do_unaligned_access:
300 /* XXX: not efficient, but simple */
6c41b272
AZ
301 /* Note: relies on the fact that tlb_fill() does not remove the
302 * previous page from the TLB cache. */
7221fa98 303 for(i = DATA_SIZE - 1; i >= 0; i--) {
b92e5a22 304#ifdef TARGET_WORDS_BIGENDIAN
5fafdf24 305 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (((DATA_SIZE - 1) * 8) - (i * 8)),
6ebbf390 306 mmu_idx, retaddr);
b92e5a22 307#else
5fafdf24 308 glue(slow_stb, MMUSUFFIX)(addr + i, val >> (i * 8),
6ebbf390 309 mmu_idx, retaddr);
b92e5a22
FB
310#endif
311 }
312 } else {
313 /* aligned/unaligned access in the same page */
0f459d16
PB
314 addend = env->tlb_table[mmu_idx][index].addend;
315 glue(glue(st, SUFFIX), _raw)((uint8_t *)(long)(addr+addend), val);
b92e5a22
FB
316 }
317 } else {
318 /* the page is not in the TLB : fill it */
6ebbf390 319 tlb_fill(addr, 1, mmu_idx, retaddr);
b92e5a22
FB
320 goto redo;
321 }
322}
323
b769d8fe
FB
324#endif /* !defined(SOFTMMU_CODE_ACCESS) */
325
326#undef READ_ACCESS_TYPE
b92e5a22
FB
327#undef SHIFT
328#undef DATA_TYPE
329#undef SUFFIX
61382a50 330#undef USUFFIX
b92e5a22 331#undef DATA_SIZE
84b7b8e7 332#undef ADDR_READ