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d4abd567
BS		 1/*
2 * These files from binutils are concatenated:
3 * include/opcode/sparc.h, opcodes/sparc-opc.c, opcodes/sparc-dis.c
4 */
5
6/* include/opcode/sparc.h */
7
46f42f29
BS		 8/* Definitions for opcode table for the sparc.
9 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 2000, 2002,
10 2003, 2005 Free Software Foundation, Inc.
11
12 This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
13 the GNU Binutils.
14
15 GAS/GDB is free software; you can redistribute it and/or modify
16 it under the terms of the GNU General Public License as published by
17 the Free Software Foundation; either version 2, or (at your option)
18 any later version.
aa0aa4fa 19
46f42f29
BS		 20 GAS/GDB is distributed in the hope that it will be useful,
21 but WITHOUT ANY WARRANTY; without even the implied warranty of
22 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 GNU General Public License for more details.
aa0aa4fa 24
46f42f29
BS		 25 You should have received a copy of the GNU General Public License
26 along with GAS or GDB; see the file COPYING. If not, write to
27 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
28 Boston, MA 02110-1301, USA. */
aa0aa4fa 29
aa0aa4fa
FB		 30#include <stdlib.h>
31#include "dis-asm.h"
32
33/* The SPARC opcode table (and other related data) is defined in
34 the opcodes library in sparc-opc.c. If you change anything here, make
35 sure you fix up that file, and vice versa. */
36
37 /* FIXME-someday: perhaps the ,a's and such should be embedded in the
38 instruction's name rather than the args. This would make gas faster, pinsn
39 slower, but would mess up some macros a bit. xoxorich. */
40
41/* List of instruction sets variations.
42 These values are such that each element is either a superset of a
43 preceding each one or they conflict in which case SPARC_OPCODE_CONFLICT_P
44 returns non-zero.
45 The values are indices into `sparc_opcode_archs' defined in sparc-opc.c.
46 Don't change this without updating sparc-opc.c. */
47
46f42f29
BS		 48enum sparc_opcode_arch_val
49{
aa0aa4fa
FB		 50 SPARC_OPCODE_ARCH_V6 = 0,
51 SPARC_OPCODE_ARCH_V7,
52 SPARC_OPCODE_ARCH_V8,
53 SPARC_OPCODE_ARCH_SPARCLET,
54 SPARC_OPCODE_ARCH_SPARCLITE,
46f42f29 55 /* V9 variants must appear last. */
aa0aa4fa 56 SPARC_OPCODE_ARCH_V9,
46f42f29
BS		 57 SPARC_OPCODE_ARCH_V9A, /* V9 with ultrasparc additions. */
58 SPARC_OPCODE_ARCH_V9B, /* V9 with ultrasparc and cheetah additions. */
59 SPARC_OPCODE_ARCH_BAD /* Error return from sparc_opcode_lookup_arch. */
aa0aa4fa
FB		 60};
61
62/* The highest architecture in the table. */
63#define SPARC_OPCODE_ARCH_MAX (SPARC_OPCODE_ARCH_BAD - 1)
64
65/* Given an enum sparc_opcode_arch_val, return the bitmask to use in
66 insn encoding/decoding. */
67#define SPARC_OPCODE_ARCH_MASK(arch) (1 << (arch))
68
69/* Given a valid sparc_opcode_arch_val, return non-zero if it's v9. */
70#define SPARC_OPCODE_ARCH_V9_P(arch) ((arch) >= SPARC_OPCODE_ARCH_V9)
71
72/* Table of cpu variants. */
73
46f42f29
BS		 74typedef struct sparc_opcode_arch
75{
aa0aa4fa
FB		 76 const char *name;
77 /* Mask of sparc_opcode_arch_val's supported.
78 EG: For v7 this would be
79 (SPARC_OPCODE_ARCH_MASK (..._V6) | SPARC_OPCODE_ARCH_MASK (..._V7)).
80 These are short's because sparc_opcode.architecture is. */
81 short supported;
46f42f29 82} sparc_opcode_arch;
aa0aa4fa 83
f82a3d48 84static const struct sparc_opcode_arch sparc_opcode_archs[];
aa0aa4fa 85
aa0aa4fa
FB		 86/* Return the bitmask of supported architectures for ARCH. */
87#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
88
89/* Non-zero if ARCH1 conflicts with ARCH2.
90 IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
91#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
46f42f29
BS		 92 (((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
93 != SPARC_OPCODE_SUPPORTED (ARCH1)) \
94 && ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
aa0aa4fa
FB		 95 != SPARC_OPCODE_SUPPORTED (ARCH2)))
96
97/* Structure of an opcode table entry. */
98
46f42f29
BS		 99typedef struct sparc_opcode
100{
aa0aa4fa 101 const char *name;
46f42f29
BS		 102 unsigned long match; /* Bits that must be set. */
103 unsigned long lose; /* Bits that must not be set. */
aa0aa4fa 104 const char *args;
46f42f29 105 /* This was called "delayed" in versions before the flags. */
aa0aa4fa 106 char flags;
f930d07e 107 short architecture; /* Bitmask of sparc_opcode_arch_val's. */
46f42f29
BS		 108} sparc_opcode;
109
110#define F_DELAYED 1 /* Delayed branch. */
111#define F_ALIAS 2 /* Alias for a "real" instruction. */
112#define F_UNBR 4 /* Unconditional branch. */
113#define F_CONDBR 8 /* Conditional branch. */
114#define F_JSR 16 /* Subroutine call. */
115#define F_FLOAT 32 /* Floating point instruction (not a branch). */
116#define F_FBR 64 /* Floating point branch. */
aa0aa4fa
FB		 117/* FIXME: Add F_ANACHRONISTIC flag for v9. */
118
46f42f29
BS		 119/* All sparc opcodes are 32 bits, except for the `set' instruction (really a
120 macro), which is 64 bits. It is handled as a special case.
aa0aa4fa 121
46f42f29
BS		 122 The match component is a mask saying which bits must match a particular
123 opcode in order for an instruction to be an instance of that opcode.
aa0aa4fa 124
46f42f29
BS		 125 The args component is a string containing one character for each operand of the
126 instruction.
aa0aa4fa 127
46f42f29 128 Kinds of operands:
f930d07e
BS		 129 # Number used by optimizer. It is ignored.
130 1 rs1 register.
131 2 rs2 register.
132 d rd register.
133 e frs1 floating point register.
134 v frs1 floating point register (double/even).
135 V frs1 floating point register (quad/multiple of 4).
136 f frs2 floating point register.
137 B frs2 floating point register (double/even).
138 R frs2 floating point register (quad/multiple of 4).
139 g frsd floating point register.
140 H frsd floating point register (double/even).
141 J frsd floating point register (quad/multiple of 4).
142 b crs1 coprocessor register
143 c crs2 coprocessor register
144 D crsd coprocessor register
145 m alternate space register (asr) in rd
146 M alternate space register (asr) in rs1
147 h 22 high bits.
148 X 5 bit unsigned immediate
149 Y 6 bit unsigned immediate
150 3 SIAM mode (3 bits). (v9b)
151 K MEMBAR mask (7 bits). (v9)
152 j 10 bit Immediate. (v9)
153 I 11 bit Immediate. (v9)
154 i 13 bit Immediate.
155 n 22 bit immediate.
156 k 2+14 bit PC relative immediate. (v9)
157 G 19 bit PC relative immediate. (v9)
158 l 22 bit PC relative immediate.
159 L 30 bit PC relative immediate.
160 a Annul. The annul bit is set.
161 A Alternate address space. Stored as 8 bits.
162 C Coprocessor state register.
163 F floating point state register.
164 p Processor state register.
165 N Branch predict clear ",pn" (v9)
166 T Branch predict set ",pt" (v9)
167 z %icc. (v9)
168 Z %xcc. (v9)
169 q Floating point queue.
170 r Single register that is both rs1 and rd.
171 O Single register that is both rs2 and rd.
172 Q Coprocessor queue.
173 S Special case.
174 t Trap base register.
175 w Window invalid mask register.
176 y Y register.
177 u sparclet coprocessor registers in rd position
178 U sparclet coprocessor registers in rs1 position
179 E %ccr. (v9)
180 s %fprs. (v9)
181 P %pc. (v9)
182 W %tick. (v9)
183 o %asi. (v9)
184 6 %fcc0. (v9)
185 7 %fcc1. (v9)
186 8 %fcc2. (v9)
187 9 %fcc3. (v9)
188 ! Privileged Register in rd (v9)
189 ? Privileged Register in rs1 (v9)
190 * Prefetch function constant. (v9)
191 x OPF field (v9 impdep).
192 0 32/64 bit immediate for set or setx (v9) insns
193 _ Ancillary state register in rd (v9a)
194 / Ancillary state register in rs1 (v9a)
aa0aa4fa 195
46f42f29
BS		 196 The following chars are unused: (note: ,[] are used as punctuation)
197 [45]. */
198
199#define OP2(x) (((x) & 0x7) << 22) /* Op2 field of format2 insns. */
200#define OP3(x) (((x) & 0x3f) << 19) /* Op3 field of format3 insns. */
201#define OP(x) ((unsigned) ((x) & 0x3) << 30) /* Op field of all insns. */
202#define OPF(x) (((x) & 0x1ff) << 5) /* Opf field of float insns. */
203#define OPF_LOW5(x) OPF ((x) & 0x1f) /* V9. */
204#define F3F(x, y, z) (OP (x) | OP3 (y) | OPF (z)) /* Format3 float insns. */
205#define F3I(x) (((x) & 0x1) << 13) /* Immediate field of format 3 insns. */
206#define F2(x, y) (OP (x) | OP2(y)) /* Format 2 insns. */
207#define F3(x, y, z) (OP (x) | OP3(y) | F3I(z)) /* Format3 insns. */
208#define F1(x) (OP (x))
209#define DISP30(x) ((x) & 0x3fffffff)
210#define ASI(x) (((x) & 0xff) << 5) /* Asi field of format3 insns. */
211#define RS2(x) ((x) & 0x1f) /* Rs2 field. */
212#define SIMM13(x) ((x) & 0x1fff) /* Simm13 field. */
213#define RD(x) (((x) & 0x1f) << 25) /* Destination register field. */
214#define RS1(x) (((x) & 0x1f) << 14) /* Rs1 field. */
215#define ASI_RS2(x) (SIMM13 (x))
216#define MEMBAR(x) ((x) & 0x7f)
217#define SLCPOP(x) (((x) & 0x7f) << 6) /* Sparclet cpop. */
218
219#define ANNUL (1 << 29)
220#define BPRED (1 << 19) /* V9. */
221#define IMMED F3I (1)
222#define RD_G0 RD (~0)
223#define RS1_G0 RS1 (~0)
224#define RS2_G0 RS2 (~0)
aa0aa4fa 225
f82a3d48 226static const struct sparc_opcode sparc_opcodes[];
aa0aa4fa 227
46f42f29
BS		 228static const char *sparc_decode_asi_v8 (int);
229static const char *sparc_decode_asi_v9 (int);
230static const char *sparc_decode_membar (int);
231static const char *sparc_decode_prefetch (int);
232static const char *sparc_decode_sparclet_cpreg (int);
233
234/* Local Variables:
235 fill-column: 131
236 comment-column: 0
237 End: */
aa0aa4fa 238
d4abd567
BS		 239/* opcodes/sparc-opc.c */
240
46f42f29
BS		 241/* Table of opcodes for the sparc.
242 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
243 2000, 2002, 2004, 2005
244 Free Software Foundation, Inc.
245
246 This file is part of the BFD library.
247
248 BFD is free software; you can redistribute it and/or modify it under
249 the terms of the GNU General Public License as published by the Free
250 Software Foundation; either version 2, or (at your option) any later
251 version.
252
253 BFD is distributed in the hope that it will be useful, but WITHOUT ANY
254 WARRANTY; without even the implied warranty of MERCHANTABILITY or
255 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
256 for more details.
257
258 You should have received a copy of the GNU General Public License
259 along with this software; see the file COPYING. If not, write to
260 the Free Software Foundation, 51 Franklin Street - Fifth Floor,
261 Boston, MA 02110-1301, USA. */
262
263/* FIXME-someday: perhaps the ,a's and such should be embedded in the
264 instruction's name rather than the args. This would make gas faster, pinsn
265 slower, but would mess up some macros a bit. xoxorich. */
266
aa0aa4fa 267/* Some defines to make life easy. */
f930d07e
BS		 268#define MASK_V6 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V6)
269#define MASK_V7 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V7)
270#define MASK_V8 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8)
271#define MASK_SPARCLET SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET)
272#define MASK_SPARCLITE SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
273#define MASK_V9 SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9)
274#define MASK_V9A SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A)
275#define MASK_V9B SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B)
aa0aa4fa
FB		 276
277/* Bit masks of architectures supporting the insn. */
278
f930d07e
BS		 279#define v6 (MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET \
280 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
46f42f29 281/* v6 insns not supported on the sparclet. */
f930d07e
BS		 282#define v6notlet (MASK_V6 | MASK_V7 | MASK_V8 \
283 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
284#define v7 (MASK_V7 | MASK_V8 | MASK_SPARCLET \
285 | MASK_SPARCLITE | MASK_V9 | MASK_V9A | MASK_V9B)
aa0aa4fa
FB		 286/* Although not all insns are implemented in hardware, sparclite is defined
287 to be a superset of v8. Unimplemented insns trap and are then theoretically
288 implemented in software.
289 It's not clear that the same is true for sparclet, although the docs
290 suggest it is. Rather than complicating things, the sparclet assembler
291 recognizes all v8 insns. */
f930d07e
BS		 292#define v8 (MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE \
293 | MASK_V9 | MASK_V9A | MASK_V9B)
294#define sparclet (MASK_SPARCLET)
295#define sparclite (MASK_SPARCLITE)
296#define v9 (MASK_V9 | MASK_V9A | MASK_V9B)
297#define v9a (MASK_V9A | MASK_V9B)
298#define v9b (MASK_V9B)
46f42f29 299/* v6 insns not supported by v9. */
f930d07e
BS		 300#define v6notv9 (MASK_V6 | MASK_V7 | MASK_V8 \
301 | MASK_SPARCLET | MASK_SPARCLITE)
aa0aa4fa 302/* v9a instructions which would appear to be aliases to v9's impdep's
46f42f29 303 otherwise. */
f930d07e 304#define v9notv9a (MASK_V9)
aa0aa4fa
FB		 305
306/* Table of opcode architectures.
307 The order is defined in opcode/sparc.h. */
308
46f42f29
BS		 309static const struct sparc_opcode_arch sparc_opcode_archs[] =
310{
aa0aa4fa
FB		 311 { "v6", MASK_V6 },
312 { "v7", MASK_V6 | MASK_V7 },
313 { "v8", MASK_V6 | MASK_V7 | MASK_V8 },
314 { "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
315 { "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
7f75ffd3 316 /* ??? Don't some v8 privileged insns conflict with v9? */
aa0aa4fa
FB		 317 { "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
318 /* v9 with ultrasparc additions */
319 { "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
320 /* v9 with cheetah additions */
321 { "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
322 { NULL, 0 }
323};
324
aa0aa4fa 325/* Branch condition field. */
46f42f29 326#define COND(x) (((x) & 0xf) << 25)
aa0aa4fa
FB		 327
328/* v9: Move (MOVcc and FMOVcc) condition field. */
46f42f29 329#define MCOND(x,i_or_f) ((((i_or_f) & 1) << 18) | (((x) >> 11) & (0xf << 14))) /* v9 */
aa0aa4fa
FB		 330
331/* v9: Move register (MOVRcc and FMOVRcc) condition field. */
46f42f29
BS		 332#define RCOND(x) (((x) & 0x7) << 10) /* v9 */
333
334#define CONDA (COND (0x8))
335#define CONDCC (COND (0xd))
336#define CONDCS (COND (0x5))
337#define CONDE (COND (0x1))
338#define CONDG (COND (0xa))
339#define CONDGE (COND (0xb))
340#define CONDGU (COND (0xc))
341#define CONDL (COND (0x3))
342#define CONDLE (COND (0x2))
343#define CONDLEU (COND (0x4))
344#define CONDN (COND (0x0))
345#define CONDNE (COND (0x9))
346#define CONDNEG (COND (0x6))
347#define CONDPOS (COND (0xe))
348#define CONDVC (COND (0xf))
349#define CONDVS (COND (0x7))
f930d07e
BS		 350
351#define CONDNZ CONDNE
352#define CONDZ CONDE
353#define CONDGEU CONDCC
354#define CONDLU CONDCS
355
46f42f29
BS		 356#define FCONDA (COND (0x8))
357#define FCONDE (COND (0x9))
358#define FCONDG (COND (0x6))
359#define FCONDGE (COND (0xb))
360#define FCONDL (COND (0x4))
361#define FCONDLE (COND (0xd))
362#define FCONDLG (COND (0x2))
363#define FCONDN (COND (0x0))
364#define FCONDNE (COND (0x1))
365#define FCONDO (COND (0xf))
366#define FCONDU (COND (0x7))
367#define FCONDUE (COND (0xa))
368#define FCONDUG (COND (0x5))
369#define FCONDUGE (COND (0xc))
370#define FCONDUL (COND (0x3))
371#define FCONDULE (COND (0xe))
f930d07e
BS		 372
373#define FCONDNZ FCONDNE
374#define FCONDZ FCONDE
375
46f42f29
BS		 376#define ICC (0) /* v9 */
377#define XCC (1 << 12) /* v9 */
378#define FCC(x) (((x) & 0x3) << 11) /* v9 */
379#define FBFCC(x) (((x) & 0x3) << 20) /* v9 */
aa0aa4fa
FB		 380\f
381/* The order of the opcodes in the table is significant:
5fafdf24 382
f930d07e
BS		 383 * The assembler requires that all instances of the same mnemonic must
384 be consecutive. If they aren't, the assembler will bomb at runtime.
aa0aa4fa 385
46f42f29 386 * The disassembler should not care about the order of the opcodes. */
aa0aa4fa
FB		 387
388/* Entries for commutative arithmetic operations. */
389/* ??? More entries can make use of this. */
390#define COMMUTEOP(opcode, op3, arch_mask) \
f930d07e
BS		 391{ opcode, F3(2, op3, 0), F3(~2, ~op3, ~0)|ASI(~0), "1,2,d", 0, arch_mask }, \
392{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "1,i,d", 0, arch_mask }, \
393{ opcode, F3(2, op3, 1), F3(~2, ~op3, ~1), "i,1,d", 0, arch_mask }
aa0aa4fa 394
f82a3d48 395static const struct sparc_opcode sparc_opcodes[] = {
aa0aa4fa 396
f930d07e
BS		 397{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", 0, v6 },
398{ "ld", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", 0, v6 }, /* ld [rs1+%g0],d */
399{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", 0, v6 },
400{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", 0, v6 },
401{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", 0, v6 },
402{ "ld", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ld [rs1+0],d */
403{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0), "[1+2],g", 0, v6 },
404{ "ld", F3(3, 0x20, 0), F3(~3, ~0x20, ~0)|RS2_G0, "[1],g", 0, v6 }, /* ld [rs1+%g0],d */
405{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[1+i],g", 0, v6 },
406{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1), "[i+1],g", 0, v6 },
407{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|RS1_G0, "[i],g", 0, v6 },
408{ "ld", F3(3, 0x20, 1), F3(~3, ~0x20, ~1)|SIMM13(~0), "[1],g", 0, v6 }, /* ld [rs1+0],d */
409
410{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RD(~0), "[1+2],F", 0, v6 },
411{ "ld", F3(3, 0x21, 0), F3(~3, ~0x21, ~0)|RS2_G0|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+%g0],d */
412{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[1+i],F", 0, v6 },
413{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RD(~0), "[i+1],F", 0, v6 },
414{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~0),"[i],F", 0, v6 },
415{ "ld", F3(3, 0x21, 1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~0),"[1],F", 0, v6 }, /* ld [rs1+0],d */
416
417{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2],D", 0, v6notv9 },
418{ "ld", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1],D", 0, v6notv9 }, /* ld [rs1+%g0],d */
419{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i],D", 0, v6notv9 },
420{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1],D", 0, v6notv9 },
421{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i],D", 0, v6notv9 },
422{ "ld", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ld [rs1+0],d */
423{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0), "[1+2],C", 0, v6notv9 },
424{ "ld", F3(3, 0x31, 0), F3(~3, ~0x31, ~0)|RS2_G0, "[1],C", 0, v6notv9 }, /* ld [rs1+%g0],d */
425{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[1+i],C", 0, v6notv9 },
426{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1), "[i+1],C", 0, v6notv9 },
427{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|RS1_G0, "[i],C", 0, v6notv9 },
428{ "ld", F3(3, 0x31, 1), F3(~3, ~0x31, ~1)|SIMM13(~0), "[1],C", 0, v6notv9 }, /* ld [rs1+0],d */
aa0aa4fa
FB		 429
430/* The v9 LDUW is the same as the old 'ld' opcode, it is not the same as the
431 'ld' pseudo-op in v9. */
f930d07e
BS		 432{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0), "[1+2],d", F_ALIAS, v9 },
433{ "lduw", F3(3, 0x00, 0), F3(~3, ~0x00, ~0)|RS2_G0, "[1],d", F_ALIAS, v9 }, /* ld [rs1+%g0],d */
434{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[1+i],d", F_ALIAS, v9 },
435{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1), "[i+1],d", F_ALIAS, v9 },
436{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|RS1_G0, "[i],d", F_ALIAS, v9 },
437{ "lduw", F3(3, 0x00, 1), F3(~3, ~0x00, ~1)|SIMM13(~0), "[1],d", F_ALIAS, v9 }, /* ld [rs1+0],d */
438
439{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI(~0), "[1+2],d", 0, v6 },
440{ "ldd", F3(3, 0x03, 0), F3(~3, ~0x03, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldd [rs1+%g0],d */
441{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[1+i],d", 0, v6 },
442{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1), "[i+1],d", 0, v6 },
443{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|RS1_G0, "[i],d", 0, v6 },
444{ "ldd", F3(3, 0x03, 1), F3(~3, ~0x03, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldd [rs1+0],d */
445{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI(~0), "[1+2],H", 0, v6 },
446{ "ldd", F3(3, 0x23, 0), F3(~3, ~0x23, ~0)|ASI_RS2(~0), "[1],H", 0, v6 }, /* ldd [rs1+%g0],d */
447{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[1+i],H", 0, v6 },
448{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1), "[i+1],H", 0, v6 },
449{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|RS1_G0, "[i],H", 0, v6 },
450{ "ldd", F3(3, 0x23, 1), F3(~3, ~0x23, ~1)|SIMM13(~0), "[1],H", 0, v6 }, /* ldd [rs1+0],d */
451
452{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI(~0), "[1+2],D", 0, v6notv9 },
453{ "ldd", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|ASI_RS2(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+%g0],d */
454{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i],D", 0, v6notv9 },
455{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1],D", 0, v6notv9 },
456{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i],D", 0, v6notv9 },
457{ "ldd", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1],D", 0, v6notv9 }, /* ldd [rs1+0],d */
458
459{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI(~0), "[1+2],J", 0, v9 },
460{ "ldq", F3(3, 0x22, 0), F3(~3, ~0x22, ~0)|ASI_RS2(~0), "[1],J", 0, v9 }, /* ldd [rs1+%g0],d */
461{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[1+i],J", 0, v9 },
462{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1), "[i+1],J", 0, v9 },
463{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|RS1_G0, "[i],J", 0, v9 },
464{ "ldq", F3(3, 0x22, 1), F3(~3, ~0x22, ~1)|SIMM13(~0), "[1],J", 0, v9 }, /* ldd [rs1+0],d */
465
466{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI(~0), "[1+2],d", 0, v6 },
467{ "ldsb", F3(3, 0x09, 0), F3(~3, ~0x09, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsb [rs1+%g0],d */
468{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[1+i],d", 0, v6 },
469{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1), "[i+1],d", 0, v6 },
470{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|RS1_G0, "[i],d", 0, v6 },
471{ "ldsb", F3(3, 0x09, 1), F3(~3, ~0x09, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsb [rs1+0],d */
472
473{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldsh [rs1+%g0],d */
474{ "ldsh", F3(3, 0x0a, 0), F3(~3, ~0x0a, ~0)|ASI(~0), "[1+2],d", 0, v6 },
475{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[1+i],d", 0, v6 },
476{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1), "[i+1],d", 0, v6 },
477{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|RS1_G0, "[i],d", 0, v6 },
478{ "ldsh", F3(3, 0x0a, 1), F3(~3, ~0x0a, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldsh [rs1+0],d */
479
480{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI(~0), "[1+2],d", 0, v6 },
481{ "ldstub", F3(3, 0x0d, 0), F3(~3, ~0x0d, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldstub [rs1+%g0],d */
482{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[1+i],d", 0, v6 },
483{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1), "[i+1],d", 0, v6 },
484{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|RS1_G0, "[i],d", 0, v6 },
485{ "ldstub", F3(3, 0x0d, 1), F3(~3, ~0x0d, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldstub [rs1+0],d */
486
487{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI(~0), "[1+2],d", 0, v9 },
488{ "ldsw", F3(3, 0x08, 0), F3(~3, ~0x08, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldsw [rs1+%g0],d */
489{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[1+i],d", 0, v9 },
490{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1), "[i+1],d", 0, v9 },
491{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|RS1_G0, "[i],d", 0, v9 },
492{ "ldsw", F3(3, 0x08, 1), F3(~3, ~0x08, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldsw [rs1+0],d */
493
494{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI(~0), "[1+2],d", 0, v6 },
495{ "ldub", F3(3, 0x01, 0), F3(~3, ~0x01, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* ldub [rs1+%g0],d */
496{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[1+i],d", 0, v6 },
497{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1), "[i+1],d", 0, v6 },
498{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|RS1_G0, "[i],d", 0, v6 },
499{ "ldub", F3(3, 0x01, 1), F3(~3, ~0x01, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* ldub [rs1+0],d */
500
501{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI(~0), "[1+2],d", 0, v6 },
502{ "lduh", F3(3, 0x02, 0), F3(~3, ~0x02, ~0)|ASI_RS2(~0), "[1],d", 0, v6 }, /* lduh [rs1+%g0],d */
503{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[1+i],d", 0, v6 },
504{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1), "[i+1],d", 0, v6 },
505{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|RS1_G0, "[i],d", 0, v6 },
506{ "lduh", F3(3, 0x02, 1), F3(~3, ~0x02, ~1)|SIMM13(~0), "[1],d", 0, v6 }, /* lduh [rs1+0],d */
507
508{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI(~0), "[1+2],d", 0, v9 },
509{ "ldx", F3(3, 0x0b, 0), F3(~3, ~0x0b, ~0)|ASI_RS2(~0), "[1],d", 0, v9 }, /* ldx [rs1+%g0],d */
510{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[1+i],d", 0, v9 },
511{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1), "[i+1],d", 0, v9 },
512{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|RS1_G0, "[i],d", 0, v9 },
513{ "ldx", F3(3, 0x0b, 1), F3(~3, ~0x0b, ~1)|SIMM13(~0), "[1],d", 0, v9 }, /* ldx [rs1+0],d */
514
515{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RD(~1), "[1+2],F", 0, v9 },
516{ "ldx", F3(3, 0x21, 0)|RD(1), F3(~3, ~0x21, ~0)|RS2_G0|RD(~1), "[1],F", 0, v9 }, /* ld [rs1+%g0],d */
517{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[1+i],F", 0, v9 },
518{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RD(~1), "[i+1],F", 0, v9 },
519{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|RS1_G0|RD(~1), "[i],F", 0, v9 },
520{ "ldx", F3(3, 0x21, 1)|RD(1), F3(~3, ~0x21, ~1)|SIMM13(~0)|RD(~1),"[1],F", 0, v9 }, /* ld [rs1+0],d */
521
522{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", 0, v6 },
523{ "lda", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lda [rs1+%g0],d */
524{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", 0, v9 },
525{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", 0, v9 },
526{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", 0, v9 },
527{ "lda", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
528{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0), "[1+2]A,g", 0, v9 },
529{ "lda", F3(3, 0x30, 0), F3(~3, ~0x30, ~0)|RS2_G0, "[1]A,g", 0, v9 }, /* lda [rs1+%g0],d */
530{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[1+i]o,g", 0, v9 },
531{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1), "[i+1]o,g", 0, v9 },
532{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|RS1_G0, "[i]o,g", 0, v9 },
533{ "lda", F3(3, 0x30, 1), F3(~3, ~0x30, ~1)|SIMM13(~0), "[1]o,g", 0, v9 }, /* ld [rs1+0],d */
534
535{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0), "[1+2]A,d", 0, v6 },
536{ "ldda", F3(3, 0x13, 0), F3(~3, ~0x13, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldda [rs1+%g0],d */
537{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[1+i]o,d", 0, v9 },
538{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1), "[i+1]o,d", 0, v9 },
539{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|RS1_G0, "[i]o,d", 0, v9 },
540{ "ldda", F3(3, 0x13, 1), F3(~3, ~0x13, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
541
542{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0), "[1+2]A,H", 0, v9 },
543{ "ldda", F3(3, 0x33, 0), F3(~3, ~0x33, ~0)|RS2_G0, "[1]A,H", 0, v9 }, /* ldda [rs1+%g0],d */
544{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[1+i]o,H", 0, v9 },
545{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1), "[i+1]o,H", 0, v9 },
546{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|RS1_G0, "[i]o,H", 0, v9 },
547{ "ldda", F3(3, 0x33, 1), F3(~3, ~0x33, ~1)|SIMM13(~0), "[1]o,H", 0, v9 }, /* ld [rs1+0],d */
548
549{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0), "[1+2]A,J", 0, v9 },
550{ "ldqa", F3(3, 0x32, 0), F3(~3, ~0x32, ~0)|RS2_G0, "[1]A,J", 0, v9 }, /* ldd [rs1+%g0],d */
551{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[1+i]o,J", 0, v9 },
552{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1), "[i+1]o,J", 0, v9 },
553{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|RS1_G0, "[i]o,J", 0, v9 },
554{ "ldqa", F3(3, 0x32, 1), F3(~3, ~0x32, ~1)|SIMM13(~0), "[1]o,J", 0, v9 }, /* ldd [rs1+0],d */
555
556{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0), "[1+2]A,d", 0, v6 },
557{ "ldsba", F3(3, 0x19, 0), F3(~3, ~0x19, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsba [rs1+%g0],d */
558{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[1+i]o,d", 0, v9 },
559{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1), "[i+1]o,d", 0, v9 },
560{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|RS1_G0, "[i]o,d", 0, v9 },
561{ "ldsba", F3(3, 0x19, 1), F3(~3, ~0x19, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
562
563{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0), "[1+2]A,d", 0, v6 },
564{ "ldsha", F3(3, 0x1a, 0), F3(~3, ~0x1a, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldsha [rs1+%g0],d */
565{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[1+i]o,d", 0, v9 },
566{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1), "[i+1]o,d", 0, v9 },
567{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|RS1_G0, "[i]o,d", 0, v9 },
568{ "ldsha", F3(3, 0x1a, 1), F3(~3, ~0x1a, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
569
570{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0), "[1+2]A,d", 0, v6 },
571{ "ldstuba", F3(3, 0x1d, 0), F3(~3, ~0x1d, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* ldstuba [rs1+%g0],d */
572{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[1+i]o,d", 0, v9 },
573{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1), "[i+1]o,d", 0, v9 },
574{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|RS1_G0, "[i]o,d", 0, v9 },
575{ "ldstuba", F3(3, 0x1d, 1), F3(~3, ~0x1d, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
576
577{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0), "[1+2]A,d", 0, v9 },
578{ "ldswa", F3(3, 0x18, 0), F3(~3, ~0x18, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
579{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[1+i]o,d", 0, v9 },
580{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1), "[i+1]o,d", 0, v9 },
581{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|RS1_G0, "[i]o,d", 0, v9 },
582{ "ldswa", F3(3, 0x18, 1), F3(~3, ~0x18, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
583
584{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0), "[1+2]A,d", 0, v6 },
585{ "lduba", F3(3, 0x11, 0), F3(~3, ~0x11, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduba [rs1+%g0],d */
586{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[1+i]o,d", 0, v9 },
587{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1), "[i+1]o,d", 0, v9 },
588{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|RS1_G0, "[i]o,d", 0, v9 },
589{ "lduba", F3(3, 0x11, 1), F3(~3, ~0x11, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
590
591{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0), "[1+2]A,d", 0, v6 },
592{ "lduha", F3(3, 0x12, 0), F3(~3, ~0x12, ~0)|RS2_G0, "[1]A,d", 0, v6 }, /* lduha [rs1+%g0],d */
593{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[1+i]o,d", 0, v9 },
594{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1), "[i+1]o,d", 0, v9 },
595{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|RS1_G0, "[i]o,d", 0, v9 },
596{ "lduha", F3(3, 0x12, 1), F3(~3, ~0x12, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
597
598{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0), "[1+2]A,d", F_ALIAS, v9 }, /* lduwa === lda */
599{ "lduwa", F3(3, 0x10, 0), F3(~3, ~0x10, ~0)|RS2_G0, "[1]A,d", F_ALIAS, v9 }, /* lda [rs1+%g0],d */
600{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[1+i]o,d", F_ALIAS, v9 },
601{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1), "[i+1]o,d", F_ALIAS, v9 },
602{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|RS1_G0, "[i]o,d", F_ALIAS, v9 },
603{ "lduwa", F3(3, 0x10, 1), F3(~3, ~0x10, ~1)|SIMM13(~0), "[1]o,d", F_ALIAS, v9 }, /* ld [rs1+0],d */
604
605{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0), "[1+2]A,d", 0, v9 },
606{ "ldxa", F3(3, 0x1b, 0), F3(~3, ~0x1b, ~0)|RS2_G0, "[1]A,d", 0, v9 }, /* lda [rs1+%g0],d */
607{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[1+i]o,d", 0, v9 },
608{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1), "[i+1]o,d", 0, v9 },
609{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|RS1_G0, "[i]o,d", 0, v9 },
610{ "ldxa", F3(3, 0x1b, 1), F3(~3, ~0x1b, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* ld [rs1+0],d */
611
612{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
613{ "st", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* st d,[rs1+%g0] */
614{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", 0, v6 },
615{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", 0, v6 },
616{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", 0, v6 },
617{ "st", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* st d,[rs1+0] */
618{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI(~0), "g,[1+2]", 0, v6 },
619{ "st", F3(3, 0x24, 0), F3(~3, ~0x24, ~0)|ASI_RS2(~0), "g,[1]", 0, v6 }, /* st d[rs1+%g0] */
620{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[1+i]", 0, v6 },
621{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1), "g,[i+1]", 0, v6 },
622{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|RS1_G0, "g,[i]", 0, v6 },
623{ "st", F3(3, 0x24, 1), F3(~3, ~0x24, ~1)|SIMM13(~0), "g,[1]", 0, v6 }, /* st d,[rs1+0] */
624
625{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 },
626{ "st", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
627{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[1+i]", 0, v6notv9 },
628{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "D,[i+1]", 0, v6notv9 },
629{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "D,[i]", 0, v6notv9 },
630{ "st", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
631{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI(~0), "C,[1+2]", 0, v6notv9 },
632{ "st", F3(3, 0x35, 0), F3(~3, ~0x35, ~0)|ASI_RS2(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+%g0] */
633{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[1+i]", 0, v6notv9 },
634{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1), "C,[i+1]", 0, v6notv9 },
635{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|RS1_G0, "C,[i]", 0, v6notv9 },
636{ "st", F3(3, 0x35, 1), F3(~3, ~0x35, ~1)|SIMM13(~0), "C,[1]", 0, v6notv9 }, /* st d,[rs1+0] */
637
638{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI(~0), "F,[1+2]", 0, v6 },
639{ "st", F3(3, 0x25, 0), F3(~3, ~0x25, ~0)|RD_G0|ASI_RS2(~0), "F,[1]", 0, v6 }, /* st d,[rs1+%g0] */
640{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[1+i]", 0, v6 },
641{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0, "F,[i+1]", 0, v6 },
642{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|RS1_G0, "F,[i]", 0, v6 },
643{ "st", F3(3, 0x25, 1), F3(~3, ~0x25, ~1)|RD_G0|SIMM13(~0), "F,[1]", 0, v6 }, /* st d,[rs1+0] */
644
645{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
646{ "stw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
647{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
648{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
649{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
650{ "stw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
651{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
652{ "stsw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
653{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
654{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
655{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
656{ "stsw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
657{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v9 },
658{ "stuw", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+%g0] */
659{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v9 },
660{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v9 },
661{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v9 },
662{ "stuw", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v9 }, /* st d,[rs1+0] */
663
664{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
665{ "spill", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+%g0] */
666{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[1+i]", F_ALIAS, v6 },
667{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1), "d,[i+1]", F_ALIAS, v6 },
668{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
669{ "spill", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* st d,[rs1+0] */
670
671{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", 0, v6 },
672{ "sta", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* sta d,[rs1+%g0] */
673{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", 0, v9 },
674{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", 0, v9 },
675{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", 0, v9 },
676{ "sta", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* st d,[rs1+0] */
677
678{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0), "g,[1+2]A", 0, v9 },
679{ "sta", F3(3, 0x34, 0), F3(~3, ~0x34, ~0)|RS2(~0), "g,[1]A", 0, v9 }, /* sta d,[rs1+%g0] */
680{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[1+i]o", 0, v9 },
681{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1), "g,[i+1]o", 0, v9 },
682{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|RS1_G0, "g,[i]o", 0, v9 },
683{ "sta", F3(3, 0x34, 1), F3(~3, ~0x34, ~1)|SIMM13(~0), "g,[1]o", 0, v9 }, /* st d,[rs1+0] */
684
685{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
686{ "stwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
687{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
688{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
689{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
690{ "stwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
691{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
692{ "stswa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
693{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
694{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
695{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
696{ "stswa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
697{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0), "d,[1+2]A", F_ALIAS, v9 },
698{ "stuwa", F3(3, 0x14, 0), F3(~3, ~0x14, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v9 }, /* sta d,[rs1+%g0] */
699{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[1+i]o", F_ALIAS, v9 },
700{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1), "d,[i+1]o", F_ALIAS, v9 },
701{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
702{ "stuwa", F3(3, 0x14, 1), F3(~3, ~0x14, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* st d,[rs1+0] */
703
704{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
705{ "stb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+%g0] */
706{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", 0, v6 },
707{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", 0, v6 },
708{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", 0, v6 },
709{ "stb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* stb d,[rs1+0] */
710
711{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
712{ "stsb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
713{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 },
714{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 },
715{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
716{ "stsb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
717{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
718{ "stub", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+%g0] */
719{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[1+i]", F_ALIAS, v6 },
720{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1), "d,[i+1]", F_ALIAS, v6 },
721{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
722{ "stub", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* stb d,[rs1+0] */
723
724{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", 0, v6 },
725{ "stba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stba d,[rs1+%g0] */
726{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", 0, v9 },
727{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", 0, v9 },
728{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", 0, v9 },
729{ "stba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stb d,[rs1+0] */
730
731{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 },
732{ "stsba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
733{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 },
734{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 },
735{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
736{ "stsba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
737{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0), "d,[1+2]A", F_ALIAS, v6 },
738{ "stuba", F3(3, 0x15, 0), F3(~3, ~0x15, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stba d,[rs1+%g0] */
739{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[1+i]o", F_ALIAS, v9 },
740{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1), "d,[i+1]o", F_ALIAS, v9 },
741{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
742{ "stuba", F3(3, 0x15, 1), F3(~3, ~0x15, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* stb d,[rs1+0] */
743
744{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
745{ "std", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* std d,[rs1+%g0] */
746{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", 0, v6 },
747{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", 0, v6 },
748{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", 0, v6 },
749{ "std", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* std d,[rs1+0] */
750
751{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "q,[1+2]", 0, v6notv9 },
752{ "std", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
753{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[1+i]", 0, v6notv9 },
754{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "q,[i+1]", 0, v6notv9 },
755{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "q,[i]", 0, v6notv9 },
756{ "std", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
757{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI(~0), "H,[1+2]", 0, v6 },
758{ "std", F3(3, 0x27, 0), F3(~3, ~0x27, ~0)|ASI_RS2(~0), "H,[1]", 0, v6 }, /* std d,[rs1+%g0] */
759{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[1+i]", 0, v6 },
760{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1), "H,[i+1]", 0, v6 },
761{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|RS1_G0, "H,[i]", 0, v6 },
762{ "std", F3(3, 0x27, 1), F3(~3, ~0x27, ~1)|SIMM13(~0), "H,[1]", 0, v6 }, /* std d,[rs1+0] */
763
764{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "Q,[1+2]", 0, v6notv9 },
765{ "std", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
766{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[1+i]", 0, v6notv9 },
767{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "Q,[i+1]", 0, v6notv9 },
768{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "Q,[i]", 0, v6notv9 },
769{ "std", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "Q,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
770{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI(~0), "D,[1+2]", 0, v6notv9 },
771{ "std", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|ASI_RS2(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+%g0] */
772{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[1+i]", 0, v6notv9 },
773{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "D,[i+1]", 0, v6notv9 },
774{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "D,[i]", 0, v6notv9 },
775{ "std", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "D,[1]", 0, v6notv9 }, /* std d,[rs1+0] */
776
777{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
778{ "spilld", F3(3, 0x07, 0), F3(~3, ~0x07, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+%g0] */
779{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[1+i]", F_ALIAS, v6 },
780{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1), "d,[i+1]", F_ALIAS, v6 },
781{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
782{ "spilld", F3(3, 0x07, 1), F3(~3, ~0x07, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* std d,[rs1+0] */
783
784{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0), "d,[1+2]A", 0, v6 },
785{ "stda", F3(3, 0x17, 0), F3(~3, ~0x17, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stda d,[rs1+%g0] */
786{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[1+i]o", 0, v9 },
787{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1), "d,[i+1]o", 0, v9 },
788{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|RS1_G0, "d,[i]o", 0, v9 },
789{ "stda", F3(3, 0x17, 1), F3(~3, ~0x17, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* std d,[rs1+0] */
790{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0), "H,[1+2]A", 0, v9 },
791{ "stda", F3(3, 0x37, 0), F3(~3, ~0x37, ~0)|RS2(~0), "H,[1]A", 0, v9 }, /* stda d,[rs1+%g0] */
792{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[1+i]o", 0, v9 },
793{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1), "H,[i+1]o", 0, v9 },
794{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|RS1_G0, "H,[i]o", 0, v9 },
795{ "stda", F3(3, 0x37, 1), F3(~3, ~0x37, ~1)|SIMM13(~0), "H,[1]o", 0, v9 }, /* std d,[rs1+0] */
796
797{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", 0, v6 },
798{ "sth", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+%g0] */
799{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", 0, v6 },
800{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", 0, v6 },
801{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", 0, v6 },
802{ "sth", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", 0, v6 }, /* sth d,[rs1+0] */
803
804{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
805{ "stsh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
806{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 },
807{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 },
808{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
809{ "stsh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
810{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI(~0), "d,[1+2]", F_ALIAS, v6 },
811{ "stuh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|ASI_RS2(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+%g0] */
812{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[1+i]", F_ALIAS, v6 },
813{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1), "d,[i+1]", F_ALIAS, v6 },
814{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RS1_G0, "d,[i]", F_ALIAS, v6 },
815{ "stuh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|SIMM13(~0), "d,[1]", F_ALIAS, v6 }, /* sth d,[rs1+0] */
816
817{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", 0, v6 },
818{ "stha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", 0, v6 }, /* stha ,[rs1+%g0] */
819{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", 0, v9 },
820{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", 0, v9 },
821{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", 0, v9 },
822{ "stha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* sth d,[rs1+0] */
823
824{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 },
825{ "stsha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
826{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 },
827{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 },
828{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
829{ "stsha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
830{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0), "d,[1+2]A", F_ALIAS, v6 },
831{ "stuha", F3(3, 0x16, 0), F3(~3, ~0x16, ~0)|RS2(~0), "d,[1]A", F_ALIAS, v6 }, /* stha ,[rs1+%g0] */
832{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[1+i]o", F_ALIAS, v9 },
833{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1), "d,[i+1]o", F_ALIAS, v9 },
834{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|RS1_G0, "d,[i]o", F_ALIAS, v9 },
835{ "stuha", F3(3, 0x16, 1), F3(~3, ~0x16, ~1)|SIMM13(~0), "d,[1]o", F_ALIAS, v9 }, /* sth d,[rs1+0] */
836
837{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI(~0), "d,[1+2]", 0, v9 },
838{ "stx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|ASI_RS2(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
839{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[1+i]", 0, v9 },
840{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1), "d,[i+1]", 0, v9 },
841{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RS1_G0, "d,[i]", 0, v9 },
842{ "stx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|SIMM13(~0), "d,[1]", 0, v9 }, /* stx d,[rs1+0] */
843
844{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI(~0)|RD(~1), "F,[1+2]", 0, v9 },
845{ "stx", F3(3, 0x25, 0)|RD(1), F3(~3, ~0x25, ~0)|ASI_RS2(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+%g0] */
846{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[1+i]", 0, v9 },
847{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RD(~1), "F,[i+1]", 0, v9 },
848{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|RS1_G0|RD(~1), "F,[i]", 0, v9 },
849{ "stx", F3(3, 0x25, 1)|RD(1), F3(~3, ~0x25, ~1)|SIMM13(~0)|RD(~1),"F,[1]", 0, v9 }, /* stx d,[rs1+0] */
850
851{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0), "d,[1+2]A", 0, v9 },
852{ "stxa", F3(3, 0x1e, 0), F3(~3, ~0x1e, ~0)|RS2(~0), "d,[1]A", 0, v9 }, /* stxa d,[rs1+%g0] */
853{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[1+i]o", 0, v9 },
854{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1), "d,[i+1]o", 0, v9 },
855{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|RS1_G0, "d,[i]o", 0, v9 },
856{ "stxa", F3(3, 0x1e, 1), F3(~3, ~0x1e, ~1)|SIMM13(~0), "d,[1]o", 0, v9 }, /* stx d,[rs1+0] */
857
858{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI(~0), "J,[1+2]", 0, v9 },
859{ "stq", F3(3, 0x26, 0), F3(~3, ~0x26, ~0)|ASI_RS2(~0), "J,[1]", 0, v9 }, /* stq [rs1+%g0] */
860{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[1+i]", 0, v9 },
861{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1), "J,[i+1]", 0, v9 },
862{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|RS1_G0, "J,[i]", 0, v9 },
863{ "stq", F3(3, 0x26, 1), F3(~3, ~0x26, ~1)|SIMM13(~0), "J,[1]", 0, v9 }, /* stq [rs1+0] */
864
865{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI(~0), "J,[1+2]A", 0, v9 },
866{ "stqa", F3(3, 0x36, 0), F3(~3, ~0x36, ~0)|ASI_RS2(~0), "J,[1]A", 0, v9 }, /* stqa [rs1+%g0] */
867{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[1+i]o", 0, v9 },
868{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1), "J,[i+1]o", 0, v9 },
869{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|RS1_G0, "J,[i]o", 0, v9 },
870{ "stqa", F3(3, 0x36, 1), F3(~3, ~0x36, ~1)|SIMM13(~0), "J,[1]o", 0, v9 }, /* stqa [rs1+0] */
871
872{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI(~0), "[1+2],d", 0, v7 },
873{ "swap", F3(3, 0x0f, 0), F3(~3, ~0x0f, ~0)|ASI_RS2(~0), "[1],d", 0, v7 }, /* swap [rs1+%g0],d */
874{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[1+i],d", 0, v7 },
875{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1), "[i+1],d", 0, v7 },
876{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|RS1_G0, "[i],d", 0, v7 },
877{ "swap", F3(3, 0x0f, 1), F3(~3, ~0x0f, ~1)|SIMM13(~0), "[1],d", 0, v7 }, /* swap [rs1+0],d */
878
879{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0), "[1+2]A,d", 0, v7 },
880{ "swapa", F3(3, 0x1f, 0), F3(~3, ~0x1f, ~0)|RS2(~0), "[1]A,d", 0, v7 }, /* swapa [rs1+%g0],d */
881{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[1+i]o,d", 0, v9 },
882{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1), "[i+1]o,d", 0, v9 },
883{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|RS1_G0, "[i]o,d", 0, v9 },
884{ "swapa", F3(3, 0x1f, 1), F3(~3, ~0x1f, ~1)|SIMM13(~0), "[1]o,d", 0, v9 }, /* swap [rs1+0],d */
885
886{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|ASI(~0), "1,2,d", 0, v6 },
887{ "restore", F3(2, 0x3d, 0), F3(~2, ~0x3d, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v6 }, /* restore %g0,%g0,%g0 */
888{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1), "1,i,d", 0, v6 },
889{ "restore", F3(2, 0x3d, 1), F3(~2, ~0x3d, ~1)|RD_G0|RS1_G0|SIMM13(~0), "", 0, v6 }, /* restore %g0,0,%g0 */
890
891{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* rett rs1+rs2 */
892{ "rett", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1,%g0 */
893{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* rett rs1+X */
894{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
895{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X+rs1 */
896{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* rett X */
897{ "rett", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* rett rs1+0 */
898
899{ "save", F3(2, 0x3c, 0), F3(~2, ~0x3c, ~0)|ASI(~0), "1,2,d", 0, v6 },
900{ "save", F3(2, 0x3c, 1), F3(~2, ~0x3c, ~1), "1,i,d", 0, v6 },
901{ "save", 0x81e00000, ~0x81e00000, "", F_ALIAS, v6 },
902
903{ "ret", F3(2, 0x38, 1)|RS1(0x1f)|SIMM13(8), F3(~2, ~0x38, ~1)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %i7+8,%g0 */
aa0aa4fa
FB		 904{ "retl", F3(2, 0x38, 1)|RS1(0x0f)|SIMM13(8), F3(~2, ~0x38, ~1)|RS1(~0x0f)|SIMM13(~8), "", F_UNBR|F_DELAYED, v6 }, /* jmpl %o7+8,%g0 */
905
f930d07e
BS		 906{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI(~0), "1+2,d", F_JSR|F_DELAYED, v6 },
907{ "jmpl", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|ASI_RS2(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,d */
908{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|SIMM13(~0), "1,d", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,d */
909{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RS1_G0, "i,d", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,d */
910{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "1+i,d", F_JSR|F_DELAYED, v6 },
911{ "jmpl", F3(2, 0x38, 1), F3(~2, ~0x38, ~1), "i+1,d", F_JSR|F_DELAYED, v6 },
912
913{ "done", F3(2, 0x3e, 0)|RD(0), F3(~2, ~0x3e, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
914{ "retry", F3(2, 0x3e, 0)|RD(1), F3(~2, ~0x3e, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
915{ "saved", F3(2, 0x31, 0)|RD(0), F3(~2, ~0x31, ~0)|RD(~0)|RS1_G0|SIMM13(~0), "", 0, v9 },
916{ "restored", F3(2, 0x31, 0)|RD(1), F3(~2, ~0x31, ~0)|RD(~1)|RS1_G0|SIMM13(~0), "", 0, v9 },
46f42f29
BS		 917{ "allclean", F3(2, 0x31, 0)|RD(2), F3(~2, ~0x31, ~0)|RD(~2)|RS1_G0|SIMM13(~0), "", 0, v9 },
918{ "otherw", F3(2, 0x31, 0)|RD(3), F3(~2, ~0x31, ~0)|RD(~3)|RS1_G0|SIMM13(~0), "", 0, v9 },
919{ "normalw", F3(2, 0x31, 0)|RD(4), F3(~2, ~0x31, ~0)|RD(~4)|RS1_G0|SIMM13(~0), "", 0, v9 },
920{ "invalw", F3(2, 0x31, 0)|RD(5), F3(~2, ~0x31, ~0)|RD(~5)|RS1_G0|SIMM13(~0), "", 0, v9 },
f930d07e
BS		 921{ "sir", F3(2, 0x30, 1)|RD(0xf), F3(~2, ~0x30, ~1)|RD(~0xf)|RS1_G0, "i", 0, v9 },
922
923{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", 0, v8 },
924{ "flush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", 0, v8 }, /* flush rs1+%g0 */
925{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", 0, v8 }, /* flush rs1+0 */
926{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", 0, v8 }, /* flush %g0+i */
927{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", 0, v8 },
928{ "flush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", 0, v8 },
aa0aa4fa
FB		 929
930/* IFLUSH was renamed to FLUSH in v8. */
f930d07e
BS		 931{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI(~0), "1+2", F_ALIAS, v6 },
932{ "iflush", F3(2, 0x3b, 0), F3(~2, ~0x3b, ~0)|ASI_RS2(~0), "1", F_ALIAS, v6 }, /* flush rs1+%g0 */
933{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|SIMM13(~0), "1", F_ALIAS, v6 }, /* flush rs1+0 */
934{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1)|RS1_G0, "i", F_ALIAS, v6 },
935{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "1+i", F_ALIAS, v6 },
936{ "iflush", F3(2, 0x3b, 1), F3(~2, ~0x3b, ~1), "i+1", F_ALIAS, v6 },
937
938{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI(~0), "1+2", 0, v9 },
939{ "return", F3(2, 0x39, 0), F3(~2, ~0x39, ~0)|ASI_RS2(~0), "1", 0, v9 }, /* return rs1+%g0 */
940{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|SIMM13(~0), "1", 0, v9 }, /* return rs1+0 */
941{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1)|RS1_G0, "i", 0, v9 }, /* return %g0+i */
942{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "1+i", 0, v9 },
943{ "return", F3(2, 0x39, 1), F3(~2, ~0x39, ~1), "i+1", 0, v9 },
944
945{ "flushw", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "", 0, v9 },
946
947{ "membar", F3(2, 0x28, 1)|RS1(0xf), F3(~2, ~0x28, ~1)|RD_G0|RS1(~0xf)|SIMM13(~127), "K", 0, v9 },
948{ "stbar", F3(2, 0x28, 0)|RS1(0xf), F3(~2, ~0x28, ~0)|RD_G0|RS1(~0xf)|SIMM13(~0), "", 0, v8 },
949
950{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0), "[1+2],*", 0, v9 },
951{ "prefetch", F3(3, 0x2d, 0), F3(~3, ~0x2d, ~0)|RS2_G0, "[1],*", 0, v9 }, /* prefetch [rs1+%g0],prefetch_fcn */
952{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[1+i],*", 0, v9 },
953{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1), "[i+1],*", 0, v9 },
954{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|RS1_G0, "[i],*", 0, v9 },
955{ "prefetch", F3(3, 0x2d, 1), F3(~3, ~0x2d, ~1)|SIMM13(~0), "[1],*", 0, v9 }, /* prefetch [rs1+0],prefetch_fcn */
956{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0), "[1+2]A,*", 0, v9 },
957{ "prefetcha", F3(3, 0x3d, 0), F3(~3, ~0x3d, ~0)|RS2_G0, "[1]A,*", 0, v9 }, /* prefetcha [rs1+%g0],prefetch_fcn */
958{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[1+i]o,*", 0, v9 },
959{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1), "[i+1]o,*", 0, v9 },
960{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|RS1_G0, "[i]o,*", 0, v9 },
961{ "prefetcha", F3(3, 0x3d, 1), F3(~3, ~0x3d, ~1)|SIMM13(~0), "[1]o,*", 0, v9 }, /* prefetcha [rs1+0],d */
962
963{ "sll", F3(2, 0x25, 0), F3(~2, ~0x25, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
964{ "sll", F3(2, 0x25, 1), F3(~2, ~0x25, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
965{ "sra", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
966{ "sra", F3(2, 0x27, 1), F3(~2, ~0x27, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
967{ "srl", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|(0x7f<<5), "1,2,d", 0, v6 },
968{ "srl", F3(2, 0x26, 1), F3(~2, ~0x26, ~1)|(1<<12)|(0x7f<<5), "1,X,d", 0, v6 },
969
970{ "sllx", F3(2, 0x25, 0)|(1<<12), F3(~2, ~0x25, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
971{ "sllx", F3(2, 0x25, 1)|(1<<12), F3(~2, ~0x25, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
972{ "srax", F3(2, 0x27, 0)|(1<<12), F3(~2, ~0x27, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
973{ "srax", F3(2, 0x27, 1)|(1<<12), F3(~2, ~0x27, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
974{ "srlx", F3(2, 0x26, 0)|(1<<12), F3(~2, ~0x26, ~0)|(0x7f<<5), "1,2,d", 0, v9 },
975{ "srlx", F3(2, 0x26, 1)|(1<<12), F3(~2, ~0x26, ~1)|(0x3f<<6), "1,Y,d", 0, v9 },
976
977{ "mulscc", F3(2, 0x24, 0), F3(~2, ~0x24, ~0)|ASI(~0), "1,2,d", 0, v6 },
978{ "mulscc", F3(2, 0x24, 1), F3(~2, ~0x24, ~1), "1,i,d", 0, v6 },
979
980{ "divscc", F3(2, 0x1d, 0), F3(~2, ~0x1d, ~0)|ASI(~0), "1,2,d", 0, sparclite },
981{ "divscc", F3(2, 0x1d, 1), F3(~2, ~0x1d, ~1), "1,i,d", 0, sparclite },
982
983{ "scan", F3(2, 0x2c, 0), F3(~2, ~0x2c, ~0)|ASI(~0), "1,2,d", 0, sparclet|sparclite },
984{ "scan", F3(2, 0x2c, 1), F3(~2, ~0x2c, ~1), "1,i,d", 0, sparclet|sparclite },
985
986{ "popc", F3(2, 0x2e, 0), F3(~2, ~0x2e, ~0)|RS1_G0|ASI(~0),"2,d", 0, v9 },
987{ "popc", F3(2, 0x2e, 1), F3(~2, ~0x2e, ~1)|RS1_G0, "i,d", 0, v9 },
988
989{ "clr", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RD_G0|RS1_G0|ASI_RS2(~0), "d", F_ALIAS, v6 }, /* or %g0,%g0,d */
990{ "clr", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0|SIMM13(~0), "d", F_ALIAS, v6 }, /* or %g0,0,d */
991{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
992{ "clr", F3(3, 0x04, 0), F3(~3, ~0x04, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+%g0] */
993{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
994{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
995{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
996{ "clr", F3(3, 0x04, 1), F3(~3, ~0x04, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* st %g0,[rs1+0] */
997
998{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
999{ "clrb", F3(3, 0x05, 0), F3(~3, ~0x05, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+%g0] */
1000{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
1001{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
1002{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
1003{ "clrb", F3(3, 0x05, 1), F3(~3, ~0x05, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* stb %g0,[rs1+0] */
1004
1005{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v6 },
1006{ "clrh", F3(3, 0x06, 0), F3(~3, ~0x06, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+%g0] */
1007{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[1+i]", F_ALIAS, v6 },
1008{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0, "[i+1]", F_ALIAS, v6 },
1009{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v6 },
1010{ "clrh", F3(3, 0x06, 1), F3(~3, ~0x06, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v6 }, /* sth %g0,[rs1+0] */
1011
1012{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI(~0), "[1+2]", F_ALIAS, v9 },
1013{ "clrx", F3(3, 0x0e, 0), F3(~3, ~0x0e, ~0)|RD_G0|ASI_RS2(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+%g0] */
1014{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[1+i]", F_ALIAS, v9 },
1015{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0, "[i+1]", F_ALIAS, v9 },
1016{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|RS1_G0, "[i]", F_ALIAS, v9 },
1017{ "clrx", F3(3, 0x0e, 1), F3(~3, ~0x0e, ~1)|RD_G0|SIMM13(~0), "[1]", F_ALIAS, v9 }, /* stx %g0,[rs1+0] */
1018
1019{ "orcc", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|ASI(~0), "1,2,d", 0, v6 },
1020{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "1,i,d", 0, v6 },
1021{ "orcc", F3(2, 0x12, 1), F3(~2, ~0x12, ~1), "i,1,d", 0, v6 },
aa0aa4fa
FB		 1022
1023/* This is not a commutative instruction. */
f930d07e
BS		 1024{ "orncc", F3(2, 0x16, 0), F3(~2, ~0x16, ~0)|ASI(~0), "1,2,d", 0, v6 },
1025{ "orncc", F3(2, 0x16, 1), F3(~2, ~0x16, ~1), "1,i,d", 0, v6 },
aa0aa4fa
FB		 1026
1027/* This is not a commutative instruction. */
f930d07e
BS		 1028{ "orn", F3(2, 0x06, 0), F3(~2, ~0x06, ~0)|ASI(~0), "1,2,d", 0, v6 },
1029{ "orn", F3(2, 0x06, 1), F3(~2, ~0x06, ~1), "1,i,d", 0, v6 },
1030
1031{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|ASI_RS2(~0), "1", 0, v6 }, /* orcc rs1, %g0, %g0 */
1032{ "tst", F3(2, 0x12, 0), F3(~2, ~0x12, ~0)|RD_G0|RS1_G0|ASI(~0), "2", 0, v6 }, /* orcc %g0, rs2, %g0 */
1033{ "tst", F3(2, 0x12, 1), F3(~2, ~0x12, ~1)|RD_G0|SIMM13(~0), "1", 0, v6 }, /* orcc rs1, 0, %g0 */
1034
1035{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", 0, v8 }, /* wr r,r,%asrX */
1036{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", 0, v8 }, /* wr r,i,%asrX */
1037{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
1038{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", 0, v6 }, /* wr r,r,%y */
1039{ "wr", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", 0, v6 }, /* wr r,i,%y */
1040{ "wr", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
1041{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", 0, v6notv9 }, /* wr r,r,%psr */
1042{ "wr", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", 0, v6notv9 }, /* wr r,i,%psr */
1043{ "wr", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
1044{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", 0, v6notv9 }, /* wr r,r,%wim */
1045{ "wr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", 0, v6notv9 }, /* wr r,i,%wim */
1046{ "wr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
1047{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", 0, v6notv9 }, /* wr r,r,%tbr */
1048{ "wr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", 0, v6notv9 }, /* wr r,i,%tbr */
1049{ "wr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
1050
1051{ "wr", F3(2, 0x30, 0)|RD(2), F3(~2, ~0x30, ~0)|RD(~2)|ASI(~0), "1,2,E", 0, v9 }, /* wr r,r,%ccr */
1052{ "wr", F3(2, 0x30, 1)|RD(2), F3(~2, ~0x30, ~1)|RD(~2), "1,i,E", 0, v9 }, /* wr r,i,%ccr */
1053{ "wr", F3(2, 0x30, 0)|RD(3), F3(~2, ~0x30, ~0)|RD(~3)|ASI(~0), "1,2,o", 0, v9 }, /* wr r,r,%asi */
1054{ "wr", F3(2, 0x30, 1)|RD(3), F3(~2, ~0x30, ~1)|RD(~3), "1,i,o", 0, v9 }, /* wr r,i,%asi */
1055{ "wr", F3(2, 0x30, 0)|RD(6), F3(~2, ~0x30, ~0)|RD(~6)|ASI(~0), "1,2,s", 0, v9 }, /* wr r,r,%fprs */
1056{ "wr", F3(2, 0x30, 1)|RD(6), F3(~2, ~0x30, ~1)|RD(~6), "1,i,s", 0, v9 }, /* wr r,i,%fprs */
1057
1058{ "wr", F3(2, 0x30, 0)|RD(16), F3(~2, ~0x30, ~0)|RD(~16)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pcr */
1059{ "wr", F3(2, 0x30, 1)|RD(16), F3(~2, ~0x30, ~1)|RD(~16), "1,i,_", 0, v9a }, /* wr r,i,%pcr */
1060{ "wr", F3(2, 0x30, 0)|RD(17), F3(~2, ~0x30, ~0)|RD(~17)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%pic */
1061{ "wr", F3(2, 0x30, 1)|RD(17), F3(~2, ~0x30, ~1)|RD(~17), "1,i,_", 0, v9a }, /* wr r,i,%pic */
1062{ "wr", F3(2, 0x30, 0)|RD(18), F3(~2, ~0x30, ~0)|RD(~18)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%dcr */
1063{ "wr", F3(2, 0x30, 1)|RD(18), F3(~2, ~0x30, ~1)|RD(~18), "1,i,_", 0, v9a }, /* wr r,i,%dcr */
1064{ "wr", F3(2, 0x30, 0)|RD(19), F3(~2, ~0x30, ~0)|RD(~19)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%gsr */
1065{ "wr", F3(2, 0x30, 1)|RD(19), F3(~2, ~0x30, ~1)|RD(~19), "1,i,_", 0, v9a }, /* wr r,i,%gsr */
1066{ "wr", F3(2, 0x30, 0)|RD(20), F3(~2, ~0x30, ~0)|RD(~20)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%set_softint */
1067{ "wr", F3(2, 0x30, 1)|RD(20), F3(~2, ~0x30, ~1)|RD(~20), "1,i,_", 0, v9a }, /* wr r,i,%set_softint */
1068{ "wr", F3(2, 0x30, 0)|RD(21), F3(~2, ~0x30, ~0)|RD(~21)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%clear_softint */
1069{ "wr", F3(2, 0x30, 1)|RD(21), F3(~2, ~0x30, ~1)|RD(~21), "1,i,_", 0, v9a }, /* wr r,i,%clear_softint */
1070{ "wr", F3(2, 0x30, 0)|RD(22), F3(~2, ~0x30, ~0)|RD(~22)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%softint */
1071{ "wr", F3(2, 0x30, 1)|RD(22), F3(~2, ~0x30, ~1)|RD(~22), "1,i,_", 0, v9a }, /* wr r,i,%softint */
1072{ "wr", F3(2, 0x30, 0)|RD(23), F3(~2, ~0x30, ~0)|RD(~23)|ASI(~0), "1,2,_", 0, v9a }, /* wr r,r,%tick_cmpr */
1073{ "wr", F3(2, 0x30, 1)|RD(23), F3(~2, ~0x30, ~1)|RD(~23), "1,i,_", 0, v9a }, /* wr r,i,%tick_cmpr */
1074{ "wr", F3(2, 0x30, 0)|RD(24), F3(~2, ~0x30, ~0)|RD(~24)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick */
1075{ "wr", F3(2, 0x30, 1)|RD(24), F3(~2, ~0x30, ~1)|RD(~24), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick */
1076{ "wr", F3(2, 0x30, 0)|RD(25), F3(~2, ~0x30, ~0)|RD(~25)|ASI(~0), "1,2,_", 0, v9b }, /* wr r,r,%sys_tick_cmpr */
1077{ "wr", F3(2, 0x30, 1)|RD(25), F3(~2, ~0x30, ~1)|RD(~25), "1,i,_", 0, v9b }, /* wr r,i,%sys_tick_cmpr */
1078
1079{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", 0, v8 }, /* rd %asrX,r */
1080{ "rd", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", 0, v6 }, /* rd %y,r */
1081{ "rd", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", 0, v6notv9 }, /* rd %psr,r */
1082{ "rd", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", 0, v6notv9 }, /* rd %wim,r */
1083{ "rd", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", 0, v6notv9 }, /* rd %tbr,r */
1084
1085{ "rd", F3(2, 0x28, 0)|RS1(2), F3(~2, ~0x28, ~0)|RS1(~2)|SIMM13(~0), "E,d", 0, v9 }, /* rd %ccr,r */
1086{ "rd", F3(2, 0x28, 0)|RS1(3), F3(~2, ~0x28, ~0)|RS1(~3)|SIMM13(~0), "o,d", 0, v9 }, /* rd %asi,r */
1087{ "rd", F3(2, 0x28, 0)|RS1(4), F3(~2, ~0x28, ~0)|RS1(~4)|SIMM13(~0), "W,d", 0, v9 }, /* rd %tick,r */
1088{ "rd", F3(2, 0x28, 0)|RS1(5), F3(~2, ~0x28, ~0)|RS1(~5)|SIMM13(~0), "P,d", 0, v9 }, /* rd %pc,r */
1089{ "rd", F3(2, 0x28, 0)|RS1(6), F3(~2, ~0x28, ~0)|RS1(~6)|SIMM13(~0), "s,d", 0, v9 }, /* rd %fprs,r */
1090
1091{ "rd", F3(2, 0x28, 0)|RS1(16), F3(~2, ~0x28, ~0)|RS1(~16)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pcr,r */
1092{ "rd", F3(2, 0x28, 0)|RS1(17), F3(~2, ~0x28, ~0)|RS1(~17)|SIMM13(~0), "/,d", 0, v9a }, /* rd %pic,r */
1093{ "rd", F3(2, 0x28, 0)|RS1(18), F3(~2, ~0x28, ~0)|RS1(~18)|SIMM13(~0), "/,d", 0, v9a }, /* rd %dcr,r */
1094{ "rd", F3(2, 0x28, 0)|RS1(19), F3(~2, ~0x28, ~0)|RS1(~19)|SIMM13(~0), "/,d", 0, v9a }, /* rd %gsr,r */
1095{ "rd", F3(2, 0x28, 0)|RS1(22), F3(~2, ~0x28, ~0)|RS1(~22)|SIMM13(~0), "/,d", 0, v9a }, /* rd %softint,r */
1096{ "rd", F3(2, 0x28, 0)|RS1(23), F3(~2, ~0x28, ~0)|RS1(~23)|SIMM13(~0), "/,d", 0, v9a }, /* rd %tick_cmpr,r */
1097{ "rd", F3(2, 0x28, 0)|RS1(24), F3(~2, ~0x28, ~0)|RS1(~24)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick,r */
1098{ "rd", F3(2, 0x28, 0)|RS1(25), F3(~2, ~0x28, ~0)|RS1(~25)|SIMM13(~0), "/,d", 0, v9b }, /* rd %sys_tick_cmpr,r */
1099
1100{ "rdpr", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|SIMM13(~0), "?,d", 0, v9 }, /* rdpr %priv,r */
1101{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0), "1,2,!", 0, v9 }, /* wrpr r1,r2,%priv */
1102{ "wrpr", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|SIMM13(~0), "1,!", 0, v9 }, /* wrpr r1,%priv */
1103{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "1,i,!", 0, v9 }, /* wrpr r1,i,%priv */
1104{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1), "i,1,!", F_ALIAS, v9 }, /* wrpr i,r1,%priv */
1105{ "wrpr", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RS1(~0), "i,!", 0, v9 }, /* wrpr i,%priv */
aa0aa4fa 1106
46f42f29
BS		 1107{ "rdhpr", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|SIMM13(~0), "$,d", 0, v9 }, /* rdhpr %hpriv,r */
1108{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0), "1,2,%", 0, v9 }, /* wrhpr r1,r2,%hpriv */
1109{ "wrhpr", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|SIMM13(~0), "1,%", 0, v9 }, /* wrhpr r1,%hpriv */
1110{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "1,i,%", 0, v9 }, /* wrhpr r1,i,%hpriv */
1111{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1), "i,1,%", F_ALIAS, v9 }, /* wrhpr i,r1,%hpriv */
1112{ "wrhpr", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RS1(~0), "i,%", 0, v9 }, /* wrhpr i,%hpriv */
1113
aa0aa4fa 1114/* ??? This group seems wrong. A three operand move? */
f930d07e
BS		 1115{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI(~0), "1,2,m", F_ALIAS, v8 }, /* wr r,r,%asrX */
1116{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "1,i,m", F_ALIAS, v8 }, /* wr r,i,%asrX */
1117{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI(~0), "1,2,y", F_ALIAS, v6 }, /* wr r,r,%y */
1118{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "1,i,y", F_ALIAS, v6 }, /* wr r,i,%y */
1119{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI(~0), "1,2,p", F_ALIAS, v6notv9 }, /* wr r,r,%psr */
1120{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "1,i,p", F_ALIAS, v6notv9 }, /* wr r,i,%psr */
1121{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI(~0), "1,2,w", F_ALIAS, v6notv9 }, /* wr r,r,%wim */
1122{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "1,i,w", F_ALIAS, v6notv9 }, /* wr r,i,%wim */
1123{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI(~0), "1,2,t", F_ALIAS, v6notv9 }, /* wr r,r,%tbr */
1124{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "1,i,t", F_ALIAS, v6notv9 }, /* wr r,i,%tbr */
1125
1126{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|SIMM13(~0), "M,d", F_ALIAS, v8 }, /* rd %asr1,r */
1127{ "mov", F3(2, 0x28, 0), F3(~2, ~0x28, ~0)|RS1_G0|SIMM13(~0), "y,d", F_ALIAS, v6 }, /* rd %y,r */
1128{ "mov", F3(2, 0x29, 0), F3(~2, ~0x29, ~0)|RS1_G0|SIMM13(~0), "p,d", F_ALIAS, v6notv9 }, /* rd %psr,r */
1129{ "mov", F3(2, 0x2a, 0), F3(~2, ~0x2a, ~0)|RS1_G0|SIMM13(~0), "w,d", F_ALIAS, v6notv9 }, /* rd %wim,r */
1130{ "mov", F3(2, 0x2b, 0), F3(~2, ~0x2b, ~0)|RS1_G0|SIMM13(~0), "t,d", F_ALIAS, v6notv9 }, /* rd %tbr,r */
1131
1132{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|ASI_RS2(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,%g0,%asrX */
1133{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1), "i,m", F_ALIAS, v8 }, /* wr %g0,i,%asrX */
1134{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|SIMM13(~0), "1,m", F_ALIAS, v8 }, /* wr rs1,0,%asrX */
1135{ "mov", F3(2, 0x30, 0), F3(~2, ~0x30, ~0)|RD_G0|ASI_RS2(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,%g0,%y */
1136{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0, "i,y", F_ALIAS, v6 }, /* wr %g0,i,%y */
1137{ "mov", F3(2, 0x30, 1), F3(~2, ~0x30, ~1)|RD_G0|SIMM13(~0), "1,y", F_ALIAS, v6 }, /* wr rs1,0,%y */
1138{ "mov", F3(2, 0x31, 0), F3(~2, ~0x31, ~0)|RD_G0|ASI_RS2(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%psr */
1139{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0, "i,p", F_ALIAS, v6notv9 }, /* wr %g0,i,%psr */
1140{ "mov", F3(2, 0x31, 1), F3(~2, ~0x31, ~1)|RD_G0|SIMM13(~0), "1,p", F_ALIAS, v6notv9 }, /* wr rs1,0,%psr */
1141{ "mov", F3(2, 0x32, 0), F3(~2, ~0x32, ~0)|RD_G0|ASI_RS2(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%wim */
1142{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0, "i,w", F_ALIAS, v6notv9 }, /* wr %g0,i,%wim */
1143{ "mov", F3(2, 0x32, 1), F3(~2, ~0x32, ~1)|RD_G0|SIMM13(~0), "1,w", F_ALIAS, v6notv9 }, /* wr rs1,0,%wim */
1144{ "mov", F3(2, 0x33, 0), F3(~2, ~0x33, ~0)|RD_G0|ASI_RS2(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,%g0,%tbr */
1145{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0, "i,t", F_ALIAS, v6notv9 }, /* wr %g0,i,%tbr */
1146{ "mov", F3(2, 0x33, 1), F3(~2, ~0x33, ~1)|RD_G0|SIMM13(~0), "1,t", F_ALIAS, v6notv9 }, /* wr rs1,0,%tbr */
1147
1148{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|RS1_G0|ASI(~0), "2,d", 0, v6 }, /* or %g0,rs2,d */
1149{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|RS1_G0, "i,d", 0, v6 }, /* or %g0,i,d */
1150{ "mov", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI_RS2(~0), "1,d", 0, v6 }, /* or rs1,%g0,d */
1151{ "mov", F3(2, 0x02, 1), F3(~2, ~0x02, ~1)|SIMM13(~0), "1,d", 0, v6 }, /* or rs1,0,d */
1152
1153{ "or", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "1,2,d", 0, v6 },
1154{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "1,i,d", 0, v6 },
1155{ "or", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,1,d", 0, v6 },
1156
1157{ "bset", F3(2, 0x02, 0), F3(~2, ~0x02, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* or rd,rs2,rd */
1158{ "bset", F3(2, 0x02, 1), F3(~2, ~0x02, ~1), "i,r", F_ALIAS, v6 }, /* or rd,i,rd */
aa0aa4fa
FB		 1159
1160/* This is not a commutative instruction. */
f930d07e
BS		 1161{ "andn", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "1,2,d", 0, v6 },
1162{ "andn", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "1,i,d", 0, v6 },
aa0aa4fa
FB		 1163
1164/* This is not a commutative instruction. */
f930d07e
BS		 1165{ "andncc", F3(2, 0x15, 0), F3(~2, ~0x15, ~0)|ASI(~0), "1,2,d", 0, v6 },
1166{ "andncc", F3(2, 0x15, 1), F3(~2, ~0x15, ~1), "1,i,d", 0, v6 },
1167
1168{ "bclr", F3(2, 0x05, 0), F3(~2, ~0x05, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* andn rd,rs2,rd */
1169{ "bclr", F3(2, 0x05, 1), F3(~2, ~0x05, ~1), "i,r", F_ALIAS, v6 }, /* andn rd,i,rd */
1170
1171{ "cmp", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|RD_G0|ASI(~0), "1,2", 0, v6 }, /* subcc rs1,rs2,%g0 */
1172{ "cmp", F3(2, 0x14, 1), F3(~2, ~0x14, ~1)|RD_G0, "1,i", 0, v6 }, /* subcc rs1,i,%g0 */
1173
1174{ "sub", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|ASI(~0), "1,2,d", 0, v6 },
1175{ "sub", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "1,i,d", 0, v6 },
1176
1177{ "subcc", F3(2, 0x14, 0), F3(~2, ~0x14, ~0)|ASI(~0), "1,2,d", 0, v6 },
1178{ "subcc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "1,i,d", 0, v6 },
1179
1180{ "subx", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1181{ "subx", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v6notv9 },
1182{ "subc", F3(2, 0x0c, 0), F3(~2, ~0x0c, ~0)|ASI(~0), "1,2,d", 0, v9 },
1183{ "subc", F3(2, 0x0c, 1), F3(~2, ~0x0c, ~1), "1,i,d", 0, v9 },
1184
1185{ "subxcc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1186{ "subxcc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v6notv9 },
1187{ "subccc", F3(2, 0x1c, 0), F3(~2, ~0x1c, ~0)|ASI(~0), "1,2,d", 0, v9 },
1188{ "subccc", F3(2, 0x1c, 1), F3(~2, ~0x1c, ~1), "1,i,d", 0, v9 },
1189
1190{ "and", F3(2, 0x01, 0), F3(~2, ~0x01, ~0)|ASI(~0), "1,2,d", 0, v6 },
1191{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "1,i,d", 0, v6 },
1192{ "and", F3(2, 0x01, 1), F3(~2, ~0x01, ~1), "i,1,d", 0, v6 },
1193
1194{ "andcc", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|ASI(~0), "1,2,d", 0, v6 },
1195{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "1,i,d", 0, v6 },
1196{ "andcc", F3(2, 0x11, 1), F3(~2, ~0x11, ~1), "i,1,d", 0, v6 },
1197
1198{ "dec", F3(2, 0x04, 1)|SIMM13(0x1), F3(~2, ~0x04, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* sub rd,1,rd */
1199{ "dec", F3(2, 0x04, 1), F3(~2, ~0x04, ~1), "i,r", F_ALIAS, v8 }, /* sub rd,imm,rd */
1200{ "deccc", F3(2, 0x14, 1)|SIMM13(0x1), F3(~2, ~0x14, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* subcc rd,1,rd */
1201{ "deccc", F3(2, 0x14, 1), F3(~2, ~0x14, ~1), "i,r", F_ALIAS, v8 }, /* subcc rd,imm,rd */
1202{ "inc", F3(2, 0x00, 1)|SIMM13(0x1), F3(~2, ~0x00, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* add rd,1,rd */
1203{ "inc", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,r", F_ALIAS, v8 }, /* add rd,imm,rd */
1204{ "inccc", F3(2, 0x10, 1)|SIMM13(0x1), F3(~2, ~0x10, ~1)|SIMM13(~0x0001), "r", F_ALIAS, v6 }, /* addcc rd,1,rd */
1205{ "inccc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,r", F_ALIAS, v8 }, /* addcc rd,imm,rd */
1206
1207{ "btst", F3(2, 0x11, 0), F3(~2, ~0x11, ~0)|RD_G0|ASI(~0), "1,2", F_ALIAS, v6 }, /* andcc rs1,rs2,%g0 */
1208{ "btst", F3(2, 0x11, 1), F3(~2, ~0x11, ~1)|RD_G0, "i,1", F_ALIAS, v6 }, /* andcc rs1,i,%g0 */
1209
1210{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "2,d", F_ALIAS, v6 }, /* sub %g0,rs2,rd */
1211{ "neg", F3(2, 0x04, 0), F3(~2, ~0x04, ~0)|RS1_G0|ASI(~0), "O", F_ALIAS, v6 }, /* sub %g0,rd,rd */
1212
1213{ "add", F3(2, 0x00, 0), F3(~2, ~0x00, ~0)|ASI(~0), "1,2,d", 0, v6 },
1214{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "1,i,d", 0, v6 },
1215{ "add", F3(2, 0x00, 1), F3(~2, ~0x00, ~1), "i,1,d", 0, v6 },
1216{ "addcc", F3(2, 0x10, 0), F3(~2, ~0x10, ~0)|ASI(~0), "1,2,d", 0, v6 },
1217{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "1,i,d", 0, v6 },
1218{ "addcc", F3(2, 0x10, 1), F3(~2, ~0x10, ~1), "i,1,d", 0, v6 },
1219
1220{ "addx", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1221{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v6notv9 },
1222{ "addx", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v6notv9 },
1223{ "addc", F3(2, 0x08, 0), F3(~2, ~0x08, ~0)|ASI(~0), "1,2,d", 0, v9 },
1224{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "1,i,d", 0, v9 },
1225{ "addc", F3(2, 0x08, 1), F3(~2, ~0x08, ~1), "i,1,d", 0, v9 },
1226
1227{ "addxcc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v6notv9 },
1228{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v6notv9 },
1229{ "addxcc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v6notv9 },
1230{ "addccc", F3(2, 0x18, 0), F3(~2, ~0x18, ~0)|ASI(~0), "1,2,d", 0, v9 },
1231{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "1,i,d", 0, v9 },
1232{ "addccc", F3(2, 0x18, 1), F3(~2, ~0x18, ~1), "i,1,d", 0, v9 },
1233
1234{ "smul", F3(2, 0x0b, 0), F3(~2, ~0x0b, ~0)|ASI(~0), "1,2,d", 0, v8 },
1235{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "1,i,d", 0, v8 },
1236{ "smul", F3(2, 0x0b, 1), F3(~2, ~0x0b, ~1), "i,1,d", 0, v8 },
1237{ "smulcc", F3(2, 0x1b, 0), F3(~2, ~0x1b, ~0)|ASI(~0), "1,2,d", 0, v8 },
1238{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "1,i,d", 0, v8 },
1239{ "smulcc", F3(2, 0x1b, 1), F3(~2, ~0x1b, ~1), "i,1,d", 0, v8 },
1240{ "umul", F3(2, 0x0a, 0), F3(~2, ~0x0a, ~0)|ASI(~0), "1,2,d", 0, v8 },
1241{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "1,i,d", 0, v8 },
1242{ "umul", F3(2, 0x0a, 1), F3(~2, ~0x0a, ~1), "i,1,d", 0, v8 },
1243{ "umulcc", F3(2, 0x1a, 0), F3(~2, ~0x1a, ~0)|ASI(~0), "1,2,d", 0, v8 },
1244{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "1,i,d", 0, v8 },
1245{ "umulcc", F3(2, 0x1a, 1), F3(~2, ~0x1a, ~1), "i,1,d", 0, v8 },
1246{ "sdiv", F3(2, 0x0f, 0), F3(~2, ~0x0f, ~0)|ASI(~0), "1,2,d", 0, v8 },
1247{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "1,i,d", 0, v8 },
1248{ "sdiv", F3(2, 0x0f, 1), F3(~2, ~0x0f, ~1), "i,1,d", 0, v8 },
1249{ "sdivcc", F3(2, 0x1f, 0), F3(~2, ~0x1f, ~0)|ASI(~0), "1,2,d", 0, v8 },
1250{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "1,i,d", 0, v8 },
1251{ "sdivcc", F3(2, 0x1f, 1), F3(~2, ~0x1f, ~1), "i,1,d", 0, v8 },
1252{ "udiv", F3(2, 0x0e, 0), F3(~2, ~0x0e, ~0)|ASI(~0), "1,2,d", 0, v8 },
1253{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "1,i,d", 0, v8 },
1254{ "udiv", F3(2, 0x0e, 1), F3(~2, ~0x0e, ~1), "i,1,d", 0, v8 },
1255{ "udivcc", F3(2, 0x1e, 0), F3(~2, ~0x1e, ~0)|ASI(~0), "1,2,d", 0, v8 },
1256{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "1,i,d", 0, v8 },
1257{ "udivcc", F3(2, 0x1e, 1), F3(~2, ~0x1e, ~1), "i,1,d", 0, v8 },
1258
1259{ "mulx", F3(2, 0x09, 0), F3(~2, ~0x09, ~0)|ASI(~0), "1,2,d", 0, v9 },
1260{ "mulx", F3(2, 0x09, 1), F3(~2, ~0x09, ~1), "1,i,d", 0, v9 },
1261{ "sdivx", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, v9 },
1262{ "sdivx", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, v9 },
1263{ "udivx", F3(2, 0x0d, 0), F3(~2, ~0x0d, ~0)|ASI(~0), "1,2,d", 0, v9 },
1264{ "udivx", F3(2, 0x0d, 1), F3(~2, ~0x0d, ~1), "1,i,d", 0, v9 },
1265
1266{ "call", F1(0x1), F1(~0x1), "L", F_JSR|F_DELAYED, v6 },
1267{ "call", F1(0x1), F1(~0x1), "L,#", F_JSR|F_DELAYED, v6 },
1268
1269{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%o7 */
1270{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI(~0), "1+2,#", F_JSR|F_DELAYED, v6 },
1271{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%o7 */
1272{ "call", F3(2, 0x38, 0)|RD(0xf), F3(~2, ~0x38, ~0)|RD(~0xf)|ASI_RS2(~0), "1,#", F_JSR|F_DELAYED, v6 },
1273{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+i,%o7 */
1274{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "1+i,#", F_JSR|F_DELAYED, v6 },
1275{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1", F_JSR|F_DELAYED, v6 }, /* jmpl i+rs1,%o7 */
1276{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf), "i+1,#", F_JSR|F_DELAYED, v6 },
1277{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i", F_JSR|F_DELAYED, v6 }, /* jmpl %g0+i,%o7 */
1278{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|RS1_G0, "i,#", F_JSR|F_DELAYED, v6 },
1279{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1", F_JSR|F_DELAYED, v6 }, /* jmpl rs1+0,%o7 */
1280{ "call", F3(2, 0x38, 1)|RD(0xf), F3(~2, ~0x38, ~1)|RD(~0xf)|SIMM13(~0), "1,#", F_JSR|F_DELAYED, v6 },
aa0aa4fa
FB		 1281
1282
1283/* Conditional instructions.
1284
1285 Because this part of the table was such a mess earlier, I have
1286 macrofied it so that all the branches and traps are generated from
1287 a single-line description of each condition value. John Gilmore. */
1288
1289/* Define branches -- one annulled, one without, etc. */
1290#define br(opcode, mask, lose, flags) \
1291 { opcode, (mask)|ANNUL, (lose), ",a l", (flags), v6 }, \
1292 { opcode, (mask) , (lose)|ANNUL, "l", (flags), v6 }
1293
1294#define brx(opcode, mask, lose, flags) /* v9 */ \
1295 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), "Z,G", (flags), v9 }, \
1296 { opcode, (mask)|(2<<20)|BPRED, ANNUL|(lose), ",T Z,G", (flags), v9 }, \
1297 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a Z,G", (flags), v9 }, \
1298 { opcode, (mask)|(2<<20)|BPRED|ANNUL, (lose), ",a,T Z,G", (flags), v9 }, \
1299 { opcode, (mask)|(2<<20), ANNUL|BPRED|(lose), ",N Z,G", (flags), v9 }, \
1300 { opcode, (mask)|(2<<20)|ANNUL, BPRED|(lose), ",a,N Z,G", (flags), v9 }, \
1301 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), "z,G", (flags), v9 }, \
1302 { opcode, (mask)|BPRED, ANNUL|(lose)|(2<<20), ",T z,G", (flags), v9 }, \
1303 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a z,G", (flags), v9 }, \
1304 { opcode, (mask)|BPRED|ANNUL, (lose)|(2<<20), ",a,T z,G", (flags), v9 }, \
1305 { opcode, (mask), ANNUL|BPRED|(lose)|(2<<20), ",N z,G", (flags), v9 }, \
1306 { opcode, (mask)|ANNUL, BPRED|(lose)|(2<<20), ",a,N z,G", (flags), v9 }
1307
1308/* Define four traps: reg+reg, reg + immediate, immediate alone, reg alone. */
1309#define tr(opcode, mask, lose, flags) \
f930d07e
BS		 1310 { opcode, (mask)|(2<<11)|IMMED, (lose)|RS1_G0, "Z,i", (flags), v9 }, /* %g0 + imm */ \
1311 { opcode, (mask)|(2<<11)|IMMED, (lose), "Z,1+i", (flags), v9 }, /* rs1 + imm */ \
1312 { opcode, (mask)|(2<<11), IMMED|(lose), "Z,1+2", (flags), v9 }, /* rs1 + rs2 */ \
1313 { opcode, (mask)|(2<<11), IMMED|(lose)|RS2_G0, "Z,1", (flags), v9 }, /* rs1 + %g0 */ \
1314 { opcode, (mask)|IMMED, (lose)|RS1_G0, "z,i", (flags)|F_ALIAS, v9 }, /* %g0 + imm */ \
1315 { opcode, (mask)|IMMED, (lose), "z,1+i", (flags)|F_ALIAS, v9 }, /* rs1 + imm */ \
1316 { opcode, (mask), IMMED|(lose), "z,1+2", (flags)|F_ALIAS, v9 }, /* rs1 + rs2 */ \
1317 { opcode, (mask), IMMED|(lose)|RS2_G0, "z,1", (flags)|F_ALIAS, v9 }, /* rs1 + %g0 */ \
1318 { opcode, (mask)|IMMED, (lose)|RS1_G0, "i", (flags), v6 }, /* %g0 + imm */ \
1319 { opcode, (mask)|IMMED, (lose), "1+i", (flags), v6 }, /* rs1 + imm */ \
1320 { opcode, (mask), IMMED|(lose), "1+2", (flags), v6 }, /* rs1 + rs2 */ \
1321 { opcode, (mask), IMMED|(lose)|RS2_G0, "1", (flags), v6 } /* rs1 + %g0 */
aa0aa4fa
FB		 1322
1323/* v9: We must put `brx' before `br', to ensure that we never match something
1324 v9: against an expression unless it is an expression. Otherwise, we end
1325 v9: up with undefined symbol tables entries, because they get added, but
1326 v9: are not deleted if the pattern fails to match. */
1327
1328/* Define both branches and traps based on condition mask */
1329#define cond(bop, top, mask, flags) \
1330 brx(bop, F2(0, 1)|(mask), F2(~0, ~1)|((~mask)&COND(~0)), F_DELAYED|(flags)), /* v9 */ \
1331 br(bop, F2(0, 2)|(mask), F2(~0, ~2)|((~mask)&COND(~0)), F_DELAYED|(flags)), \
1332 tr(top, F3(2, 0x3a, 0)|(mask), F3(~2, ~0x3a, 0)|((~mask)&COND(~0)), ((flags) & ~(F_UNBR|F_CONDBR)))
1333
1334/* Define all the conditions, all the branches, all the traps. */
1335
1336/* Standard branch, trap mnemonics */
f930d07e 1337cond ("b", "ta", CONDA, F_UNBR),
aa0aa4fa 1338/* Alternative form (just for assembly, not for disassembly) */
f930d07e
BS		 1339cond ("ba", "t", CONDA, F_UNBR|F_ALIAS),
1340
1341cond ("bcc", "tcc", CONDCC, F_CONDBR),
1342cond ("bcs", "tcs", CONDCS, F_CONDBR),
1343cond ("be", "te", CONDE, F_CONDBR),
1344cond ("beq", "teq", CONDE, F_CONDBR|F_ALIAS),
1345cond ("bg", "tg", CONDG, F_CONDBR),
1346cond ("bgt", "tgt", CONDG, F_CONDBR|F_ALIAS),
1347cond ("bge", "tge", CONDGE, F_CONDBR),
1348cond ("bgeu", "tgeu", CONDGEU, F_CONDBR|F_ALIAS), /* for cc */
1349cond ("bgu", "tgu", CONDGU, F_CONDBR),
1350cond ("bl", "tl", CONDL, F_CONDBR),
1351cond ("blt", "tlt", CONDL, F_CONDBR|F_ALIAS),
1352cond ("ble", "tle", CONDLE, F_CONDBR),
1353cond ("bleu", "tleu", CONDLEU, F_CONDBR),
1354cond ("blu", "tlu", CONDLU, F_CONDBR|F_ALIAS), /* for cs */
1355cond ("bn", "tn", CONDN, F_CONDBR),
1356cond ("bne", "tne", CONDNE, F_CONDBR),
1357cond ("bneg", "tneg", CONDNEG, F_CONDBR),
1358cond ("bnz", "tnz", CONDNZ, F_CONDBR|F_ALIAS), /* for ne */
1359cond ("bpos", "tpos", CONDPOS, F_CONDBR),
1360cond ("bvc", "tvc", CONDVC, F_CONDBR),
1361cond ("bvs", "tvs", CONDVS, F_CONDBR),
1362cond ("bz", "tz", CONDZ, F_CONDBR|F_ALIAS), /* for e */
aa0aa4fa
FB		 1363
1364#undef cond
1365#undef br
1366#undef brr /* v9 */
1367#undef tr
1368
1369#define brr(opcode, mask, lose, flags) /* v9 */ \
1370 { opcode, (mask)|BPRED, ANNUL|(lose), "1,k", F_DELAYED|(flags), v9 }, \
1371 { opcode, (mask)|BPRED, ANNUL|(lose), ",T 1,k", F_DELAYED|(flags), v9 }, \
1372 { opcode, (mask)|BPRED|ANNUL, (lose), ",a 1,k", F_DELAYED|(flags), v9 }, \
1373 { opcode, (mask)|BPRED|ANNUL, (lose), ",a,T 1,k", F_DELAYED|(flags), v9 }, \
1374 { opcode, (mask), ANNUL|BPRED|(lose), ",N 1,k", F_DELAYED|(flags), v9 }, \
1375 { opcode, (mask)|ANNUL, BPRED|(lose), ",a,N 1,k", F_DELAYED|(flags), v9 }
1376
1377#define condr(bop, mask, flags) /* v9 */ \
1378 brr(bop, F2(0, 3)|COND(mask), F2(~0, ~3)|COND(~(mask)), (flags)) /* v9 */
1379
1380/* v9 */ condr("brnz", 0x5, F_CONDBR),
1381/* v9 */ condr("brz", 0x1, F_CONDBR),
1382/* v9 */ condr("brgez", 0x7, F_CONDBR),
1383/* v9 */ condr("brlz", 0x3, F_CONDBR),
1384/* v9 */ condr("brlez", 0x2, F_CONDBR),
1385/* v9 */ condr("brgz", 0x6, F_CONDBR),
1386
1387#undef condr /* v9 */
1388#undef brr /* v9 */
1389
1390#define movr(opcode, mask, flags) /* v9 */ \
1391 { opcode, F3(2, 0x2f, 0)|RCOND(mask), F3(~2, ~0x2f, ~0)|RCOND(~(mask)), "1,2,d", (flags), v9 }, \
1392 { opcode, F3(2, 0x2f, 1)|RCOND(mask), F3(~2, ~0x2f, ~1)|RCOND(~(mask)), "1,j,d", (flags), v9 }
1393
1394#define fmrrs(opcode, mask, lose, flags) /* v9 */ \
1395 { opcode, (mask), (lose), "1,f,g", (flags) | F_FLOAT, v9 }
1396#define fmrrd(opcode, mask, lose, flags) /* v9 */ \
1397 { opcode, (mask), (lose), "1,B,H", (flags) | F_FLOAT, v9 }
1398#define fmrrq(opcode, mask, lose, flags) /* v9 */ \
1399 { opcode, (mask), (lose), "1,R,J", (flags) | F_FLOAT, v9 }
1400
1401#define fmovrs(mop, mask, flags) /* v9 */ \
1402 fmrrs(mop, F3(2, 0x35, 0)|OPF_LOW5(5)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~5)|RCOND(~(mask)), (flags)) /* v9 */
1403#define fmovrd(mop, mask, flags) /* v9 */ \
1404 fmrrd(mop, F3(2, 0x35, 0)|OPF_LOW5(6)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~6)|RCOND(~(mask)), (flags)) /* v9 */
1405#define fmovrq(mop, mask, flags) /* v9 */ \
1406 fmrrq(mop, F3(2, 0x35, 0)|OPF_LOW5(7)|RCOND(mask), F3(~2, ~0x35, 0)|OPF_LOW5(~7)|RCOND(~(mask)), (flags)) /* v9 */
1407
1408/* v9 */ movr("movrne", 0x5, 0),
1409/* v9 */ movr("movre", 0x1, 0),
1410/* v9 */ movr("movrgez", 0x7, 0),
1411/* v9 */ movr("movrlz", 0x3, 0),
1412/* v9 */ movr("movrlez", 0x2, 0),
1413/* v9 */ movr("movrgz", 0x6, 0),
1414/* v9 */ movr("movrnz", 0x5, F_ALIAS),
1415/* v9 */ movr("movrz", 0x1, F_ALIAS),
1416
1417/* v9 */ fmovrs("fmovrsne", 0x5, 0),
1418/* v9 */ fmovrs("fmovrse", 0x1, 0),
1419/* v9 */ fmovrs("fmovrsgez", 0x7, 0),
1420/* v9 */ fmovrs("fmovrslz", 0x3, 0),
1421/* v9 */ fmovrs("fmovrslez", 0x2, 0),
1422/* v9 */ fmovrs("fmovrsgz", 0x6, 0),
1423/* v9 */ fmovrs("fmovrsnz", 0x5, F_ALIAS),
1424/* v9 */ fmovrs("fmovrsz", 0x1, F_ALIAS),
1425
1426/* v9 */ fmovrd("fmovrdne", 0x5, 0),
1427/* v9 */ fmovrd("fmovrde", 0x1, 0),
1428/* v9 */ fmovrd("fmovrdgez", 0x7, 0),
1429/* v9 */ fmovrd("fmovrdlz", 0x3, 0),
1430/* v9 */ fmovrd("fmovrdlez", 0x2, 0),
1431/* v9 */ fmovrd("fmovrdgz", 0x6, 0),
1432/* v9 */ fmovrd("fmovrdnz", 0x5, F_ALIAS),
1433/* v9 */ fmovrd("fmovrdz", 0x1, F_ALIAS),
1434
1435/* v9 */ fmovrq("fmovrqne", 0x5, 0),
1436/* v9 */ fmovrq("fmovrqe", 0x1, 0),
1437/* v9 */ fmovrq("fmovrqgez", 0x7, 0),
1438/* v9 */ fmovrq("fmovrqlz", 0x3, 0),
1439/* v9 */ fmovrq("fmovrqlez", 0x2, 0),
1440/* v9 */ fmovrq("fmovrqgz", 0x6, 0),
1441/* v9 */ fmovrq("fmovrqnz", 0x5, F_ALIAS),
1442/* v9 */ fmovrq("fmovrqz", 0x1, F_ALIAS),
1443
1444#undef movr /* v9 */
1445#undef fmovr /* v9 */
1446#undef fmrr /* v9 */
1447
1448#define movicc(opcode, cond, flags) /* v9 */ \
1449 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|XCC|(1<<11), "z,2,d", flags, v9 }, \
1450 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|ICC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|XCC|(1<<11), "z,I,d", flags, v9 }, \
1451 { opcode, F3(2, 0x2c, 0)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~0)|MCOND(~cond,~1)|(1<<11), "Z,2,d", flags, v9 }, \
1452 { opcode, F3(2, 0x2c, 1)|MCOND(cond,1)|XCC, F3(~2, ~0x2c, ~1)|MCOND(~cond,~1)|(1<<11), "Z,I,d", flags, v9 }
1453
1454#define movfcc(opcode, fcond, flags) /* v9 */ \
1455 { opcode, F3(2, 0x2c, 0)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~0), "6,2,d", flags, v9 }, \
1456 { opcode, F3(2, 0x2c, 1)|FCC(0)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~0)|F3(~2, ~0x2c, ~1), "6,I,d", flags, v9 }, \
1457 { opcode, F3(2, 0x2c, 0)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~0), "7,2,d", flags, v9 }, \
1458 { opcode, F3(2, 0x2c, 1)|FCC(1)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~1)|F3(~2, ~0x2c, ~1), "7,I,d", flags, v9 }, \
1459 { opcode, F3(2, 0x2c, 0)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~0), "8,2,d", flags, v9 }, \
1460 { opcode, F3(2, 0x2c, 1)|FCC(2)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~2)|F3(~2, ~0x2c, ~1), "8,I,d", flags, v9 }, \
1461 { opcode, F3(2, 0x2c, 0)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~0), "9,2,d", flags, v9 }, \
1462 { opcode, F3(2, 0x2c, 1)|FCC(3)|MCOND(fcond,0), MCOND(~fcond,~0)|FCC(~3)|F3(~2, ~0x2c, ~1), "9,I,d", flags, v9 }
1463
1464#define movcc(opcode, cond, fcond, flags) /* v9 */ \
1465 movfcc (opcode, fcond, flags), /* v9 */ \
1466 movicc (opcode, cond, flags) /* v9 */
1467
f930d07e
BS		 1468/* v9 */ movcc ("mova", CONDA, FCONDA, 0),
1469/* v9 */ movicc ("movcc", CONDCC, 0),
1470/* v9 */ movicc ("movgeu", CONDGEU, F_ALIAS),
1471/* v9 */ movicc ("movcs", CONDCS, 0),
1472/* v9 */ movicc ("movlu", CONDLU, F_ALIAS),
1473/* v9 */ movcc ("move", CONDE, FCONDE, 0),
1474/* v9 */ movcc ("movg", CONDG, FCONDG, 0),
1475/* v9 */ movcc ("movge", CONDGE, FCONDGE, 0),
1476/* v9 */ movicc ("movgu", CONDGU, 0),
1477/* v9 */ movcc ("movl", CONDL, FCONDL, 0),
1478/* v9 */ movcc ("movle", CONDLE, FCONDLE, 0),
1479/* v9 */ movicc ("movleu", CONDLEU, 0),
1480/* v9 */ movfcc ("movlg", FCONDLG, 0),
1481/* v9 */ movcc ("movn", CONDN, FCONDN, 0),
1482/* v9 */ movcc ("movne", CONDNE, FCONDNE, 0),
1483/* v9 */ movicc ("movneg", CONDNEG, 0),
1484/* v9 */ movcc ("movnz", CONDNZ, FCONDNZ, F_ALIAS),
1485/* v9 */ movfcc ("movo", FCONDO, 0),
1486/* v9 */ movicc ("movpos", CONDPOS, 0),
1487/* v9 */ movfcc ("movu", FCONDU, 0),
1488/* v9 */ movfcc ("movue", FCONDUE, 0),
1489/* v9 */ movfcc ("movug", FCONDUG, 0),
1490/* v9 */ movfcc ("movuge", FCONDUGE, 0),
1491/* v9 */ movfcc ("movul", FCONDUL, 0),
1492/* v9 */ movfcc ("movule", FCONDULE, 0),
1493/* v9 */ movicc ("movvc", CONDVC, 0),
1494/* v9 */ movicc ("movvs", CONDVS, 0),
1495/* v9 */ movcc ("movz", CONDZ, FCONDZ, F_ALIAS),
aa0aa4fa
FB		 1496
1497#undef movicc /* v9 */
1498#undef movfcc /* v9 */
1499#undef movcc /* v9 */
1500
f930d07e
BS		 1501#define FM_SF 1 /* v9 - values for fpsize */
1502#define FM_DF 2 /* v9 */
1503#define FM_QF 3 /* v9 */
aa0aa4fa 1504
46f42f29
BS		 1505#define fmoviccx(opcode, fpsize, args, cond, flags) /* v9 */ \
1506{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags, v9 }, \
1507{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags, v9 }
aa0aa4fa 1508
46f42f29
BS		 1509#define fmovfccx(opcode, fpsize, args, fcond, flags) /* v9 */ \
1510{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags, v9 }, \
1511{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags, v9 }, \
1512{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags, v9 }, \
1513{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags, v9 }
aa0aa4fa
FB		 1514
1515/* FIXME: use fmovicc/fmovfcc? */ /* v9 */
46f42f29
BS		 1516#define fmovccx(opcode, fpsize, args, cond, fcond, flags) /* v9 */ \
1517{ opcode, F3F(2, 0x35, 0x100+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x100+fpsize))|MCOND(~cond,~0), "z," args, flags | F_FLOAT, v9 }, \
1518{ opcode, F3F(2, 0x35, 0x000+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x000+fpsize))|MCOND(~fcond,~0), "6," args, flags | F_FLOAT, v9 }, \
1519{ opcode, F3F(2, 0x35, 0x180+fpsize)|MCOND(cond,0), F3F(~2, ~0x35, ~(0x180+fpsize))|MCOND(~cond,~0), "Z," args, flags | F_FLOAT, v9 }, \
1520{ opcode, F3F(2, 0x35, 0x040+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x040+fpsize))|MCOND(~fcond,~0), "7," args, flags | F_FLOAT, v9 }, \
1521{ opcode, F3F(2, 0x35, 0x080+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x080+fpsize))|MCOND(~fcond,~0), "8," args, flags | F_FLOAT, v9 }, \
1522{ opcode, F3F(2, 0x35, 0x0c0+fpsize)|MCOND(fcond,0), F3F(~2, ~0x35, ~(0x0c0+fpsize))|MCOND(~fcond,~0), "9," args, flags | F_FLOAT, v9 }
1523
1524#define fmovicc(suffix, cond, flags) /* v9 */ \
1525fmoviccx("fmovd" suffix, FM_DF, "B,H", cond, flags), \
1526fmoviccx("fmovq" suffix, FM_QF, "R,J", cond, flags), \
1527fmoviccx("fmovs" suffix, FM_SF, "f,g", cond, flags)
1528
1529#define fmovfcc(suffix, fcond, flags) /* v9 */ \
1530fmovfccx("fmovd" suffix, FM_DF, "B,H", fcond, flags), \
1531fmovfccx("fmovq" suffix, FM_QF, "R,J", fcond, flags), \
1532fmovfccx("fmovs" suffix, FM_SF, "f,g", fcond, flags)
1533
1534#define fmovcc(suffix, cond, fcond, flags) /* v9 */ \
1535fmovccx("fmovd" suffix, FM_DF, "B,H", cond, fcond, flags), \
1536fmovccx("fmovq" suffix, FM_QF, "R,J", cond, fcond, flags), \
1537fmovccx("fmovs" suffix, FM_SF, "f,g", cond, fcond, flags)
1538
1539/* v9 */ fmovcc ("a", CONDA, FCONDA, 0),
1540/* v9 */ fmovicc ("cc", CONDCC, 0),
1541/* v9 */ fmovicc ("cs", CONDCS, 0),
1542/* v9 */ fmovcc ("e", CONDE, FCONDE, 0),
1543/* v9 */ fmovcc ("g", CONDG, FCONDG, 0),
1544/* v9 */ fmovcc ("ge", CONDGE, FCONDGE, 0),
1545/* v9 */ fmovicc ("geu", CONDGEU, F_ALIAS),
1546/* v9 */ fmovicc ("gu", CONDGU, 0),
1547/* v9 */ fmovcc ("l", CONDL, FCONDL, 0),
1548/* v9 */ fmovcc ("le", CONDLE, FCONDLE, 0),
1549/* v9 */ fmovicc ("leu", CONDLEU, 0),
1550/* v9 */ fmovfcc ("lg", FCONDLG, 0),
1551/* v9 */ fmovicc ("lu", CONDLU, F_ALIAS),
1552/* v9 */ fmovcc ("n", CONDN, FCONDN, 0),
1553/* v9 */ fmovcc ("ne", CONDNE, FCONDNE, 0),
1554/* v9 */ fmovicc ("neg", CONDNEG, 0),
1555/* v9 */ fmovcc ("nz", CONDNZ, FCONDNZ, F_ALIAS),
1556/* v9 */ fmovfcc ("o", FCONDO, 0),
1557/* v9 */ fmovicc ("pos", CONDPOS, 0),
1558/* v9 */ fmovfcc ("u", FCONDU, 0),
1559/* v9 */ fmovfcc ("ue", FCONDUE, 0),
1560/* v9 */ fmovfcc ("ug", FCONDUG, 0),
1561/* v9 */ fmovfcc ("uge", FCONDUGE, 0),
1562/* v9 */ fmovfcc ("ul", FCONDUL, 0),
1563/* v9 */ fmovfcc ("ule", FCONDULE, 0),
1564/* v9 */ fmovicc ("vc", CONDVC, 0),
1565/* v9 */ fmovicc ("vs", CONDVS, 0),
1566/* v9 */ fmovcc ("z", CONDZ, FCONDZ, F_ALIAS),
1567
1568#undef fmoviccx /* v9 */
1569#undef fmovfccx /* v9 */
1570#undef fmovccx /* v9 */
aa0aa4fa
FB		 1571#undef fmovicc /* v9 */
1572#undef fmovfcc /* v9 */
1573#undef fmovcc /* v9 */
1574#undef FM_DF /* v9 */
1575#undef FM_QF /* v9 */
1576#undef FM_SF /* v9 */
1577
1578/* Coprocessor branches. */
1579#define CBR(opcode, mask, lose, flags, arch) \
46f42f29
BS		 1580 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED, arch }, \
1581 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED, arch }
aa0aa4fa
FB		 1582
1583/* Floating point branches. */
1584#define FBR(opcode, mask, lose, flags) \
46f42f29
BS		 1585 { opcode, (mask), ANNUL | (lose), "l", flags | F_DELAYED | F_FBR, v6 }, \
1586 { opcode, (mask) | ANNUL, (lose), ",a l", flags | F_DELAYED | F_FBR, v6 }
aa0aa4fa
FB		 1587
1588/* V9 extended floating point branches. */
1589#define FBRX(opcode, mask, lose, flags) /* v9 */ \
1590 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), "6,G", flags|F_DELAYED|F_FBR, v9 }, \
1591 { opcode, FBFCC(0)|(mask)|BPRED, ANNUL|FBFCC(~0)|(lose), ",T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1592 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1593 { opcode, FBFCC(0)|(mask)|BPRED|ANNUL, FBFCC(~0)|(lose), ",a,T 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1594 { opcode, FBFCC(0)|(mask), ANNUL|BPRED|FBFCC(~0)|(lose), ",N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1595 { opcode, FBFCC(0)|(mask)|ANNUL, BPRED|FBFCC(~0)|(lose), ",a,N 6,G", flags|F_DELAYED|F_FBR, v9 }, \
1596 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), "7,G", flags|F_DELAYED|F_FBR, v9 }, \
1597 { opcode, FBFCC(1)|(mask)|BPRED, ANNUL|FBFCC(~1)|(lose), ",T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1598 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1599 { opcode, FBFCC(1)|(mask)|BPRED|ANNUL, FBFCC(~1)|(lose), ",a,T 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1600 { opcode, FBFCC(1)|(mask), ANNUL|BPRED|FBFCC(~1)|(lose), ",N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1601 { opcode, FBFCC(1)|(mask)|ANNUL, BPRED|FBFCC(~1)|(lose), ",a,N 7,G", flags|F_DELAYED|F_FBR, v9 }, \
1602 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), "8,G", flags|F_DELAYED|F_FBR, v9 }, \
1603 { opcode, FBFCC(2)|(mask)|BPRED, ANNUL|FBFCC(~2)|(lose), ",T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1604 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1605 { opcode, FBFCC(2)|(mask)|BPRED|ANNUL, FBFCC(~2)|(lose), ",a,T 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1606 { opcode, FBFCC(2)|(mask), ANNUL|BPRED|FBFCC(~2)|(lose), ",N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1607 { opcode, FBFCC(2)|(mask)|ANNUL, BPRED|FBFCC(~2)|(lose), ",a,N 8,G", flags|F_DELAYED|F_FBR, v9 }, \
1608 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), "9,G", flags|F_DELAYED|F_FBR, v9 }, \
1609 { opcode, FBFCC(3)|(mask)|BPRED, ANNUL|FBFCC(~3)|(lose), ",T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1610 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1611 { opcode, FBFCC(3)|(mask)|BPRED|ANNUL, FBFCC(~3)|(lose), ",a,T 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1612 { opcode, FBFCC(3)|(mask), ANNUL|BPRED|FBFCC(~3)|(lose), ",N 9,G", flags|F_DELAYED|F_FBR, v9 }, \
1613 { opcode, FBFCC(3)|(mask)|ANNUL, BPRED|FBFCC(~3)|(lose), ",a,N 9,G", flags|F_DELAYED|F_FBR, v9 }
1614
1615/* v9: We must put `FBRX' before `FBR', to ensure that we never match
1616 v9: something against an expression unless it is an expression. Otherwise,
1617 v9: we end up with undefined symbol tables entries, because they get added,
1618 v9: but are not deleted if the pattern fails to match. */
1619
1620#define CONDFC(fop, cop, mask, flags) \
1621 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1622 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1623 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6notlet)
1624
1625#define CONDFCL(fop, cop, mask, flags) \
1626 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1627 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags), \
1628 CBR(cop, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)), flags, v6)
1629
1630#define CONDF(fop, mask, flags) \
1631 FBRX(fop, F2(0, 5)|COND(mask), F2(~0, ~5)|COND(~(mask)), flags), /* v9 */ \
1632 FBR(fop, F2(0, 6)|COND(mask), F2(~0, ~6)|COND(~(mask)), flags)
1633
1634CONDFC ("fb", "cb", 0x8, F_UNBR),
f930d07e
BS		 1635CONDFCL ("fba", "cba", 0x8, F_UNBR|F_ALIAS),
1636CONDFC ("fbe", "cb0", 0x9, F_CONDBR),
aa0aa4fa 1637CONDF ("fbz", 0x9, F_CONDBR|F_ALIAS),
f930d07e 1638CONDFC ("fbg", "cb2", 0x6, F_CONDBR),
aa0aa4fa 1639CONDFC ("fbge", "cb02", 0xb, F_CONDBR),
f930d07e 1640CONDFC ("fbl", "cb1", 0x4, F_CONDBR),
aa0aa4fa
FB		 1641CONDFC ("fble", "cb01", 0xd, F_CONDBR),
1642CONDFC ("fblg", "cb12", 0x2, F_CONDBR),
f930d07e 1643CONDFCL ("fbn", "cbn", 0x0, F_UNBR),
aa0aa4fa
FB		 1644CONDFC ("fbne", "cb123", 0x1, F_CONDBR),
1645CONDF ("fbnz", 0x1, F_CONDBR|F_ALIAS),
f930d07e
BS		 1646CONDFC ("fbo", "cb012", 0xf, F_CONDBR),
1647CONDFC ("fbu", "cb3", 0x7, F_CONDBR),
aa0aa4fa
FB		 1648CONDFC ("fbue", "cb03", 0xa, F_CONDBR),
1649CONDFC ("fbug", "cb23", 0x5, F_CONDBR),
1650CONDFC ("fbuge", "cb023", 0xc, F_CONDBR),
1651CONDFC ("fbul", "cb13", 0x3, F_CONDBR),
1652CONDFC ("fbule", "cb013", 0xe, F_CONDBR),
1653
1654#undef CONDFC
1655#undef CONDFCL
1656#undef CONDF
1657#undef CBR
1658#undef FBR
f930d07e 1659#undef FBRX /* v9 */
aa0aa4fa 1660
f930d07e
BS		 1661{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI(~0), "1+2", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+rs2,%g0 */
1662{ "jmp", F3(2, 0x38, 0), F3(~2, ~0x38, ~0)|RD_G0|ASI_RS2(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+%g0,%g0 */
1663{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "1+i", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+i,%g0 */
1664{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0, "i+1", F_UNBR|F_DELAYED, v6 }, /* jmpl i+rs1,%g0 */
1665{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|RS1_G0, "i", F_UNBR|F_DELAYED, v6 }, /* jmpl %g0+i,%g0 */
1666{ "jmp", F3(2, 0x38, 1), F3(~2, ~0x38, ~1)|RD_G0|SIMM13(~0), "1", F_UNBR|F_DELAYED, v6 }, /* jmpl rs1+0,%g0 */
aa0aa4fa 1667
f930d07e 1668{ "nop", F2(0, 4), 0xfeffffff, "", 0, v6 }, /* sethi 0, %g0 */
aa0aa4fa 1669
f930d07e
BS		 1670{ "set", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v6 },
1671{ "setuw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
1672{ "setsw", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,d", F_ALIAS, v9 },
1673{ "setx", F2(0x0, 0x4), F2(~0x0, ~0x4), "S0,1,d", F_ALIAS, v9 },
aa0aa4fa 1674
f930d07e 1675{ "sethi", F2(0x0, 0x4), F2(~0x0, ~0x4), "h,d", 0, v6 },
aa0aa4fa 1676
f930d07e
BS		 1677{ "taddcc", F3(2, 0x20, 0), F3(~2, ~0x20, ~0)|ASI(~0), "1,2,d", 0, v6 },
1678{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "1,i,d", 0, v6 },
1679{ "taddcc", F3(2, 0x20, 1), F3(~2, ~0x20, ~1), "i,1,d", 0, v6 },
1680{ "taddcctv", F3(2, 0x22, 0), F3(~2, ~0x22, ~0)|ASI(~0), "1,2,d", 0, v6 },
1681{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "1,i,d", 0, v6 },
1682{ "taddcctv", F3(2, 0x22, 1), F3(~2, ~0x22, ~1), "i,1,d", 0, v6 },
aa0aa4fa 1683
f930d07e
BS		 1684{ "tsubcc", F3(2, 0x21, 0), F3(~2, ~0x21, ~0)|ASI(~0), "1,2,d", 0, v6 },
1685{ "tsubcc", F3(2, 0x21, 1), F3(~2, ~0x21, ~1), "1,i,d", 0, v6 },
1686{ "tsubcctv", F3(2, 0x23, 0), F3(~2, ~0x23, ~0)|ASI(~0), "1,2,d", 0, v6 },
1687{ "tsubcctv", F3(2, 0x23, 1), F3(~2, ~0x23, ~1), "1,i,d", 0, v6 },
aa0aa4fa 1688
f930d07e
BS		 1689{ "unimp", F2(0x0, 0x0), 0xffc00000, "n", 0, v6notv9 },
1690{ "illtrap", F2(0, 0), F2(~0, ~0)|RD_G0, "n", 0, v9 },
aa0aa4fa
FB		 1691
1692/* This *is* a commutative instruction. */
f930d07e
BS		 1693{ "xnor", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,2,d", 0, v6 },
1694{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "1,i,d", 0, v6 },
1695{ "xnor", F3(2, 0x07, 1), F3(~2, ~0x07, ~1), "i,1,d", 0, v6 },
aa0aa4fa 1696/* This *is* a commutative instruction. */
f930d07e
BS		 1697{ "xnorcc", F3(2, 0x17, 0), F3(~2, ~0x17, ~0)|ASI(~0), "1,2,d", 0, v6 },
1698{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "1,i,d", 0, v6 },
1699{ "xnorcc", F3(2, 0x17, 1), F3(~2, ~0x17, ~1), "i,1,d", 0, v6 },
1700{ "xor", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "1,2,d", 0, v6 },
1701{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "1,i,d", 0, v6 },
1702{ "xor", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,1,d", 0, v6 },
1703{ "xorcc", F3(2, 0x13, 0), F3(~2, ~0x13, ~0)|ASI(~0), "1,2,d", 0, v6 },
1704{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "1,i,d", 0, v6 },
1705{ "xorcc", F3(2, 0x13, 1), F3(~2, ~0x13, ~1), "i,1,d", 0, v6 },
1706
1707{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "1,d", F_ALIAS, v6 }, /* xnor rs1,%0,rd */
1708{ "not", F3(2, 0x07, 0), F3(~2, ~0x07, ~0)|ASI(~0), "r", F_ALIAS, v6 }, /* xnor rd,%0,rd */
1709
1710{ "btog", F3(2, 0x03, 0), F3(~2, ~0x03, ~0)|ASI(~0), "2,r", F_ALIAS, v6 }, /* xor rd,rs2,rd */
1711{ "btog", F3(2, 0x03, 1), F3(~2, ~0x03, ~1), "i,r", F_ALIAS, v6 }, /* xor rd,i,rd */
aa0aa4fa
FB		 1712
1713/* FPop1 and FPop2 are not instructions. Don't accept them. */
1714
f930d07e
BS		 1715{ "fdtoi", F3F(2, 0x34, 0x0d2), F3F(~2, ~0x34, ~0x0d2)|RS1_G0, "B,g", F_FLOAT, v6 },
1716{ "fstoi", F3F(2, 0x34, 0x0d1), F3F(~2, ~0x34, ~0x0d1)|RS1_G0, "f,g", F_FLOAT, v6 },
1717{ "fqtoi", F3F(2, 0x34, 0x0d3), F3F(~2, ~0x34, ~0x0d3)|RS1_G0, "R,g", F_FLOAT, v8 },
1718
46f42f29
BS		 1719{ "fdtox", F3F(2, 0x34, 0x082), F3F(~2, ~0x34, ~0x082)|RS1_G0, "B,H", F_FLOAT, v9 },
1720{ "fstox", F3F(2, 0x34, 0x081), F3F(~2, ~0x34, ~0x081)|RS1_G0, "f,H", F_FLOAT, v9 },
1721{ "fqtox", F3F(2, 0x34, 0x083), F3F(~2, ~0x34, ~0x083)|RS1_G0, "R,H", F_FLOAT, v9 },
f930d07e
BS		 1722
1723{ "fitod", F3F(2, 0x34, 0x0c8), F3F(~2, ~0x34, ~0x0c8)|RS1_G0, "f,H", F_FLOAT, v6 },
1724{ "fitos", F3F(2, 0x34, 0x0c4), F3F(~2, ~0x34, ~0x0c4)|RS1_G0, "f,g", F_FLOAT, v6 },
1725{ "fitoq", F3F(2, 0x34, 0x0cc), F3F(~2, ~0x34, ~0x0cc)|RS1_G0, "f,J", F_FLOAT, v8 },
1726
46f42f29
BS		 1727{ "fxtod", F3F(2, 0x34, 0x088), F3F(~2, ~0x34, ~0x088)|RS1_G0, "B,H", F_FLOAT, v9 },
1728{ "fxtos", F3F(2, 0x34, 0x084), F3F(~2, ~0x34, ~0x084)|RS1_G0, "B,g", F_FLOAT, v9 },
1729{ "fxtoq", F3F(2, 0x34, 0x08c), F3F(~2, ~0x34, ~0x08c)|RS1_G0, "B,J", F_FLOAT, v9 },
f930d07e
BS		 1730
1731{ "fdtoq", F3F(2, 0x34, 0x0ce), F3F(~2, ~0x34, ~0x0ce)|RS1_G0, "B,J", F_FLOAT, v8 },
1732{ "fdtos", F3F(2, 0x34, 0x0c6), F3F(~2, ~0x34, ~0x0c6)|RS1_G0, "B,g", F_FLOAT, v6 },
1733{ "fqtod", F3F(2, 0x34, 0x0cb), F3F(~2, ~0x34, ~0x0cb)|RS1_G0, "R,H", F_FLOAT, v8 },
1734{ "fqtos", F3F(2, 0x34, 0x0c7), F3F(~2, ~0x34, ~0x0c7)|RS1_G0, "R,g", F_FLOAT, v8 },
1735{ "fstod", F3F(2, 0x34, 0x0c9), F3F(~2, ~0x34, ~0x0c9)|RS1_G0, "f,H", F_FLOAT, v6 },
1736{ "fstoq", F3F(2, 0x34, 0x0cd), F3F(~2, ~0x34, ~0x0cd)|RS1_G0, "f,J", F_FLOAT, v8 },
1737
1738{ "fdivd", F3F(2, 0x34, 0x04e), F3F(~2, ~0x34, ~0x04e), "v,B,H", F_FLOAT, v6 },
1739{ "fdivq", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT, v8 },
1740{ "fdivx", F3F(2, 0x34, 0x04f), F3F(~2, ~0x34, ~0x04f), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1741{ "fdivs", F3F(2, 0x34, 0x04d), F3F(~2, ~0x34, ~0x04d), "e,f,g", F_FLOAT, v6 },
1742{ "fmuld", F3F(2, 0x34, 0x04a), F3F(~2, ~0x34, ~0x04a), "v,B,H", F_FLOAT, v6 },
1743{ "fmulq", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT, v8 },
1744{ "fmulx", F3F(2, 0x34, 0x04b), F3F(~2, ~0x34, ~0x04b), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1745{ "fmuls", F3F(2, 0x34, 0x049), F3F(~2, ~0x34, ~0x049), "e,f,g", F_FLOAT, v6 },
1746
1747{ "fdmulq", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT, v8 },
1748{ "fdmulx", F3F(2, 0x34, 0x06e), F3F(~2, ~0x34, ~0x06e), "v,B,J", F_FLOAT|F_ALIAS, v8 },
1749{ "fsmuld", F3F(2, 0x34, 0x069), F3F(~2, ~0x34, ~0x069), "e,f,H", F_FLOAT, v8 },
1750
1751{ "fsqrtd", F3F(2, 0x34, 0x02a), F3F(~2, ~0x34, ~0x02a)|RS1_G0, "B,H", F_FLOAT, v7 },
1752{ "fsqrtq", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT, v8 },
1753{ "fsqrtx", F3F(2, 0x34, 0x02b), F3F(~2, ~0x34, ~0x02b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v8 },
1754{ "fsqrts", F3F(2, 0x34, 0x029), F3F(~2, ~0x34, ~0x029)|RS1_G0, "f,g", F_FLOAT, v7 },
1755
1756{ "fabsd", F3F(2, 0x34, 0x00a), F3F(~2, ~0x34, ~0x00a)|RS1_G0, "B,H", F_FLOAT, v9 },
1757{ "fabsq", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT, v9 },
1758{ "fabsx", F3F(2, 0x34, 0x00b), F3F(~2, ~0x34, ~0x00b)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1759{ "fabss", F3F(2, 0x34, 0x009), F3F(~2, ~0x34, ~0x009)|RS1_G0, "f,g", F_FLOAT, v6 },
1760{ "fmovd", F3F(2, 0x34, 0x002), F3F(~2, ~0x34, ~0x002)|RS1_G0, "B,H", F_FLOAT, v9 },
1761{ "fmovq", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT, v9 },
1762{ "fmovx", F3F(2, 0x34, 0x003), F3F(~2, ~0x34, ~0x003)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1763{ "fmovs", F3F(2, 0x34, 0x001), F3F(~2, ~0x34, ~0x001)|RS1_G0, "f,g", F_FLOAT, v6 },
1764{ "fnegd", F3F(2, 0x34, 0x006), F3F(~2, ~0x34, ~0x006)|RS1_G0, "B,H", F_FLOAT, v9 },
1765{ "fnegq", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT, v9 },
1766{ "fnegx", F3F(2, 0x34, 0x007), F3F(~2, ~0x34, ~0x007)|RS1_G0, "R,J", F_FLOAT|F_ALIAS, v9 },
1767{ "fnegs", F3F(2, 0x34, 0x005), F3F(~2, ~0x34, ~0x005)|RS1_G0, "f,g", F_FLOAT, v6 },
1768
1769{ "faddd", F3F(2, 0x34, 0x042), F3F(~2, ~0x34, ~0x042), "v,B,H", F_FLOAT, v6 },
1770{ "faddq", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT, v8 },
1771{ "faddx", F3F(2, 0x34, 0x043), F3F(~2, ~0x34, ~0x043), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1772{ "fadds", F3F(2, 0x34, 0x041), F3F(~2, ~0x34, ~0x041), "e,f,g", F_FLOAT, v6 },
1773{ "fsubd", F3F(2, 0x34, 0x046), F3F(~2, ~0x34, ~0x046), "v,B,H", F_FLOAT, v6 },
1774{ "fsubq", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT, v8 },
1775{ "fsubx", F3F(2, 0x34, 0x047), F3F(~2, ~0x34, ~0x047), "V,R,J", F_FLOAT|F_ALIAS, v8 },
1776{ "fsubs", F3F(2, 0x34, 0x045), F3F(~2, ~0x34, ~0x045), "e,f,g", F_FLOAT, v6 },
1777
1778#define CMPFCC(x) (((x)&0x3)<<25)
1779
1780{ "fcmpd", F3F(2, 0x35, 0x052), F3F(~2, ~0x35, ~0x052)|RD_G0, "v,B", F_FLOAT, v6 },
1781{ "fcmpd", CMPFCC(0)|F3F(2, 0x35, 0x052), CMPFCC(~0)|F3F(~2, ~0x35, ~0x052), "6,v,B", F_FLOAT, v9 },
1782{ "fcmpd", CMPFCC(1)|F3F(2, 0x35, 0x052), CMPFCC(~1)|F3F(~2, ~0x35, ~0x052), "7,v,B", F_FLOAT, v9 },
1783{ "fcmpd", CMPFCC(2)|F3F(2, 0x35, 0x052), CMPFCC(~2)|F3F(~2, ~0x35, ~0x052), "8,v,B", F_FLOAT, v9 },
1784{ "fcmpd", CMPFCC(3)|F3F(2, 0x35, 0x052), CMPFCC(~3)|F3F(~2, ~0x35, ~0x052), "9,v,B", F_FLOAT, v9 },
1785{ "fcmped", F3F(2, 0x35, 0x056), F3F(~2, ~0x35, ~0x056)|RD_G0, "v,B", F_FLOAT, v6 },
1786{ "fcmped", CMPFCC(0)|F3F(2, 0x35, 0x056), CMPFCC(~0)|F3F(~2, ~0x35, ~0x056), "6,v,B", F_FLOAT, v9 },
1787{ "fcmped", CMPFCC(1)|F3F(2, 0x35, 0x056), CMPFCC(~1)|F3F(~2, ~0x35, ~0x056), "7,v,B", F_FLOAT, v9 },
1788{ "fcmped", CMPFCC(2)|F3F(2, 0x35, 0x056), CMPFCC(~2)|F3F(~2, ~0x35, ~0x056), "8,v,B", F_FLOAT, v9 },
1789{ "fcmped", CMPFCC(3)|F3F(2, 0x35, 0x056), CMPFCC(~3)|F3F(~2, ~0x35, ~0x056), "9,v,B", F_FLOAT, v9 },
1790{ "fcmpq", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT, v8 },
1791{ "fcmpq", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT, v9 },
1792{ "fcmpq", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT, v9 },
1793{ "fcmpq", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT, v9 },
1794{ "fcmpq", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT, v9 },
1795{ "fcmpeq", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT, v8 },
1796{ "fcmpeq", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT, v9 },
1797{ "fcmpeq", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT, v9 },
1798{ "fcmpeq", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT, v9 },
1799{ "fcmpeq", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT, v9 },
1800{ "fcmpx", F3F(2, 0x35, 0x053), F3F(~2, ~0x35, ~0x053)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 },
1801{ "fcmpx", CMPFCC(0)|F3F(2, 0x35, 0x053), CMPFCC(~0)|F3F(~2, ~0x35, ~0x053), "6,V,R", F_FLOAT|F_ALIAS, v9 },
1802{ "fcmpx", CMPFCC(1)|F3F(2, 0x35, 0x053), CMPFCC(~1)|F3F(~2, ~0x35, ~0x053), "7,V,R", F_FLOAT|F_ALIAS, v9 },
1803{ "fcmpx", CMPFCC(2)|F3F(2, 0x35, 0x053), CMPFCC(~2)|F3F(~2, ~0x35, ~0x053), "8,V,R", F_FLOAT|F_ALIAS, v9 },
1804{ "fcmpx", CMPFCC(3)|F3F(2, 0x35, 0x053), CMPFCC(~3)|F3F(~2, ~0x35, ~0x053), "9,V,R", F_FLOAT|F_ALIAS, v9 },
1805{ "fcmpex", F3F(2, 0x35, 0x057), F3F(~2, ~0x35, ~0x057)|RD_G0, "V,R", F_FLOAT|F_ALIAS, v8 },
1806{ "fcmpex", CMPFCC(0)|F3F(2, 0x35, 0x057), CMPFCC(~0)|F3F(~2, ~0x35, ~0x057), "6,V,R", F_FLOAT|F_ALIAS, v9 },
1807{ "fcmpex", CMPFCC(1)|F3F(2, 0x35, 0x057), CMPFCC(~1)|F3F(~2, ~0x35, ~0x057), "7,V,R", F_FLOAT|F_ALIAS, v9 },
1808{ "fcmpex", CMPFCC(2)|F3F(2, 0x35, 0x057), CMPFCC(~2)|F3F(~2, ~0x35, ~0x057), "8,V,R", F_FLOAT|F_ALIAS, v9 },
1809{ "fcmpex", CMPFCC(3)|F3F(2, 0x35, 0x057), CMPFCC(~3)|F3F(~2, ~0x35, ~0x057), "9,V,R", F_FLOAT|F_ALIAS, v9 },
1810{ "fcmps", F3F(2, 0x35, 0x051), F3F(~2, ~0x35, ~0x051)|RD_G0, "e,f", F_FLOAT, v6 },
1811{ "fcmps", CMPFCC(0)|F3F(2, 0x35, 0x051), CMPFCC(~0)|F3F(~2, ~0x35, ~0x051), "6,e,f", F_FLOAT, v9 },
1812{ "fcmps", CMPFCC(1)|F3F(2, 0x35, 0x051), CMPFCC(~1)|F3F(~2, ~0x35, ~0x051), "7,e,f", F_FLOAT, v9 },
1813{ "fcmps", CMPFCC(2)|F3F(2, 0x35, 0x051), CMPFCC(~2)|F3F(~2, ~0x35, ~0x051), "8,e,f", F_FLOAT, v9 },
1814{ "fcmps", CMPFCC(3)|F3F(2, 0x35, 0x051), CMPFCC(~3)|F3F(~2, ~0x35, ~0x051), "9,e,f", F_FLOAT, v9 },
1815{ "fcmpes", F3F(2, 0x35, 0x055), F3F(~2, ~0x35, ~0x055)|RD_G0, "e,f", F_FLOAT, v6 },
1816{ "fcmpes", CMPFCC(0)|F3F(2, 0x35, 0x055), CMPFCC(~0)|F3F(~2, ~0x35, ~0x055), "6,e,f", F_FLOAT, v9 },
1817{ "fcmpes", CMPFCC(1)|F3F(2, 0x35, 0x055), CMPFCC(~1)|F3F(~2, ~0x35, ~0x055), "7,e,f", F_FLOAT, v9 },
1818{ "fcmpes", CMPFCC(2)|F3F(2, 0x35, 0x055), CMPFCC(~2)|F3F(~2, ~0x35, ~0x055), "8,e,f", F_FLOAT, v9 },
1819{ "fcmpes", CMPFCC(3)|F3F(2, 0x35, 0x055), CMPFCC(~3)|F3F(~2, ~0x35, ~0x055), "9,e,f", F_FLOAT, v9 },
aa0aa4fa
FB		 1820
1821/* These Extended FPop (FIFO) instructions are new in the Fujitsu
1822 MB86934, replacing the CPop instructions from v6 and later
1823 processors. */
1824
1825#define EFPOP1_2(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op)|RS1_G0, args, 0, sparclite }
1826#define EFPOP1_3(name, op, args) { name, F3F(2, 0x36, op), F3F(~2, ~0x36, ~op), args, 0, sparclite }
1827#define EFPOP2_2(name, op, args) { name, F3F(2, 0x37, op), F3F(~2, ~0x37, ~op)|RD_G0, args, 0, sparclite }
1828
f930d07e
BS		 1829EFPOP1_2 ("efitod", 0x0c8, "f,H"),
1830EFPOP1_2 ("efitos", 0x0c4, "f,g"),
1831EFPOP1_2 ("efdtoi", 0x0d2, "B,g"),
1832EFPOP1_2 ("efstoi", 0x0d1, "f,g"),
1833EFPOP1_2 ("efstod", 0x0c9, "f,H"),
1834EFPOP1_2 ("efdtos", 0x0c6, "B,g"),
1835EFPOP1_2 ("efmovs", 0x001, "f,g"),
1836EFPOP1_2 ("efnegs", 0x005, "f,g"),
1837EFPOP1_2 ("efabss", 0x009, "f,g"),
1838EFPOP1_2 ("efsqrtd", 0x02a, "B,H"),
1839EFPOP1_2 ("efsqrts", 0x029, "f,g"),
1840EFPOP1_3 ("efaddd", 0x042, "v,B,H"),
1841EFPOP1_3 ("efadds", 0x041, "e,f,g"),
1842EFPOP1_3 ("efsubd", 0x046, "v,B,H"),
1843EFPOP1_3 ("efsubs", 0x045, "e,f,g"),
1844EFPOP1_3 ("efdivd", 0x04e, "v,B,H"),
1845EFPOP1_3 ("efdivs", 0x04d, "e,f,g"),
1846EFPOP1_3 ("efmuld", 0x04a, "v,B,H"),
1847EFPOP1_3 ("efmuls", 0x049, "e,f,g"),
1848EFPOP1_3 ("efsmuld", 0x069, "e,f,H"),
1849EFPOP2_2 ("efcmpd", 0x052, "v,B"),
1850EFPOP2_2 ("efcmped", 0x056, "v,B"),
1851EFPOP2_2 ("efcmps", 0x051, "e,f"),
1852EFPOP2_2 ("efcmpes", 0x055, "e,f"),
aa0aa4fa
FB		 1853
1854#undef EFPOP1_2
1855#undef EFPOP1_3
1856#undef EFPOP2_2
1857
1858/* These are marked F_ALIAS, so that they won't conflict with sparclite insns
1859 present. Otherwise, the F_ALIAS flag is ignored. */
f930d07e
BS		 1860{ "cpop1", F3(2, 0x36, 0), F3(~2, ~0x36, ~1), "[1+2],d", F_ALIAS, v6notv9 },
1861{ "cpop2", F3(2, 0x37, 0), F3(~2, ~0x37, ~1), "[1+2],d", F_ALIAS, v6notv9 },
aa0aa4fa
FB		 1862
1863/* sparclet specific insns */
1864
1865COMMUTEOP ("umac", 0x3e, sparclet),
1866COMMUTEOP ("smac", 0x3f, sparclet),
1867COMMUTEOP ("umacd", 0x2e, sparclet),
1868COMMUTEOP ("smacd", 0x2f, sparclet),
1869COMMUTEOP ("umuld", 0x09, sparclet),
1870COMMUTEOP ("smuld", 0x0d, sparclet),
1871
f930d07e
BS		 1872{ "shuffle", F3(2, 0x2d, 0), F3(~2, ~0x2d, ~0)|ASI(~0), "1,2,d", 0, sparclet },
1873{ "shuffle", F3(2, 0x2d, 1), F3(~2, ~0x2d, ~1), "1,i,d", 0, sparclet },
aa0aa4fa
FB		 1874
1875/* The manual isn't completely accurate on these insns. The `rs2' field is
1876 treated as being 6 bits to account for 6 bit immediates to cpush. It is
1877 assumed that it is intended that bit 5 is 0 when rs2 contains a reg. */
1878#define BIT5 (1<<5)
f930d07e
BS		 1879{ "crdcxt", F3(2, 0x36, 0)|SLCPOP(4), F3(~2, ~0x36, ~0)|SLCPOP(~4)|BIT5|RS2(~0), "U,d", 0, sparclet },
1880{ "cwrcxt", F3(2, 0x36, 0)|SLCPOP(3), F3(~2, ~0x36, ~0)|SLCPOP(~3)|BIT5|RS2(~0), "1,u", 0, sparclet },
1881{ "cpush", F3(2, 0x36, 0)|SLCPOP(0), F3(~2, ~0x36, ~0)|SLCPOP(~0)|BIT5|RD(~0), "1,2", 0, sparclet },
1882{ "cpush", F3(2, 0x36, 1)|SLCPOP(0), F3(~2, ~0x36, ~1)|SLCPOP(~0)|RD(~0), "1,Y", 0, sparclet },
1883{ "cpusha", F3(2, 0x36, 0)|SLCPOP(1), F3(~2, ~0x36, ~0)|SLCPOP(~1)|BIT5|RD(~0), "1,2", 0, sparclet },
1884{ "cpusha", F3(2, 0x36, 1)|SLCPOP(1), F3(~2, ~0x36, ~1)|SLCPOP(~1)|RD(~0), "1,Y", 0, sparclet },
1885{ "cpull", F3(2, 0x36, 0)|SLCPOP(2), F3(~2, ~0x36, ~0)|SLCPOP(~2)|BIT5|RS1(~0)|RS2(~0), "d", 0, sparclet },
aa0aa4fa
FB		 1886#undef BIT5
1887
1888/* sparclet coprocessor branch insns */
1889#define SLCBCC2(opcode, mask, lose) \
1890 { opcode, (mask), ANNUL|(lose), "l", F_DELAYED|F_CONDBR, sparclet }, \
1891 { opcode, (mask)|ANNUL, (lose), ",a l", F_DELAYED|F_CONDBR, sparclet }
1892#define SLCBCC(opcode, mask) \
1893 SLCBCC2(opcode, F2(0, 7)|COND(mask), F2(~0, ~7)|COND(~(mask)))
1894
1895/* cbn,cba can't be defined here because they're defined elsewhere and GAS
1896 requires all mnemonics of the same name to be consecutive. */
1897/*SLCBCC("cbn", 0), - already defined */
1898SLCBCC("cbe", 1),
1899SLCBCC("cbf", 2),
1900SLCBCC("cbef", 3),
1901SLCBCC("cbr", 4),
1902SLCBCC("cber", 5),
1903SLCBCC("cbfr", 6),
1904SLCBCC("cbefr", 7),
1905/*SLCBCC("cba", 8), - already defined */
1906SLCBCC("cbne", 9),
1907SLCBCC("cbnf", 10),
1908SLCBCC("cbnef", 11),
1909SLCBCC("cbnr", 12),
1910SLCBCC("cbner", 13),
1911SLCBCC("cbnfr", 14),
1912SLCBCC("cbnefr", 15),
1913
1914#undef SLCBCC2
1915#undef SLCBCC
1916
f930d07e
BS		 1917{ "casa", F3(3, 0x3c, 0), F3(~3, ~0x3c, ~0), "[1]A,2,d", 0, v9 },
1918{ "casa", F3(3, 0x3c, 1), F3(~3, ~0x3c, ~1), "[1]o,2,d", 0, v9 },
1919{ "casxa", F3(3, 0x3e, 0), F3(~3, ~0x3e, ~0), "[1]A,2,d", 0, v9 },
1920{ "casxa", F3(3, 0x3e, 1), F3(~3, ~0x3e, ~1), "[1]o,2,d", 0, v9 },
aa0aa4fa
FB		 1921
1922/* v9 synthetic insns */
f930d07e
BS		 1923{ "iprefetch", F2(0, 1)|(2<<20)|BPRED, F2(~0, ~1)|(1<<20)|ANNUL|COND(~0), "G", 0, v9 }, /* bn,a,pt %xcc,label */
1924{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* sra rs1,%g0,rd */
1925{ "signx", F3(2, 0x27, 0), F3(~2, ~0x27, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* sra rd,%g0,rd */
1926{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "1,d", F_ALIAS, v9 }, /* srl rs1,%g0,rd */
1927{ "clruw", F3(2, 0x26, 0), F3(~2, ~0x26, ~0)|(1<<12)|ASI(~0)|RS2_G0, "r", F_ALIAS, v9 }, /* srl rd,%g0,rd */
1928{ "cas", F3(3, 0x3c, 0)|ASI(0x80), F3(~3, ~0x3c, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P,rs2,rd */
1929{ "casl", F3(3, 0x3c, 0)|ASI(0x88), F3(~3, ~0x3c, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casa [rs1]ASI_P_L,rs2,rd */
1930{ "casx", F3(3, 0x3e, 0)|ASI(0x80), F3(~3, ~0x3e, ~0)|ASI(~0x80), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P,rs2,rd */
1931{ "casxl", F3(3, 0x3e, 0)|ASI(0x88), F3(~3, ~0x3e, ~0)|ASI(~0x88), "[1],2,d", F_ALIAS, v9 }, /* casxa [rs1]ASI_P_L,rs2,rd */
aa0aa4fa
FB		 1932
1933/* Ultrasparc extensions */
f930d07e 1934{ "shutdown", F3F(2, 0x36, 0x080), F3F(~2, ~0x36, ~0x080)|RD_G0|RS1_G0|RS2_G0, "", 0, v9a },
aa0aa4fa
FB		 1935
1936/* FIXME: Do we want to mark these as F_FLOAT, or something similar? */
f930d07e
BS		 1937{ "fpadd16", F3F(2, 0x36, 0x050), F3F(~2, ~0x36, ~0x050), "v,B,H", 0, v9a },
1938{ "fpadd16s", F3F(2, 0x36, 0x051), F3F(~2, ~0x36, ~0x051), "e,f,g", 0, v9a },
1939{ "fpadd32", F3F(2, 0x36, 0x052), F3F(~2, ~0x36, ~0x052), "v,B,H", 0, v9a },
1940{ "fpadd32s", F3F(2, 0x36, 0x053), F3F(~2, ~0x36, ~0x053), "e,f,g", 0, v9a },
1941{ "fpsub16", F3F(2, 0x36, 0x054), F3F(~2, ~0x36, ~0x054), "v,B,H", 0, v9a },
1942{ "fpsub16s", F3F(2, 0x36, 0x055), F3F(~2, ~0x36, ~0x055), "e,f,g", 0, v9a },
1943{ "fpsub32", F3F(2, 0x36, 0x056), F3F(~2, ~0x36, ~0x056), "v,B,H", 0, v9a },
1944{ "fpsub32s", F3F(2, 0x36, 0x057), F3F(~2, ~0x36, ~0x057), "e,f,g", 0, v9a },
1945
1946{ "fpack32", F3F(2, 0x36, 0x03a), F3F(~2, ~0x36, ~0x03a), "v,B,H", 0, v9a },
1947{ "fpack16", F3F(2, 0x36, 0x03b), F3F(~2, ~0x36, ~0x03b)|RS1_G0, "B,g", 0, v9a },
1948{ "fpackfix", F3F(2, 0x36, 0x03d), F3F(~2, ~0x36, ~0x03d)|RS1_G0, "B,g", 0, v9a },
1949{ "fexpand", F3F(2, 0x36, 0x04d), F3F(~2, ~0x36, ~0x04d)|RS1_G0, "f,H", 0, v9a },
1950{ "fpmerge", F3F(2, 0x36, 0x04b), F3F(~2, ~0x36, ~0x04b), "e,f,H", 0, v9a },
aa0aa4fa
FB		 1951
1952/* Note that the mixing of 32/64 bit regs is intentional. */
f930d07e
BS		 1953{ "fmul8x16", F3F(2, 0x36, 0x031), F3F(~2, ~0x36, ~0x031), "e,B,H", 0, v9a },
1954{ "fmul8x16au", F3F(2, 0x36, 0x033), F3F(~2, ~0x36, ~0x033), "e,f,H", 0, v9a },
1955{ "fmul8x16al", F3F(2, 0x36, 0x035), F3F(~2, ~0x36, ~0x035), "e,f,H", 0, v9a },
1956{ "fmul8sux16", F3F(2, 0x36, 0x036), F3F(~2, ~0x36, ~0x036), "v,B,H", 0, v9a },
1957{ "fmul8ulx16", F3F(2, 0x36, 0x037), F3F(~2, ~0x36, ~0x037), "v,B,H", 0, v9a },
1958{ "fmuld8sux16", F3F(2, 0x36, 0x038), F3F(~2, ~0x36, ~0x038), "e,f,H", 0, v9a },
1959{ "fmuld8ulx16", F3F(2, 0x36, 0x039), F3F(~2, ~0x36, ~0x039), "e,f,H", 0, v9a },
1960
1961{ "alignaddr", F3F(2, 0x36, 0x018), F3F(~2, ~0x36, ~0x018), "1,2,d", 0, v9a },
1962{ "alignaddrl", F3F(2, 0x36, 0x01a), F3F(~2, ~0x36, ~0x01a), "1,2,d", 0, v9a },
1963{ "faligndata", F3F(2, 0x36, 0x048), F3F(~2, ~0x36, ~0x048), "v,B,H", 0, v9a },
1964
1965{ "fzero", F3F(2, 0x36, 0x060), F3F(~2, ~0x36, ~0x060), "H", 0, v9a },
1966{ "fzeros", F3F(2, 0x36, 0x061), F3F(~2, ~0x36, ~0x061), "g", 0, v9a },
1967{ "fone", F3F(2, 0x36, 0x07e), F3F(~2, ~0x36, ~0x07e), "H", 0, v9a },
1968{ "fones", F3F(2, 0x36, 0x07f), F3F(~2, ~0x36, ~0x07f), "g", 0, v9a },
1969{ "fsrc1", F3F(2, 0x36, 0x074), F3F(~2, ~0x36, ~0x074), "v,H", 0, v9a },
1970{ "fsrc1s", F3F(2, 0x36, 0x075), F3F(~2, ~0x36, ~0x075), "e,g", 0, v9a },
1971{ "fsrc2", F3F(2, 0x36, 0x078), F3F(~2, ~0x36, ~0x078), "B,H", 0, v9a },
1972{ "fsrc2s", F3F(2, 0x36, 0x079), F3F(~2, ~0x36, ~0x079), "f,g", 0, v9a },
1973{ "fnot1", F3F(2, 0x36, 0x06a), F3F(~2, ~0x36, ~0x06a), "v,H", 0, v9a },
1974{ "fnot1s", F3F(2, 0x36, 0x06b), F3F(~2, ~0x36, ~0x06b), "e,g", 0, v9a },
1975{ "fnot2", F3F(2, 0x36, 0x066), F3F(~2, ~0x36, ~0x066), "B,H", 0, v9a },
1976{ "fnot2s", F3F(2, 0x36, 0x067), F3F(~2, ~0x36, ~0x067), "f,g", 0, v9a },
1977{ "for", F3F(2, 0x36, 0x07c), F3F(~2, ~0x36, ~0x07c), "v,B,H", 0, v9a },
1978{ "fors", F3F(2, 0x36, 0x07d), F3F(~2, ~0x36, ~0x07d), "e,f,g", 0, v9a },
1979{ "fnor", F3F(2, 0x36, 0x062), F3F(~2, ~0x36, ~0x062), "v,B,H", 0, v9a },
1980{ "fnors", F3F(2, 0x36, 0x063), F3F(~2, ~0x36, ~0x063), "e,f,g", 0, v9a },
1981{ "fand", F3F(2, 0x36, 0x070), F3F(~2, ~0x36, ~0x070), "v,B,H", 0, v9a },
1982{ "fands", F3F(2, 0x36, 0x071), F3F(~2, ~0x36, ~0x071), "e,f,g", 0, v9a },
1983{ "fnand", F3F(2, 0x36, 0x06e), F3F(~2, ~0x36, ~0x06e), "v,B,H", 0, v9a },
1984{ "fnands", F3F(2, 0x36, 0x06f), F3F(~2, ~0x36, ~0x06f), "e,f,g", 0, v9a },
1985{ "fxor", F3F(2, 0x36, 0x06c), F3F(~2, ~0x36, ~0x06c), "v,B,H", 0, v9a },
1986{ "fxors", F3F(2, 0x36, 0x06d), F3F(~2, ~0x36, ~0x06d), "e,f,g", 0, v9a },
1987{ "fxnor", F3F(2, 0x36, 0x072), F3F(~2, ~0x36, ~0x072), "v,B,H", 0, v9a },
1988{ "fxnors", F3F(2, 0x36, 0x073), F3F(~2, ~0x36, ~0x073), "e,f,g", 0, v9a },
1989{ "fornot1", F3F(2, 0x36, 0x07a), F3F(~2, ~0x36, ~0x07a), "v,B,H", 0, v9a },
1990{ "fornot1s", F3F(2, 0x36, 0x07b), F3F(~2, ~0x36, ~0x07b), "e,f,g", 0, v9a },
1991{ "fornot2", F3F(2, 0x36, 0x076), F3F(~2, ~0x36, ~0x076), "v,B,H", 0, v9a },
1992{ "fornot2s", F3F(2, 0x36, 0x077), F3F(~2, ~0x36, ~0x077), "e,f,g", 0, v9a },
1993{ "fandnot1", F3F(2, 0x36, 0x068), F3F(~2, ~0x36, ~0x068), "v,B,H", 0, v9a },
1994{ "fandnot1s", F3F(2, 0x36, 0x069), F3F(~2, ~0x36, ~0x069), "e,f,g", 0, v9a },
1995{ "fandnot2", F3F(2, 0x36, 0x064), F3F(~2, ~0x36, ~0x064), "v,B,H", 0, v9a },
1996{ "fandnot2s", F3F(2, 0x36, 0x065), F3F(~2, ~0x36, ~0x065), "e,f,g", 0, v9a },
1997
1998{ "fcmpgt16", F3F(2, 0x36, 0x028), F3F(~2, ~0x36, ~0x028), "v,B,d", 0, v9a },
1999{ "fcmpgt32", F3F(2, 0x36, 0x02c), F3F(~2, ~0x36, ~0x02c), "v,B,d", 0, v9a },
2000{ "fcmple16", F3F(2, 0x36, 0x020), F3F(~2, ~0x36, ~0x020), "v,B,d", 0, v9a },
2001{ "fcmple32", F3F(2, 0x36, 0x024), F3F(~2, ~0x36, ~0x024), "v,B,d", 0, v9a },
2002{ "fcmpne16", F3F(2, 0x36, 0x022), F3F(~2, ~0x36, ~0x022), "v,B,d", 0, v9a },
2003{ "fcmpne32", F3F(2, 0x36, 0x026), F3F(~2, ~0x36, ~0x026), "v,B,d", 0, v9a },
2004{ "fcmpeq16", F3F(2, 0x36, 0x02a), F3F(~2, ~0x36, ~0x02a), "v,B,d", 0, v9a },
2005{ "fcmpeq32", F3F(2, 0x36, 0x02e), F3F(~2, ~0x36, ~0x02e), "v,B,d", 0, v9a },
2006
2007{ "edge8", F3F(2, 0x36, 0x000), F3F(~2, ~0x36, ~0x000), "1,2,d", 0, v9a },
2008{ "edge8l", F3F(2, 0x36, 0x002), F3F(~2, ~0x36, ~0x002), "1,2,d", 0, v9a },
2009{ "edge16", F3F(2, 0x36, 0x004), F3F(~2, ~0x36, ~0x004), "1,2,d", 0, v9a },
2010{ "edge16l", F3F(2, 0x36, 0x006), F3F(~2, ~0x36, ~0x006), "1,2,d", 0, v9a },
2011{ "edge32", F3F(2, 0x36, 0x008), F3F(~2, ~0x36, ~0x008), "1,2,d", 0, v9a },
2012{ "edge32l", F3F(2, 0x36, 0x00a), F3F(~2, ~0x36, ~0x00a), "1,2,d", 0, v9a },
2013
2014{ "pdist", F3F(2, 0x36, 0x03e), F3F(~2, ~0x36, ~0x03e), "v,B,H", 0, v9a },
2015
2016{ "array8", F3F(2, 0x36, 0x010), F3F(~2, ~0x36, ~0x010), "1,2,d", 0, v9a },
2017{ "array16", F3F(2, 0x36, 0x012), F3F(~2, ~0x36, ~0x012), "1,2,d", 0, v9a },
2018{ "array32", F3F(2, 0x36, 0x014), F3F(~2, ~0x36, ~0x014), "1,2,d", 0, v9a },
aa0aa4fa
FB		 2019
2020/* Cheetah instructions */
2021{ "edge8n", F3F(2, 0x36, 0x001), F3F(~2, ~0x36, ~0x001), "1,2,d", 0, v9b },
2022{ "edge8ln", F3F(2, 0x36, 0x003), F3F(~2, ~0x36, ~0x003), "1,2,d", 0, v9b },
2023{ "edge16n", F3F(2, 0x36, 0x005), F3F(~2, ~0x36, ~0x005), "1,2,d", 0, v9b },
2024{ "edge16ln", F3F(2, 0x36, 0x007), F3F(~2, ~0x36, ~0x007), "1,2,d", 0, v9b },
2025{ "edge32n", F3F(2, 0x36, 0x009), F3F(~2, ~0x36, ~0x009), "1,2,d", 0, v9b },
2026{ "edge32ln", F3F(2, 0x36, 0x00b), F3F(~2, ~0x36, ~0x00b), "1,2,d", 0, v9b },
2027
2028{ "bmask", F3F(2, 0x36, 0x019), F3F(~2, ~0x36, ~0x019), "1,2,d", 0, v9b },
2029{ "bshuffle", F3F(2, 0x36, 0x04c), F3F(~2, ~0x36, ~0x04c), "v,B,H", 0, v9b },
2030
2031{ "siam", F3F(2, 0x36, 0x081), F3F(~2, ~0x36, ~0x081)|RD_G0|RS1_G0|RS2(~7), "3", 0, v9b },
2032
2033/* More v9 specific insns, these need to come last so they do not clash
2034 with v9a instructions such as "edge8" which looks like impdep1. */
2035
2036#define IMPDEP(name, code) \
f930d07e
BS		 2037{ name, F3(2, code, 0), F3(~2, ~code, ~0)|ASI(~0), "1,2,d", 0, v9notv9a }, \
2038{ name, F3(2, code, 1), F3(~2, ~code, ~1), "1,i,d", 0, v9notv9a }, \
aa0aa4fa
FB		 2039{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,1,2,d", 0, v9notv9a }, \
2040{ name, F3(2, code, 0), F3(~2, ~code, ~0), "x,e,f,g", 0, v9notv9a }
2041
2042IMPDEP ("impdep1", 0x36),
2043IMPDEP ("impdep2", 0x37),
2044
2045#undef IMPDEP
2046
2047};
2048
f82a3d48 2049static const int sparc_num_opcodes = ((sizeof sparc_opcodes)/(sizeof sparc_opcodes[0]));
aa0aa4fa
FB		 2050\f
2051/* Utilities for argument parsing. */
2052
2053typedef struct
2054{
2055 int value;
2056 const char *name;
2057} arg;
2058
aa0aa4fa
FB		 2059/* Look up VALUE in TABLE. */
2060
2061static const char *
46f42f29 2062lookup_value (const arg *table, int value)
aa0aa4fa
FB		 2063{
2064 const arg *p;
2065
2066 for (p = table; p->name; ++p)
2067 if (value == p->value)
2068 return p->name;
2069
46f42f29 2070 return NULL;
aa0aa4fa
FB		 2071}
2072\f
2073/* Handle ASI's. */
2074
1983a395
FB		 2075static const arg asi_table_v8[] =
2076{
2077 { 0x00, "#ASI_M_RES00" },
2078 { 0x01, "#ASI_M_UNA01" },
2079 { 0x02, "#ASI_M_MXCC" },
2080 { 0x03, "#ASI_M_FLUSH_PROBE" },
2081 { 0x04, "#ASI_M_MMUREGS" },
2082 { 0x05, "#ASI_M_TLBDIAG" },
2083 { 0x06, "#ASI_M_DIAGS" },
2084 { 0x07, "#ASI_M_IODIAG" },
2085 { 0x08, "#ASI_M_USERTXT" },
2086 { 0x09, "#ASI_M_KERNELTXT" },
2087 { 0x0A, "#ASI_M_USERDATA" },
2088 { 0x0B, "#ASI_M_KERNELDATA" },
2089 { 0x0C, "#ASI_M_TXTC_TAG" },
2090 { 0x0D, "#ASI_M_TXTC_DATA" },
2091 { 0x0E, "#ASI_M_DATAC_TAG" },
2092 { 0x0F, "#ASI_M_DATAC_DATA" },
2093 { 0x10, "#ASI_M_FLUSH_PAGE" },
2094 { 0x11, "#ASI_M_FLUSH_SEG" },
2095 { 0x12, "#ASI_M_FLUSH_REGION" },
2096 { 0x13, "#ASI_M_FLUSH_CTX" },
2097 { 0x14, "#ASI_M_FLUSH_USER" },
2098 { 0x17, "#ASI_M_BCOPY" },
2099 { 0x18, "#ASI_M_IFLUSH_PAGE" },
2100 { 0x19, "#ASI_M_IFLUSH_SEG" },
2101 { 0x1A, "#ASI_M_IFLUSH_REGION" },
2102 { 0x1B, "#ASI_M_IFLUSH_CTX" },
2103 { 0x1C, "#ASI_M_IFLUSH_USER" },
2104 { 0x1F, "#ASI_M_BFILL" },
2105 { 0x20, "#ASI_M_BYPASS" },
2106 { 0x29, "#ASI_M_FBMEM" },
2107 { 0x2A, "#ASI_M_VMEUS" },
2108 { 0x2B, "#ASI_M_VMEPS" },
2109 { 0x2C, "#ASI_M_VMEUT" },
2110 { 0x2D, "#ASI_M_VMEPT" },
2111 { 0x2E, "#ASI_M_SBUS" },
2112 { 0x2F, "#ASI_M_CTL" },
2113 { 0x31, "#ASI_M_FLUSH_IWHOLE" },
2114 { 0x36, "#ASI_M_IC_FLCLEAR" },
2115 { 0x37, "#ASI_M_DC_FLCLEAR" },
2116 { 0x39, "#ASI_M_DCDR" },
2117 { 0x40, "#ASI_M_VIKING_TMP1" },
2118 { 0x41, "#ASI_M_VIKING_TMP2" },
2119 { 0x4c, "#ASI_M_ACTION" },
2120 { 0, 0 }
2121};
2122
2123static const arg asi_table_v9[] =
aa0aa4fa
FB		 2124{
2125 /* These are in the v9 architecture manual. */
2126 /* The shorter versions appear first, they're here because Sun's as has them.
2127 Sun's as uses #ASI_P_L instead of #ASI_PL (which appears in the
2128 UltraSPARC architecture manual). */
2129 { 0x04, "#ASI_N" },
2130 { 0x0c, "#ASI_N_L" },
2131 { 0x10, "#ASI_AIUP" },
2132 { 0x11, "#ASI_AIUS" },
2133 { 0x18, "#ASI_AIUP_L" },
2134 { 0x19, "#ASI_AIUS_L" },
2135 { 0x80, "#ASI_P" },
2136 { 0x81, "#ASI_S" },
2137 { 0x82, "#ASI_PNF" },
2138 { 0x83, "#ASI_SNF" },
2139 { 0x88, "#ASI_P_L" },
2140 { 0x89, "#ASI_S_L" },
2141 { 0x8a, "#ASI_PNF_L" },
2142 { 0x8b, "#ASI_SNF_L" },
2143 { 0x04, "#ASI_NUCLEUS" },
2144 { 0x0c, "#ASI_NUCLEUS_LITTLE" },
2145 { 0x10, "#ASI_AS_IF_USER_PRIMARY" },
2146 { 0x11, "#ASI_AS_IF_USER_SECONDARY" },
2147 { 0x18, "#ASI_AS_IF_USER_PRIMARY_LITTLE" },
2148 { 0x19, "#ASI_AS_IF_USER_SECONDARY_LITTLE" },
2149 { 0x80, "#ASI_PRIMARY" },
2150 { 0x81, "#ASI_SECONDARY" },
2151 { 0x82, "#ASI_PRIMARY_NOFAULT" },
2152 { 0x83, "#ASI_SECONDARY_NOFAULT" },
2153 { 0x88, "#ASI_PRIMARY_LITTLE" },
2154 { 0x89, "#ASI_SECONDARY_LITTLE" },
2155 { 0x8a, "#ASI_PRIMARY_NOFAULT_LITTLE" },
2156 { 0x8b, "#ASI_SECONDARY_NOFAULT_LITTLE" },
2157 /* These are UltraSPARC extensions. */
2158 /* FIXME: There are dozens of them. Not sure we want them all.
2159 Most are for kernel building but some are for vis type stuff. */
2160 { 0, 0 }
2161};
2162
1983a395 2163/* Return the name for ASI value VALUE or NULL if not found. */
aa0aa4fa 2164
1983a395
FB		 2165static const char *
2166sparc_decode_asi_v9 (int value)
aa0aa4fa 2167{
1983a395 2168 return lookup_value (asi_table_v9, value);
aa0aa4fa
FB		 2169}
2170
1983a395
FB		 2171static const char *
2172sparc_decode_asi_v8 (int value)
aa0aa4fa 2173{
1983a395 2174 return lookup_value (asi_table_v8, value);
aa0aa4fa
FB		 2175}
2176\f
2177/* Handle membar masks. */
2178
d88bbf95 2179static const arg membar_table[] =
aa0aa4fa
FB		 2180{
2181 { 0x40, "#Sync" },
2182 { 0x20, "#MemIssue" },
2183 { 0x10, "#Lookaside" },
2184 { 0x08, "#StoreStore" },
2185 { 0x04, "#LoadStore" },
2186 { 0x02, "#StoreLoad" },
2187 { 0x01, "#LoadLoad" },
2188 { 0, 0 }
2189};
2190
aa0aa4fa
FB		 2191/* Return the name for membar value VALUE or NULL if not found. */
2192
b1d8e52e 2193static const char *
46f42f29 2194sparc_decode_membar (int value)
aa0aa4fa
FB		 2195{
2196 return lookup_value (membar_table, value);
2197}
2198\f
2199/* Handle prefetch args. */
2200
d88bbf95 2201static const arg prefetch_table[] =
aa0aa4fa
FB		 2202{
2203 { 0, "#n_reads" },
2204 { 1, "#one_read" },
2205 { 2, "#n_writes" },
2206 { 3, "#one_write" },
2207 { 4, "#page" },
2208 { 16, "#invalidate" },
2209 { 0, 0 }
2210};
2211
aa0aa4fa
FB		 2212/* Return the name for prefetch value VALUE or NULL if not found. */
2213
b1d8e52e 2214static const char *
46f42f29 2215sparc_decode_prefetch (int value)
aa0aa4fa
FB		 2216{
2217 return lookup_value (prefetch_table, value);
2218}
2219\f
2220/* Handle sparclet coprocessor registers. */
2221
d88bbf95 2222static const arg sparclet_cpreg_table[] =
aa0aa4fa
FB		 2223{
2224 { 0, "%ccsr" },
2225 { 1, "%ccfr" },
2226 { 2, "%cccrcr" },
2227 { 3, "%ccpr" },
2228 { 4, "%ccsr2" },
2229 { 5, "%cccrr" },
2230 { 6, "%ccrstr" },
2231 { 0, 0 }
2232};
2233
aa0aa4fa
FB		 2234/* Return the name for sparclet cpreg value VALUE or NULL if not found. */
2235
b1d8e52e 2236static const char *
46f42f29 2237sparc_decode_sparclet_cpreg (int value)
aa0aa4fa
FB		 2238{
2239 return lookup_value (sparclet_cpreg_table, value);
2240}
2241
2242#undef MASK_V9
2243
d4abd567
BS		 2244/* opcodes/sparc-dis.c */
2245
46f42f29
BS		 2246/* Print SPARC instructions.
2247 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2248 2000, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
2249
2250 This program is free software; you can redistribute it and/or modify
2251 it under the terms of the GNU General Public License as published by
2252 the Free Software Foundation; either version 2 of the License, or
2253 (at your option) any later version.
2254
2255 This program is distributed in the hope that it will be useful,
2256 but WITHOUT ANY WARRANTY; without even the implied warranty of
2257 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
2258 GNU General Public License for more details.
2259
2260 You should have received a copy of the GNU General Public License
2261 along with this program; if not, write to the Free Software
2262 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
2263 MA 02110-1301, USA. */
2264
aa0aa4fa
FB		 2265/* Bitmask of v9 architectures. */
2266#define MASK_V9 ((1 << SPARC_OPCODE_ARCH_V9) \
f930d07e
BS		 2267 | (1 << SPARC_OPCODE_ARCH_V9A) \
2268 | (1 << SPARC_OPCODE_ARCH_V9B))
aa0aa4fa
FB		 2269/* 1 if INSN is for v9 only. */
2270#define V9_ONLY_P(insn) (! ((insn)->architecture & ~MASK_V9))
2271/* 1 if INSN is for v9. */
2272#define V9_P(insn) (((insn)->architecture & MASK_V9) != 0)
2273
2274/* The sorted opcode table. */
46f42f29 2275static const sparc_opcode **sorted_opcodes;
aa0aa4fa
FB		 2276
2277/* For faster lookup, after insns are sorted they are hashed. */
2278/* ??? I think there is room for even more improvement. */
2279
2280#define HASH_SIZE 256
2281/* It is important that we only look at insn code bits as that is how the
2282 opcode table is hashed. OPCODE_BITS is a table of valid bits for each
2283 of the main types (0,1,2,3). */
d88bbf95 2284static const int opcode_bits[4] = { 0x01c00000, 0x0, 0x01f80000, 0x01f80000 };
aa0aa4fa
FB		 2285#define HASH_INSN(INSN) \
2286 ((((INSN) >> 24) & 0xc0) | (((INSN) & opcode_bits[((INSN) >> 30) & 3]) >> 19))
46f42f29
BS		 2287typedef struct sparc_opcode_hash
2288{
2289 struct sparc_opcode_hash *next;
2290 const sparc_opcode *opcode;
2291} sparc_opcode_hash;
aa0aa4fa 2292
46f42f29 2293static sparc_opcode_hash *opcode_hash_table[HASH_SIZE];
aa0aa4fa
FB		 2294
2295/* Sign-extend a value which is N bits long. */
f930d07e
BS		 2296#define SEX(value, bits) \
2297 ((((int)(value)) << ((8 * sizeof (int)) - bits)) \
2298 >> ((8 * sizeof (int)) - bits) )
aa0aa4fa 2299
d88bbf95 2300static const char * const reg_names[] =
5fafdf24
TS		 2301{ "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
2302 "o0", "o1", "o2", "o3", "o4", "o5", "sp", "o7",
2303 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
2304 "i0", "i1", "i2", "i3", "i4", "i5", "fp", "i7",
2305 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
2306 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
aa0aa4fa
FB		 2307 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
2308 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
5fafdf24
TS		 2309 "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39",
2310 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47",
aa0aa4fa
FB		 2311 "f48", "f49", "f50", "f51", "f52", "f53", "f54", "f55",
2312 "f56", "f57", "f58", "f59", "f60", "f61", "f62", "f63",
2313/* psr, wim, tbr, fpsr, cpsr are v8 only. */
2314 "y", "psr", "wim", "tbr", "pc", "npc", "fpsr", "cpsr"
2315};
2316
f930d07e 2317#define freg_names (&reg_names[4 * 8])
aa0aa4fa
FB		 2318
2319/* These are ordered according to there register number in
2320 rdpr and wrpr insns. */
d88bbf95 2321static const char * const v9_priv_reg_names[] =
aa0aa4fa
FB		 2322{
2323 "tpc", "tnpc", "tstate", "tt", "tick", "tba", "pstate", "tl",
2324 "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
46f42f29 2325 "wstate", "fq", "gl"
aa0aa4fa
FB		 2326 /* "ver" - special cased */
2327};
2328
46f42f29
BS		 2329/* These are ordered according to there register number in
2330 rdhpr and wrhpr insns. */
2331static const char * const v9_hpriv_reg_names[] =
2332{
2333 "hpstate", "htstate", "resv2", "hintp", "resv4", "htba", "hver",
2334 "resv7", "resv8", "resv9", "resv10", "resv11", "resv12", "resv13",
2335 "resv14", "resv15", "resv16", "resv17", "resv18", "resv19", "resv20",
2336 "resv21", "resv22", "resv23", "resv24", "resv25", "resv26", "resv27",
2337 "resv28", "resv29", "resv30", "hstick_cmpr"
2338};
2339
aa0aa4fa
FB		 2340/* These are ordered according to there register number in
2341 rd and wr insns (-16). */
d88bbf95 2342static const char * const v9a_asr_reg_names[] =
aa0aa4fa
FB		 2343{
2344 "pcr", "pic", "dcr", "gsr", "set_softint", "clear_softint",
2345 "softint", "tick_cmpr", "sys_tick", "sys_tick_cmpr"
2346};
2347
2348/* Macros used to extract instruction fields. Not all fields have
2349 macros defined here, only those which are actually used. */
2350
46f42f29
BS		 2351#define X_RD(i) (((i) >> 25) & 0x1f)
2352#define X_RS1(i) (((i) >> 14) & 0x1f)
2353#define X_LDST_I(i) (((i) >> 13) & 1)
2354#define X_ASI(i) (((i) >> 5) & 0xff)
2355#define X_RS2(i) (((i) >> 0) & 0x1f)
2356#define X_IMM(i,n) (((i) >> 0) & ((1 << (n)) - 1))
2357#define X_SIMM(i,n) SEX (X_IMM ((i), (n)), (n))
2358#define X_DISP22(i) (((i) >> 0) & 0x3fffff)
2359#define X_IMM22(i) X_DISP22 (i)
2360#define X_DISP30(i) (((i) >> 0) & 0x3fffffff)
aa0aa4fa
FB		 2361
2362/* These are for v9. */
46f42f29
BS		 2363#define X_DISP16(i) (((((i) >> 20) & 3) << 14) | (((i) >> 0) & 0x3fff))
2364#define X_DISP19(i) (((i) >> 0) & 0x7ffff)
2365#define X_MEMBAR(i) ((i) & 0x7f)
aa0aa4fa
FB		 2366
2367/* Here is the union which was used to extract instruction fields
2368 before the shift and mask macros were written.
2369
2370 union sparc_insn
2371 {
2372 unsigned long int code;
2373 struct
f930d07e
BS		 2374 {
2375 unsigned int anop:2;
2376 #define op ldst.anop
2377 unsigned int anrd:5;
2378 #define rd ldst.anrd
2379 unsigned int op3:6;
2380 unsigned int anrs1:5;
2381 #define rs1 ldst.anrs1
2382 unsigned int i:1;
2383 unsigned int anasi:8;
2384 #define asi ldst.anasi
2385 unsigned int anrs2:5;
2386 #define rs2 ldst.anrs2
2387 #define shcnt rs2
2388 } ldst;
aa0aa4fa 2389 struct
f930d07e
BS		 2390 {
2391 unsigned int anop:2, anrd:5, op3:6, anrs1:5, i:1;
2392 unsigned int IMM13:13;
2393 #define imm13 IMM13.IMM13
2394 } IMM13;
aa0aa4fa 2395 struct
f930d07e
BS		 2396 {
2397 unsigned int anop:2;
2398 unsigned int a:1;
2399 unsigned int cond:4;
2400 unsigned int op2:3;
2401 unsigned int DISP22:22;
2402 #define disp22 branch.DISP22
2403 #define imm22 disp22
2404 } branch;
aa0aa4fa 2405 struct
f930d07e
BS		 2406 {
2407 unsigned int anop:2;
2408 unsigned int a:1;
2409 unsigned int z:1;
2410 unsigned int rcond:3;
2411 unsigned int op2:3;
2412 unsigned int DISP16HI:2;
2413 unsigned int p:1;
2414 unsigned int _rs1:5;
2415 unsigned int DISP16LO:14;
2416 } branch16;
aa0aa4fa 2417 struct
f930d07e
BS		 2418 {
2419 unsigned int anop:2;
2420 unsigned int adisp30:30;
2421 #define disp30 call.adisp30
2422 } call;
46f42f29 2423 }; */
aa0aa4fa
FB		 2424
2425/* Nonzero if INSN is the opcode for a delayed branch. */
46f42f29 2426
aa0aa4fa 2427static int
46f42f29 2428is_delayed_branch (unsigned long insn)
aa0aa4fa 2429{
46f42f29 2430 sparc_opcode_hash *op;
aa0aa4fa
FB		 2431
2432 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
2433 {
46f42f29
BS		 2434 const sparc_opcode *opcode = op->opcode;
2435
aa0aa4fa 2436 if ((opcode->match & insn) == opcode->match
f930d07e 2437 && (opcode->lose & insn) == 0)
46f42f29 2438 return opcode->flags & F_DELAYED;
aa0aa4fa
FB		 2439 }
2440 return 0;
2441}
2442
2443/* extern void qsort (); */
2444
2445/* Records current mask of SPARC_OPCODE_ARCH_FOO values, used to pass value
2446 to compare_opcodes. */
2447static unsigned int current_arch_mask;
2448
46f42f29
BS		 2449/* Given BFD mach number, return a mask of SPARC_OPCODE_ARCH_FOO values. */
2450
2451static int
2452compute_arch_mask (unsigned long mach)
2453{
2454 switch (mach)
2455 {
2456 case 0 :
2457 case bfd_mach_sparc :
2458 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8);
2459 case bfd_mach_sparc_sparclet :
2460 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLET);
2461 case bfd_mach_sparc_sparclite :
2462 case bfd_mach_sparc_sparclite_le :
2463 /* sparclites insns are recognized by default (because that's how
2464 they've always been treated, for better or worse). Kludge this by
2465 indicating generic v8 is also selected. */
2466 return (SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_SPARCLITE)
2467 | SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V8));
2468 case bfd_mach_sparc_v8plus :
2469 case bfd_mach_sparc_v9 :
2470 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9);
2471 case bfd_mach_sparc_v8plusa :
2472 case bfd_mach_sparc_v9a :
2473 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9A);
2474 case bfd_mach_sparc_v8plusb :
2475 case bfd_mach_sparc_v9b :
2476 return SPARC_OPCODE_ARCH_MASK (SPARC_OPCODE_ARCH_V9B);
2477 }
2478 abort ();
2479}
2480
2481/* Compare opcodes A and B. */
2482
2483static int
2484compare_opcodes (const void * a, const void * b)
2485{
2486 sparc_opcode *op0 = * (sparc_opcode **) a;
2487 sparc_opcode *op1 = * (sparc_opcode **) b;
2488 unsigned long int match0 = op0->match, match1 = op1->match;
2489 unsigned long int lose0 = op0->lose, lose1 = op1->lose;
2490 register unsigned int i;
2491
2492 /* If one (and only one) insn isn't supported by the current architecture,
2493 prefer the one that is. If neither are supported, but they're both for
2494 the same architecture, continue processing. Otherwise (both unsupported
2495 and for different architectures), prefer lower numbered arch's (fudged
2496 by comparing the bitmasks). */
2497 if (op0->architecture & current_arch_mask)
2498 {
2499 if (! (op1->architecture & current_arch_mask))
2500 return -1;
2501 }
2502 else
2503 {
2504 if (op1->architecture & current_arch_mask)
2505 return 1;
2506 else if (op0->architecture != op1->architecture)
2507 return op0->architecture - op1->architecture;
2508 }
2509
2510 /* If a bit is set in both match and lose, there is something
2511 wrong with the opcode table. */
2512 if (match0 & lose0)
2513 {
2514 fprintf
2515 (stderr,
2516 /* xgettext:c-format */
2517 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
2518 op0->name, match0, lose0);
2519 op0->lose &= ~op0->match;
2520 lose0 = op0->lose;
2521 }
2522
2523 if (match1 & lose1)
2524 {
2525 fprintf
2526 (stderr,
2527 /* xgettext:c-format */
2528 _("Internal error: bad sparc-opcode.h: \"%s\", %#.8lx, %#.8lx\n"),
2529 op1->name, match1, lose1);
2530 op1->lose &= ~op1->match;
2531 lose1 = op1->lose;
2532 }
2533
2534 /* Because the bits that are variable in one opcode are constant in
2535 another, it is important to order the opcodes in the right order. */
2536 for (i = 0; i < 32; ++i)
2537 {
2538 unsigned long int x = 1 << i;
2539 int x0 = (match0 & x) != 0;
2540 int x1 = (match1 & x) != 0;
2541
2542 if (x0 != x1)
2543 return x1 - x0;
2544 }
2545
2546 for (i = 0; i < 32; ++i)
2547 {
2548 unsigned long int x = 1 << i;
2549 int x0 = (lose0 & x) != 0;
2550 int x1 = (lose1 & x) != 0;
2551
2552 if (x0 != x1)
2553 return x1 - x0;
2554 }
2555
2556 /* They are functionally equal. So as long as the opcode table is
2557 valid, we can put whichever one first we want, on aesthetic grounds. */
2558
2559 /* Our first aesthetic ground is that aliases defer to real insns. */
2560 {
2561 int alias_diff = (op0->flags & F_ALIAS) - (op1->flags & F_ALIAS);
2562
2563 if (alias_diff != 0)
2564 /* Put the one that isn't an alias first. */
2565 return alias_diff;
2566 }
2567
2568 /* Except for aliases, two "identical" instructions had
2569 better have the same opcode. This is a sanity check on the table. */
2570 i = strcmp (op0->name, op1->name);
2571 if (i)
2572 {
2573 if (op0->flags & F_ALIAS) /* If they're both aliases, be arbitrary. */
2574 return i;
2575 else
2576 fprintf (stderr,
2577 /* xgettext:c-format */
2578 _("Internal error: bad sparc-opcode.h: \"%s\" == \"%s\"\n"),
2579 op0->name, op1->name);
2580 }
2581
2582 /* Fewer arguments are preferred. */
2583 {
2584 int length_diff = strlen (op0->args) - strlen (op1->args);
2585
2586 if (length_diff != 0)
2587 /* Put the one with fewer arguments first. */
2588 return length_diff;
2589 }
2590
2591 /* Put 1+i before i+1. */
2592 {
2593 char *p0 = (char *) strchr (op0->args, '+');
2594 char *p1 = (char *) strchr (op1->args, '+');
2595
2596 if (p0 && p1)
2597 {
2598 /* There is a plus in both operands. Note that a plus
2599 sign cannot be the first character in args,
2600 so the following [-1]'s are valid. */
2601 if (p0[-1] == 'i' && p1[1] == 'i')
2602 /* op0 is i+1 and op1 is 1+i, so op1 goes first. */
2603 return 1;
2604 if (p0[1] == 'i' && p1[-1] == 'i')
2605 /* op0 is 1+i and op1 is i+1, so op0 goes first. */
2606 return -1;
2607 }
2608 }
2609
2610 /* Put 1,i before i,1. */
2611 {
2612 int i0 = strncmp (op0->args, "i,1", 3) == 0;
2613 int i1 = strncmp (op1->args, "i,1", 3) == 0;
2614
2615 if (i0 ^ i1)
2616 return i0 - i1;
2617 }
2618
2619 /* They are, as far as we can tell, identical.
2620 Since qsort may have rearranged the table partially, there is
2621 no way to tell which one was first in the opcode table as
2622 written, so just say there are equal. */
2623 /* ??? This is no longer true now that we sort a vector of pointers,
2624 not the table itself. */
2625 return 0;
2626}
2627
2628/* Build a hash table from the opcode table.
2629 OPCODE_TABLE is a sorted list of pointers into the opcode table. */
2630
2631static void
2632build_hash_table (const sparc_opcode **opcode_table,
2633 sparc_opcode_hash **hash_table,
2634 int num_opcodes)
2635{
2636 int i;
2637 int hash_count[HASH_SIZE];
2638 static sparc_opcode_hash *hash_buf = NULL;
2639
2640 /* Start at the end of the table and work backwards so that each
2641 chain is sorted. */
2642
2643 memset (hash_table, 0, HASH_SIZE * sizeof (hash_table[0]));
2644 memset (hash_count, 0, HASH_SIZE * sizeof (hash_count[0]));
2645 if (hash_buf != NULL)
2646 free (hash_buf);
2647 hash_buf = malloc (sizeof (* hash_buf) * num_opcodes);
2648 for (i = num_opcodes - 1; i >= 0; --i)
2649 {
2650 int hash = HASH_INSN (opcode_table[i]->match);
2651 sparc_opcode_hash *h = &hash_buf[i];
2652
2653 h->next = hash_table[hash];
2654 h->opcode = opcode_table[i];
2655 hash_table[hash] = h;
2656 ++hash_count[hash];
2657 }
2658
2659#if 0 /* for debugging */
2660 {
2661 int min_count = num_opcodes, max_count = 0;
2662 int total;
2663
2664 for (i = 0; i < HASH_SIZE; ++i)
2665 {
2666 if (hash_count[i] < min_count)
2667 min_count = hash_count[i];
2668 if (hash_count[i] > max_count)
2669 max_count = hash_count[i];
2670 total += hash_count[i];
2671 }
2672
2673 printf ("Opcode hash table stats: min %d, max %d, ave %f\n",
2674 min_count, max_count, (double) total / HASH_SIZE);
2675 }
2676#endif
2677}
2678
aa0aa4fa
FB		 2679/* Print one instruction from MEMADDR on INFO->STREAM.
2680
2681 We suffix the instruction with a comment that gives the absolute
2682 address involved, as well as its symbolic form, if the instruction
2683 is preceded by a findable `sethi' and it either adds an immediate
2684 displacement to that register, or it is an `add' or `or' instruction
2685 on that register. */
2686
2687int
46f42f29 2688print_insn_sparc (bfd_vma memaddr, disassemble_info *info)
aa0aa4fa
FB		 2689{
2690 FILE *stream = info->stream;
2691 bfd_byte buffer[4];
2692 unsigned long insn;
46f42f29 2693 sparc_opcode_hash *op;
aa0aa4fa
FB		 2694 /* Nonzero of opcode table has been initialized. */
2695 static int opcodes_initialized = 0;
2696 /* bfd mach number of last call. */
2697 static unsigned long current_mach = 0;
46f42f29 2698 bfd_vma (*getword) (const unsigned char *);
aa0aa4fa
FB		 2699
2700 if (!opcodes_initialized
2701 || info->mach != current_mach)
2702 {
2703 int i;
2704
2705 current_arch_mask = compute_arch_mask (info->mach);
2706
2707 if (!opcodes_initialized)
46f42f29
BS		 2708 sorted_opcodes =
2709 malloc (sparc_num_opcodes * sizeof (sparc_opcode *));
aa0aa4fa
FB		 2710 /* Reset the sorted table so we can resort it. */
2711 for (i = 0; i < sparc_num_opcodes; ++i)
f930d07e 2712 sorted_opcodes[i] = &sparc_opcodes[i];
aa0aa4fa 2713 qsort ((char *) sorted_opcodes, sparc_num_opcodes,
f930d07e 2714 sizeof (sorted_opcodes[0]), compare_opcodes);
aa0aa4fa
FB		 2715
2716 build_hash_table (sorted_opcodes, opcode_hash_table, sparc_num_opcodes);
2717 current_mach = info->mach;
2718 opcodes_initialized = 1;
2719 }
2720
2721 {
2722 int status =
2723 (*info->read_memory_func) (memaddr, buffer, sizeof (buffer), info);
46f42f29 2724
aa0aa4fa
FB		 2725 if (status != 0)
2726 {
f930d07e
BS		 2727 (*info->memory_error_func) (status, memaddr, info);
2728 return -1;
aa0aa4fa
FB		 2729 }
2730 }
2731
2732 /* On SPARClite variants such as DANlite (sparc86x), instructions
46f42f29 2733 are always big-endian even when the machine is in little-endian mode. */
aa0aa4fa
FB		 2734 if (info->endian == BFD_ENDIAN_BIG || info->mach == bfd_mach_sparc_sparclite)
2735 getword = bfd_getb32;
2736 else
2737 getword = bfd_getl32;
2738
2739 insn = getword (buffer);
2740
46f42f29
BS		 2741 info->insn_info_valid = 1; /* We do return this info. */
2742 info->insn_type = dis_nonbranch; /* Assume non branch insn. */
2743 info->branch_delay_insns = 0; /* Assume no delay. */
2744 info->target = 0; /* Assume no target known. */
aa0aa4fa
FB		 2745
2746 for (op = opcode_hash_table[HASH_INSN (insn)]; op; op = op->next)
2747 {
46f42f29 2748 const sparc_opcode *opcode = op->opcode;
aa0aa4fa
FB		 2749
2750 /* If the insn isn't supported by the current architecture, skip it. */
2751 if (! (opcode->architecture & current_arch_mask))
f930d07e 2752 continue;
aa0aa4fa
FB		 2753
2754 if ((opcode->match & insn) == opcode->match
f930d07e
BS		 2755 && (opcode->lose & insn) == 0)
2756 {
2757 /* Nonzero means that we have found an instruction which has
2758 the effect of adding or or'ing the imm13 field to rs1. */
2759 int imm_added_to_rs1 = 0;
2760 int imm_ored_to_rs1 = 0;
aa0aa4fa 2761
f930d07e
BS		 2762 /* Nonzero means that we have found a plus sign in the args
2763 field of the opcode table. */
2764 int found_plus = 0;
3b46e624 2765
f930d07e
BS		 2766 /* Nonzero means we have an annulled branch. */
2767 int is_annulled = 0;
aa0aa4fa 2768
f930d07e 2769 /* Do we have an `add' or `or' instruction combining an
aa0aa4fa 2770 immediate with rs1? */
f930d07e
BS		 2771 if (opcode->match == 0x80102000) /* or */
2772 imm_ored_to_rs1 = 1;
2773 if (opcode->match == 0x80002000) /* add */
2774 imm_added_to_rs1 = 1;
2775
2776 if (X_RS1 (insn) != X_RD (insn)
2777 && strchr (opcode->args, 'r') != 0)
2778 /* Can't do simple format if source and dest are different. */
2779 continue;
2780 if (X_RS2 (insn) != X_RD (insn)
2781 && strchr (opcode->args, 'O') != 0)
2782 /* Can't do simple format if source and dest are different. */
2783 continue;
2784
2785 (*info->fprintf_func) (stream, opcode->name);
2786
2787 {
46f42f29 2788 const char *s;
f930d07e
BS		 2789
2790 if (opcode->args[0] != ',')
2791 (*info->fprintf_func) (stream, " ");
46f42f29 2792
f930d07e
BS		 2793 for (s = opcode->args; *s != '\0'; ++s)
2794 {
2795 while (*s == ',')
2796 {
2797 (*info->fprintf_func) (stream, ",");
2798 ++s;
46f42f29
BS		 2799 switch (*s)
2800 {
2801 case 'a':
2802 (*info->fprintf_func) (stream, "a");
2803 is_annulled = 1;
2804 ++s;
2805 continue;
2806 case 'N':
2807 (*info->fprintf_func) (stream, "pn");
2808 ++s;
2809 continue;
2810
2811 case 'T':
2812 (*info->fprintf_func) (stream, "pt");
2813 ++s;
2814 continue;
2815
2816 default:
2817 break;
2818 }
2819 }
f930d07e
BS		 2820
2821 (*info->fprintf_func) (stream, " ");
2822
2823 switch (*s)
2824 {
2825 case '+':
2826 found_plus = 1;
46f42f29 2827 /* Fall through. */
f930d07e 2828
f930d07e
BS		 2829 default:
2830 (*info->fprintf_func) (stream, "%c", *s);
2831 break;
2832
2833 case '#':
2834 (*info->fprintf_func) (stream, "0");
2835 break;
2836
2837#define reg(n) (*info->fprintf_func) (stream, "%%%s", reg_names[n])
2838 case '1':
2839 case 'r':
2840 reg (X_RS1 (insn));
2841 break;
2842
2843 case '2':
2844 case 'O':
2845 reg (X_RS2 (insn));
2846 break;
2847
2848 case 'd':
2849 reg (X_RD (insn));
2850 break;
2851#undef reg
2852
2853#define freg(n) (*info->fprintf_func) (stream, "%%%s", freg_names[n])
2854#define fregx(n) (*info->fprintf_func) (stream, "%%%s", freg_names[((n) & ~1) | (((n) & 1) << 5)])
2855 case 'e':
2856 freg (X_RS1 (insn));
2857 break;
46f42f29
BS		 2858 case 'v': /* Double/even. */
2859 case 'V': /* Quad/multiple of 4. */
f930d07e
BS		 2860 fregx (X_RS1 (insn));
2861 break;
2862
2863 case 'f':
2864 freg (X_RS2 (insn));
2865 break;
46f42f29
BS		 2866 case 'B': /* Double/even. */
2867 case 'R': /* Quad/multiple of 4. */
f930d07e
BS		 2868 fregx (X_RS2 (insn));
2869 break;
2870
2871 case 'g':
2872 freg (X_RD (insn));
2873 break;
46f42f29
BS		 2874 case 'H': /* Double/even. */
2875 case 'J': /* Quad/multiple of 4. */
f930d07e
BS		 2876 fregx (X_RD (insn));
2877 break;
2878#undef freg
2879#undef fregx
2880
2881#define creg(n) (*info->fprintf_func) (stream, "%%c%u", (unsigned int) (n))
2882 case 'b':
2883 creg (X_RS1 (insn));
2884 break;
2885
2886 case 'c':
2887 creg (X_RS2 (insn));
2888 break;
2889
2890 case 'D':
2891 creg (X_RD (insn));
2892 break;
2893#undef creg
2894
2895 case 'h':
2896 (*info->fprintf_func) (stream, "%%hi(%#x)",
2897 ((unsigned) 0xFFFFFFFF
2898 & ((int) X_IMM22 (insn) << 10)));
2899 break;
2900
46f42f29
BS		 2901 case 'i': /* 13 bit immediate. */
2902 case 'I': /* 11 bit immediate. */
2903 case 'j': /* 10 bit immediate. */
f930d07e
BS		 2904 {
2905 int imm;
2906
2907 if (*s == 'i')
2908 imm = X_SIMM (insn, 13);
2909 else if (*s == 'I')
2910 imm = X_SIMM (insn, 11);
2911 else
2912 imm = X_SIMM (insn, 10);
2913
2914 /* Check to see whether we have a 1+i, and take
2915 note of that fact.
2916
2917 Note: because of the way we sort the table,
2918 we will be matching 1+i rather than i+1,
2919 so it is OK to assume that i is after +,
2920 not before it. */
2921 if (found_plus)
2922 imm_added_to_rs1 = 1;
2923
2924 if (imm <= 9)
2925 (*info->fprintf_func) (stream, "%d", imm);
2926 else
2927 (*info->fprintf_func) (stream, "%#x", imm);
2928 }
2929 break;
2930
46f42f29
BS		 2931 case 'X': /* 5 bit unsigned immediate. */
2932 case 'Y': /* 6 bit unsigned immediate. */
f930d07e
BS		 2933 {
2934 int imm = X_IMM (insn, *s == 'X' ? 5 : 6);
2935
2936 if (imm <= 9)
2937 (info->fprintf_func) (stream, "%d", imm);
2938 else
2939 (info->fprintf_func) (stream, "%#x", (unsigned) imm);
2940 }
2941 break;
2942
2943 case '3':
46f42f29 2944 (info->fprintf_func) (stream, "%ld", X_IMM (insn, 3));
f930d07e
BS		 2945 break;
2946
2947 case 'K':
2948 {
2949 int mask = X_MEMBAR (insn);
2950 int bit = 0x40, printed_one = 0;
2951 const char *name;
2952
2953 if (mask == 0)
2954 (info->fprintf_func) (stream, "0");
2955 else
2956 while (bit)
2957 {
2958 if (mask & bit)
2959 {
2960 if (printed_one)
2961 (info->fprintf_func) (stream, "|");
2962 name = sparc_decode_membar (bit);
2963 (info->fprintf_func) (stream, "%s", name);
2964 printed_one = 1;
2965 }
2966 bit >>= 1;
2967 }
2968 break;
2969 }
2970
2971 case 'k':
2972 info->target = memaddr + SEX (X_DISP16 (insn), 16) * 4;
2973 (*info->print_address_func) (info->target, info);
2974 break;
2975
2976 case 'G':
2977 info->target = memaddr + SEX (X_DISP19 (insn), 19) * 4;
2978 (*info->print_address_func) (info->target, info);
2979 break;
2980
2981 case '6':
2982 case '7':
2983 case '8':
2984 case '9':
2985 (*info->fprintf_func) (stream, "%%fcc%c", *s - '6' + '0');
2986 break;
2987
2988 case 'z':
2989 (*info->fprintf_func) (stream, "%%icc");
2990 break;
2991
2992 case 'Z':
2993 (*info->fprintf_func) (stream, "%%xcc");
2994 break;
2995
2996 case 'E':
2997 (*info->fprintf_func) (stream, "%%ccr");
2998 break;
2999
3000 case 's':
3001 (*info->fprintf_func) (stream, "%%fprs");
3002 break;
3003
3004 case 'o':
3005 (*info->fprintf_func) (stream, "%%asi");
3006 break;
3007
3008 case 'W':
3009 (*info->fprintf_func) (stream, "%%tick");
3010 break;
3011
3012 case 'P':
3013 (*info->fprintf_func) (stream, "%%pc");
3014 break;
3015
3016 case '?':
3017 if (X_RS1 (insn) == 31)
3018 (*info->fprintf_func) (stream, "%%ver");
46f42f29 3019 else if ((unsigned) X_RS1 (insn) < 17)
f930d07e
BS		 3020 (*info->fprintf_func) (stream, "%%%s",
3021 v9_priv_reg_names[X_RS1 (insn)]);
3022 else
3023 (*info->fprintf_func) (stream, "%%reserved");
3024 break;
3025
3026 case '!':
46f42f29 3027 if ((unsigned) X_RD (insn) < 17)
f930d07e
BS		 3028 (*info->fprintf_func) (stream, "%%%s",
3029 v9_priv_reg_names[X_RD (insn)]);
3030 else
3031 (*info->fprintf_func) (stream, "%%reserved");
3032 break;
3033
46f42f29
BS		 3034 case '$':
3035 if ((unsigned) X_RS1 (insn) < 32)
3036 (*info->fprintf_func) (stream, "%%%s",
3037 v9_hpriv_reg_names[X_RS1 (insn)]);
3038 else
3039 (*info->fprintf_func) (stream, "%%reserved");
3040 break;
3041
3042 case '%':
3043 if ((unsigned) X_RD (insn) < 32)
3044 (*info->fprintf_func) (stream, "%%%s",
3045 v9_hpriv_reg_names[X_RD (insn)]);
3046 else
3047 (*info->fprintf_func) (stream, "%%reserved");
3048 break;
3049
f930d07e
BS		 3050 case '/':
3051 if (X_RS1 (insn) < 16 || X_RS1 (insn) > 25)
3052 (*info->fprintf_func) (stream, "%%reserved");
3053 else
3054 (*info->fprintf_func) (stream, "%%%s",
3055 v9a_asr_reg_names[X_RS1 (insn)-16]);
3056 break;
3057
3058 case '_':
3059 if (X_RD (insn) < 16 || X_RD (insn) > 25)
3060 (*info->fprintf_func) (stream, "%%reserved");
3061 else
3062 (*info->fprintf_func) (stream, "%%%s",
3063 v9a_asr_reg_names[X_RD (insn)-16]);
3064 break;
3065
3066 case '*':
3067 {
3068 const char *name = sparc_decode_prefetch (X_RD (insn));
3069
3070 if (name)
3071 (*info->fprintf_func) (stream, "%s", name);
3072 else
46f42f29 3073 (*info->fprintf_func) (stream, "%ld", X_RD (insn));
f930d07e
BS		 3074 break;
3075 }
3076
3077 case 'M':
46f42f29 3078 (*info->fprintf_func) (stream, "%%asr%ld", X_RS1 (insn));
f930d07e
BS		 3079 break;
3080
3081 case 'm':
46f42f29 3082 (*info->fprintf_func) (stream, "%%asr%ld", X_RD (insn));
f930d07e
BS		 3083 break;
3084
3085 case 'L':
3086 info->target = memaddr + SEX (X_DISP30 (insn), 30) * 4;
3087 (*info->print_address_func) (info->target, info);
3088 break;
3089
3090 case 'n':
3091 (*info->fprintf_func)
3092 (stream, "%#x", SEX (X_DISP22 (insn), 22));
3093 break;
3094
3095 case 'l':
3096 info->target = memaddr + SEX (X_DISP22 (insn), 22) * 4;
3097 (*info->print_address_func) (info->target, info);
3098 break;
3099
3100 case 'A':
3101 {
3102 const char *name;
3103
3104 if ((info->mach == bfd_mach_sparc_v8plusa) ||
725cb90b
FB		 3105 ((info->mach >= bfd_mach_sparc_v9) &&
3106 (info->mach <= bfd_mach_sparc_v9b)))
f930d07e
BS		 3107 name = sparc_decode_asi_v9 (X_ASI (insn));
3108 else
3109 name = sparc_decode_asi_v8 (X_ASI (insn));
3110
3111 if (name)
3112 (*info->fprintf_func) (stream, "%s", name);
3113 else
46f42f29 3114 (*info->fprintf_func) (stream, "(%ld)", X_ASI (insn));
f930d07e
BS		 3115 break;
3116 }
3117
3118 case 'C':
3119 (*info->fprintf_func) (stream, "%%csr");
3120 break;
3121
3122 case 'F':
3123 (*info->fprintf_func) (stream, "%%fsr");
3124 break;
3125
3126 case 'p':
3127 (*info->fprintf_func) (stream, "%%psr");
3128 break;
3129
3130 case 'q':
3131 (*info->fprintf_func) (stream, "%%fq");
3132 break;
3133
3134 case 'Q':
3135 (*info->fprintf_func) (stream, "%%cq");
3136 break;
3137
3138 case 't':
3139 (*info->fprintf_func) (stream, "%%tbr");
3140 break;
3141
3142 case 'w':
3143 (*info->fprintf_func) (stream, "%%wim");
3144 break;
3145
3146 case 'x':
46f42f29 3147 (*info->fprintf_func) (stream, "%ld",
f930d07e
BS		 3148 ((X_LDST_I (insn) << 8)
3149 + X_ASI (insn)));
3150 break;
3151
3152 case 'y':
3153 (*info->fprintf_func) (stream, "%%y");
3154 break;
3155
3156 case 'u':
3157 case 'U':
3158 {
3159 int val = *s == 'U' ? X_RS1 (insn) : X_RD (insn);
3160 const char *name = sparc_decode_sparclet_cpreg (val);
3161
3162 if (name)
3163 (*info->fprintf_func) (stream, "%s", name);
3164 else
3165 (*info->fprintf_func) (stream, "%%cpreg(%d)", val);
3166 break;
3167 }
3168 }
3169 }
3170 }
3171
3172 /* If we are adding or or'ing something to rs1, then
3173 check to see whether the previous instruction was
3174 a sethi to the same register as in the sethi.
3175 If so, attempt to print the result of the add or
3176 or (in this context add and or do the same thing)
3177 and its symbolic value. */
3178 if (imm_ored_to_rs1 || imm_added_to_rs1)
3179 {
3180 unsigned long prev_insn;
3181 int errcode;
3182
46f42f29
BS		 3183 if (memaddr >= 4)
3184 errcode =
3185 (*info->read_memory_func)
f930d07e 3186 (memaddr - 4, buffer, sizeof (buffer), info);
46f42f29
BS		 3187 else
3188 errcode = 1;
3189
f930d07e
BS		 3190 prev_insn = getword (buffer);
3191
3192 if (errcode == 0)
3193 {
3194 /* If it is a delayed branch, we need to look at the
3195 instruction before the delayed branch. This handles
46f42f29 3196 sequences such as:
f930d07e
BS		 3197
3198 sethi %o1, %hi(_foo), %o1
3199 call _printf
46f42f29 3200 or %o1, %lo(_foo), %o1 */
f930d07e
BS		 3201
3202 if (is_delayed_branch (prev_insn))
3203 {
46f42f29
BS		 3204 if (memaddr >= 8)
3205 errcode = (*info->read_memory_func)
3206 (memaddr - 8, buffer, sizeof (buffer), info);
3207 else
3208 errcode = 1;
3209
f930d07e
BS		 3210 prev_insn = getword (buffer);
3211 }
3212 }
3213
3214 /* If there was a problem reading memory, then assume
3215 the previous instruction was not sethi. */
3216 if (errcode == 0)
3217 {
3218 /* Is it sethi to the same register? */
3219 if ((prev_insn & 0xc1c00000) == 0x01000000
3220 && X_RD (prev_insn) == X_RS1 (insn))
3221 {
3222 (*info->fprintf_func) (stream, "\t! ");
3223 info->target =
3224 ((unsigned) 0xFFFFFFFF
3225 & ((int) X_IMM22 (prev_insn) << 10));
3226 if (imm_added_to_rs1)
3227 info->target += X_SIMM (insn, 13);
3228 else
3229 info->target |= X_SIMM (insn, 13);
3230 (*info->print_address_func) (info->target, info);
3231 info->insn_type = dis_dref;
3232 info->data_size = 4; /* FIXME!!! */
3233 }
3234 }
3235 }
3236
3237 if (opcode->flags & (F_UNBR|F_CONDBR|F_JSR))
3238 {
46f42f29 3239 /* FIXME -- check is_annulled flag. */
f930d07e
BS		 3240 if (opcode->flags & F_UNBR)
3241 info->insn_type = dis_branch;
3242 if (opcode->flags & F_CONDBR)
3243 info->insn_type = dis_condbranch;
3244 if (opcode->flags & F_JSR)
3245 info->insn_type = dis_jsr;
3246 if (opcode->flags & F_DELAYED)
3247 info->branch_delay_insns = 1;
3248 }
3249
3250 return sizeof (buffer);
3251 }
aa0aa4fa
FB		 3252 }
3253
46f42f29 3254 info->insn_type = dis_noninsn; /* Mark as non-valid instruction. */
aa0aa4fa
FB		 3255 (*info->fprintf_func) (stream, _("unknown"));
3256 return sizeof (buffer);
3257}
Qemu copy for testing