[qemu.git] / target-alpha / cpu.h

/*
 *  Alpha emulation cpu definitions for qemu.
 *
 *  Copyright (c) 2007 Jocelyn Mayer
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#if !defined (__CPU_ALPHA_H__)
#define __CPU_ALPHA_H__

#include "config.h"
#include "qemu-common.h"

#define TARGET_LONG_BITS 64

#define CPUArchState struct CPUAlphaState

#include "exec/cpu-defs.h"

#include "fpu/softfloat.h"

#define TARGET_HAS_ICE 1

#define ELF_MACHINE     EM_ALPHA

#define ICACHE_LINE_SIZE 32
#define DCACHE_LINE_SIZE 32

#define TARGET_PAGE_BITS 13

#ifdef CONFIG_USER_ONLY
/* ??? The kernel likes to give addresses in high memory.  If the host has
   more virtual address space than the guest, this can lead to impossible
   allocations.  Honor the long-standing assumption that only kernel addrs
   are negative, but otherwise allow allocations anywhere.  This could lead
   to tricky emulation problems for programs doing tagged addressing, but
   that's far fewer than encounter the impossible allocation problem.  */
#define TARGET_PHYS_ADDR_SPACE_BITS  63
#define TARGET_VIRT_ADDR_SPACE_BITS  63
#else
/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44.  */
#define TARGET_PHYS_ADDR_SPACE_BITS  44
#define TARGET_VIRT_ADDR_SPACE_BITS  (30 + TARGET_PAGE_BITS)
#endif

/* Alpha major type */
enum {
    ALPHA_EV3  = 1,
    ALPHA_EV4  = 2,
    ALPHA_SIM  = 3,
    ALPHA_LCA  = 4,
    ALPHA_EV5  = 5, /* 21164 */
    ALPHA_EV45 = 6, /* 21064A */
    ALPHA_EV56 = 7, /* 21164A */
};

/* EV4 minor type */
enum {
    ALPHA_EV4_2 = 0,
    ALPHA_EV4_3 = 1,
};

/* LCA minor type */
enum {
    ALPHA_LCA_1 = 1, /* 21066 */
    ALPHA_LCA_2 = 2, /* 20166 */
    ALPHA_LCA_3 = 3, /* 21068 */
    ALPHA_LCA_4 = 4, /* 21068 */
    ALPHA_LCA_5 = 5, /* 21066A */
    ALPHA_LCA_6 = 6, /* 21068A */
};

/* EV5 minor type */
enum {
    ALPHA_EV5_1 = 1, /* Rev BA, CA */
    ALPHA_EV5_2 = 2, /* Rev DA, EA */
    ALPHA_EV5_3 = 3, /* Pass 3 */
    ALPHA_EV5_4 = 4, /* Pass 3.2 */
    ALPHA_EV5_5 = 5, /* Pass 4 */
};

/* EV45 minor type */
enum {
    ALPHA_EV45_1 = 1, /* Pass 1 */
    ALPHA_EV45_2 = 2, /* Pass 1.1 */
    ALPHA_EV45_3 = 3, /* Pass 2 */
};

/* EV56 minor type */
enum {
    ALPHA_EV56_1 = 1, /* Pass 1 */
    ALPHA_EV56_2 = 2, /* Pass 2 */
};

enum {
    IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
    IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
    IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
    IMPLVER_21364 = 3, /* EV7 & EV79 */
};

enum {
    AMASK_BWX      = 0x00000001,
    AMASK_FIX      = 0x00000002,
    AMASK_CIX      = 0x00000004,
    AMASK_MVI      = 0x00000100,
    AMASK_TRAP     = 0x00000200,
    AMASK_PREFETCH = 0x00001000,
};

enum {
    VAX_ROUND_NORMAL = 0,
    VAX_ROUND_CHOPPED,
};

enum {
    IEEE_ROUND_NORMAL = 0,
    IEEE_ROUND_DYNAMIC,
    IEEE_ROUND_PLUS,
    IEEE_ROUND_MINUS,
    IEEE_ROUND_CHOPPED,
};

/* IEEE floating-point operations encoding */
/* Trap mode */
enum {
    FP_TRAP_I   = 0x0,
    FP_TRAP_U   = 0x1,
    FP_TRAP_S  = 0x4,
    FP_TRAP_SU  = 0x5,
    FP_TRAP_SUI = 0x7,
};

/* Rounding mode */
enum {
    FP_ROUND_CHOPPED = 0x0,
    FP_ROUND_MINUS   = 0x1,
    FP_ROUND_NORMAL  = 0x2,
    FP_ROUND_DYNAMIC = 0x3,
};

/* FPCR bits */
#define FPCR_SUM		(1ULL << 63)
#define FPCR_INED		(1ULL << 62)
#define FPCR_UNFD		(1ULL << 61)
#define FPCR_UNDZ		(1ULL << 60)
#define FPCR_DYN_SHIFT		58
#define FPCR_DYN_CHOPPED	(0ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_MINUS		(1ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_NORMAL		(2ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_PLUS		(3ULL << FPCR_DYN_SHIFT)
#define FPCR_DYN_MASK		(3ULL << FPCR_DYN_SHIFT)
#define FPCR_IOV		(1ULL << 57)
#define FPCR_INE		(1ULL << 56)
#define FPCR_UNF		(1ULL << 55)
#define FPCR_OVF		(1ULL << 54)
#define FPCR_DZE		(1ULL << 53)
#define FPCR_INV		(1ULL << 52)
#define FPCR_OVFD		(1ULL << 51)
#define FPCR_DZED		(1ULL << 50)
#define FPCR_INVD		(1ULL << 49)
#define FPCR_DNZ		(1ULL << 48)
#define FPCR_DNOD		(1ULL << 47)
#define FPCR_STATUS_MASK	(FPCR_IOV | FPCR_INE | FPCR_UNF \
				 | FPCR_OVF | FPCR_DZE | FPCR_INV)

/* The silly software trap enables implemented by the kernel emulation.
   These are more or less architecturally required, since the real hardware
   has read-as-zero bits in the FPCR when the features aren't implemented.
   For the purposes of QEMU, we pretend the FPCR can hold everything.  */
#define SWCR_TRAP_ENABLE_INV	(1ULL << 1)
#define SWCR_TRAP_ENABLE_DZE	(1ULL << 2)
#define SWCR_TRAP_ENABLE_OVF	(1ULL << 3)
#define SWCR_TRAP_ENABLE_UNF	(1ULL << 4)
#define SWCR_TRAP_ENABLE_INE	(1ULL << 5)
#define SWCR_TRAP_ENABLE_DNO	(1ULL << 6)
#define SWCR_TRAP_ENABLE_MASK	((1ULL << 7) - (1ULL << 1))

#define SWCR_MAP_DMZ		(1ULL << 12)
#define SWCR_MAP_UMZ		(1ULL << 13)
#define SWCR_MAP_MASK		(SWCR_MAP_DMZ | SWCR_MAP_UMZ)

#define SWCR_STATUS_INV		(1ULL << 17)
#define SWCR_STATUS_DZE		(1ULL << 18)
#define SWCR_STATUS_OVF		(1ULL << 19)
#define SWCR_STATUS_UNF		(1ULL << 20)
#define SWCR_STATUS_INE		(1ULL << 21)
#define SWCR_STATUS_DNO		(1ULL << 22)
#define SWCR_STATUS_MASK	((1ULL << 23) - (1ULL << 17))

#define SWCR_MASK  (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)

/* MMU modes definitions */

/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
   The Unix PALcode only exposes the kernel and user modes; presumably
   executive and supervisor are used by VMS.

   PALcode itself uses physical mode for code and kernel mode for data;
   there are PALmode instructions that can access data via physical mode
   or via an os-installed "alternate mode", which is one of the 4 above.

   QEMU does not currently properly distinguish between code/data when
   looking up addresses.  To avoid having to address this issue, our
   emulated PALcode will cheat and use the KSEG mapping for its code+data
   rather than physical addresses.

   Moreover, we're only emulating Unix PALcode, and not attempting VMS.

   All of which allows us to drop all but kernel and user modes.
   Elide the unused MMU modes to save space.  */

#define NB_MMU_MODES 2

#define MMU_MODE0_SUFFIX _kernel
#define MMU_MODE1_SUFFIX _user
#define MMU_KERNEL_IDX   0
#define MMU_USER_IDX     1

typedef struct CPUAlphaState CPUAlphaState;

struct CPUAlphaState {
    uint64_t ir[31];
    float64 fir[31];
    uint64_t pc;
    uint64_t unique;
    uint64_t lock_addr;
    uint64_t lock_st_addr;
    uint64_t lock_value;
    float_status fp_status;
    /* The following fields make up the FPCR, but in FP_STATUS format.  */
    uint8_t fpcr_exc_status;
    uint8_t fpcr_exc_mask;
    uint8_t fpcr_dyn_round;
    uint8_t fpcr_flush_to_zero;
    uint8_t fpcr_dnod;
    uint8_t fpcr_undz;

    /* The Internal Processor Registers.  Some of these we assume always
       exist for use in user-mode.  */
    uint8_t ps;
    uint8_t intr_flag;
    uint8_t pal_mode;
    uint8_t fen;

    uint32_t pcc_ofs;

    /* These pass data from the exception logic in the translator and
       helpers to the OS entry point.  This is used for both system
       emulation and user-mode.  */
    uint64_t trap_arg0;
    uint64_t trap_arg1;
    uint64_t trap_arg2;

#if !defined(CONFIG_USER_ONLY)
    /* The internal data required by our emulation of the Unix PALcode.  */
    uint64_t exc_addr;
    uint64_t palbr;
    uint64_t ptbr;
    uint64_t vptptr;
    uint64_t sysval;
    uint64_t usp;
    uint64_t shadow[8];
    uint64_t scratch[24];
#endif

    /* This alarm doesn't exist in real hardware; we wish it did.  */
    uint64_t alarm_expire;

    /* Those resources are used only in QEMU core */
    CPU_COMMON

    int error_code;

    uint32_t features;
    uint32_t amask;
    int implver;
};

#define cpu_list alpha_cpu_list
#define cpu_exec cpu_alpha_exec
#define cpu_gen_code cpu_alpha_gen_code
#define cpu_signal_handler cpu_alpha_signal_handler

#include "exec/cpu-all.h"
#include "cpu-qom.h"

enum {
    FEATURE_ASN    = 0x00000001,
    FEATURE_SPS    = 0x00000002,
    FEATURE_VIRBND = 0x00000004,
    FEATURE_TBCHK  = 0x00000008,
};

enum {
    EXCP_RESET,
    EXCP_MCHK,
    EXCP_SMP_INTERRUPT,
    EXCP_CLK_INTERRUPT,
    EXCP_DEV_INTERRUPT,
    EXCP_MMFAULT,
    EXCP_UNALIGN,
    EXCP_OPCDEC,
    EXCP_ARITH,
    EXCP_FEN,
    EXCP_CALL_PAL,
    /* For Usermode emulation.  */
    EXCP_STL_C,
    EXCP_STQ_C,
};

/* Alpha-specific interrupt pending bits.  */
#define CPU_INTERRUPT_TIMER	CPU_INTERRUPT_TGT_EXT_0
#define CPU_INTERRUPT_SMP	CPU_INTERRUPT_TGT_EXT_1
#define CPU_INTERRUPT_MCHK	CPU_INTERRUPT_TGT_EXT_2

/* OSF/1 Page table bits.  */
enum {
    PTE_VALID = 0x0001,
    PTE_FOR   = 0x0002,  /* used for page protection (fault on read) */
    PTE_FOW   = 0x0004,  /* used for page protection (fault on write) */
    PTE_FOE   = 0x0008,  /* used for page protection (fault on exec) */
    PTE_ASM   = 0x0010,
    PTE_KRE   = 0x0100,
    PTE_URE   = 0x0200,
    PTE_KWE   = 0x1000,
    PTE_UWE   = 0x2000
};

/* Hardware interrupt (entInt) constants.  */
enum {
    INT_K_IP,
    INT_K_CLK,
    INT_K_MCHK,
    INT_K_DEV,
    INT_K_PERF,
};

/* Memory management (entMM) constants.  */
enum {
    MM_K_TNV,
    MM_K_ACV,
    MM_K_FOR,
    MM_K_FOE,
    MM_K_FOW
};

/* Arithmetic exception (entArith) constants.  */
enum {
    EXC_M_SWC = 1,      /* Software completion */
    EXC_M_INV = 2,      /* Invalid operation */
    EXC_M_DZE = 4,      /* Division by zero */
    EXC_M_FOV = 8,      /* Overflow */
    EXC_M_UNF = 16,     /* Underflow */
    EXC_M_INE = 32,     /* Inexact result */
    EXC_M_IOV = 64      /* Integer Overflow */
};

/* Processor status constants.  */
enum {
    /* Low 3 bits are interrupt mask level.  */
    PS_INT_MASK = 7,

    /* Bits 4 and 5 are the mmu mode.  The VMS PALcode uses all 4 modes;
       The Unix PALcode only uses bit 4.  */
    PS_USER_MODE = 8
};

static inline int cpu_mmu_index(CPUAlphaState *env)
{
    if (env->pal_mode) {
        return MMU_KERNEL_IDX;
    } else if (env->ps & PS_USER_MODE) {
        return MMU_USER_IDX;
    } else {
        return MMU_KERNEL_IDX;
    }
}

enum {
    IR_V0   = 0,
    IR_T0   = 1,
    IR_T1   = 2,
    IR_T2   = 3,
    IR_T3   = 4,
    IR_T4   = 5,
    IR_T5   = 6,
    IR_T6   = 7,
    IR_T7   = 8,
    IR_S0   = 9,
    IR_S1   = 10,
    IR_S2   = 11,
    IR_S3   = 12,
    IR_S4   = 13,
    IR_S5   = 14,
    IR_S6   = 15,
    IR_FP   = IR_S6,
    IR_A0   = 16,
    IR_A1   = 17,
    IR_A2   = 18,
    IR_A3   = 19,
    IR_A4   = 20,
    IR_A5   = 21,
    IR_T8   = 22,
    IR_T9   = 23,
    IR_T10  = 24,
    IR_T11  = 25,
    IR_RA   = 26,
    IR_T12  = 27,
    IR_PV   = IR_T12,
    IR_AT   = 28,
    IR_GP   = 29,
    IR_SP   = 30,
    IR_ZERO = 31,
};

void alpha_translate_init(void);

AlphaCPU *cpu_alpha_init(const char *cpu_model);

static inline CPUAlphaState *cpu_init(const char *cpu_model)
{
    AlphaCPU *cpu = cpu_alpha_init(cpu_model);
    if (cpu == NULL) {
        return NULL;
    }
    return &cpu->env;
}

void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf);
int cpu_alpha_exec(CPUAlphaState *s);
/* you can call this signal handler from your SIGBUS and SIGSEGV
   signal handlers to inform the virtual CPU of exceptions. non zero
   is returned if the signal was handled by the virtual CPU.  */
int cpu_alpha_signal_handler(int host_signum, void *pinfo,
                             void *puc);
int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw,
                                int mmu_idx);
#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);

uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
#ifndef CONFIG_USER_ONLY
void swap_shadow_regs(CPUAlphaState *env);
QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
                                               bool is_write, bool is_exec,
                                               int unused, unsigned size);
#endif

/* Bits in TB->FLAGS that control how translation is processed.  */
enum {
    TB_FLAGS_PAL_MODE = 1,
    TB_FLAGS_FEN = 2,
    TB_FLAGS_USER_MODE = 8,

    TB_FLAGS_AMASK_SHIFT = 4,
    TB_FLAGS_AMASK_BWX = AMASK_BWX << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_FIX = AMASK_FIX << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_CIX = AMASK_CIX << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_MVI = AMASK_MVI << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_TRAP = AMASK_TRAP << TB_FLAGS_AMASK_SHIFT,
    TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
};

static inline void cpu_get_tb_cpu_state(CPUAlphaState *env, target_ulong *pc,
                                        target_ulong *cs_base, int *pflags)
{
    int flags = 0;

    *pc = env->pc;
    *cs_base = 0;

    if (env->pal_mode) {
        flags = TB_FLAGS_PAL_MODE;
    } else {
        flags = env->ps & PS_USER_MODE;
    }
    if (env->fen) {
        flags |= TB_FLAGS_FEN;
    }
    flags |= env->amask << TB_FLAGS_AMASK_SHIFT;

    *pflags = flags;
}

static inline bool cpu_has_work(CPUState *cpu)
{
    /* Here we are checking to see if the CPU should wake up from HALT.
       We will have gotten into this state only for WTINT from PALmode.  */
    /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
       asleep even if (some) interrupts have been asserted.  For now,
       assume that if a CPU really wants to stay asleep, it will mask
       interrupts at the chipset level, which will prevent these bits
       from being set in the first place.  */
    return cpu->interrupt_request & (CPU_INTERRUPT_HARD
                                     | CPU_INTERRUPT_TIMER
                                     | CPU_INTERRUPT_SMP
                                     | CPU_INTERRUPT_MCHK);
}

#include "exec/exec-all.h"

#endif /* !defined (__CPU_ALPHA_H__) */
Commit	Line	Data
4c9649a9 JM	1	/*
4c9649a9 JM	2	* Alpha emulation cpu definitions for qemu.
5fafdf24	3	*
4c9649a9 JM	4	* Copyright (c) 2007 Jocelyn Mayer
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
8167ee88	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4c9649a9 JM	18	*/
	19
	20	#if !defined (__CPU_ALPHA_H__)
	21	#define __CPU_ALPHA_H__
	22
	23	#include "config.h"
2c976297	24	#include "qemu-common.h"
4c9649a9 JM	25
	26	#define TARGET_LONG_BITS 64
	27
9349b4f9	28	#define CPUArchState struct CPUAlphaState
c2764719	29
022c62cb	30	#include "exec/cpu-defs.h"
4c9649a9	31
6b4c305c	32	#include "fpu/softfloat.h"
4c9649a9	33
4c9649a9 JM	34	#define TARGET_HAS_ICE 1
4c9649a9 JM	35
f071b4d3	36	#define ELF_MACHINE EM_ALPHA
4c9649a9 JM	37
	38	#define ICACHE_LINE_SIZE 32
	39	#define DCACHE_LINE_SIZE 32
	40
b09d9d46	41	#define TARGET_PAGE_BITS 13
4c9649a9	42
76393642 RH	43	#ifdef CONFIG_USER_ONLY
	44	/* ??? The kernel likes to give addresses in high memory. If the host has
	45	more virtual address space than the guest, this can lead to impossible
	46	allocations. Honor the long-standing assumption that only kernel addrs
	47	are negative, but otherwise allow allocations anywhere. This could lead
	48	to tricky emulation problems for programs doing tagged addressing, but
	49	that's far fewer than encounter the impossible allocation problem. */
	50	#define TARGET_PHYS_ADDR_SPACE_BITS 63
	51	#define TARGET_VIRT_ADDR_SPACE_BITS 63
	52	#else
52705890	53	/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
76393642 RH	54	#define TARGET_PHYS_ADDR_SPACE_BITS 44
	55	#define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
	56	#endif
4c9649a9 JM	57
	58	/* Alpha major type */
	59	enum {
	60	ALPHA_EV3 = 1,
	61	ALPHA_EV4 = 2,
	62	ALPHA_SIM = 3,
	63	ALPHA_LCA = 4,
	64	ALPHA_EV5 = 5, /* 21164 */
	65	ALPHA_EV45 = 6, /* 21064A */
	66	ALPHA_EV56 = 7, /* 21164A */
	67	};
	68
	69	/* EV4 minor type */
	70	enum {
	71	ALPHA_EV4_2 = 0,
	72	ALPHA_EV4_3 = 1,
	73	};
	74
	75	/* LCA minor type */
	76	enum {
	77	ALPHA_LCA_1 = 1, /* 21066 */
	78	ALPHA_LCA_2 = 2, /* 20166 */
	79	ALPHA_LCA_3 = 3, /* 21068 */
	80	ALPHA_LCA_4 = 4, /* 21068 */
	81	ALPHA_LCA_5 = 5, /* 21066A */
	82	ALPHA_LCA_6 = 6, /* 21068A */
	83	};
	84
	85	/* EV5 minor type */
	86	enum {
	87	ALPHA_EV5_1 = 1, /* Rev BA, CA */
	88	ALPHA_EV5_2 = 2, /* Rev DA, EA */
	89	ALPHA_EV5_3 = 3, /* Pass 3 */
	90	ALPHA_EV5_4 = 4, /* Pass 3.2 */
	91	ALPHA_EV5_5 = 5, /* Pass 4 */
	92	};
	93
	94	/* EV45 minor type */
	95	enum {
	96	ALPHA_EV45_1 = 1, /* Pass 1 */
	97	ALPHA_EV45_2 = 2, /* Pass 1.1 */
	98	ALPHA_EV45_3 = 3, /* Pass 2 */
	99	};
	100
	101	/* EV56 minor type */
	102	enum {
	103	ALPHA_EV56_1 = 1, /* Pass 1 */
	104	ALPHA_EV56_2 = 2, /* Pass 2 */
	105	};
	106
	107	enum {
	108	IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
	109	IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
	110	IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
	111	IMPLVER_21364 = 3, /* EV7 & EV79 */
	112	};
	113
	114	enum {
	115	AMASK_BWX = 0x00000001,
	116	AMASK_FIX = 0x00000002,
	117	AMASK_CIX = 0x00000004,
	118	AMASK_MVI = 0x00000100,
	119	AMASK_TRAP = 0x00000200,
	120	AMASK_PREFETCH = 0x00001000,
121	};
122
123	enum {
124	VAX_ROUND_NORMAL = 0,
125	VAX_ROUND_CHOPPED,
126	};
127
128	enum {
129	IEEE_ROUND_NORMAL = 0,
130	IEEE_ROUND_DYNAMIC,
131	IEEE_ROUND_PLUS,
132	IEEE_ROUND_MINUS,
133	IEEE_ROUND_CHOPPED,
134	};
135
136	/* IEEE floating-point operations encoding */
137	/* Trap mode */
138	enum {
139	FP_TRAP_I = 0x0,
140	FP_TRAP_U = 0x1,
141	FP_TRAP_S = 0x4,
142	FP_TRAP_SU = 0x5,
143	FP_TRAP_SUI = 0x7,
144	};
145
146	/* Rounding mode */
147	enum {
148	FP_ROUND_CHOPPED = 0x0,
149	FP_ROUND_MINUS = 0x1,
150	FP_ROUND_NORMAL = 0x2,
151	FP_ROUND_DYNAMIC = 0x3,
152	};
153
ba0e276d RH	154	/* FPCR bits */
	155	#define FPCR_SUM (1ULL << 63)
	156	#define FPCR_INED (1ULL << 62)
	157	#define FPCR_UNFD (1ULL << 61)
	158	#define FPCR_UNDZ (1ULL << 60)
	159	#define FPCR_DYN_SHIFT 58
8443effb RH	160	#define FPCR_DYN_CHOPPED (0ULL << FPCR_DYN_SHIFT)
	161	#define FPCR_DYN_MINUS (1ULL << FPCR_DYN_SHIFT)
	162	#define FPCR_DYN_NORMAL (2ULL << FPCR_DYN_SHIFT)
	163	#define FPCR_DYN_PLUS (3ULL << FPCR_DYN_SHIFT)
ba0e276d RH	164	#define FPCR_DYN_MASK (3ULL << FPCR_DYN_SHIFT)
	165	#define FPCR_IOV (1ULL << 57)
	166	#define FPCR_INE (1ULL << 56)
	167	#define FPCR_UNF (1ULL << 55)
	168	#define FPCR_OVF (1ULL << 54)
	169	#define FPCR_DZE (1ULL << 53)
	170	#define FPCR_INV (1ULL << 52)
	171	#define FPCR_OVFD (1ULL << 51)
	172	#define FPCR_DZED (1ULL << 50)
	173	#define FPCR_INVD (1ULL << 49)
	174	#define FPCR_DNZ (1ULL << 48)
	175	#define FPCR_DNOD (1ULL << 47)
	176	#define FPCR_STATUS_MASK (FPCR_IOV \| FPCR_INE \| FPCR_UNF \
	177	\| FPCR_OVF \| FPCR_DZE \| FPCR_INV)
	178
	179	/* The silly software trap enables implemented by the kernel emulation.
	180	These are more or less architecturally required, since the real hardware
	181	has read-as-zero bits in the FPCR when the features aren't implemented.
	182	For the purposes of QEMU, we pretend the FPCR can hold everything. */
	183	#define SWCR_TRAP_ENABLE_INV (1ULL << 1)
	184	#define SWCR_TRAP_ENABLE_DZE (1ULL << 2)
	185	#define SWCR_TRAP_ENABLE_OVF (1ULL << 3)
	186	#define SWCR_TRAP_ENABLE_UNF (1ULL << 4)
	187	#define SWCR_TRAP_ENABLE_INE (1ULL << 5)
	188	#define SWCR_TRAP_ENABLE_DNO (1ULL << 6)
	189	#define SWCR_TRAP_ENABLE_MASK ((1ULL << 7) - (1ULL << 1))
	190
	191	#define SWCR_MAP_DMZ (1ULL << 12)
	192	#define SWCR_MAP_UMZ (1ULL << 13)
	193	#define SWCR_MAP_MASK (SWCR_MAP_DMZ \| SWCR_MAP_UMZ)
	194
	195	#define SWCR_STATUS_INV (1ULL << 17)
	196	#define SWCR_STATUS_DZE (1ULL << 18)
	197	#define SWCR_STATUS_OVF (1ULL << 19)
	198	#define SWCR_STATUS_UNF (1ULL << 20)
	199	#define SWCR_STATUS_INE (1ULL << 21)
	200	#define SWCR_STATUS_DNO (1ULL << 22)
	201	#define SWCR_STATUS_MASK ((1ULL << 23) - (1ULL << 17))
	202
	203	#define SWCR_MASK (SWCR_TRAP_ENABLE_MASK \| SWCR_MAP_MASK \| SWCR_STATUS_MASK)
	204
8417845e RH	205	/* MMU modes definitions */
	206
	207	/* Alpha has 5 MMU modes: PALcode, kernel, executive, supervisor, and user.
	208	The Unix PALcode only exposes the kernel and user modes; presumably
	209	executive and supervisor are used by VMS.
	210
	211	PALcode itself uses physical mode for code and kernel mode for data;
	212	there are PALmode instructions that can access data via physical mode
	213	or via an os-installed "alternate mode", which is one of the 4 above.
	214
	215	QEMU does not currently properly distinguish between code/data when
	216	looking up addresses. To avoid having to address this issue, our
	217	emulated PALcode will cheat and use the KSEG mapping for its code+data
	218	rather than physical addresses.
	219
	220	Moreover, we're only emulating Unix PALcode, and not attempting VMS.
	221
	222	All of which allows us to drop all but kernel and user modes.
	223	Elide the unused MMU modes to save space. */
4c9649a9	224
8417845e RH	225	#define NB_MMU_MODES 2
	226
	227	#define MMU_MODE0_SUFFIX _kernel
	228	#define MMU_MODE1_SUFFIX _user
	229	#define MMU_KERNEL_IDX 0
	230	#define MMU_USER_IDX 1
	231
	232	typedef struct CPUAlphaState CPUAlphaState;
6ebbf390	233
4c9649a9 JM	234	struct CPUAlphaState {
4c9649a9 JM	235	uint64_t ir[31];
8443effb	236	float64 fir[31];
4c9649a9	237	uint64_t pc;
4c9649a9	238	uint64_t unique;
6910b8f6 RH	239	uint64_t lock_addr;
	240	uint64_t lock_st_addr;
	241	uint64_t lock_value;
8443effb RH	242	float_status fp_status;
	243	/* The following fields make up the FPCR, but in FP_STATUS format. */
	244	uint8_t fpcr_exc_status;
	245	uint8_t fpcr_exc_mask;
	246	uint8_t fpcr_dyn_round;
	247	uint8_t fpcr_flush_to_zero;
8443effb RH	248	uint8_t fpcr_dnod;
	249	uint8_t fpcr_undz;
	250
129d8aa5 RH	251	/* The Internal Processor Registers. Some of these we assume always
	252	exist for use in user-mode. */
	253	uint8_t ps;
8443effb	254	uint8_t intr_flag;
129d8aa5	255	uint8_t pal_mode;
26b46094 RH	256	uint8_t fen;
	257
	258	uint32_t pcc_ofs;
129d8aa5 RH	259
	260	/* These pass data from the exception logic in the translator and
	261	helpers to the OS entry point. This is used for both system
	262	emulation and user-mode. */
	263	uint64_t trap_arg0;
	264	uint64_t trap_arg1;
	265	uint64_t trap_arg2;
4c9649a9	266
26b46094 RH	267	#if !defined(CONFIG_USER_ONLY)
	268	/* The internal data required by our emulation of the Unix PALcode. */
	269	uint64_t exc_addr;
	270	uint64_t palbr;
	271	uint64_t ptbr;
	272	uint64_t vptptr;
	273	uint64_t sysval;
	274	uint64_t usp;
	275	uint64_t shadow[8];
	276	uint64_t scratch[24];
	277	#endif
	278
c781cf96	279	/* This alarm doesn't exist in real hardware; we wish it did. */
c781cf96 RH	280	uint64_t alarm_expire;
c781cf96 RH	281
5cbdb3a3	282	/* Those resources are used only in QEMU core */
4c9649a9 JM	283	CPU_COMMON
4c9649a9 JM	284
4c9649a9	285	int error_code;
4c9649a9 JM	286
	287	uint32_t features;
	288	uint32_t amask;
	289	int implver;
4c9649a9 JM	290	};
4c9649a9 JM	291
494342b3	292	#define cpu_list alpha_cpu_list
9467d44c TS	293	#define cpu_exec cpu_alpha_exec
	294	#define cpu_gen_code cpu_alpha_gen_code
	295	#define cpu_signal_handler cpu_alpha_signal_handler
	296
022c62cb	297	#include "exec/cpu-all.h"
25ebd80f	298	#include "cpu-qom.h"
4c9649a9 JM	299
	300	enum {
	301	FEATURE_ASN = 0x00000001,
	302	FEATURE_SPS = 0x00000002,
	303	FEATURE_VIRBND = 0x00000004,
	304	FEATURE_TBCHK = 0x00000008,
	305	};
	306
	307	enum {
07b6c13b RH	308	EXCP_RESET,
	309	EXCP_MCHK,
	310	EXCP_SMP_INTERRUPT,
	311	EXCP_CLK_INTERRUPT,
	312	EXCP_DEV_INTERRUPT,
	313	EXCP_MMFAULT,
	314	EXCP_UNALIGN,
	315	EXCP_OPCDEC,
	316	EXCP_ARITH,
	317	EXCP_FEN,
	318	EXCP_CALL_PAL,
	319	/* For Usermode emulation. */
	320	EXCP_STL_C,
	321	EXCP_STQ_C,
4c9649a9 JM	322	};
4c9649a9 JM	323
6a80e088 RH	324	/* Alpha-specific interrupt pending bits. */
	325	#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_EXT_0
	326	#define CPU_INTERRUPT_SMP CPU_INTERRUPT_TGT_EXT_1
	327	#define CPU_INTERRUPT_MCHK CPU_INTERRUPT_TGT_EXT_2
	328
a3b9af16 RH	329	/* OSF/1 Page table bits. */
	330	enum {
	331	PTE_VALID = 0x0001,
	332	PTE_FOR = 0x0002, /* used for page protection (fault on read) */
	333	PTE_FOW = 0x0004, /* used for page protection (fault on write) */
	334	PTE_FOE = 0x0008, /* used for page protection (fault on exec) */
	335	PTE_ASM = 0x0010,
	336	PTE_KRE = 0x0100,
	337	PTE_URE = 0x0200,
	338	PTE_KWE = 0x1000,
	339	PTE_UWE = 0x2000
	340	};
	341
ea879fc7 RH	342	/* Hardware interrupt (entInt) constants. */
	343	enum {
	344	INT_K_IP,
	345	INT_K_CLK,
	346	INT_K_MCHK,
	347	INT_K_DEV,
	348	INT_K_PERF,
	349	};
	350
	351	/* Memory management (entMM) constants. */
	352	enum {
	353	MM_K_TNV,
	354	MM_K_ACV,
	355	MM_K_FOR,
	356	MM_K_FOE,
	357	MM_K_FOW
	358	};
	359
	360	/* Arithmetic exception (entArith) constants. */
	361	enum {
	362	EXC_M_SWC = 1, /* Software completion */
	363	EXC_M_INV = 2, /* Invalid operation */
	364	EXC_M_DZE = 4, /* Division by zero */
	365	EXC_M_FOV = 8, /* Overflow */
	366	EXC_M_UNF = 16, /* Underflow */
	367	EXC_M_INE = 32, /* Inexact result */
	368	EXC_M_IOV = 64 /* Integer Overflow */
	369	};
	370
	371	/* Processor status constants. */
	372	enum {
	373	/* Low 3 bits are interrupt mask level. */
	374	PS_INT_MASK = 7,
	375
	376	/* Bits 4 and 5 are the mmu mode. The VMS PALcode uses all 4 modes;
	377	The Unix PALcode only uses bit 4. */
	378	PS_USER_MODE = 8
	379	};
	380
4d5712f1	381	static inline int cpu_mmu_index(CPUAlphaState *env)
ea879fc7	382	{
bba9bdce RH	383	if (env->pal_mode) {
	384	return MMU_KERNEL_IDX;
	385	} else if (env->ps & PS_USER_MODE) {
	386	return MMU_USER_IDX;
	387	} else {
	388	return MMU_KERNEL_IDX;
	389	}
ea879fc7	390	}
4c9649a9	391
4c9649a9 JM	392	enum {
	393	IR_V0 = 0,
	394	IR_T0 = 1,
	395	IR_T1 = 2,
	396	IR_T2 = 3,
	397	IR_T3 = 4,
	398	IR_T4 = 5,
	399	IR_T5 = 6,
	400	IR_T6 = 7,
	401	IR_T7 = 8,
	402	IR_S0 = 9,
	403	IR_S1 = 10,
	404	IR_S2 = 11,
	405	IR_S3 = 12,
	406	IR_S4 = 13,
	407	IR_S5 = 14,
	408	IR_S6 = 15,
a4b388ff	409	IR_FP = IR_S6,
4c9649a9 JM	410	IR_A0 = 16,
	411	IR_A1 = 17,
	412	IR_A2 = 18,
	413	IR_A3 = 19,
	414	IR_A4 = 20,
	415	IR_A5 = 21,
	416	IR_T8 = 22,
	417	IR_T9 = 23,
	418	IR_T10 = 24,
	419	IR_T11 = 25,
	420	IR_RA = 26,
	421	IR_T12 = 27,
a4b388ff	422	IR_PV = IR_T12,
4c9649a9 JM	423	IR_AT = 28,
	424	IR_GP = 29,
	425	IR_SP = 30,
	426	IR_ZERO = 31,
	427	};
	428
0c28246f AF	429	void alpha_translate_init(void);
0c28246f AF	430
5f5e3350 AF	431	AlphaCPU cpu_alpha_init(const char cpu_model);
	432
	433	static inline CPUAlphaState cpu_init(const char cpu_model)
	434	{
	435	AlphaCPU *cpu = cpu_alpha_init(cpu_model);
	436	if (cpu == NULL) {
	437	return NULL;
	438	}
	439	return &cpu->env;
	440	}
	441
494342b3	442	void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf);
e96efcfc JM	443	int cpu_alpha_exec(CPUAlphaState *s);
	444	/* you can call this signal handler from your SIGBUS and SIGSEGV
	445	signal handlers to inform the virtual CPU of exceptions. non zero
	446	is returned if the signal was handled by the virtual CPU. */
5fafdf24	447	int cpu_alpha_signal_handler(int host_signum, void *pinfo,
e96efcfc	448	void *puc);
4d5712f1	449	int cpu_alpha_handle_mmu_fault (CPUAlphaState *env, uint64_t address, int rw,
97b348e7	450	int mmu_idx);
0b5c1ce8	451	#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
20503968 BS	452	void do_restore_state(CPUAlphaState *, uintptr_t retaddr);
	453	void QEMU_NORETURN dynamic_excp(CPUAlphaState *, uintptr_t, int, int);
	454	void QEMU_NORETURN arith_excp(CPUAlphaState *, uintptr_t, int, uint64_t);
95870356	455
4d5712f1 AF	456	uint64_t cpu_alpha_load_fpcr (CPUAlphaState *env);
4d5712f1 AF	457	void cpu_alpha_store_fpcr (CPUAlphaState *env, uint64_t val);
5b450407	458	#ifndef CONFIG_USER_ONLY
4d5712f1	459	void swap_shadow_regs(CPUAlphaState *env);
c658b94f AF	460	QEMU_NORETURN void alpha_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
	461	bool is_write, bool is_exec,
	462	int unused, unsigned size);
5b450407	463	#endif
4c9649a9	464
a18ad893 RH	465	/* Bits in TB->FLAGS that control how translation is processed. */
	466	enum {
	467	TB_FLAGS_PAL_MODE = 1,
	468	TB_FLAGS_FEN = 2,
	469	TB_FLAGS_USER_MODE = 8,
	470
	471	TB_FLAGS_AMASK_SHIFT = 4,
	472	TB_FLAGS_AMASK_BWX = AMASK_BWX << TB_FLAGS_AMASK_SHIFT,
	473	TB_FLAGS_AMASK_FIX = AMASK_FIX << TB_FLAGS_AMASK_SHIFT,
	474	TB_FLAGS_AMASK_CIX = AMASK_CIX << TB_FLAGS_AMASK_SHIFT,
	475	TB_FLAGS_AMASK_MVI = AMASK_MVI << TB_FLAGS_AMASK_SHIFT,
	476	TB_FLAGS_AMASK_TRAP = AMASK_TRAP << TB_FLAGS_AMASK_SHIFT,
	477	TB_FLAGS_AMASK_PREFETCH = AMASK_PREFETCH << TB_FLAGS_AMASK_SHIFT,
	478	};
	479
4d5712f1	480	static inline void cpu_get_tb_cpu_state(CPUAlphaState env, target_ulong pc,
a18ad893	481	target_ulong cs_base, int pflags)
6b917547	482	{
a18ad893 RH	483	int flags = 0;
a18ad893 RH	484
6b917547 AL	485	*pc = env->pc;
6b917547 AL	486	*cs_base = 0;
a18ad893 RH	487
	488	if (env->pal_mode) {
	489	flags = TB_FLAGS_PAL_MODE;
	490	} else {
	491	flags = env->ps & PS_USER_MODE;
	492	}
	493	if (env->fen) {
	494	flags \|= TB_FLAGS_FEN;
	495	}
	496	flags \|= env->amask << TB_FLAGS_AMASK_SHIFT;
	497
	498	*pflags = flags;
6b917547 AL	499	}
6b917547 AL	500
3993c6bd	501	static inline bool cpu_has_work(CPUState *cpu)
f081c76c BS	502	{
	503	/* Here we are checking to see if the CPU should wake up from HALT.
	504	We will have gotten into this state only for WTINT from PALmode. */
	505	/* ??? I'm not sure how the IPL state works with WTINT to keep a CPU
	506	asleep even if (some) interrupts have been asserted. For now,
	507	assume that if a CPU really wants to stay asleep, it will mask
	508	interrupts at the chipset level, which will prevent these bits
	509	from being set in the first place. */
259186a7	510	return cpu->interrupt_request & (CPU_INTERRUPT_HARD
f081c76c BS	511	\| CPU_INTERRUPT_TIMER
	512	\| CPU_INTERRUPT_SMP
	513	\| CPU_INTERRUPT_MCHK);
	514	}
	515
022c62cb	516	#include "exec/exec-all.h"
f081c76c	517
4c9649a9	518	#endif /* !defined (__CPU_ALPHA_H__) */