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target-alpha: switch a few helpers to TCG
[qemu.git] / target-alpha / translate.c
CommitLineData
4c9649a9
JM		 1/*
2 * Alpha emulation cpu translation for qemu.
5fafdf24 3 *
4c9649a9
JM		 4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20
21#include <stdint.h>
22#include <stdlib.h>
23#include <stdio.h>
24
25#include "cpu.h"
26#include "exec-all.h"
27#include "disas.h"
ae8ecd42 28#include "host-utils.h"
496cb5b9 29#include "helper.h"
57fec1fe 30#include "tcg-op.h"
ca10f867 31#include "qemu-common.h"
4c9649a9
JM		 32
33#define DO_SINGLE_STEP
34#define GENERATE_NOP
35#define ALPHA_DEBUG_DISAS
36#define DO_TB_FLUSH
37
38typedef struct DisasContext DisasContext;
39struct DisasContext {
40 uint64_t pc;
41 int mem_idx;
42#if !defined (CONFIG_USER_ONLY)
43 int pal_mode;
44#endif
45 uint32_t amask;
46};
47
3761035f 48/* global register indexes */
b2437bf2 49static TCGv cpu_env;
496cb5b9
AJ		 50static TCGv cpu_ir[31];
51static TCGv cpu_pc;
52
3761035f
AJ		 53/* dyngen register indexes */
54static TCGv cpu_T[3];
55
56/* register names */
6ba8dcd7 57static char cpu_reg_names[10*4+21*5];
2e70f6ef
PB		 58
59#include "gen-icount.h"
60
a5f1b965 61static void alpha_translate_init(void)
2e70f6ef 62{
496cb5b9
AJ		 63 int i;
64 char *p;
2e70f6ef 65 static int done_init = 0;
496cb5b9 66
2e70f6ef
PB		 67 if (done_init)
68 return;
496cb5b9 69
2e70f6ef 70 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
496cb5b9 71
3761035f
AJ		 72#if TARGET_LONG_BITS > HOST_LONG_BITS
73 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
74 offsetof(CPUState, t0), "T0");
75 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
76 offsetof(CPUState, t1), "T1");
77 cpu_T[2] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
78 offsetof(CPUState, t2), "T2");
79#else
80 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG1, "T0");
81 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG2, "T1");
82 cpu_T[2] = tcg_global_reg_new(TCG_TYPE_I64, TCG_AREG3, "T2");
83#endif
84
496cb5b9
AJ		 85 p = cpu_reg_names;
86 for (i = 0; i < 31; i++) {
87 sprintf(p, "ir%d", i);
88 cpu_ir[i] = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
89 offsetof(CPUState, ir[i]), p);
6ba8dcd7 90 p += (i < 10) ? 4 : 5;
496cb5b9
AJ		 91 }
92
93 cpu_pc = tcg_global_mem_new(TCG_TYPE_I64, TCG_AREG0,
94 offsetof(CPUState, pc), "pc");
95
96 /* register helpers */
97#undef DEF_HELPER
98#define DEF_HELPER(ret, name, params) tcg_register_helper(name, #name);
99#include "helper.h"
100
2e70f6ef
PB		 101 done_init = 1;
102}
103
f071b4d3 104static always_inline void gen_op_nop (void)
4c9649a9
JM		 105{
106#if defined(GENERATE_NOP)
107 gen_op_no_op();
108#endif
109}
110
111#define GEN32(func, NAME) \
112static GenOpFunc *NAME ## _table [32] = { \
113NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3, \
114NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7, \
115NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11, \
116NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15, \
117NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19, \
118NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23, \
119NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27, \
120NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31, \
121}; \
f071b4d3 122static always_inline void func (int n) \
4c9649a9
JM		 123{ \
124 NAME ## _table[n](); \
125}
126
4c9649a9
JM		 127/* FIR moves */
128/* Special hacks for fir31 */
129#define gen_op_load_FT0_fir31 gen_op_reset_FT0
130#define gen_op_load_FT1_fir31 gen_op_reset_FT1
131#define gen_op_load_FT2_fir31 gen_op_reset_FT2
132#define gen_op_store_FT0_fir31 gen_op_nop
133#define gen_op_store_FT1_fir31 gen_op_nop
134#define gen_op_store_FT2_fir31 gen_op_nop
135#define gen_op_cmov_fir31 gen_op_nop
136GEN32(gen_op_load_FT0_fir, gen_op_load_FT0_fir);
137GEN32(gen_op_load_FT1_fir, gen_op_load_FT1_fir);
138GEN32(gen_op_load_FT2_fir, gen_op_load_FT2_fir);
139GEN32(gen_op_store_FT0_fir, gen_op_store_FT0_fir);
140GEN32(gen_op_store_FT1_fir, gen_op_store_FT1_fir);
141GEN32(gen_op_store_FT2_fir, gen_op_store_FT2_fir);
142GEN32(gen_op_cmov_fir, gen_op_cmov_fir);
143
f071b4d3 144static always_inline void gen_load_fir (DisasContext *ctx, int firn, int Tn)
4c9649a9
JM		 145{
146 switch (Tn) {
147 case 0:
148 gen_op_load_FT0_fir(firn);
149 break;
150 case 1:
151 gen_op_load_FT1_fir(firn);
152 break;
153 case 2:
154 gen_op_load_FT2_fir(firn);
155 break;
156 }
157}
158
f071b4d3 159static always_inline void gen_store_fir (DisasContext *ctx, int firn, int Tn)
4c9649a9
JM		 160{
161 switch (Tn) {
162 case 0:
163 gen_op_store_FT0_fir(firn);
164 break;
165 case 1:
166 gen_op_store_FT1_fir(firn);
167 break;
168 case 2:
169 gen_op_store_FT2_fir(firn);
170 break;
171 }
172}
173
174/* Memory moves */
175#if defined(CONFIG_USER_ONLY)
176#define OP_LD_TABLE(width) \
177static GenOpFunc *gen_op_ld##width[] = { \
178 &gen_op_ld##width##_raw, \
179}
180#define OP_ST_TABLE(width) \
181static GenOpFunc *gen_op_st##width[] = { \
182 &gen_op_st##width##_raw, \
183}
184#else
185#define OP_LD_TABLE(width) \
186static GenOpFunc *gen_op_ld##width[] = { \
187 &gen_op_ld##width##_kernel, \
bb6f6792
JM		 188 &gen_op_ld##width##_executive, \
189 &gen_op_ld##width##_supervisor, \
190 &gen_op_ld##width##_user, \
4c9649a9
JM		 191}
192#define OP_ST_TABLE(width) \
193static GenOpFunc *gen_op_st##width[] = { \
194 &gen_op_st##width##_kernel, \
bb6f6792
JM		 195 &gen_op_st##width##_executive, \
196 &gen_op_st##width##_supervisor, \
197 &gen_op_st##width##_user, \
4c9649a9
JM		 198}
199#endif
200
201#define GEN_LD(width) \
202OP_LD_TABLE(width); \
f071b4d3 203static always_inline void gen_ld##width (DisasContext *ctx) \
4c9649a9
JM		 204{ \
205 (*gen_op_ld##width[ctx->mem_idx])(); \
206}
207
208#define GEN_ST(width) \
209OP_ST_TABLE(width); \
f071b4d3 210static always_inline void gen_st##width (DisasContext *ctx) \
4c9649a9
JM		 211{ \
212 (*gen_op_st##width[ctx->mem_idx])(); \
213}
214
215GEN_LD(bu);
216GEN_ST(b);
217GEN_LD(wu);
218GEN_ST(w);
219GEN_LD(l);
220GEN_ST(l);
221GEN_LD(q);
222GEN_ST(q);
223GEN_LD(q_u);
224GEN_ST(q_u);
225GEN_LD(l_l);
226GEN_ST(l_c);
227GEN_LD(q_l);
228GEN_ST(q_c);
229
08ab123c 230#if 0 /* currently unused */
4c9649a9
JM		 231GEN_LD(f);
232GEN_ST(f);
233GEN_LD(g);
234GEN_ST(g);
08ab123c 235#endif /* 0 */
4c9649a9
JM		 236GEN_LD(s);
237GEN_ST(s);
238GEN_LD(t);
239GEN_ST(t);
240
f071b4d3 241static always_inline void _gen_op_bcond (DisasContext *ctx)
4c9649a9
JM		 242{
243#if 0 // Qemu does not know how to do this...
244 gen_op_bcond(ctx->pc);
245#else
246 gen_op_bcond(ctx->pc >> 32, ctx->pc);
247#endif
248}
249
f071b4d3
JM		 250static always_inline void gen_excp (DisasContext *ctx,
251 int exception, int error_code)
4c9649a9 252{
6ad02592
AJ		 253 TCGv tmp1, tmp2;
254
496cb5b9 255 tcg_gen_movi_i64(cpu_pc, ctx->pc);
6ad02592
AJ		 256 tmp1 = tcg_const_i32(exception);
257 tmp2 = tcg_const_i32(error_code);
258 tcg_gen_helper_0_2(helper_excp, tmp1, tmp2);
259 tcg_temp_free(tmp2);
260 tcg_temp_free(tmp1);
4c9649a9
JM		 261}
262
f071b4d3 263static always_inline void gen_invalid (DisasContext *ctx)
4c9649a9
JM		 264{
265 gen_excp(ctx, EXCP_OPCDEC, 0);
266}
267
f071b4d3
JM		 268static always_inline void gen_load_mem (DisasContext *ctx,
269 void (*gen_load_op)(DisasContext *ctx),
270 int ra, int rb, int32_t disp16,
271 int clear)
4c9649a9
JM		 272{
273 if (ra == 31 && disp16 == 0) {
274 /* UNOP */
275 gen_op_nop();
276 } else {
3761035f 277 if (rb != 31)
4f821e17 278 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
3761035f 279 else
4f821e17 280 tcg_gen_movi_i64(cpu_T[0], disp16);
4c9649a9 281 if (clear)
4f821e17 282 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);
4c9649a9 283 (*gen_load_op)(ctx);
3761035f
AJ		 284 if (ra != 31)
285 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
4c9649a9
JM		 286 }
287}
288
f071b4d3
JM		 289static always_inline void gen_store_mem (DisasContext *ctx,
290 void (*gen_store_op)(DisasContext *ctx),
291 int ra, int rb, int32_t disp16,
292 int clear)
4c9649a9 293{
3761035f 294 if (rb != 31)
4f821e17 295 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
3761035f 296 else
4f821e17 297 tcg_gen_movi_i64(cpu_T[0], disp16);
4c9649a9 298 if (clear)
4f821e17 299 tcg_gen_andi_i64(cpu_T[0], cpu_T[0], ~0x7);
3761035f
AJ		 300 if (ra != 31)
301 tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
302 else
303 tcg_gen_movi_i64(cpu_T[1], 0);
4c9649a9
JM		 304 (*gen_store_op)(ctx);
305}
306
f071b4d3
JM		 307static always_inline void gen_load_fmem (DisasContext *ctx,
308 void (*gen_load_fop)(DisasContext *ctx),
309 int ra, int rb, int32_t disp16)
4c9649a9 310{
3761035f 311 if (rb != 31)
4f821e17 312 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
3761035f 313 else
4f821e17 314 tcg_gen_movi_i64(cpu_T[0], disp16);
4c9649a9
JM		 315 (*gen_load_fop)(ctx);
316 gen_store_fir(ctx, ra, 1);
317}
318
f071b4d3
JM		 319static always_inline void gen_store_fmem (DisasContext *ctx,
320 void (*gen_store_fop)(DisasContext *ctx),
321 int ra, int rb, int32_t disp16)
4c9649a9 322{
3761035f 323 if (rb != 31)
4f821e17 324 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp16);
3761035f 325 else
4f821e17 326 tcg_gen_movi_i64(cpu_T[0], disp16);
4c9649a9
JM		 327 gen_load_fir(ctx, ra, 1);
328 (*gen_store_fop)(ctx);
329}
330
f071b4d3 331static always_inline void gen_bcond (DisasContext *ctx,
9c29504e
AJ		 332 TCGCond cond,
333 int ra, int32_t disp16, int mask)
4c9649a9 334{
9c29504e
AJ		 335 int l1, l2;
336
337 l1 = gen_new_label();
338 l2 = gen_new_label();
339 if (likely(ra != 31)) {
340 if (mask) {
341 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
342 tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
343 tcg_gen_brcondi_i64(cond, tmp, 0, l1);
344 tcg_temp_free(tmp);
345 } else
346 tcg_gen_brcondi_i64(cond, cpu_ir[ra], 0, l1);
347 } else {
348 /* Very uncommon case - Do not bother to optimize. */
349 TCGv tmp = tcg_const_i64(0);
350 tcg_gen_brcondi_i64(cond, tmp, 0, l1);
351 tcg_temp_free(tmp);
352 }
353 tcg_gen_movi_i64(cpu_pc, ctx->pc);
354 tcg_gen_br(l2);
355 gen_set_label(l1);
356 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp16 << 2));
357 gen_set_label(l2);
4c9649a9
JM		 358}
359
f071b4d3
JM		 360static always_inline void gen_fbcond (DisasContext *ctx,
361 void (*gen_test_op)(void),
362 int ra, int32_t disp16)
4c9649a9 363{
4f821e17 364 tcg_gen_movi_i64(cpu_T[1], ctx->pc + (int64_t)(disp16 << 2));
4c9649a9
JM		 365 gen_load_fir(ctx, ra, 0);
366 (*gen_test_op)();
367 _gen_op_bcond(ctx);
368}
369
f071b4d3
JM		 370static always_inline void gen_arith3 (DisasContext *ctx,
371 void (*gen_arith_op)(void),
372 int ra, int rb, int rc,
9e85e9bd 373 int islit, uint8_t lit)
4c9649a9 374{
3761035f
AJ		 375 if (ra != 31)
376 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
377 else
378 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9 379 if (islit)
3761035f
AJ		 380 tcg_gen_movi_i64(cpu_T[1], lit);
381 else if (rb != 31)
382 tcg_gen_mov_i64(cpu_T[1], cpu_ir[rb]);
4c9649a9 383 else
3761035f 384 tcg_gen_movi_i64(cpu_T[1], 0);
4c9649a9 385 (*gen_arith_op)();
3761035f
AJ		 386 if (rc != 31)
387 tcg_gen_mov_i64(cpu_ir[rc], cpu_T[0]);
4c9649a9
JM		 388}
389
f071b4d3 390static always_inline void gen_cmov (DisasContext *ctx,
9c29504e 391 TCGCond inv_cond,
f071b4d3 392 int ra, int rb, int rc,
9c29504e 393 int islit, int8_t lit, int mask)
4c9649a9 394{
9c29504e
AJ		 395 int l1;
396
397 if (unlikely(rc == 31))
398 return;
399
400 l1 = gen_new_label();
401
402 if (ra != 31) {
403 if (mask) {
404 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
405 tcg_gen_andi_i64(tmp, cpu_ir[ra], 1);
406 tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
407 tcg_temp_free(tmp);
408 } else
409 tcg_gen_brcondi_i64(inv_cond, cpu_ir[ra], 0, l1);
410 } else {
411 /* Very uncommon case - Do not bother to optimize. */
412 TCGv tmp = tcg_const_i64(0);
413 tcg_gen_brcondi_i64(inv_cond, tmp, 0, l1);
414 tcg_temp_free(tmp);
415 }
416
4c9649a9 417 if (islit)
9c29504e 418 tcg_gen_movi_i64(cpu_ir[rc], lit);
3761035f 419 else if (rb != 31)
9c29504e 420 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
4c9649a9 421 else
9c29504e
AJ		 422 tcg_gen_movi_i64(cpu_ir[rc], 0);
423 gen_set_label(l1);
4c9649a9
JM		 424}
425
f071b4d3
JM		 426static always_inline void gen_farith2 (DisasContext *ctx,
427 void (*gen_arith_fop)(void),
428 int rb, int rc)
4c9649a9
JM		 429{
430 gen_load_fir(ctx, rb, 0);
431 (*gen_arith_fop)();
432 gen_store_fir(ctx, rc, 0);
433}
434
f071b4d3
JM		 435static always_inline void gen_farith3 (DisasContext *ctx,
436 void (*gen_arith_fop)(void),
437 int ra, int rb, int rc)
4c9649a9
JM		 438{
439 gen_load_fir(ctx, ra, 0);
440 gen_load_fir(ctx, rb, 1);
441 (*gen_arith_fop)();
442 gen_store_fir(ctx, rc, 0);
443}
444
f071b4d3
JM		 445static always_inline void gen_fcmov (DisasContext *ctx,
446 void (*gen_test_fop)(void),
447 int ra, int rb, int rc)
4c9649a9
JM		 448{
449 gen_load_fir(ctx, ra, 0);
450 gen_load_fir(ctx, rb, 1);
451 (*gen_test_fop)();
452 gen_op_cmov_fir(rc);
453}
454
f071b4d3
JM		 455static always_inline void gen_fti (DisasContext *ctx,
456 void (*gen_move_fop)(void),
457 int ra, int rc)
4c9649a9
JM		 458{
459 gen_load_fir(ctx, rc, 0);
460 (*gen_move_fop)();
3761035f
AJ		 461 if (ra != 31)
462 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
4c9649a9
JM		 463}
464
f071b4d3
JM		 465static always_inline void gen_itf (DisasContext *ctx,
466 void (*gen_move_fop)(void),
467 int ra, int rc)
4c9649a9 468{
3761035f
AJ		 469 if (ra != 31)
470 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
471 else
472 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9
JM		 473 (*gen_move_fop)();
474 gen_store_fir(ctx, rc, 0);
475}
476
b3249f63
AJ		 477/* EXTWH, EXTWH, EXTLH, EXTQH */
478static always_inline void gen_ext_h(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
479 int ra, int rb, int rc,
480 int islit, int8_t lit)
481{
482 if (unlikely(rc == 31))
483 return;
484
485 if (ra != 31) {
486 if (islit)
487 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 64 - ((lit & 7) * 8));
488 else if (rb != 31) {
489 TCGv tmp1, tmp2;
490 tmp1 = tcg_temp_new(TCG_TYPE_I64);
491 tcg_gen_andi_i64(tmp1, cpu_ir[rb], 7);
492 tcg_gen_shli_i64(tmp1, tmp1, 3);
493 tmp2 = tcg_const_i64(64);
494 tcg_gen_sub_i64(tmp1, tmp2, tmp1);
495 tcg_temp_free(tmp2);
496 if (tcg_gen_ext_i64) {
497 tcg_gen_shl_i64(tmp1, cpu_ir[ra], tmp1);
498 tcg_gen_ext_i64(cpu_ir[rc], tmp1);
499 } else
500 tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], tmp1);
501 tcg_temp_free(tmp1);
502 } else
503 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
504 } else
505 tcg_gen_movi_i64(cpu_ir[rc], 0);
506}
507
508/* EXTBL, EXTWL, EXTWL, EXTLL, EXTQL */
509static always_inline void gen_ext_l(void (*tcg_gen_ext_i64)(TCGv t0, TCGv t1),
510 int ra, int rb, int rc,
511 int islit, int8_t lit)
512{
513 if (unlikely(rc == 31))
514 return;
515
516 if (ra != 31) {
517 if (islit)
518 tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], (lit & 7) * 8);
519 else if (rb != 31) {
520 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
521 tcg_gen_andi_i64(tmp, cpu_ir[rb], 7);
522 tcg_gen_shli_i64(tmp, tmp, 3);
523 if (tcg_gen_ext_i64) {
524 tcg_gen_shr_i64(tmp, cpu_ir[ra], tmp);
525 tcg_gen_ext_i64(cpu_ir[rc], tmp);
526 } else
527 tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], tmp);
528 tcg_temp_free(tmp);
529 } else
530 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
531 } else
532 tcg_gen_movi_i64(cpu_ir[rc], 0);
533}
534
535/* Code to call byte manipulation helpers, used by:
536 INSWH, INSLH, INSQH, INSBL, INSWL, INSLL, INSQL,
537 MSKWH, MSKLH, MSKQH, MSKBL, MSKWL, MSKLL, MSKQL,
538 ZAP, ZAPNOT
539
540 WARNING: it assumes that when ra31 is used, the result is 0.
541*/
542static always_inline void gen_byte_manipulation(void *helper,
543 int ra, int rb, int rc,
544 int islit, uint8_t lit)
545{
546 if (unlikely(rc == 31))
547 return;
548
549 if (ra != 31) {
550 if (islit || rb == 31) {
551 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
552 if (islit)
553 tcg_gen_movi_i64(tmp, lit);
554 else
555 tcg_gen_movi_i64(tmp, 0);
556 tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], tmp);
557 tcg_temp_free(tmp);
558 } else
559 tcg_gen_helper_1_2(helper, cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
560 } else
561 tcg_gen_movi_i64(cpu_ir[rc], 0);
562}
563
f071b4d3 564static always_inline int translate_one (DisasContext *ctx, uint32_t insn)
4c9649a9
JM		 565{
566 uint32_t palcode;
567 int32_t disp21, disp16, disp12;
568 uint16_t fn11, fn16;
569 uint8_t opc, ra, rb, rc, sbz, fpfn, fn7, fn2, islit;
570 int8_t lit;
571 int ret;
572
573 /* Decode all instruction fields */
574 opc = insn >> 26;
575 ra = (insn >> 21) & 0x1F;
576 rb = (insn >> 16) & 0x1F;
577 rc = insn & 0x1F;
578 sbz = (insn >> 13) & 0x07;
579 islit = (insn >> 12) & 1;
580 lit = (insn >> 13) & 0xFF;
581 palcode = insn & 0x03FFFFFF;
582 disp21 = ((int32_t)((insn & 0x001FFFFF) << 11)) >> 11;
583 disp16 = (int16_t)(insn & 0x0000FFFF);
584 disp12 = (int32_t)((insn & 0x00000FFF) << 20) >> 20;
585 fn16 = insn & 0x0000FFFF;
586 fn11 = (insn >> 5) & 0x000007FF;
587 fpfn = fn11 & 0x3F;
588 fn7 = (insn >> 5) & 0x0000007F;
589 fn2 = (insn >> 5) & 0x00000003;
590 ret = 0;
591#if defined ALPHA_DEBUG_DISAS
592 if (logfile != NULL) {
593 fprintf(logfile, "opc %02x ra %d rb %d rc %d disp16 %04x\n",
594 opc, ra, rb, rc, disp16);
595 }
596#endif
597 switch (opc) {
598 case 0x00:
599 /* CALL_PAL */
600 if (palcode >= 0x80 && palcode < 0xC0) {
601 /* Unprivileged PAL call */
602 gen_excp(ctx, EXCP_CALL_PAL + ((palcode & 0x1F) << 6), 0);
603#if !defined (CONFIG_USER_ONLY)
604 } else if (palcode < 0x40) {
605 /* Privileged PAL code */
606 if (ctx->mem_idx & 1)
607 goto invalid_opc;
608 else
609 gen_excp(ctx, EXCP_CALL_PALP + ((palcode & 0x1F) << 6), 0);
610#endif
611 } else {
612 /* Invalid PAL call */
613 goto invalid_opc;
614 }
615 ret = 3;
616 break;
617 case 0x01:
618 /* OPC01 */
619 goto invalid_opc;
620 case 0x02:
621 /* OPC02 */
622 goto invalid_opc;
623 case 0x03:
624 /* OPC03 */
625 goto invalid_opc;
626 case 0x04:
627 /* OPC04 */
628 goto invalid_opc;
629 case 0x05:
630 /* OPC05 */
631 goto invalid_opc;
632 case 0x06:
633 /* OPC06 */
634 goto invalid_opc;
635 case 0x07:
636 /* OPC07 */
637 goto invalid_opc;
638 case 0x08:
639 /* LDA */
1ef4ef4e 640 if (likely(ra != 31)) {
496cb5b9 641 if (rb != 31)
3761035f
AJ		 642 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16);
643 else
644 tcg_gen_movi_i64(cpu_ir[ra], disp16);
496cb5b9 645 }
4c9649a9
JM		 646 break;
647 case 0x09:
648 /* LDAH */
1ef4ef4e 649 if (likely(ra != 31)) {
496cb5b9 650 if (rb != 31)
3761035f
AJ		 651 tcg_gen_addi_i64(cpu_ir[ra], cpu_ir[rb], disp16 << 16);
652 else
653 tcg_gen_movi_i64(cpu_ir[ra], disp16 << 16);
496cb5b9 654 }
4c9649a9
JM		 655 break;
656 case 0x0A:
657 /* LDBU */
658 if (!(ctx->amask & AMASK_BWX))
659 goto invalid_opc;
660 gen_load_mem(ctx, &gen_ldbu, ra, rb, disp16, 0);
661 break;
662 case 0x0B:
663 /* LDQ_U */
664 gen_load_mem(ctx, &gen_ldq_u, ra, rb, disp16, 1);
665 break;
666 case 0x0C:
667 /* LDWU */
668 if (!(ctx->amask & AMASK_BWX))
669 goto invalid_opc;
670 gen_load_mem(ctx, &gen_ldwu, ra, rb, disp16, 0);
671 break;
672 case 0x0D:
673 /* STW */
674 if (!(ctx->amask & AMASK_BWX))
675 goto invalid_opc;
676 gen_store_mem(ctx, &gen_stw, ra, rb, disp16, 0);
677 break;
678 case 0x0E:
679 /* STB */
680 if (!(ctx->amask & AMASK_BWX))
681 goto invalid_opc;
682 gen_store_mem(ctx, &gen_stb, ra, rb, disp16, 0);
683 break;
684 case 0x0F:
685 /* STQ_U */
686 gen_store_mem(ctx, &gen_stq_u, ra, rb, disp16, 1);
687 break;
688 case 0x10:
689 switch (fn7) {
690 case 0x00:
691 /* ADDL */
30c7183b
AJ		 692 if (likely(rc != 31)) {
693 if (ra != 31) {
694 if (islit) {
695 tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);
696 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
697 } else if (rb != 31) {
698 tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
699 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
700 } else
701 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[ra]);
702 } else {
703 if (islit)
704 tcg_gen_movi_i64(cpu_ir[rc], (int32_t)lit);
705 else if (rb != 31)
706 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
707 else
708 tcg_gen_movi_i64(cpu_ir[rc], 0);
709 }
710 }
4c9649a9
JM		 711 break;
712 case 0x02:
713 /* S4ADDL */
30c7183b
AJ		 714 if (likely(rc != 31)) {
715 if (ra != 31) {
716 if (islit || rb != 31) {
717 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
718 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
719 if (islit)
720 tcg_gen_addi_i64(tmp, tmp, lit);
721 else
722 tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);
723 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
724 tcg_temp_free(tmp);
725 } else {
726 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 2);
727 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
728 }
729 } else {
730 if (islit)
731 tcg_gen_movi_i64(cpu_ir[rc], lit);
732 else if (rb != 31)
733 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
734 else
735 tcg_gen_movi_i64(cpu_ir[rc], 0);
736 }
737 }
4c9649a9
JM		 738 break;
739 case 0x09:
740 /* SUBL */
30c7183b
AJ		 741 if (likely(rc != 31)) {
742 if (ra != 31) {
743 if (islit) {
744 tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit);
745 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
746 } else if (rb != 31) {
747 tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
748 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
749 } else
750 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[ra]);
751 } else {
752 if (islit)
753 tcg_gen_movi_i64(cpu_ir[rc], -lit);
754 else if (rb != 31) {
755 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
756 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
757 } else
758 tcg_gen_movi_i64(cpu_ir[rc], 0);
759 }
760 }
4c9649a9
JM		 761 break;
762 case 0x0B:
763 /* S4SUBL */
30c7183b
AJ		 764 if (likely(rc != 31)) {
765 if (ra != 31) {
766 if (islit || rb != 31) {
767 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
768 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
769 if (islit)
770 tcg_gen_subi_i64(tmp, tmp, lit);
771 else
772 tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);
773 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
774 tcg_temp_free(tmp);
775 } else {
776 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 2);
777 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
778 }
779 } else {
780 if (islit)
781 tcg_gen_movi_i64(cpu_ir[rc], -lit);
782 else if (rb != 31) {
783 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
784 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
785 } else
786 tcg_gen_movi_i64(cpu_ir[rc], 0);
787 }
788 }
4c9649a9
JM		 789 break;
790 case 0x0F:
791 /* CMPBGE */
792 gen_arith3(ctx, &gen_op_cmpbge, ra, rb, rc, islit, lit);
793 break;
794 case 0x12:
795 /* S8ADDL */
30c7183b
AJ		 796 if (likely(rc != 31)) {
797 if (ra != 31) {
798 if (islit || rb != 31) {
799 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
800 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
801 if (islit)
802 tcg_gen_addi_i64(tmp, tmp, lit);
803 else
804 tcg_gen_add_i64(tmp, tmp, cpu_ir[rb]);
805 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
806 tcg_temp_free(tmp);
807 } else {
808 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 3);
809 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
810 }
811 } else {
812 if (islit)
813 tcg_gen_movi_i64(cpu_ir[rc], lit);
814 else if (rb != 31)
815 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rb]);
816 else
817 tcg_gen_movi_i64(cpu_ir[rc], 0);
818 }
819 }
4c9649a9
JM		 820 break;
821 case 0x1B:
822 /* S8SUBL */
30c7183b
AJ		 823 if (likely(rc != 31)) {
824 if (ra != 31) {
825 if (islit || rb != 31) {
826 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
827 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
828 if (islit)
829 tcg_gen_subi_i64(tmp, tmp, lit);
830 else
831 tcg_gen_sub_i64(tmp, tmp, cpu_ir[rb]);
832 tcg_gen_ext32s_i64(cpu_ir[rc], tmp);
833 tcg_temp_free(tmp);
834 } else {
835 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 3);
836 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
837 }
838 } else {
839 if (islit)
840 tcg_gen_movi_i64(cpu_ir[rc], -lit);
841 else if (rb != 31) {
842 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
843 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
844 } else
845 tcg_gen_movi_i64(cpu_ir[rc], 0);
846 }
847 }
4c9649a9
JM		 848 break;
849 case 0x1D:
850 /* CMPULT */
851 gen_arith3(ctx, &gen_op_cmpult, ra, rb, rc, islit, lit);
852 break;
853 case 0x20:
854 /* ADDQ */
30c7183b
AJ		 855 if (likely(rc != 31)) {
856 if (ra != 31) {
857 if (islit)
858 tcg_gen_addi_i64(cpu_ir[rc], cpu_ir[ra], lit);
859 else if (rb != 31)
860 tcg_gen_add_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
861 else
862 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
863 } else {
864 if (islit)
865 tcg_gen_movi_i64(cpu_ir[rc], lit);
866 else if (rb != 31)
867 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
868 else
869 tcg_gen_movi_i64(cpu_ir[rc], 0);
870 }
871 }
4c9649a9
JM		 872 break;
873 case 0x22:
874 /* S4ADDQ */
30c7183b
AJ		 875 if (likely(rc != 31)) {
876 if (ra != 31) {
877 if (islit || rb != 31) {
878 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
879 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
880 if (islit)
881 tcg_gen_addi_i64(cpu_ir[rc], tmp, lit);
882 else
883 tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
884 tcg_temp_free(tmp);
885 } else
886 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 2);
887 } else {
888 if (islit)
889 tcg_gen_movi_i64(cpu_ir[rc], lit);
890 else if (rb != 31)
891 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
892 else
893 tcg_gen_movi_i64(cpu_ir[rc], 0);
894 }
895 }
4c9649a9
JM		 896 break;
897 case 0x29:
898 /* SUBQ */
30c7183b
AJ		 899 if (likely(rc != 31)) {
900 if (ra != 31) {
901 if (islit)
902 tcg_gen_subi_i64(cpu_ir[rc], cpu_ir[ra], lit);
903 else if (rb != 31)
904 tcg_gen_sub_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
905 else
906 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
907 } else {
908 if (islit)
909 tcg_gen_movi_i64(cpu_ir[rc], -lit);
910 else if (rb != 31)
911 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
912 else
913 tcg_gen_movi_i64(cpu_ir[rc], 0);
914 }
915 }
4c9649a9
JM		 916 break;
917 case 0x2B:
918 /* S4SUBQ */
30c7183b
AJ		 919 if (likely(rc != 31)) {
920 if (ra != 31) {
921 if (islit || rb != 31) {
922 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
923 tcg_gen_shli_i64(tmp, cpu_ir[ra], 2);
924 if (islit)
925 tcg_gen_subi_i64(cpu_ir[rc], tmp, lit);
926 else
927 tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
928 tcg_temp_free(tmp);
929 } else
930 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 2);
931 } else {
932 if (islit)
933 tcg_gen_movi_i64(cpu_ir[rc], -lit);
934 else if (rb != 31)
935 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
936 else
937 tcg_gen_movi_i64(cpu_ir[rc], 0);
938 }
939 }
4c9649a9
JM		 940 break;
941 case 0x2D:
942 /* CMPEQ */
943 gen_arith3(ctx, &gen_op_cmpeq, ra, rb, rc, islit, lit);
944 break;
945 case 0x32:
946 /* S8ADDQ */
30c7183b
AJ		 947 if (likely(rc != 31)) {
948 if (ra != 31) {
949 if (islit || rb != 31) {
950 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
951 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
952 if (islit)
953 tcg_gen_addi_i64(cpu_ir[rc], tmp, lit);
954 else
955 tcg_gen_add_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
956 tcg_temp_free(tmp);
957 } else
958 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 3);
959 } else {
960 if (islit)
961 tcg_gen_movi_i64(cpu_ir[rc], lit);
962 else if (rb != 31)
963 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
964 else
965 tcg_gen_movi_i64(cpu_ir[rc], 0);
966 }
967 }
4c9649a9
JM		 968 break;
969 case 0x3B:
970 /* S8SUBQ */
30c7183b
AJ		 971 if (likely(rc != 31)) {
972 if (ra != 31) {
973 if (islit || rb != 31) {
974 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
975 tcg_gen_shli_i64(tmp, cpu_ir[ra], 3);
976 if (islit)
977 tcg_gen_subi_i64(cpu_ir[rc], tmp, lit);
978 else
979 tcg_gen_sub_i64(cpu_ir[rc], tmp, cpu_ir[rb]);
980 tcg_temp_free(tmp);
981 } else
982 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], 3);
983 } else {
984 if (islit)
985 tcg_gen_movi_i64(cpu_ir[rc], -lit);
986 else if (rb != 31)
987 tcg_gen_neg_i64(cpu_ir[rc], cpu_ir[rb]);
988 else
989 tcg_gen_movi_i64(cpu_ir[rc], 0);
990 }
991 }
4c9649a9
JM		 992 break;
993 case 0x3D:
994 /* CMPULE */
995 gen_arith3(ctx, &gen_op_cmpule, ra, rb, rc, islit, lit);
996 break;
997 case 0x40:
998 /* ADDL/V */
999 gen_arith3(ctx, &gen_op_addlv, ra, rb, rc, islit, lit);
1000 break;
1001 case 0x49:
1002 /* SUBL/V */
1003 gen_arith3(ctx, &gen_op_sublv, ra, rb, rc, islit, lit);
1004 break;
1005 case 0x4D:
1006 /* CMPLT */
1007 gen_arith3(ctx, &gen_op_cmplt, ra, rb, rc, islit, lit);
1008 break;
1009 case 0x60:
1010 /* ADDQ/V */
1011 gen_arith3(ctx, &gen_op_addqv, ra, rb, rc, islit, lit);
1012 break;
1013 case 0x69:
1014 /* SUBQ/V */
1015 gen_arith3(ctx, &gen_op_subqv, ra, rb, rc, islit, lit);
1016 break;
1017 case 0x6D:
1018 /* CMPLE */
1019 gen_arith3(ctx, &gen_op_cmple, ra, rb, rc, islit, lit);
1020 break;
1021 default:
1022 goto invalid_opc;
1023 }
1024 break;
1025 case 0x11:
1026 switch (fn7) {
1027 case 0x00:
1028 /* AND */
30c7183b
AJ		 1029 if (likely(rc != 31)) {
1030 if (ra == 31 || (rb == 31 && !islit))
1031 tcg_gen_movi_i64(cpu_ir[rc], 0);
1032 else if (islit)
1033 tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit);
1034 else
1035 tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1036 }
4c9649a9
JM		 1037 break;
1038 case 0x08:
1039 /* BIC */
30c7183b
AJ		 1040 if (likely(rc != 31)) {
1041 if (ra != 31) {
1042 if (islit)
1043 tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1044 else if (rb != 31) {
1045 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
1046 tcg_gen_not_i64(tmp, cpu_ir[rb]);
1047 tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], tmp);
1048 tcg_temp_free(tmp);
1049 } else
1050 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
1051 } else
1052 tcg_gen_movi_i64(cpu_ir[rc], 0);
1053 }
4c9649a9
JM		 1054 break;
1055 case 0x14:
1056 /* CMOVLBS */
9c29504e 1057 gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 1);
4c9649a9
JM		 1058 break;
1059 case 0x16:
1060 /* CMOVLBC */
9c29504e 1061 gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 1);
4c9649a9
JM		 1062 break;
1063 case 0x20:
1064 /* BIS */
30c7183b
AJ		 1065 if (likely(rc != 31)) {
1066 if (ra != 31) {
1067 if (islit)
1068 tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit);
1069 else if (rb != 31)
1070 tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1071 else
1072 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
4c9649a9 1073 } else {
30c7183b
AJ		 1074 if (islit)
1075 tcg_gen_movi_i64(cpu_ir[rc], lit);
1076 else if (rb != 31)
1077 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1078 else
1079 tcg_gen_movi_i64(cpu_ir[rc], 0);
4c9649a9 1080 }
4c9649a9
JM		 1081 }
1082 break;
1083 case 0x24:
1084 /* CMOVEQ */
9c29504e 1085 gen_cmov(ctx, TCG_COND_NE, ra, rb, rc, islit, lit, 0);
4c9649a9
JM		 1086 break;
1087 case 0x26:
1088 /* CMOVNE */
9c29504e 1089 gen_cmov(ctx, TCG_COND_EQ, ra, rb, rc, islit, lit, 0);
4c9649a9
JM		 1090 break;
1091 case 0x28:
1092 /* ORNOT */
30c7183b
AJ		 1093 if (likely(rc != 31)) {
1094 if (rb == 31 && !islit)
1095 tcg_gen_movi_i64(cpu_ir[rc], ~0);
1096 else if (ra != 31) {
1097 if (islit)
1098 tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1099 else {
1100 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
1101 tcg_gen_not_i64(tmp, cpu_ir[rb]);
1102 tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], tmp);
1103 tcg_temp_free(tmp);
1104 }
1105 } else {
1106 if (islit)
1107 tcg_gen_movi_i64(cpu_ir[rc], ~lit);
1108 else
1109 tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
1110 }
1111 }
4c9649a9
JM		 1112 break;
1113 case 0x40:
1114 /* XOR */
30c7183b
AJ		 1115 if (likely(rc != 31)) {
1116 if (ra != 31) {
1117 if (islit)
1118 tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit);
1119 else if (rb != 31)
1120 tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1121 else
1122 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
1123 } else {
1124 if (islit)
1125 tcg_gen_movi_i64(cpu_ir[rc], lit);
1126 else if (rb != 31)
1127 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
1128 else
1129 tcg_gen_movi_i64(cpu_ir[rc], 0);
1130 }
1131 }
4c9649a9
JM		 1132 break;
1133 case 0x44:
1134 /* CMOVLT */
9c29504e 1135 gen_cmov(ctx, TCG_COND_GE, ra, rb, rc, islit, lit, 0);
4c9649a9
JM		 1136 break;
1137 case 0x46:
1138 /* CMOVGE */
9c29504e 1139 gen_cmov(ctx, TCG_COND_LT, ra, rb, rc, islit, lit, 0);
4c9649a9
JM		 1140 break;
1141 case 0x48:
1142 /* EQV */
30c7183b
AJ		 1143 if (likely(rc != 31)) {
1144 if (ra != 31) {
1145 if (islit)
1146 tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
1147 else if (rb != 31) {
1148 TCGv tmp = tcg_temp_new(TCG_TYPE_I64);
1149 tcg_gen_not_i64(tmp, cpu_ir[rb]);
1150 tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], tmp);
1151 tcg_temp_free(tmp);
1152 } else
1153 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
1154 } else {
1155 if (islit)
1156 tcg_gen_movi_i64(cpu_ir[rc], ~lit);
1157 else if (rb != 31)
1158 tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
1159 else
1160 tcg_gen_movi_i64(cpu_ir[rc], ~0);
1161 }
1162 }
4c9649a9
JM		 1163 break;
1164 case 0x61:
1165 /* AMASK */
ae8ecd42
AJ		 1166 if (likely(rc != 31)) {
1167 if (islit)
1168 tcg_gen_movi_i64(cpu_ir[rc], helper_amask(lit));
1169 else if (rb != 31)
1170 tcg_gen_helper_1_1(helper_amask, cpu_ir[rc], cpu_ir[rb]);
1171 else
1172 tcg_gen_movi_i64(cpu_ir[rc], 0);
1173 }
4c9649a9
JM		 1174 break;
1175 case 0x64:
1176 /* CMOVLE */
9c29504e 1177 gen_cmov(ctx, TCG_COND_GT, ra, rb, rc, islit, lit, 0);
4c9649a9
JM		 1178 break;
1179 case 0x66:
1180 /* CMOVGT */
9c29504e 1181 gen_cmov(ctx, TCG_COND_LE, ra, rb, rc, islit, lit, 0);
4c9649a9
JM		 1182 break;
1183 case 0x6C:
1184 /* IMPLVER */
3761035f 1185 if (rc != 31)
6ad02592 1186 tcg_gen_helper_1_0(helper_load_implver, cpu_ir[rc]);
4c9649a9
JM		 1187 break;
1188 default:
1189 goto invalid_opc;
1190 }
1191 break;
1192 case 0x12:
1193 switch (fn7) {
1194 case 0x02:
1195 /* MSKBL */
b3249f63 1196 gen_byte_manipulation(helper_mskbl, ra, rb, rc, islit, lit);
4c9649a9
JM		 1197 break;
1198 case 0x06:
1199 /* EXTBL */
b3249f63 1200 gen_ext_l(&tcg_gen_ext8u_i64, ra, rb, rc, islit, lit);
4c9649a9
JM		 1201 break;
1202 case 0x0B:
1203 /* INSBL */
b3249f63 1204 gen_byte_manipulation(helper_insbl, ra, rb, rc, islit, lit);
4c9649a9
JM		 1205 break;
1206 case 0x12:
1207 /* MSKWL */
b3249f63 1208 gen_byte_manipulation(helper_mskwl, ra, rb, rc, islit, lit);
4c9649a9
JM		 1209 break;
1210 case 0x16:
1211 /* EXTWL */
b3249f63 1212 gen_ext_l(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
4c9649a9
JM		 1213 break;
1214 case 0x1B:
1215 /* INSWL */
b3249f63 1216 gen_byte_manipulation(helper_inswl, ra, rb, rc, islit, lit);
4c9649a9
JM		 1217 break;
1218 case 0x22:
1219 /* MSKLL */
b3249f63 1220 gen_byte_manipulation(helper_mskll, ra, rb, rc, islit, lit);
4c9649a9
JM		 1221 break;
1222 case 0x26:
1223 /* EXTLL */
b3249f63 1224 gen_ext_l(&tcg_gen_ext32u_i64, ra, rb, rc, islit, lit);
4c9649a9
JM		 1225 break;
1226 case 0x2B:
1227 /* INSLL */
b3249f63 1228 gen_byte_manipulation(helper_insll, ra, rb, rc, islit, lit);
4c9649a9
JM		 1229 break;
1230 case 0x30:
1231 /* ZAP */
b3249f63 1232 gen_byte_manipulation(helper_zap, ra, rb, rc, islit, lit);
4c9649a9
JM		 1233 break;
1234 case 0x31:
1235 /* ZAPNOT */
b3249f63 1236 gen_byte_manipulation(helper_zapnot, ra, rb, rc, islit, lit);
4c9649a9
JM		 1237 break;
1238 case 0x32:
1239 /* MSKQL */
b3249f63 1240 gen_byte_manipulation(helper_mskql, ra, rb, rc, islit, lit);
4c9649a9
JM		 1241 break;
1242 case 0x34:
1243 /* SRL */
30c7183b
AJ		 1244 if (likely(rc != 31)) {
1245 if (ra != 31) {
1246 if (islit)
1247 tcg_gen_shri_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1248 else if (rb != 31) {
1249 TCGv shift = tcg_temp_new(TCG_TYPE_I64);
1250 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1251 tcg_gen_shr_i64(cpu_ir[rc], cpu_ir[ra], shift);
1252 tcg_temp_free(shift);
1253 } else
1254 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
1255 } else
1256 tcg_gen_movi_i64(cpu_ir[rc], 0);
1257 }
4c9649a9
JM		 1258 break;
1259 case 0x36:
1260 /* EXTQL */
b3249f63 1261 gen_ext_l(NULL, ra, rb, rc, islit, lit);
4c9649a9
JM		 1262 break;
1263 case 0x39:
1264 /* SLL */
30c7183b
AJ		 1265 if (likely(rc != 31)) {
1266 if (ra != 31) {
1267 if (islit)
1268 tcg_gen_shli_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1269 else if (rb != 31) {
1270 TCGv shift = tcg_temp_new(TCG_TYPE_I64);
1271 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1272 tcg_gen_shl_i64(cpu_ir[rc], cpu_ir[ra], shift);
1273 tcg_temp_free(shift);
1274 } else
1275 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
1276 } else
1277 tcg_gen_movi_i64(cpu_ir[rc], 0);
1278 }
4c9649a9
JM		 1279 break;
1280 case 0x3B:
1281 /* INSQL */
b3249f63 1282 gen_byte_manipulation(helper_insql, ra, rb, rc, islit, lit);
4c9649a9
JM		 1283 break;
1284 case 0x3C:
1285 /* SRA */
30c7183b
AJ		 1286 if (likely(rc != 31)) {
1287 if (ra != 31) {
1288 if (islit)
1289 tcg_gen_sari_i64(cpu_ir[rc], cpu_ir[ra], lit & 0x3f);
1290 else if (rb != 31) {
1291 TCGv shift = tcg_temp_new(TCG_TYPE_I64);
1292 tcg_gen_andi_i64(shift, cpu_ir[rb], 0x3f);
1293 tcg_gen_sar_i64(cpu_ir[rc], cpu_ir[ra], shift);
1294 tcg_temp_free(shift);
1295 } else
1296 tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[ra]);
1297 } else
1298 tcg_gen_movi_i64(cpu_ir[rc], 0);
1299 }
4c9649a9
JM		 1300 break;
1301 case 0x52:
1302 /* MSKWH */
b3249f63 1303 gen_byte_manipulation(helper_mskwh, ra, rb, rc, islit, lit);
4c9649a9
JM		 1304 break;
1305 case 0x57:
1306 /* INSWH */
b3249f63 1307 gen_byte_manipulation(helper_inswh, ra, rb, rc, islit, lit);
4c9649a9
JM		 1308 break;
1309 case 0x5A:
1310 /* EXTWH */
b3249f63 1311 gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
4c9649a9
JM		 1312 break;
1313 case 0x62:
1314 /* MSKLH */
b3249f63 1315 gen_byte_manipulation(helper_msklh, ra, rb, rc, islit, lit);
4c9649a9
JM		 1316 break;
1317 case 0x67:
1318 /* INSLH */
b3249f63 1319 gen_byte_manipulation(helper_inslh, ra, rb, rc, islit, lit);
4c9649a9
JM		 1320 break;
1321 case 0x6A:
1322 /* EXTLH */
b3249f63 1323 gen_ext_h(&tcg_gen_ext16u_i64, ra, rb, rc, islit, lit);
4c9649a9
JM		 1324 break;
1325 case 0x72:
1326 /* MSKQH */
b3249f63 1327 gen_byte_manipulation(helper_mskqh, ra, rb, rc, islit, lit);
4c9649a9
JM		 1328 break;
1329 case 0x77:
1330 /* INSQH */
b3249f63 1331 gen_byte_manipulation(helper_insqh, ra, rb, rc, islit, lit);
4c9649a9
JM		 1332 break;
1333 case 0x7A:
1334 /* EXTQH */
b3249f63 1335 gen_ext_h(NULL, ra, rb, rc, islit, lit);
4c9649a9
JM		 1336 break;
1337 default:
1338 goto invalid_opc;
1339 }
1340 break;
1341 case 0x13:
1342 switch (fn7) {
1343 case 0x00:
1344 /* MULL */
30c7183b
AJ		 1345 if (likely(rc != 31)) {
1346 if (ra == 31 || (rb == 31 && !islit))
1347 tcg_gen_movi_i64(cpu_ir[rc], 0);
1348 else {
1349 if (islit)
1350 tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
1351 else
1352 tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1353 tcg_gen_ext32s_i64(cpu_ir[rc], cpu_ir[rc]);
1354 }
1355 }
4c9649a9
JM		 1356 break;
1357 case 0x20:
1358 /* MULQ */
30c7183b
AJ		 1359 if (likely(rc != 31)) {
1360 if (ra == 31 || (rb == 31 && !islit))
1361 tcg_gen_movi_i64(cpu_ir[rc], 0);
1362 else if (islit)
1363 tcg_gen_muli_i64(cpu_ir[rc], cpu_ir[ra], lit);
1364 else
1365 tcg_gen_mul_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
1366 }
4c9649a9
JM		 1367 break;
1368 case 0x30:
1369 /* UMULH */
1370 gen_arith3(ctx, &gen_op_umulh, ra, rb, rc, islit, lit);
1371 break;
1372 case 0x40:
1373 /* MULL/V */
1374 gen_arith3(ctx, &gen_op_mullv, ra, rb, rc, islit, lit);
1375 break;
1376 case 0x60:
1377 /* MULQ/V */
1378 gen_arith3(ctx, &gen_op_mulqv, ra, rb, rc, islit, lit);
1379 break;
1380 default:
1381 goto invalid_opc;
1382 }
1383 break;
1384 case 0x14:
1385 switch (fpfn) { /* f11 & 0x3F */
1386 case 0x04:
1387 /* ITOFS */
1388 if (!(ctx->amask & AMASK_FIX))
1389 goto invalid_opc;
1390 gen_itf(ctx, &gen_op_itofs, ra, rc);
1391 break;
1392 case 0x0A:
1393 /* SQRTF */
1394 if (!(ctx->amask & AMASK_FIX))
1395 goto invalid_opc;
1396 gen_farith2(ctx, &gen_op_sqrtf, rb, rc);
1397 break;
1398 case 0x0B:
1399 /* SQRTS */
1400 if (!(ctx->amask & AMASK_FIX))
1401 goto invalid_opc;
1402 gen_farith2(ctx, &gen_op_sqrts, rb, rc);
1403 break;
1404 case 0x14:
1405 /* ITOFF */
1406 if (!(ctx->amask & AMASK_FIX))
1407 goto invalid_opc;
1408#if 0 // TODO
1409 gen_itf(ctx, &gen_op_itoff, ra, rc);
1410#else
1411 goto invalid_opc;
1412#endif
1413 break;
1414 case 0x24:
1415 /* ITOFT */
1416 if (!(ctx->amask & AMASK_FIX))
1417 goto invalid_opc;
1418 gen_itf(ctx, &gen_op_itoft, ra, rc);
1419 break;
1420 case 0x2A:
1421 /* SQRTG */
1422 if (!(ctx->amask & AMASK_FIX))
1423 goto invalid_opc;
1424 gen_farith2(ctx, &gen_op_sqrtg, rb, rc);
1425 break;
1426 case 0x02B:
1427 /* SQRTT */
1428 if (!(ctx->amask & AMASK_FIX))
1429 goto invalid_opc;
1430 gen_farith2(ctx, &gen_op_sqrtt, rb, rc);
1431 break;
1432 default:
1433 goto invalid_opc;
1434 }
1435 break;
1436 case 0x15:
1437 /* VAX floating point */
1438 /* XXX: rounding mode and trap are ignored (!) */
1439 switch (fpfn) { /* f11 & 0x3F */
1440 case 0x00:
1441 /* ADDF */
1442 gen_farith3(ctx, &gen_op_addf, ra, rb, rc);
1443 break;
1444 case 0x01:
1445 /* SUBF */
1446 gen_farith3(ctx, &gen_op_subf, ra, rb, rc);
1447 break;
1448 case 0x02:
1449 /* MULF */
1450 gen_farith3(ctx, &gen_op_mulf, ra, rb, rc);
1451 break;
1452 case 0x03:
1453 /* DIVF */
1454 gen_farith3(ctx, &gen_op_divf, ra, rb, rc);
1455 break;
1456 case 0x1E:
1457 /* CVTDG */
1458#if 0 // TODO
1459 gen_farith2(ctx, &gen_op_cvtdg, rb, rc);
1460#else
1461 goto invalid_opc;
1462#endif
1463 break;
1464 case 0x20:
1465 /* ADDG */
1466 gen_farith3(ctx, &gen_op_addg, ra, rb, rc);
1467 break;
1468 case 0x21:
1469 /* SUBG */
1470 gen_farith3(ctx, &gen_op_subg, ra, rb, rc);
1471 break;
1472 case 0x22:
1473 /* MULG */
1474 gen_farith3(ctx, &gen_op_mulg, ra, rb, rc);
1475 break;
1476 case 0x23:
1477 /* DIVG */
1478 gen_farith3(ctx, &gen_op_divg, ra, rb, rc);
1479 break;
1480 case 0x25:
1481 /* CMPGEQ */
1482 gen_farith3(ctx, &gen_op_cmpgeq, ra, rb, rc);
1483 break;
1484 case 0x26:
1485 /* CMPGLT */
1486 gen_farith3(ctx, &gen_op_cmpglt, ra, rb, rc);
1487 break;
1488 case 0x27:
1489 /* CMPGLE */
1490 gen_farith3(ctx, &gen_op_cmpgle, ra, rb, rc);
1491 break;
1492 case 0x2C:
1493 /* CVTGF */
1494 gen_farith2(ctx, &gen_op_cvtgf, rb, rc);
1495 break;
1496 case 0x2D:
1497 /* CVTGD */
1498#if 0 // TODO
1499 gen_farith2(ctx, &gen_op_cvtgd, rb, rc);
1500#else
1501 goto invalid_opc;
1502#endif
1503 break;
1504 case 0x2F:
1505 /* CVTGQ */
1506 gen_farith2(ctx, &gen_op_cvtgq, rb, rc);
1507 break;
1508 case 0x3C:
1509 /* CVTQF */
1510 gen_farith2(ctx, &gen_op_cvtqf, rb, rc);
1511 break;
1512 case 0x3E:
1513 /* CVTQG */
1514 gen_farith2(ctx, &gen_op_cvtqg, rb, rc);
1515 break;
1516 default:
1517 goto invalid_opc;
1518 }
1519 break;
1520 case 0x16:
1521 /* IEEE floating-point */
1522 /* XXX: rounding mode and traps are ignored (!) */
1523 switch (fpfn) { /* f11 & 0x3F */
1524 case 0x00:
1525 /* ADDS */
1526 gen_farith3(ctx, &gen_op_adds, ra, rb, rc);
1527 break;
1528 case 0x01:
1529 /* SUBS */
1530 gen_farith3(ctx, &gen_op_subs, ra, rb, rc);
1531 break;
1532 case 0x02:
1533 /* MULS */
1534 gen_farith3(ctx, &gen_op_muls, ra, rb, rc);
1535 break;
1536 case 0x03:
1537 /* DIVS */
1538 gen_farith3(ctx, &gen_op_divs, ra, rb, rc);
1539 break;
1540 case 0x20:
1541 /* ADDT */
1542 gen_farith3(ctx, &gen_op_addt, ra, rb, rc);
1543 break;
1544 case 0x21:
1545 /* SUBT */
1546 gen_farith3(ctx, &gen_op_subt, ra, rb, rc);
1547 break;
1548 case 0x22:
1549 /* MULT */
1550 gen_farith3(ctx, &gen_op_mult, ra, rb, rc);
1551 break;
1552 case 0x23:
1553 /* DIVT */
1554 gen_farith3(ctx, &gen_op_divt, ra, rb, rc);
1555 break;
1556 case 0x24:
1557 /* CMPTUN */
1558 gen_farith3(ctx, &gen_op_cmptun, ra, rb, rc);
1559 break;
1560 case 0x25:
1561 /* CMPTEQ */
1562 gen_farith3(ctx, &gen_op_cmpteq, ra, rb, rc);
1563 break;
1564 case 0x26:
1565 /* CMPTLT */
1566 gen_farith3(ctx, &gen_op_cmptlt, ra, rb, rc);
1567 break;
1568 case 0x27:
1569 /* CMPTLE */
1570 gen_farith3(ctx, &gen_op_cmptle, ra, rb, rc);
1571 break;
1572 case 0x2C:
1573 /* XXX: incorrect */
1574 if (fn11 == 0x2AC) {
1575 /* CVTST */
1576 gen_farith2(ctx, &gen_op_cvtst, rb, rc);
1577 } else {
1578 /* CVTTS */
1579 gen_farith2(ctx, &gen_op_cvtts, rb, rc);
1580 }
1581 break;
1582 case 0x2F:
1583 /* CVTTQ */
1584 gen_farith2(ctx, &gen_op_cvttq, rb, rc);
1585 break;
1586 case 0x3C:
1587 /* CVTQS */
1588 gen_farith2(ctx, &gen_op_cvtqs, rb, rc);
1589 break;
1590 case 0x3E:
1591 /* CVTQT */
1592 gen_farith2(ctx, &gen_op_cvtqt, rb, rc);
1593 break;
1594 default:
1595 goto invalid_opc;
1596 }
1597 break;
1598 case 0x17:
1599 switch (fn11) {
1600 case 0x010:
1601 /* CVTLQ */
1602 gen_farith2(ctx, &gen_op_cvtlq, rb, rc);
1603 break;
1604 case 0x020:
1605 /* CPYS */
1606 if (ra == rb) {
1607 if (ra == 31 && rc == 31) {
1608 /* FNOP */
1609 gen_op_nop();
1610 } else {
1611 /* FMOV */
1612 gen_load_fir(ctx, rb, 0);
1613 gen_store_fir(ctx, rc, 0);
1614 }
1615 } else {
1616 gen_farith3(ctx, &gen_op_cpys, ra, rb, rc);
1617 }
1618 break;
1619 case 0x021:
1620 /* CPYSN */
1621 gen_farith2(ctx, &gen_op_cpysn, rb, rc);
1622 break;
1623 case 0x022:
1624 /* CPYSE */
1625 gen_farith2(ctx, &gen_op_cpyse, rb, rc);
1626 break;
1627 case 0x024:
1628 /* MT_FPCR */
1629 gen_load_fir(ctx, ra, 0);
1630 gen_op_store_fpcr();
1631 break;
1632 case 0x025:
1633 /* MF_FPCR */
1634 gen_op_load_fpcr();
1635 gen_store_fir(ctx, ra, 0);
1636 break;
1637 case 0x02A:
1638 /* FCMOVEQ */
1639 gen_fcmov(ctx, &gen_op_cmpfeq, ra, rb, rc);
1640 break;
1641 case 0x02B:
1642 /* FCMOVNE */
1643 gen_fcmov(ctx, &gen_op_cmpfne, ra, rb, rc);
1644 break;
1645 case 0x02C:
1646 /* FCMOVLT */
1647 gen_fcmov(ctx, &gen_op_cmpflt, ra, rb, rc);
1648 break;
1649 case 0x02D:
1650 /* FCMOVGE */
1651 gen_fcmov(ctx, &gen_op_cmpfge, ra, rb, rc);
1652 break;
1653 case 0x02E:
1654 /* FCMOVLE */
1655 gen_fcmov(ctx, &gen_op_cmpfle, ra, rb, rc);
1656 break;
1657 case 0x02F:
1658 /* FCMOVGT */
1659 gen_fcmov(ctx, &gen_op_cmpfgt, ra, rb, rc);
1660 break;
1661 case 0x030:
1662 /* CVTQL */
1663 gen_farith2(ctx, &gen_op_cvtql, rb, rc);
1664 break;
1665 case 0x130:
1666 /* CVTQL/V */
1667 gen_farith2(ctx, &gen_op_cvtqlv, rb, rc);
1668 break;
1669 case 0x530:
1670 /* CVTQL/SV */
1671 gen_farith2(ctx, &gen_op_cvtqlsv, rb, rc);
1672 break;
1673 default:
1674 goto invalid_opc;
1675 }
1676 break;
1677 case 0x18:
1678 switch ((uint16_t)disp16) {
1679 case 0x0000:
1680 /* TRAPB */
1681 /* No-op. Just exit from the current tb */
1682 ret = 2;
1683 break;
1684 case 0x0400:
1685 /* EXCB */
1686 /* No-op. Just exit from the current tb */
1687 ret = 2;
1688 break;
1689 case 0x4000:
1690 /* MB */
1691 /* No-op */
1692 break;
1693 case 0x4400:
1694 /* WMB */
1695 /* No-op */
1696 break;
1697 case 0x8000:
1698 /* FETCH */
1699 /* No-op */
1700 break;
1701 case 0xA000:
1702 /* FETCH_M */
1703 /* No-op */
1704 break;
1705 case 0xC000:
1706 /* RPCC */
3761035f 1707 if (ra != 31)
6ad02592 1708 tcg_gen_helper_1_0(helper_load_pcc, cpu_ir[ra]);
4c9649a9
JM		 1709 break;
1710 case 0xE000:
1711 /* RC */
3761035f 1712 if (ra != 31)
6ad02592 1713 tcg_gen_helper_1_0(helper_rc, cpu_ir[ra]);
4c9649a9
JM		 1714 break;
1715 case 0xE800:
1716 /* ECB */
1717 /* XXX: TODO: evict tb cache at address rb */
1718#if 0
1719 ret = 2;
1720#else
1721 goto invalid_opc;
1722#endif
1723 break;
1724 case 0xF000:
1725 /* RS */
3761035f 1726 if (ra != 31)
6ad02592 1727 tcg_gen_helper_1_0(helper_rs, cpu_ir[ra]);
4c9649a9
JM		 1728 break;
1729 case 0xF800:
1730 /* WH64 */
1731 /* No-op */
1732 break;
1733 default:
1734 goto invalid_opc;
1735 }
1736 break;
1737 case 0x19:
1738 /* HW_MFPR (PALcode) */
1739#if defined (CONFIG_USER_ONLY)
1740 goto invalid_opc;
1741#else
1742 if (!ctx->pal_mode)
1743 goto invalid_opc;
1744 gen_op_mfpr(insn & 0xFF);
3761035f
AJ		 1745 if (ra != 31)
1746 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[0]);
4c9649a9
JM		 1747 break;
1748#endif
1749 case 0x1A:
3761035f
AJ		 1750 if (ra != 31)
1751 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
1752 if (rb != 31)
1753 tcg_gen_andi_i64(cpu_pc, cpu_ir[rb], ~3);
1754 else
1755 tcg_gen_movi_i64(cpu_pc, 0);
4c9649a9
JM		 1756 /* Those four jumps only differ by the branch prediction hint */
1757 switch (fn2) {
1758 case 0x0:
1759 /* JMP */
1760 break;
1761 case 0x1:
1762 /* JSR */
1763 break;
1764 case 0x2:
1765 /* RET */
1766 break;
1767 case 0x3:
1768 /* JSR_COROUTINE */
1769 break;
1770 }
1771 ret = 1;
1772 break;
1773 case 0x1B:
1774 /* HW_LD (PALcode) */
1775#if defined (CONFIG_USER_ONLY)
1776 goto invalid_opc;
1777#else
1778 if (!ctx->pal_mode)
1779 goto invalid_opc;
3761035f
AJ		 1780 if (rb != 31)
1781 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
1782 else
1783 tcg_gen_movi_i64(cpu_T[0], 0);
1784 tcg_gen_movi_i64(cpu_T[1], disp12);
4f821e17 1785 tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
4c9649a9
JM		 1786 switch ((insn >> 12) & 0xF) {
1787 case 0x0:
1788 /* Longword physical access */
1789 gen_op_ldl_raw();
1790 break;
1791 case 0x1:
1792 /* Quadword physical access */
1793 gen_op_ldq_raw();
1794 break;
1795 case 0x2:
1796 /* Longword physical access with lock */
1797 gen_op_ldl_l_raw();
1798 break;
1799 case 0x3:
1800 /* Quadword physical access with lock */
1801 gen_op_ldq_l_raw();
1802 break;
1803 case 0x4:
1804 /* Longword virtual PTE fetch */
1805 gen_op_ldl_kernel();
1806 break;
1807 case 0x5:
1808 /* Quadword virtual PTE fetch */
1809 gen_op_ldq_kernel();
1810 break;
1811 case 0x6:
1812 /* Invalid */
1813 goto invalid_opc;
1814 case 0x7:
1815 /* Invalid */
1816 goto invalid_opc;
1817 case 0x8:
1818 /* Longword virtual access */
1819 gen_op_ld_phys_to_virt();
1820 gen_op_ldl_raw();
1821 break;
1822 case 0x9:
1823 /* Quadword virtual access */
1824 gen_op_ld_phys_to_virt();
1825 gen_op_ldq_raw();
1826 break;
1827 case 0xA:
1828 /* Longword virtual access with protection check */
1829 gen_ldl(ctx);
1830 break;
1831 case 0xB:
1832 /* Quadword virtual access with protection check */
1833 gen_ldq(ctx);
1834 break;
1835 case 0xC:
1836 /* Longword virtual access with altenate access mode */
1837 gen_op_set_alt_mode();
1838 gen_op_ld_phys_to_virt();
1839 gen_op_ldl_raw();
1840 gen_op_restore_mode();
1841 break;
1842 case 0xD:
1843 /* Quadword virtual access with altenate access mode */
1844 gen_op_set_alt_mode();
1845 gen_op_ld_phys_to_virt();
1846 gen_op_ldq_raw();
1847 gen_op_restore_mode();
1848 break;
1849 case 0xE:
1850 /* Longword virtual access with alternate access mode and
1851 * protection checks
1852 */
1853 gen_op_set_alt_mode();
1854 gen_op_ldl_data();
1855 gen_op_restore_mode();
1856 break;
1857 case 0xF:
1858 /* Quadword virtual access with alternate access mode and
1859 * protection checks
1860 */
1861 gen_op_set_alt_mode();
1862 gen_op_ldq_data();
1863 gen_op_restore_mode();
1864 break;
1865 }
3761035f
AJ		 1866 if (ra != 31)
1867 tcg_gen_mov_i64(cpu_ir[ra], cpu_T[1]);
4c9649a9
JM		 1868 break;
1869#endif
1870 case 0x1C:
1871 switch (fn7) {
1872 case 0x00:
1873 /* SEXTB */
1874 if (!(ctx->amask & AMASK_BWX))
1875 goto invalid_opc;
ae8ecd42
AJ		 1876 if (likely(rc != 31)) {
1877 if (islit)
1878 tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int8_t)lit));
1879 else if (rb != 31)
1880 tcg_gen_ext8s_i64(cpu_ir[rc], cpu_ir[rb]);
1881 else
1882 tcg_gen_movi_i64(cpu_ir[rc], 0);
1883 }
4c9649a9
JM		 1884 break;
1885 case 0x01:
1886 /* SEXTW */
1887 if (!(ctx->amask & AMASK_BWX))
1888 goto invalid_opc;
ae8ecd42
AJ		 1889 if (likely(rc != 31)) {
1890 if (islit)
1891 tcg_gen_movi_i64(cpu_ir[rc], (int64_t)((int16_t)lit));
1892 else if (rb != 31)
1893 tcg_gen_ext16s_i64(cpu_ir[rc], cpu_ir[rb]);
1894 else
1895 tcg_gen_movi_i64(cpu_ir[rc], 0);
1896 }
4c9649a9
JM		 1897 break;
1898 case 0x30:
1899 /* CTPOP */
1900 if (!(ctx->amask & AMASK_CIX))
1901 goto invalid_opc;
ae8ecd42
AJ		 1902 if (likely(rc != 31)) {
1903 if (islit)
1904 tcg_gen_movi_i64(cpu_ir[rc], ctpop64(lit));
1905 else if (rb != 31)
1906 tcg_gen_helper_1_1(helper_ctpop, cpu_ir[rc], cpu_ir[rb]);
1907 else
1908 tcg_gen_movi_i64(cpu_ir[rc], 0);
1909 }
4c9649a9
JM		 1910 break;
1911 case 0x31:
1912 /* PERR */
1913 if (!(ctx->amask & AMASK_MVI))
1914 goto invalid_opc;
1915 /* XXX: TODO */
1916 goto invalid_opc;
1917 break;
1918 case 0x32:
1919 /* CTLZ */
1920 if (!(ctx->amask & AMASK_CIX))
1921 goto invalid_opc;
ae8ecd42
AJ		 1922 if (likely(rc != 31)) {
1923 if (islit)
1924 tcg_gen_movi_i64(cpu_ir[rc], clz64(lit));
1925 else if (rb != 31)
1926 tcg_gen_helper_1_1(helper_ctlz, cpu_ir[rc], cpu_ir[rb]);
1927 else
1928 tcg_gen_movi_i64(cpu_ir[rc], 0);
1929 }
4c9649a9
JM		 1930 break;
1931 case 0x33:
1932 /* CTTZ */
1933 if (!(ctx->amask & AMASK_CIX))
1934 goto invalid_opc;
ae8ecd42
AJ		 1935 if (likely(rc != 31)) {
1936 if (islit)
1937 tcg_gen_movi_i64(cpu_ir[rc], ctz64(lit));
1938 else if (rb != 31)
1939 tcg_gen_helper_1_1(helper_cttz, cpu_ir[rc], cpu_ir[rb]);
1940 else
1941 tcg_gen_movi_i64(cpu_ir[rc], 0);
1942 }
4c9649a9
JM		 1943 break;
1944 case 0x34:
1945 /* UNPKBW */
1946 if (!(ctx->amask & AMASK_MVI))
1947 goto invalid_opc;
1948 /* XXX: TODO */
1949 goto invalid_opc;
1950 break;
1951 case 0x35:
1952 /* UNPKWL */
1953 if (!(ctx->amask & AMASK_MVI))
1954 goto invalid_opc;
1955 /* XXX: TODO */
1956 goto invalid_opc;
1957 break;
1958 case 0x36:
1959 /* PKWB */
1960 if (!(ctx->amask & AMASK_MVI))
1961 goto invalid_opc;
1962 /* XXX: TODO */
1963 goto invalid_opc;
1964 break;
1965 case 0x37:
1966 /* PKLB */
1967 if (!(ctx->amask & AMASK_MVI))
1968 goto invalid_opc;
1969 /* XXX: TODO */
1970 goto invalid_opc;
1971 break;
1972 case 0x38:
1973 /* MINSB8 */
1974 if (!(ctx->amask & AMASK_MVI))
1975 goto invalid_opc;
1976 /* XXX: TODO */
1977 goto invalid_opc;
1978 break;
1979 case 0x39:
1980 /* MINSW4 */
1981 if (!(ctx->amask & AMASK_MVI))
1982 goto invalid_opc;
1983 /* XXX: TODO */
1984 goto invalid_opc;
1985 break;
1986 case 0x3A:
1987 /* MINUB8 */
1988 if (!(ctx->amask & AMASK_MVI))
1989 goto invalid_opc;
1990 /* XXX: TODO */
1991 goto invalid_opc;
1992 break;
1993 case 0x3B:
1994 /* MINUW4 */
1995 if (!(ctx->amask & AMASK_MVI))
1996 goto invalid_opc;
1997 /* XXX: TODO */
1998 goto invalid_opc;
1999 break;
2000 case 0x3C:
2001 /* MAXUB8 */
2002 if (!(ctx->amask & AMASK_MVI))
2003 goto invalid_opc;
2004 /* XXX: TODO */
2005 goto invalid_opc;
2006 break;
2007 case 0x3D:
2008 /* MAXUW4 */
2009 if (!(ctx->amask & AMASK_MVI))
2010 goto invalid_opc;
2011 /* XXX: TODO */
2012 goto invalid_opc;
2013 break;
2014 case 0x3E:
2015 /* MAXSB8 */
2016 if (!(ctx->amask & AMASK_MVI))
2017 goto invalid_opc;
2018 /* XXX: TODO */
2019 goto invalid_opc;
2020 break;
2021 case 0x3F:
2022 /* MAXSW4 */
2023 if (!(ctx->amask & AMASK_MVI))
2024 goto invalid_opc;
2025 /* XXX: TODO */
2026 goto invalid_opc;
2027 break;
2028 case 0x70:
2029 /* FTOIT */
2030 if (!(ctx->amask & AMASK_FIX))
2031 goto invalid_opc;
2032 gen_fti(ctx, &gen_op_ftoit, ra, rb);
2033 break;
2034 case 0x78:
2035 /* FTOIS */
2036 if (!(ctx->amask & AMASK_FIX))
2037 goto invalid_opc;
2038 gen_fti(ctx, &gen_op_ftois, ra, rb);
2039 break;
2040 default:
2041 goto invalid_opc;
2042 }
2043 break;
2044 case 0x1D:
2045 /* HW_MTPR (PALcode) */
2046#if defined (CONFIG_USER_ONLY)
2047 goto invalid_opc;
2048#else
2049 if (!ctx->pal_mode)
2050 goto invalid_opc;
3761035f
AJ		 2051 if (ra != 31)
2052 tcg_gen_mov_i64(cpu_T[0], cpu_ir[ra]);
2053 else
2054 tcg_gen_movi_i64(cpu_T[0], 0);
4c9649a9
JM		 2055 gen_op_mtpr(insn & 0xFF);
2056 ret = 2;
2057 break;
2058#endif
2059 case 0x1E:
2060 /* HW_REI (PALcode) */
2061#if defined (CONFIG_USER_ONLY)
2062 goto invalid_opc;
2063#else
2064 if (!ctx->pal_mode)
2065 goto invalid_opc;
2066 if (rb == 31) {
2067 /* "Old" alpha */
2068 gen_op_hw_rei();
2069 } else {
3761035f
AJ		 2070 if (ra != 31)
2071 tcg_gen_mov_i64(cpu_T[0], cpu_ir[rb]);
2072 else
2073 tcg_gen_movi_i64(cpu_T[0], 0);
2074 tcg_gen_movi_i64(cpu_T[1], (((int64_t)insn << 51) >> 51));
4f821e17 2075 tcg_gen_add_i64(cpu_T[0], cpu_T[0], cpu_T[1]);
4c9649a9
JM		 2076 gen_op_hw_ret();
2077 }
2078 ret = 2;
2079 break;
2080#endif
2081 case 0x1F:
2082 /* HW_ST (PALcode) */
2083#if defined (CONFIG_USER_ONLY)
2084 goto invalid_opc;
2085#else
2086 if (!ctx->pal_mode)
2087 goto invalid_opc;
3761035f 2088 if (ra != 31)
4f821e17 2089 tcg_gen_addi_i64(cpu_T[0], cpu_ir[rb], disp12);
3761035f 2090 else
4f821e17 2091 tcg_gen_movi_i64(cpu_T[0], disp12);
3761035f
AJ		 2092 if (ra != 31)
2093 tcg_gen_mov_i64(cpu_T[1], cpu_ir[ra]);
2094 else
2095 tcg_gen_movi_i64(cpu_T[1], 0);
4c9649a9
JM		 2096 switch ((insn >> 12) & 0xF) {
2097 case 0x0:
2098 /* Longword physical access */
2099 gen_op_stl_raw();
2100 break;
2101 case 0x1:
2102 /* Quadword physical access */
2103 gen_op_stq_raw();
2104 break;
2105 case 0x2:
2106 /* Longword physical access with lock */
2107 gen_op_stl_c_raw();
2108 break;
2109 case 0x3:
2110 /* Quadword physical access with lock */
2111 gen_op_stq_c_raw();
2112 break;
2113 case 0x4:
2114 /* Longword virtual access */
2115 gen_op_st_phys_to_virt();
2116 gen_op_stl_raw();
2117 break;
2118 case 0x5:
2119 /* Quadword virtual access */
2120 gen_op_st_phys_to_virt();
2121 gen_op_stq_raw();
2122 break;
2123 case 0x6:
2124 /* Invalid */
2125 goto invalid_opc;
2126 case 0x7:
2127 /* Invalid */
2128 goto invalid_opc;
2129 case 0x8:
2130 /* Invalid */
2131 goto invalid_opc;
2132 case 0x9:
2133 /* Invalid */
2134 goto invalid_opc;
2135 case 0xA:
2136 /* Invalid */
2137 goto invalid_opc;
2138 case 0xB:
2139 /* Invalid */
2140 goto invalid_opc;
2141 case 0xC:
2142 /* Longword virtual access with alternate access mode */
2143 gen_op_set_alt_mode();
2144 gen_op_st_phys_to_virt();
2145 gen_op_ldl_raw();
2146 gen_op_restore_mode();
2147 break;
2148 case 0xD:
2149 /* Quadword virtual access with alternate access mode */
2150 gen_op_set_alt_mode();
2151 gen_op_st_phys_to_virt();
2152 gen_op_ldq_raw();
2153 gen_op_restore_mode();
2154 break;
2155 case 0xE:
2156 /* Invalid */
2157 goto invalid_opc;
2158 case 0xF:
2159 /* Invalid */
2160 goto invalid_opc;
2161 }
2162 ret = 2;
2163 break;
2164#endif
2165 case 0x20:
2166 /* LDF */
2167#if 0 // TODO
2168 gen_load_fmem(ctx, &gen_ldf, ra, rb, disp16);
2169#else
2170 goto invalid_opc;
2171#endif
2172 break;
2173 case 0x21:
2174 /* LDG */
2175#if 0 // TODO
2176 gen_load_fmem(ctx, &gen_ldg, ra, rb, disp16);
2177#else
2178 goto invalid_opc;
2179#endif
2180 break;
2181 case 0x22:
2182 /* LDS */
2183 gen_load_fmem(ctx, &gen_lds, ra, rb, disp16);
2184 break;
2185 case 0x23:
2186 /* LDT */
2187 gen_load_fmem(ctx, &gen_ldt, ra, rb, disp16);
2188 break;
2189 case 0x24:
2190 /* STF */
2191#if 0 // TODO
2192 gen_store_fmem(ctx, &gen_stf, ra, rb, disp16);
2193#else
2194 goto invalid_opc;
2195#endif
2196 break;
2197 case 0x25:
2198 /* STG */
2199#if 0 // TODO
2200 gen_store_fmem(ctx, &gen_stg, ra, rb, disp16);
2201#else
2202 goto invalid_opc;
2203#endif
2204 break;
2205 case 0x26:
2206 /* STS */
2207 gen_store_fmem(ctx, &gen_sts, ra, rb, disp16);
2208 break;
2209 case 0x27:
2210 /* STT */
2211 gen_store_fmem(ctx, &gen_stt, ra, rb, disp16);
2212 break;
2213 case 0x28:
2214 /* LDL */
2215 gen_load_mem(ctx, &gen_ldl, ra, rb, disp16, 0);
2216 break;
2217 case 0x29:
2218 /* LDQ */
2219 gen_load_mem(ctx, &gen_ldq, ra, rb, disp16, 0);
2220 break;
2221 case 0x2A:
2222 /* LDL_L */
2223 gen_load_mem(ctx, &gen_ldl_l, ra, rb, disp16, 0);
2224 break;
2225 case 0x2B:
2226 /* LDQ_L */
2227 gen_load_mem(ctx, &gen_ldq_l, ra, rb, disp16, 0);
2228 break;
2229 case 0x2C:
2230 /* STL */
2231 gen_store_mem(ctx, &gen_stl, ra, rb, disp16, 0);
2232 break;
2233 case 0x2D:
2234 /* STQ */
2235 gen_store_mem(ctx, &gen_stq, ra, rb, disp16, 0);
2236 break;
2237 case 0x2E:
2238 /* STL_C */
2239 gen_store_mem(ctx, &gen_stl_c, ra, rb, disp16, 0);
2240 break;
2241 case 0x2F:
2242 /* STQ_C */
2243 gen_store_mem(ctx, &gen_stq_c, ra, rb, disp16, 0);
2244 break;
2245 case 0x30:
2246 /* BR */
3761035f
AJ		 2247 if (ra != 31)
2248 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
2249 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
4c9649a9
JM		 2250 ret = 1;
2251 break;
2252 case 0x31:
2253 /* FBEQ */
2254 gen_fbcond(ctx, &gen_op_cmpfeq, ra, disp16);
2255 ret = 1;
2256 break;
2257 case 0x32:
2258 /* FBLT */
2259 gen_fbcond(ctx, &gen_op_cmpflt, ra, disp16);
2260 ret = 1;
2261 break;
2262 case 0x33:
2263 /* FBLE */
2264 gen_fbcond(ctx, &gen_op_cmpfle, ra, disp16);
2265 ret = 1;
2266 break;
2267 case 0x34:
2268 /* BSR */
3761035f
AJ		 2269 if (ra != 31)
2270 tcg_gen_movi_i64(cpu_ir[ra], ctx->pc);
2271 tcg_gen_movi_i64(cpu_pc, ctx->pc + (int64_t)(disp21 << 2));
4c9649a9
JM		 2272 ret = 1;
2273 break;
2274 case 0x35:
2275 /* FBNE */
2276 gen_fbcond(ctx, &gen_op_cmpfne, ra, disp16);
2277 ret = 1;
2278 break;
2279 case 0x36:
2280 /* FBGE */
2281 gen_fbcond(ctx, &gen_op_cmpfge, ra, disp16);
2282 ret = 1;
2283 break;
2284 case 0x37:
2285 /* FBGT */
2286 gen_fbcond(ctx, &gen_op_cmpfgt, ra, disp16);
2287 ret = 1;
2288 break;
2289 case 0x38:
2290 /* BLBC */
9c29504e 2291 gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 1);
4c9649a9
JM		 2292 ret = 1;
2293 break;
2294 case 0x39:
2295 /* BEQ */
9c29504e 2296 gen_bcond(ctx, TCG_COND_EQ, ra, disp16, 0);
4c9649a9
JM		 2297 ret = 1;
2298 break;
2299 case 0x3A:
2300 /* BLT */
9c29504e 2301 gen_bcond(ctx, TCG_COND_LT, ra, disp16, 0);
4c9649a9
JM		 2302 ret = 1;
2303 break;
2304 case 0x3B:
2305 /* BLE */
9c29504e 2306 gen_bcond(ctx, TCG_COND_LE, ra, disp16, 0);
4c9649a9
JM		 2307 ret = 1;
2308 break;
2309 case 0x3C:
2310 /* BLBS */
9c29504e 2311 gen_bcond(ctx, TCG_COND_NE, ra, disp16, 1);
4c9649a9
JM		 2312 ret = 1;
2313 break;
2314 case 0x3D:
2315 /* BNE */
9c29504e 2316 gen_bcond(ctx, TCG_COND_NE, ra, disp16, 0);
4c9649a9
JM		 2317 ret = 1;
2318 break;
2319 case 0x3E:
2320 /* BGE */
9c29504e 2321 gen_bcond(ctx, TCG_COND_GE, ra, disp16, 0);
4c9649a9
JM		 2322 ret = 1;
2323 break;
2324 case 0x3F:
2325 /* BGT */
9c29504e 2326 gen_bcond(ctx, TCG_COND_GT, ra, disp16, 0);
4c9649a9
JM		 2327 ret = 1;
2328 break;
2329 invalid_opc:
2330 gen_invalid(ctx);
2331 ret = 3;
2332 break;
2333 }
2334
2335 return ret;
2336}
2337
2cfc5f17
TS		 2338static always_inline void gen_intermediate_code_internal (CPUState *env,
2339 TranslationBlock *tb,
2340 int search_pc)
4c9649a9
JM		 2341{
2342#if defined ALPHA_DEBUG_DISAS
2343 static int insn_count;
2344#endif
2345 DisasContext ctx, *ctxp = &ctx;
2346 target_ulong pc_start;
2347 uint32_t insn;
2348 uint16_t *gen_opc_end;
2349 int j, lj = -1;
2350 int ret;
2e70f6ef
PB		 2351 int num_insns;
2352 int max_insns;
4c9649a9
JM		 2353
2354 pc_start = tb->pc;
4c9649a9 2355 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4c9649a9
JM		 2356 ctx.pc = pc_start;
2357 ctx.amask = env->amask;
2358#if defined (CONFIG_USER_ONLY)
2359 ctx.mem_idx = 0;
2360#else
2361 ctx.mem_idx = ((env->ps >> 3) & 3);
2362 ctx.pal_mode = env->ipr[IPR_EXC_ADDR] & 1;
2363#endif
2e70f6ef
PB		 2364 num_insns = 0;
2365 max_insns = tb->cflags & CF_COUNT_MASK;
2366 if (max_insns == 0)
2367 max_insns = CF_COUNT_MASK;
2368
2369 gen_icount_start();
4c9649a9
JM		 2370 for (ret = 0; ret == 0;) {
2371 if (env->nb_breakpoints > 0) {
2372 for(j = 0; j < env->nb_breakpoints; j++) {
2373 if (env->breakpoints[j] == ctx.pc) {
2374 gen_excp(&ctx, EXCP_DEBUG, 0);
2375 break;
2376 }
2377 }
2378 }
2379 if (search_pc) {
2380 j = gen_opc_ptr - gen_opc_buf;
2381 if (lj < j) {
2382 lj++;
2383 while (lj < j)
2384 gen_opc_instr_start[lj++] = 0;
2385 gen_opc_pc[lj] = ctx.pc;
2386 gen_opc_instr_start[lj] = 1;
2e70f6ef 2387 gen_opc_icount[lj] = num_insns;
4c9649a9
JM		 2388 }
2389 }
2e70f6ef
PB		 2390 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
2391 gen_io_start();
4c9649a9
JM		 2392#if defined ALPHA_DEBUG_DISAS
2393 insn_count++;
2394 if (logfile != NULL) {
e96efcfc
JM		 2395 fprintf(logfile, "pc " TARGET_FMT_lx " mem_idx %d\n",
2396 ctx.pc, ctx.mem_idx);
4c9649a9
JM		 2397 }
2398#endif
2399 insn = ldl_code(ctx.pc);
2400#if defined ALPHA_DEBUG_DISAS
2401 insn_count++;
2402 if (logfile != NULL) {
2403 fprintf(logfile, "opcode %08x %d\n", insn, insn_count);
2404 }
2405#endif
2e70f6ef 2406 num_insns++;
4c9649a9
JM		 2407 ctx.pc += 4;
2408 ret = translate_one(ctxp, insn);
2409 if (ret != 0)
2410 break;
2411 /* if we reach a page boundary or are single stepping, stop
2412 * generation
2413 */
2414 if (((ctx.pc & (TARGET_PAGE_SIZE - 1)) == 0) ||
2e70f6ef
PB		 2415 (env->singlestep_enabled) ||
2416 num_insns >= max_insns) {
4c9649a9
JM		 2417 break;
2418 }
2419#if defined (DO_SINGLE_STEP)
2420 break;
2421#endif
2422 }
2423 if (ret != 1 && ret != 3) {
496cb5b9 2424 tcg_gen_movi_i64(cpu_pc, ctx.pc);
4c9649a9 2425 }
4c9649a9 2426#if defined (DO_TB_FLUSH)
496cb5b9 2427 tcg_gen_helper_0_0(helper_tb_flush);
4c9649a9 2428#endif
2e70f6ef
PB		 2429 if (tb->cflags & CF_LAST_IO)
2430 gen_io_end();
4c9649a9 2431 /* Generate the return instruction */
57fec1fe 2432 tcg_gen_exit_tb(0);
2e70f6ef 2433 gen_icount_end(tb, num_insns);
4c9649a9
JM		 2434 *gen_opc_ptr = INDEX_op_end;
2435 if (search_pc) {
2436 j = gen_opc_ptr - gen_opc_buf;
2437 lj++;
2438 while (lj <= j)
2439 gen_opc_instr_start[lj++] = 0;
4c9649a9
JM		 2440 } else {
2441 tb->size = ctx.pc - pc_start;
2e70f6ef 2442 tb->icount = num_insns;
4c9649a9
JM		 2443 }
2444#if defined ALPHA_DEBUG_DISAS
2445 if (loglevel & CPU_LOG_TB_CPU) {
2446 cpu_dump_state(env, logfile, fprintf, 0);
2447 }
2448 if (loglevel & CPU_LOG_TB_IN_ASM) {
2449 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2450 target_disas(logfile, pc_start, ctx.pc - pc_start, 1);
2451 fprintf(logfile, "\n");
2452 }
4c9649a9 2453#endif
4c9649a9
JM		 2454}
2455
2cfc5f17 2456void gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
4c9649a9 2457{
2cfc5f17 2458 gen_intermediate_code_internal(env, tb, 0);
4c9649a9
JM		 2459}
2460
2cfc5f17 2461void gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
4c9649a9 2462{
2cfc5f17 2463 gen_intermediate_code_internal(env, tb, 1);
4c9649a9
JM		 2464}
2465
aaed909a 2466CPUAlphaState * cpu_alpha_init (const char *cpu_model)
4c9649a9
JM		 2467{
2468 CPUAlphaState *env;
2469 uint64_t hwpcb;
2470
2471 env = qemu_mallocz(sizeof(CPUAlphaState));
2472 if (!env)
2473 return NULL;
2474 cpu_exec_init(env);
2e70f6ef 2475 alpha_translate_init();
4c9649a9
JM		 2476 tlb_flush(env, 1);
2477 /* XXX: should not be hardcoded */
2478 env->implver = IMPLVER_2106x;
2479 env->ps = 0x1F00;
2480#if defined (CONFIG_USER_ONLY)
2481 env->ps |= 1 << 3;
2482#endif
2483 pal_init(env);
2484 /* Initialize IPR */
2485 hwpcb = env->ipr[IPR_PCBB];
2486 env->ipr[IPR_ASN] = 0;
2487 env->ipr[IPR_ASTEN] = 0;
2488 env->ipr[IPR_ASTSR] = 0;
2489 env->ipr[IPR_DATFX] = 0;
2490 /* XXX: fix this */
2491 // env->ipr[IPR_ESP] = ldq_raw(hwpcb + 8);
2492 // env->ipr[IPR_KSP] = ldq_raw(hwpcb + 0);
2493 // env->ipr[IPR_SSP] = ldq_raw(hwpcb + 16);
2494 // env->ipr[IPR_USP] = ldq_raw(hwpcb + 24);
2495 env->ipr[IPR_FEN] = 0;
2496 env->ipr[IPR_IPL] = 31;
2497 env->ipr[IPR_MCES] = 0;
2498 env->ipr[IPR_PERFMON] = 0; /* Implementation specific */
2499 // env->ipr[IPR_PTBR] = ldq_raw(hwpcb + 32);
2500 env->ipr[IPR_SISR] = 0;
2501 env->ipr[IPR_VIRBND] = -1ULL;
2502
2503 return env;
2504}
aaed909a 2505
d2856f1a
AJ		 2506void gen_pc_load(CPUState *env, TranslationBlock *tb,
2507 unsigned long searched_pc, int pc_pos, void *puc)
2508{
2509 env->pc = gen_opc_pc[pc_pos];
2510}
Qemu copy for testing