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target-arm: use clz32() instead of a for loop
[qemu.git] / target-arm / helper.c
CommitLineData
b5ff1b31
FB		 1#include <stdio.h>
2#include <stdlib.h>
3#include <string.h>
4
5#include "cpu.h"
6#include "exec-all.h"
9ee6e8bb 7#include "gdbstub.h"
b26eefb6 8#include "helpers.h"
ca10f867 9#include "qemu-common.h"
7bbcb0af 10#include "host-utils.h"
9ee6e8bb
PB		 11
12static uint32_t cortexa8_cp15_c0_c1[8] =
13{ 0x1031, 0x11, 0x400, 0, 0x31100003, 0x20000000, 0x01202000, 0x11 };
14
15static uint32_t cortexa8_cp15_c0_c2[8] =
16{ 0x00101111, 0x12112111, 0x21232031, 0x11112131, 0x00111142, 0, 0, 0 };
17
18static uint32_t mpcore_cp15_c0_c1[8] =
19{ 0x111, 0x1, 0, 0x2, 0x01100103, 0x10020302, 0x01222000, 0 };
20
21static uint32_t mpcore_cp15_c0_c2[8] =
22{ 0x00100011, 0x12002111, 0x11221011, 0x01102131, 0x141, 0, 0, 0 };
23
24static uint32_t arm1136_cp15_c0_c1[8] =
25{ 0x111, 0x1, 0x2, 0x3, 0x01130003, 0x10030302, 0x01222110, 0 };
26
27static uint32_t arm1136_cp15_c0_c2[8] =
28{ 0x00140011, 0x12002111, 0x11231111, 0x01102131, 0x141, 0, 0, 0 };
b5ff1b31 29
aaed909a
FB		 30static uint32_t cpu_arm_find_by_name(const char *name);
31
f3d6b95e
PB		 32static inline void set_feature(CPUARMState *env, int feature)
33{
34 env->features |= 1u << feature;
35}
36
37static void cpu_reset_model_id(CPUARMState *env, uint32_t id)
38{
39 env->cp15.c0_cpuid = id;
40 switch (id) {
41 case ARM_CPUID_ARM926:
42 set_feature(env, ARM_FEATURE_VFP);
43 env->vfp.xregs[ARM_VFP_FPSID] = 0x41011090;
c1713132 44 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 45 env->cp15.c1_sys = 0x00090078;
f3d6b95e 46 break;
ce819861
PB		 47 case ARM_CPUID_ARM946:
48 set_feature(env, ARM_FEATURE_MPU);
49 env->cp15.c0_cachetype = 0x0f004006;
610c3c8a 50 env->cp15.c1_sys = 0x00000078;
ce819861 51 break;
f3d6b95e
PB		 52 case ARM_CPUID_ARM1026:
53 set_feature(env, ARM_FEATURE_VFP);
54 set_feature(env, ARM_FEATURE_AUXCR);
55 env->vfp.xregs[ARM_VFP_FPSID] = 0x410110a0;
c1713132 56 env->cp15.c0_cachetype = 0x1dd20d2;
610c3c8a 57 env->cp15.c1_sys = 0x00090078;
c1713132 58 break;
827df9f3 59 case ARM_CPUID_ARM1136_R2:
9ee6e8bb
PB		 60 case ARM_CPUID_ARM1136:
61 set_feature(env, ARM_FEATURE_V6);
62 set_feature(env, ARM_FEATURE_VFP);
63 set_feature(env, ARM_FEATURE_AUXCR);
64 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
65 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
66 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
67 memcpy(env->cp15.c0_c1, arm1136_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 68 memcpy(env->cp15.c0_c2, arm1136_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 69 env->cp15.c0_cachetype = 0x1dd20d2;
70 break;
71 case ARM_CPUID_ARM11MPCORE:
72 set_feature(env, ARM_FEATURE_V6);
73 set_feature(env, ARM_FEATURE_V6K);
74 set_feature(env, ARM_FEATURE_VFP);
75 set_feature(env, ARM_FEATURE_AUXCR);
76 env->vfp.xregs[ARM_VFP_FPSID] = 0x410120b4;
77 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11111111;
78 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00000000;
79 memcpy(env->cp15.c0_c1, mpcore_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 80 memcpy(env->cp15.c0_c2, mpcore_cp15_c0_c2, 8 * sizeof(uint32_t));
9ee6e8bb
PB		 81 env->cp15.c0_cachetype = 0x1dd20d2;
82 break;
83 case ARM_CPUID_CORTEXA8:
84 set_feature(env, ARM_FEATURE_V6);
85 set_feature(env, ARM_FEATURE_V6K);
86 set_feature(env, ARM_FEATURE_V7);
87 set_feature(env, ARM_FEATURE_AUXCR);
88 set_feature(env, ARM_FEATURE_THUMB2);
89 set_feature(env, ARM_FEATURE_VFP);
90 set_feature(env, ARM_FEATURE_VFP3);
91 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 92 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb
PB		 93 env->vfp.xregs[ARM_VFP_FPSID] = 0x410330c0;
94 env->vfp.xregs[ARM_VFP_MVFR0] = 0x11110222;
95 env->vfp.xregs[ARM_VFP_MVFR1] = 0x00011100;
96 memcpy(env->cp15.c0_c1, cortexa8_cp15_c0_c1, 8 * sizeof(uint32_t));
22478e79 97 memcpy(env->cp15.c0_c2, cortexa8_cp15_c0_c2, 8 * sizeof(uint32_t));
a49ea279
PB		 98 env->cp15.c0_cachetype = 0x82048004;
99 env->cp15.c0_clid = (1 << 27) | (2 << 24) | 3;
100 env->cp15.c0_ccsid[0] = 0xe007e01a; /* 16k L1 dcache. */
101 env->cp15.c0_ccsid[1] = 0x2007e01a; /* 16k L1 icache. */
102 env->cp15.c0_ccsid[2] = 0xf0000000; /* No L2 icache. */
9ee6e8bb
PB		 103 break;
104 case ARM_CPUID_CORTEXM3:
105 set_feature(env, ARM_FEATURE_V6);
106 set_feature(env, ARM_FEATURE_THUMB2);
107 set_feature(env, ARM_FEATURE_V7);
108 set_feature(env, ARM_FEATURE_M);
109 set_feature(env, ARM_FEATURE_DIV);
110 break;
111 case ARM_CPUID_ANY: /* For userspace emulation. */
112 set_feature(env, ARM_FEATURE_V6);
113 set_feature(env, ARM_FEATURE_V6K);
114 set_feature(env, ARM_FEATURE_V7);
115 set_feature(env, ARM_FEATURE_THUMB2);
116 set_feature(env, ARM_FEATURE_VFP);
117 set_feature(env, ARM_FEATURE_VFP3);
118 set_feature(env, ARM_FEATURE_NEON);
fe1479c3 119 set_feature(env, ARM_FEATURE_THUMB2EE);
9ee6e8bb
PB		 120 set_feature(env, ARM_FEATURE_DIV);
121 break;
c3d2689d
AZ		 122 case ARM_CPUID_TI915T:
123 case ARM_CPUID_TI925T:
124 set_feature(env, ARM_FEATURE_OMAPCP);
125 env->cp15.c0_cpuid = ARM_CPUID_TI925T; /* Depends on wiring. */
126 env->cp15.c0_cachetype = 0x5109149;
127 env->cp15.c1_sys = 0x00000070;
128 env->cp15.c15_i_max = 0x000;
129 env->cp15.c15_i_min = 0xff0;
130 break;
c1713132
AZ		 131 case ARM_CPUID_PXA250:
132 case ARM_CPUID_PXA255:
133 case ARM_CPUID_PXA260:
134 case ARM_CPUID_PXA261:
135 case ARM_CPUID_PXA262:
136 set_feature(env, ARM_FEATURE_XSCALE);
137 /* JTAG_ID is ((id << 28) | 0x09265013) */
138 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 139 env->cp15.c1_sys = 0x00000078;
c1713132
AZ		 140 break;
141 case ARM_CPUID_PXA270_A0:
142 case ARM_CPUID_PXA270_A1:
143 case ARM_CPUID_PXA270_B0:
144 case ARM_CPUID_PXA270_B1:
145 case ARM_CPUID_PXA270_C0:
146 case ARM_CPUID_PXA270_C5:
147 set_feature(env, ARM_FEATURE_XSCALE);
148 /* JTAG_ID is ((id << 28) | 0x09265013) */
18c9b560
AZ		 149 set_feature(env, ARM_FEATURE_IWMMXT);
150 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
c1713132 151 env->cp15.c0_cachetype = 0xd172172;
610c3c8a 152 env->cp15.c1_sys = 0x00000078;
f3d6b95e
PB		 153 break;
154 default:
155 cpu_abort(env, "Bad CPU ID: %x\n", id);
156 break;
157 }
158}
159
40f137e1
PB		 160void cpu_reset(CPUARMState *env)
161{
f3d6b95e 162 uint32_t id;
eca1bdf4
AL		 163
164 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
165 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
166 log_cpu_state(env, 0);
167 }
168
f3d6b95e
PB		 169 id = env->cp15.c0_cpuid;
170 memset(env, 0, offsetof(CPUARMState, breakpoints));
171 if (id)
172 cpu_reset_model_id(env, id);
40f137e1
PB		 173#if defined (CONFIG_USER_ONLY)
174 env->uncached_cpsr = ARM_CPU_MODE_USR;
175 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
176#else
177 /* SVC mode with interrupts disabled. */
178 env->uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
9ee6e8bb
PB		 179 /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
180 clear at reset. */
181 if (IS_M(env))
182 env->uncached_cpsr &= ~CPSR_I;
40f137e1 183 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
b2fa1797 184 env->cp15.c2_base_mask = 0xffffc000u;
40f137e1
PB		 185#endif
186 env->regs[15] = 0;
f3d6b95e 187 tlb_flush(env, 1);
40f137e1
PB		 188}
189
56aebc89
PB		 190static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
191{
192 int nregs;
193
194 /* VFP data registers are always little-endian. */
195 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
196 if (reg < nregs) {
197 stfq_le_p(buf, env->vfp.regs[reg]);
198 return 8;
199 }
200 if (arm_feature(env, ARM_FEATURE_NEON)) {
201 /* Aliases for Q regs. */
202 nregs += 16;
203 if (reg < nregs) {
204 stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
205 stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
206 return 16;
207 }
208 }
209 switch (reg - nregs) {
210 case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
211 case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
212 case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
213 }
214 return 0;
215}
216
217static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
218{
219 int nregs;
220
221 nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
222 if (reg < nregs) {
223 env->vfp.regs[reg] = ldfq_le_p(buf);
224 return 8;
225 }
226 if (arm_feature(env, ARM_FEATURE_NEON)) {
227 nregs += 16;
228 if (reg < nregs) {
229 env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
230 env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
231 return 16;
232 }
233 }
234 switch (reg - nregs) {
235 case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
236 case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
237 case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf); return 4;
238 }
239 return 0;
240}
241
aaed909a 242CPUARMState *cpu_arm_init(const char *cpu_model)
40f137e1
PB		 243{
244 CPUARMState *env;
aaed909a 245 uint32_t id;
b26eefb6 246 static int inited = 0;
40f137e1 247
aaed909a
FB		 248 id = cpu_arm_find_by_name(cpu_model);
249 if (id == 0)
250 return NULL;
40f137e1 251 env = qemu_mallocz(sizeof(CPUARMState));
40f137e1 252 cpu_exec_init(env);
b26eefb6
PB		 253 if (!inited) {
254 inited = 1;
255 arm_translate_init();
256 }
257
01ba9816 258 env->cpu_model_str = cpu_model;
aaed909a 259 env->cp15.c0_cpuid = id;
40f137e1 260 cpu_reset(env);
56aebc89
PB		 261 if (arm_feature(env, ARM_FEATURE_NEON)) {
262 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
263 51, "arm-neon.xml", 0);
264 } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
265 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
266 35, "arm-vfp3.xml", 0);
267 } else if (arm_feature(env, ARM_FEATURE_VFP)) {
268 gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg,
269 19, "arm-vfp.xml", 0);
270 }
0bf46a40 271 qemu_init_vcpu(env);
40f137e1
PB		 272 return env;
273}
274
3371d272
PB		 275struct arm_cpu_t {
276 uint32_t id;
277 const char *name;
278};
279
280static const struct arm_cpu_t arm_cpu_names[] = {
281 { ARM_CPUID_ARM926, "arm926"},
ce819861 282 { ARM_CPUID_ARM946, "arm946"},
3371d272 283 { ARM_CPUID_ARM1026, "arm1026"},
9ee6e8bb 284 { ARM_CPUID_ARM1136, "arm1136"},
827df9f3 285 { ARM_CPUID_ARM1136_R2, "arm1136-r2"},
9ee6e8bb
PB		 286 { ARM_CPUID_ARM11MPCORE, "arm11mpcore"},
287 { ARM_CPUID_CORTEXM3, "cortex-m3"},
288 { ARM_CPUID_CORTEXA8, "cortex-a8"},
c3d2689d 289 { ARM_CPUID_TI925T, "ti925t" },
c1713132
AZ		 290 { ARM_CPUID_PXA250, "pxa250" },
291 { ARM_CPUID_PXA255, "pxa255" },
292 { ARM_CPUID_PXA260, "pxa260" },
293 { ARM_CPUID_PXA261, "pxa261" },
294 { ARM_CPUID_PXA262, "pxa262" },
295 { ARM_CPUID_PXA270, "pxa270" },
296 { ARM_CPUID_PXA270_A0, "pxa270-a0" },
297 { ARM_CPUID_PXA270_A1, "pxa270-a1" },
298 { ARM_CPUID_PXA270_B0, "pxa270-b0" },
299 { ARM_CPUID_PXA270_B1, "pxa270-b1" },
300 { ARM_CPUID_PXA270_C0, "pxa270-c0" },
301 { ARM_CPUID_PXA270_C5, "pxa270-c5" },
9ee6e8bb 302 { ARM_CPUID_ANY, "any"},
3371d272
PB		 303 { 0, NULL}
304};
305
c732abe2 306void arm_cpu_list(FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
5adb4839
PB		 307{
308 int i;
309
c732abe2 310 (*cpu_fprintf)(f, "Available CPUs:\n");
5adb4839 311 for (i = 0; arm_cpu_names[i].name; i++) {
c732abe2 312 (*cpu_fprintf)(f, " %s\n", arm_cpu_names[i].name);
5adb4839
PB		 313 }
314}
315
aaed909a
FB		 316/* return 0 if not found */
317static uint32_t cpu_arm_find_by_name(const char *name)
40f137e1 318{
3371d272
PB		 319 int i;
320 uint32_t id;
321
322 id = 0;
3371d272
PB		 323 for (i = 0; arm_cpu_names[i].name; i++) {
324 if (strcmp(name, arm_cpu_names[i].name) == 0) {
325 id = arm_cpu_names[i].id;
326 break;
327 }
328 }
aaed909a 329 return id;
40f137e1
PB		 330}
331
332void cpu_arm_close(CPUARMState *env)
333{
334 free(env);
335}
336
2f4a40e5
AZ		 337uint32_t cpsr_read(CPUARMState *env)
338{
339 int ZF;
6fbe23d5
PB		 340 ZF = (env->ZF == 0);
341 return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2f4a40e5
AZ		 342 (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
343 | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
344 | ((env->condexec_bits & 0xfc) << 8)
345 | (env->GE << 16);
346}
347
348void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
349{
2f4a40e5 350 if (mask & CPSR_NZCV) {
6fbe23d5
PB		 351 env->ZF = (~val) & CPSR_Z;
352 env->NF = val;
2f4a40e5
AZ		 353 env->CF = (val >> 29) & 1;
354 env->VF = (val << 3) & 0x80000000;
355 }
356 if (mask & CPSR_Q)
357 env->QF = ((val & CPSR_Q) != 0);
358 if (mask & CPSR_T)
359 env->thumb = ((val & CPSR_T) != 0);
360 if (mask & CPSR_IT_0_1) {
361 env->condexec_bits &= ~3;
362 env->condexec_bits |= (val >> 25) & 3;
363 }
364 if (mask & CPSR_IT_2_7) {
365 env->condexec_bits &= 3;
366 env->condexec_bits |= (val >> 8) & 0xfc;
367 }
368 if (mask & CPSR_GE) {
369 env->GE = (val >> 16) & 0xf;
370 }
371
372 if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
373 switch_mode(env, val & CPSR_M);
374 }
375 mask &= ~CACHED_CPSR_BITS;
376 env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
377}
378
b26eefb6
PB		 379/* Sign/zero extend */
380uint32_t HELPER(sxtb16)(uint32_t x)
381{
382 uint32_t res;
383 res = (uint16_t)(int8_t)x;
384 res |= (uint32_t)(int8_t)(x >> 16) << 16;
385 return res;
386}
387
388uint32_t HELPER(uxtb16)(uint32_t x)
389{
390 uint32_t res;
391 res = (uint16_t)(uint8_t)x;
392 res |= (uint32_t)(uint8_t)(x >> 16) << 16;
393 return res;
394}
395
f51bbbfe
PB		 396uint32_t HELPER(clz)(uint32_t x)
397{
7bbcb0af 398 return clz32(x);
f51bbbfe
PB		 399}
400
3670669c
PB		 401int32_t HELPER(sdiv)(int32_t num, int32_t den)
402{
403 if (den == 0)
404 return 0;
405 return num / den;
406}
407
408uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
409{
410 if (den == 0)
411 return 0;
412 return num / den;
413}
414
415uint32_t HELPER(rbit)(uint32_t x)
416{
417 x = ((x & 0xff000000) >> 24)
418 | ((x & 0x00ff0000) >> 8)
419 | ((x & 0x0000ff00) << 8)
420 | ((x & 0x000000ff) << 24);
421 x = ((x & 0xf0f0f0f0) >> 4)
422 | ((x & 0x0f0f0f0f) << 4);
423 x = ((x & 0x88888888) >> 3)
424 | ((x & 0x44444444) >> 1)
425 | ((x & 0x22222222) << 1)
426 | ((x & 0x11111111) << 3);
427 return x;
428}
429
ad69471c
PB		 430uint32_t HELPER(abs)(uint32_t x)
431{
432 return ((int32_t)x < 0) ? -x : x;
433}
434
5fafdf24 435#if defined(CONFIG_USER_ONLY)
b5ff1b31
FB		 436
437void do_interrupt (CPUState *env)
438{
439 env->exception_index = -1;
440}
441
9ee6e8bb
PB		 442/* Structure used to record exclusive memory locations. */
443typedef struct mmon_state {
444 struct mmon_state *next;
445 CPUARMState *cpu_env;
446 uint32_t addr;
447} mmon_state;
448
449/* Chain of current locks. */
450static mmon_state* mmon_head = NULL;
451
b5ff1b31 452int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
6ebbf390 453 int mmu_idx, int is_softmmu)
b5ff1b31
FB		 454{
455 if (rw == 2) {
456 env->exception_index = EXCP_PREFETCH_ABORT;
457 env->cp15.c6_insn = address;
458 } else {
459 env->exception_index = EXCP_DATA_ABORT;
460 env->cp15.c6_data = address;
461 }
462 return 1;
463}
464
9ee6e8bb
PB		 465static void allocate_mmon_state(CPUState *env)
466{
467 env->mmon_entry = malloc(sizeof (mmon_state));
9ee6e8bb
PB		 468 memset (env->mmon_entry, 0, sizeof (mmon_state));
469 env->mmon_entry->cpu_env = env;
470 mmon_head = env->mmon_entry;
471}
472
473/* Flush any monitor locks for the specified address. */
474static void flush_mmon(uint32_t addr)
475{
476 mmon_state *mon;
477
478 for (mon = mmon_head; mon; mon = mon->next)
479 {
480 if (mon->addr != addr)
481 continue;
482
483 mon->addr = 0;
484 break;
485 }
486}
487
488/* Mark an address for exclusive access. */
8f8e3aa4 489void HELPER(mark_exclusive)(CPUState *env, uint32_t addr)
9ee6e8bb
PB		 490{
491 if (!env->mmon_entry)
492 allocate_mmon_state(env);
493 /* Clear any previous locks. */
494 flush_mmon(addr);
495 env->mmon_entry->addr = addr;
496}
497
498/* Test if an exclusive address is still exclusive. Returns zero
499 if the address is still exclusive. */
8f8e3aa4 500uint32_t HELPER(test_exclusive)(CPUState *env, uint32_t addr)
9ee6e8bb
PB		 501{
502 int res;
503
504 if (!env->mmon_entry)
505 return 1;
506 if (env->mmon_entry->addr == addr)
507 res = 0;
508 else
509 res = 1;
510 flush_mmon(addr);
511 return res;
512}
513
8f8e3aa4 514void HELPER(clrex)(CPUState *env)
9ee6e8bb
PB		 515{
516 if (!(env->mmon_entry && env->mmon_entry->addr))
517 return;
518 flush_mmon(env->mmon_entry->addr);
519}
520
c227f099 521target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
b5ff1b31
FB		 522{
523 return addr;
524}
525
526/* These should probably raise undefined insn exceptions. */
8984bd2e 527void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 528{
529 int op1 = (insn >> 8) & 0xf;
530 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
531 return;
532}
533
8984bd2e 534uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 535{
536 int op1 = (insn >> 8) & 0xf;
537 cpu_abort(env, "cp%i insn %08x\n", op1, insn);
538 return 0;
539}
540
8984bd2e 541void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31
FB		 542{
543 cpu_abort(env, "cp15 insn %08x\n", insn);
544}
545
8984bd2e 546uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31
FB		 547{
548 cpu_abort(env, "cp15 insn %08x\n", insn);
549 return 0;
550}
551
9ee6e8bb 552/* These should probably raise undefined insn exceptions. */
8984bd2e 553void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 554{
555 cpu_abort(env, "v7m_mrs %d\n", reg);
556}
557
8984bd2e 558uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 559{
560 cpu_abort(env, "v7m_mrs %d\n", reg);
561 return 0;
562}
563
b5ff1b31
FB		 564void switch_mode(CPUState *env, int mode)
565{
566 if (mode != ARM_CPU_MODE_USR)
567 cpu_abort(env, "Tried to switch out of user mode\n");
568}
569
b0109805 570void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 571{
572 cpu_abort(env, "banked r13 write\n");
573}
574
b0109805 575uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb
PB		 576{
577 cpu_abort(env, "banked r13 read\n");
578 return 0;
579}
580
b5ff1b31
FB		 581#else
582
8e71621f
PB		 583extern int semihosting_enabled;
584
b5ff1b31
FB		 585/* Map CPU modes onto saved register banks. */
586static inline int bank_number (int mode)
587{
588 switch (mode) {
589 case ARM_CPU_MODE_USR:
590 case ARM_CPU_MODE_SYS:
591 return 0;
592 case ARM_CPU_MODE_SVC:
593 return 1;
594 case ARM_CPU_MODE_ABT:
595 return 2;
596 case ARM_CPU_MODE_UND:
597 return 3;
598 case ARM_CPU_MODE_IRQ:
599 return 4;
600 case ARM_CPU_MODE_FIQ:
601 return 5;
602 }
603 cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
604 return -1;
605}
606
607void switch_mode(CPUState *env, int mode)
608{
609 int old_mode;
610 int i;
611
612 old_mode = env->uncached_cpsr & CPSR_M;
613 if (mode == old_mode)
614 return;
615
616 if (old_mode == ARM_CPU_MODE_FIQ) {
617 memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 618 memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 619 } else if (mode == ARM_CPU_MODE_FIQ) {
620 memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
8637c67f 621 memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
b5ff1b31
FB		 622 }
623
624 i = bank_number(old_mode);
625 env->banked_r13[i] = env->regs[13];
626 env->banked_r14[i] = env->regs[14];
627 env->banked_spsr[i] = env->spsr;
628
629 i = bank_number(mode);
630 env->regs[13] = env->banked_r13[i];
631 env->regs[14] = env->banked_r14[i];
632 env->spsr = env->banked_spsr[i];
633}
634
9ee6e8bb
PB		 635static void v7m_push(CPUARMState *env, uint32_t val)
636{
637 env->regs[13] -= 4;
638 stl_phys(env->regs[13], val);
639}
640
641static uint32_t v7m_pop(CPUARMState *env)
642{
643 uint32_t val;
644 val = ldl_phys(env->regs[13]);
645 env->regs[13] += 4;
646 return val;
647}
648
649/* Switch to V7M main or process stack pointer. */
650static void switch_v7m_sp(CPUARMState *env, int process)
651{
652 uint32_t tmp;
653 if (env->v7m.current_sp != process) {
654 tmp = env->v7m.other_sp;
655 env->v7m.other_sp = env->regs[13];
656 env->regs[13] = tmp;
657 env->v7m.current_sp = process;
658 }
659}
660
661static void do_v7m_exception_exit(CPUARMState *env)
662{
663 uint32_t type;
664 uint32_t xpsr;
665
666 type = env->regs[15];
667 if (env->v7m.exception != 0)
668 armv7m_nvic_complete_irq(env->v7m.nvic, env->v7m.exception);
669
670 /* Switch to the target stack. */
671 switch_v7m_sp(env, (type & 4) != 0);
672 /* Pop registers. */
673 env->regs[0] = v7m_pop(env);
674 env->regs[1] = v7m_pop(env);
675 env->regs[2] = v7m_pop(env);
676 env->regs[3] = v7m_pop(env);
677 env->regs[12] = v7m_pop(env);
678 env->regs[14] = v7m_pop(env);
679 env->regs[15] = v7m_pop(env);
680 xpsr = v7m_pop(env);
681 xpsr_write(env, xpsr, 0xfffffdff);
682 /* Undo stack alignment. */
683 if (xpsr & 0x200)
684 env->regs[13] |= 4;
685 /* ??? The exception return type specifies Thread/Handler mode. However
686 this is also implied by the xPSR value. Not sure what to do
687 if there is a mismatch. */
688 /* ??? Likewise for mismatches between the CONTROL register and the stack
689 pointer. */
690}
691
2b3ea315 692static void do_interrupt_v7m(CPUARMState *env)
9ee6e8bb
PB		 693{
694 uint32_t xpsr = xpsr_read(env);
695 uint32_t lr;
696 uint32_t addr;
697
698 lr = 0xfffffff1;
699 if (env->v7m.current_sp)
700 lr |= 4;
701 if (env->v7m.exception == 0)
702 lr |= 8;
703
704 /* For exceptions we just mark as pending on the NVIC, and let that
705 handle it. */
706 /* TODO: Need to escalate if the current priority is higher than the
707 one we're raising. */
708 switch (env->exception_index) {
709 case EXCP_UDEF:
710 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_USAGE);
711 return;
712 case EXCP_SWI:
713 env->regs[15] += 2;
714 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_SVC);
715 return;
716 case EXCP_PREFETCH_ABORT:
717 case EXCP_DATA_ABORT:
718 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_MEM);
719 return;
720 case EXCP_BKPT:
2ad207d4
PB		 721 if (semihosting_enabled) {
722 int nr;
723 nr = lduw_code(env->regs[15]) & 0xff;
724 if (nr == 0xab) {
725 env->regs[15] += 2;
726 env->regs[0] = do_arm_semihosting(env);
727 return;
728 }
729 }
9ee6e8bb
PB		 730 armv7m_nvic_set_pending(env->v7m.nvic, ARMV7M_EXCP_DEBUG);
731 return;
732 case EXCP_IRQ:
733 env->v7m.exception = armv7m_nvic_acknowledge_irq(env->v7m.nvic);
734 break;
735 case EXCP_EXCEPTION_EXIT:
736 do_v7m_exception_exit(env);
737 return;
738 default:
739 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
740 return; /* Never happens. Keep compiler happy. */
741 }
742
743 /* Align stack pointer. */
744 /* ??? Should only do this if Configuration Control Register
745 STACKALIGN bit is set. */
746 if (env->regs[13] & 4) {
ab19b0ec 747 env->regs[13] -= 4;
9ee6e8bb
PB		 748 xpsr |= 0x200;
749 }
6c95676b 750 /* Switch to the handler mode. */
9ee6e8bb
PB		 751 v7m_push(env, xpsr);
752 v7m_push(env, env->regs[15]);
753 v7m_push(env, env->regs[14]);
754 v7m_push(env, env->regs[12]);
755 v7m_push(env, env->regs[3]);
756 v7m_push(env, env->regs[2]);
757 v7m_push(env, env->regs[1]);
758 v7m_push(env, env->regs[0]);
759 switch_v7m_sp(env, 0);
760 env->uncached_cpsr &= ~CPSR_IT;
761 env->regs[14] = lr;
762 addr = ldl_phys(env->v7m.vecbase + env->v7m.exception * 4);
763 env->regs[15] = addr & 0xfffffffe;
764 env->thumb = addr & 1;
765}
766
b5ff1b31
FB		 767/* Handle a CPU exception. */
768void do_interrupt(CPUARMState *env)
769{
770 uint32_t addr;
771 uint32_t mask;
772 int new_mode;
773 uint32_t offset;
774
9ee6e8bb
PB		 775 if (IS_M(env)) {
776 do_interrupt_v7m(env);
777 return;
778 }
b5ff1b31
FB		 779 /* TODO: Vectored interrupt controller. */
780 switch (env->exception_index) {
781 case EXCP_UDEF:
782 new_mode = ARM_CPU_MODE_UND;
783 addr = 0x04;
784 mask = CPSR_I;
785 if (env->thumb)
786 offset = 2;
787 else
788 offset = 4;
789 break;
790 case EXCP_SWI:
8e71621f
PB		 791 if (semihosting_enabled) {
792 /* Check for semihosting interrupt. */
793 if (env->thumb) {
794 mask = lduw_code(env->regs[15] - 2) & 0xff;
795 } else {
796 mask = ldl_code(env->regs[15] - 4) & 0xffffff;
797 }
798 /* Only intercept calls from privileged modes, to provide some
799 semblance of security. */
800 if (((mask == 0x123456 && !env->thumb)
801 || (mask == 0xab && env->thumb))
802 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
803 env->regs[0] = do_arm_semihosting(env);
804 return;
805 }
806 }
b5ff1b31
FB		 807 new_mode = ARM_CPU_MODE_SVC;
808 addr = 0x08;
809 mask = CPSR_I;
601d70b9 810 /* The PC already points to the next instruction. */
b5ff1b31
FB		 811 offset = 0;
812 break;
06c949e6 813 case EXCP_BKPT:
9ee6e8bb 814 /* See if this is a semihosting syscall. */
2ad207d4 815 if (env->thumb && semihosting_enabled) {
9ee6e8bb
PB		 816 mask = lduw_code(env->regs[15]) & 0xff;
817 if (mask == 0xab
818 && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
819 env->regs[15] += 2;
820 env->regs[0] = do_arm_semihosting(env);
821 return;
822 }
823 }
824 /* Fall through to prefetch abort. */
825 case EXCP_PREFETCH_ABORT:
b5ff1b31
FB		 826 new_mode = ARM_CPU_MODE_ABT;
827 addr = 0x0c;
828 mask = CPSR_A | CPSR_I;
829 offset = 4;
830 break;
831 case EXCP_DATA_ABORT:
832 new_mode = ARM_CPU_MODE_ABT;
833 addr = 0x10;
834 mask = CPSR_A | CPSR_I;
835 offset = 8;
836 break;
837 case EXCP_IRQ:
838 new_mode = ARM_CPU_MODE_IRQ;
839 addr = 0x18;
840 /* Disable IRQ and imprecise data aborts. */
841 mask = CPSR_A | CPSR_I;
842 offset = 4;
843 break;
844 case EXCP_FIQ:
845 new_mode = ARM_CPU_MODE_FIQ;
846 addr = 0x1c;
847 /* Disable FIQ, IRQ and imprecise data aborts. */
848 mask = CPSR_A | CPSR_I | CPSR_F;
849 offset = 4;
850 break;
851 default:
852 cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
853 return; /* Never happens. Keep compiler happy. */
854 }
855 /* High vectors. */
856 if (env->cp15.c1_sys & (1 << 13)) {
857 addr += 0xffff0000;
858 }
859 switch_mode (env, new_mode);
860 env->spsr = cpsr_read(env);
9ee6e8bb
PB		 861 /* Clear IT bits. */
862 env->condexec_bits = 0;
6d7e6326 863 /* Switch to the new mode, and switch to Arm mode. */
b5ff1b31 864 /* ??? Thumb interrupt handlers not implemented. */
6d7e6326 865 env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
b5ff1b31 866 env->uncached_cpsr |= mask;
6d7e6326 867 env->thumb = 0;
b5ff1b31
FB		 868 env->regs[14] = env->regs[15] + offset;
869 env->regs[15] = addr;
870 env->interrupt_request |= CPU_INTERRUPT_EXITTB;
871}
872
873/* Check section/page access permissions.
874 Returns the page protection flags, or zero if the access is not
875 permitted. */
876static inline int check_ap(CPUState *env, int ap, int domain, int access_type,
877 int is_user)
878{
9ee6e8bb
PB		 879 int prot_ro;
880
b5ff1b31
FB		 881 if (domain == 3)
882 return PAGE_READ | PAGE_WRITE;
883
9ee6e8bb
PB		 884 if (access_type == 1)
885 prot_ro = 0;
886 else
887 prot_ro = PAGE_READ;
888
b5ff1b31
FB		 889 switch (ap) {
890 case 0:
78600320 891 if (access_type == 1)
b5ff1b31
FB		 892 return 0;
893 switch ((env->cp15.c1_sys >> 8) & 3) {
894 case 1:
895 return is_user ? 0 : PAGE_READ;
896 case 2:
897 return PAGE_READ;
898 default:
899 return 0;
900 }
901 case 1:
902 return is_user ? 0 : PAGE_READ | PAGE_WRITE;
903 case 2:
904 if (is_user)
9ee6e8bb 905 return prot_ro;
b5ff1b31
FB		 906 else
907 return PAGE_READ | PAGE_WRITE;
908 case 3:
909 return PAGE_READ | PAGE_WRITE;
d4934d18 910 case 4: /* Reserved. */
9ee6e8bb
PB		 911 return 0;
912 case 5:
913 return is_user ? 0 : prot_ro;
914 case 6:
915 return prot_ro;
d4934d18
PB		 916 case 7:
917 if (!arm_feature (env, ARM_FEATURE_V7))
918 return 0;
919 return prot_ro;
b5ff1b31
FB		 920 default:
921 abort();
922 }
923}
924
b2fa1797
PB		 925static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
926{
927 uint32_t table;
928
929 if (address & env->cp15.c2_mask)
930 table = env->cp15.c2_base1 & 0xffffc000;
931 else
932 table = env->cp15.c2_base0 & env->cp15.c2_base_mask;
933
934 table |= (address >> 18) & 0x3ffc;
935 return table;
936}
937
9ee6e8bb
PB		 938static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
939 int is_user, uint32_t *phys_ptr, int *prot)
b5ff1b31
FB		 940{
941 int code;
942 uint32_t table;
943 uint32_t desc;
944 int type;
945 int ap;
946 int domain;
947 uint32_t phys_addr;
948
9ee6e8bb
PB		 949 /* Pagetable walk. */
950 /* Lookup l1 descriptor. */
b2fa1797 951 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 952 desc = ldl_phys(table);
953 type = (desc & 3);
954 domain = (env->cp15.c3 >> ((desc >> 4) & 0x1e)) & 3;
955 if (type == 0) {
601d70b9 956 /* Section translation fault. */
9ee6e8bb
PB		 957 code = 5;
958 goto do_fault;
959 }
960 if (domain == 0 || domain == 2) {
961 if (type == 2)
962 code = 9; /* Section domain fault. */
963 else
964 code = 11; /* Page domain fault. */
965 goto do_fault;
966 }
967 if (type == 2) {
968 /* 1Mb section. */
969 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
970 ap = (desc >> 10) & 3;
971 code = 13;
972 } else {
973 /* Lookup l2 entry. */
974 if (type == 1) {
975 /* Coarse pagetable. */
976 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
977 } else {
978 /* Fine pagetable. */
979 table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
980 }
981 desc = ldl_phys(table);
982 switch (desc & 3) {
983 case 0: /* Page translation fault. */
984 code = 7;
985 goto do_fault;
986 case 1: /* 64k page. */
987 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
988 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
ce819861 989 break;
9ee6e8bb
PB		 990 case 2: /* 4k page. */
991 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
992 ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
ce819861 993 break;
9ee6e8bb
PB		 994 case 3: /* 1k page. */
995 if (type == 1) {
996 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
997 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
998 } else {
999 /* Page translation fault. */
1000 code = 7;
1001 goto do_fault;
1002 }
1003 } else {
1004 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
1005 }
1006 ap = (desc >> 4) & 3;
ce819861
PB		 1007 break;
1008 default:
9ee6e8bb
PB		 1009 /* Never happens, but compiler isn't smart enough to tell. */
1010 abort();
ce819861 1011 }
9ee6e8bb
PB		 1012 code = 15;
1013 }
1014 *prot = check_ap(env, ap, domain, access_type, is_user);
1015 if (!*prot) {
1016 /* Access permission fault. */
1017 goto do_fault;
1018 }
1019 *phys_ptr = phys_addr;
1020 return 0;
1021do_fault:
1022 return code | (domain << 4);
1023}
1024
1025static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
1026 int is_user, uint32_t *phys_ptr, int *prot)
1027{
1028 int code;
1029 uint32_t table;
1030 uint32_t desc;
1031 uint32_t xn;
1032 int type;
1033 int ap;
1034 int domain;
1035 uint32_t phys_addr;
1036
1037 /* Pagetable walk. */
1038 /* Lookup l1 descriptor. */
b2fa1797 1039 table = get_level1_table_address(env, address);
9ee6e8bb
PB		 1040 desc = ldl_phys(table);
1041 type = (desc & 3);
1042 if (type == 0) {
601d70b9 1043 /* Section translation fault. */
9ee6e8bb
PB		 1044 code = 5;
1045 domain = 0;
1046 goto do_fault;
1047 } else if (type == 2 && (desc & (1 << 18))) {
1048 /* Supersection. */
1049 domain = 0;
b5ff1b31 1050 } else {
9ee6e8bb
PB		 1051 /* Section or page. */
1052 domain = (desc >> 4) & 0x1e;
1053 }
1054 domain = (env->cp15.c3 >> domain) & 3;
1055 if (domain == 0 || domain == 2) {
1056 if (type == 2)
1057 code = 9; /* Section domain fault. */
1058 else
1059 code = 11; /* Page domain fault. */
1060 goto do_fault;
1061 }
1062 if (type == 2) {
1063 if (desc & (1 << 18)) {
1064 /* Supersection. */
1065 phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
b5ff1b31 1066 } else {
9ee6e8bb
PB		 1067 /* Section. */
1068 phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
b5ff1b31 1069 }
9ee6e8bb
PB		 1070 ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
1071 xn = desc & (1 << 4);
1072 code = 13;
1073 } else {
1074 /* Lookup l2 entry. */
1075 table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
1076 desc = ldl_phys(table);
1077 ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
1078 switch (desc & 3) {
1079 case 0: /* Page translation fault. */
1080 code = 7;
b5ff1b31 1081 goto do_fault;
9ee6e8bb
PB		 1082 case 1: /* 64k page. */
1083 phys_addr = (desc & 0xffff0000) | (address & 0xffff);
1084 xn = desc & (1 << 15);
1085 break;
1086 case 2: case 3: /* 4k page. */
1087 phys_addr = (desc & 0xfffff000) | (address & 0xfff);
1088 xn = desc & 1;
1089 break;
1090 default:
1091 /* Never happens, but compiler isn't smart enough to tell. */
1092 abort();
b5ff1b31 1093 }
9ee6e8bb
PB		 1094 code = 15;
1095 }
1096 if (xn && access_type == 2)
1097 goto do_fault;
1098
d4934d18
PB		 1099 /* The simplified model uses AP[0] as an access control bit. */
1100 if ((env->cp15.c1_sys & (1 << 29)) && (ap & 1) == 0) {
1101 /* Access flag fault. */
1102 code = (code == 15) ? 6 : 3;
1103 goto do_fault;
1104 }
9ee6e8bb
PB		 1105 *prot = check_ap(env, ap, domain, access_type, is_user);
1106 if (!*prot) {
1107 /* Access permission fault. */
1108 goto do_fault;
b5ff1b31 1109 }
9ee6e8bb 1110 *phys_ptr = phys_addr;
b5ff1b31
FB		 1111 return 0;
1112do_fault:
1113 return code | (domain << 4);
1114}
1115
9ee6e8bb
PB		 1116static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
1117 int is_user, uint32_t *phys_ptr, int *prot)
1118{
1119 int n;
1120 uint32_t mask;
1121 uint32_t base;
1122
1123 *phys_ptr = address;
1124 for (n = 7; n >= 0; n--) {
1125 base = env->cp15.c6_region[n];
1126 if ((base & 1) == 0)
1127 continue;
1128 mask = 1 << ((base >> 1) & 0x1f);
1129 /* Keep this shift separate from the above to avoid an
1130 (undefined) << 32. */
1131 mask = (mask << 1) - 1;
1132 if (((base ^ address) & ~mask) == 0)
1133 break;
1134 }
1135 if (n < 0)
1136 return 2;
1137
1138 if (access_type == 2) {
1139 mask = env->cp15.c5_insn;
1140 } else {
1141 mask = env->cp15.c5_data;
1142 }
1143 mask = (mask >> (n * 4)) & 0xf;
1144 switch (mask) {
1145 case 0:
1146 return 1;
1147 case 1:
1148 if (is_user)
1149 return 1;
1150 *prot = PAGE_READ | PAGE_WRITE;
1151 break;
1152 case 2:
1153 *prot = PAGE_READ;
1154 if (!is_user)
1155 *prot |= PAGE_WRITE;
1156 break;
1157 case 3:
1158 *prot = PAGE_READ | PAGE_WRITE;
1159 break;
1160 case 5:
1161 if (is_user)
1162 return 1;
1163 *prot = PAGE_READ;
1164 break;
1165 case 6:
1166 *prot = PAGE_READ;
1167 break;
1168 default:
1169 /* Bad permission. */
1170 return 1;
1171 }
1172 return 0;
1173}
1174
1175static inline int get_phys_addr(CPUState *env, uint32_t address,
1176 int access_type, int is_user,
1177 uint32_t *phys_ptr, int *prot)
1178{
1179 /* Fast Context Switch Extension. */
1180 if (address < 0x02000000)
1181 address += env->cp15.c13_fcse;
1182
1183 if ((env->cp15.c1_sys & 1) == 0) {
1184 /* MMU/MPU disabled. */
1185 *phys_ptr = address;
1186 *prot = PAGE_READ | PAGE_WRITE;
1187 return 0;
1188 } else if (arm_feature(env, ARM_FEATURE_MPU)) {
1189 return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
1190 prot);
1191 } else if (env->cp15.c1_sys & (1 << 23)) {
1192 return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
1193 prot);
1194 } else {
1195 return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
1196 prot);
1197 }
1198}
1199
b5ff1b31 1200int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
6ebbf390 1201 int access_type, int mmu_idx, int is_softmmu)
b5ff1b31
FB		 1202{
1203 uint32_t phys_addr;
1204 int prot;
6ebbf390 1205 int ret, is_user;
b5ff1b31 1206
6ebbf390 1207 is_user = mmu_idx == MMU_USER_IDX;
b5ff1b31
FB		 1208 ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot);
1209 if (ret == 0) {
1210 /* Map a single [sub]page. */
1211 phys_addr &= ~(uint32_t)0x3ff;
1212 address &= ~(uint32_t)0x3ff;
6ebbf390 1213 return tlb_set_page (env, address, phys_addr, prot, mmu_idx,
b5ff1b31
FB		 1214 is_softmmu);
1215 }
1216
1217 if (access_type == 2) {
1218 env->cp15.c5_insn = ret;
1219 env->cp15.c6_insn = address;
1220 env->exception_index = EXCP_PREFETCH_ABORT;
1221 } else {
1222 env->cp15.c5_data = ret;
9ee6e8bb
PB		 1223 if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6))
1224 env->cp15.c5_data |= (1 << 11);
b5ff1b31
FB		 1225 env->cp15.c6_data = address;
1226 env->exception_index = EXCP_DATA_ABORT;
1227 }
1228 return 1;
1229}
1230
c227f099 1231target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
b5ff1b31
FB		 1232{
1233 uint32_t phys_addr;
1234 int prot;
1235 int ret;
1236
1237 ret = get_phys_addr(env, addr, 0, 0, &phys_addr, &prot);
1238
1239 if (ret != 0)
1240 return -1;
1241
1242 return phys_addr;
1243}
1244
9ee6e8bb
PB		 1245/* Not really implemented. Need to figure out a sane way of doing this.
1246 Maybe add generic watchpoint support and use that. */
1247
8f8e3aa4 1248void HELPER(mark_exclusive)(CPUState *env, uint32_t addr)
9ee6e8bb
PB		 1249{
1250 env->mmon_addr = addr;
1251}
1252
8f8e3aa4 1253uint32_t HELPER(test_exclusive)(CPUState *env, uint32_t addr)
9ee6e8bb
PB		 1254{
1255 return (env->mmon_addr != addr);
1256}
1257
8f8e3aa4 1258void HELPER(clrex)(CPUState *env)
9ee6e8bb
PB		 1259{
1260 env->mmon_addr = -1;
1261}
1262
8984bd2e 1263void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
c1713132
AZ		 1264{
1265 int cp_num = (insn >> 8) & 0xf;
1266 int cp_info = (insn >> 5) & 7;
1267 int src = (insn >> 16) & 0xf;
1268 int operand = insn & 0xf;
1269
1270 if (env->cp[cp_num].cp_write)
1271 env->cp[cp_num].cp_write(env->cp[cp_num].opaque,
1272 cp_info, src, operand, val);
1273}
1274
8984bd2e 1275uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
c1713132
AZ		 1276{
1277 int cp_num = (insn >> 8) & 0xf;
1278 int cp_info = (insn >> 5) & 7;
1279 int dest = (insn >> 16) & 0xf;
1280 int operand = insn & 0xf;
1281
1282 if (env->cp[cp_num].cp_read)
1283 return env->cp[cp_num].cp_read(env->cp[cp_num].opaque,
1284 cp_info, dest, operand);
1285 return 0;
1286}
1287
ce819861
PB		 1288/* Return basic MPU access permission bits. */
1289static uint32_t simple_mpu_ap_bits(uint32_t val)
1290{
1291 uint32_t ret;
1292 uint32_t mask;
1293 int i;
1294 ret = 0;
1295 mask = 3;
1296 for (i = 0; i < 16; i += 2) {
1297 ret |= (val >> i) & mask;
1298 mask <<= 2;
1299 }
1300 return ret;
1301}
1302
1303/* Pad basic MPU access permission bits to extended format. */
1304static uint32_t extended_mpu_ap_bits(uint32_t val)
1305{
1306 uint32_t ret;
1307 uint32_t mask;
1308 int i;
1309 ret = 0;
1310 mask = 3;
1311 for (i = 0; i < 16; i += 2) {
1312 ret |= (val & mask) << i;
1313 mask <<= 2;
1314 }
1315 return ret;
1316}
1317
8984bd2e 1318void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
b5ff1b31 1319{
9ee6e8bb
PB		 1320 int op1;
1321 int op2;
1322 int crm;
b5ff1b31 1323
9ee6e8bb 1324 op1 = (insn >> 21) & 7;
b5ff1b31 1325 op2 = (insn >> 5) & 7;
ce819861 1326 crm = insn & 0xf;
b5ff1b31 1327 switch ((insn >> 16) & 0xf) {
9ee6e8bb 1328 case 0:
9ee6e8bb 1329 /* ID codes. */
610c3c8a
AZ		 1330 if (arm_feature(env, ARM_FEATURE_XSCALE))
1331 break;
c3d2689d
AZ		 1332 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1333 break;
a49ea279
PB		 1334 if (arm_feature(env, ARM_FEATURE_V7)
1335 && op1 == 2 && crm == 0 && op2 == 0) {
1336 env->cp15.c0_cssel = val & 0xf;
1337 break;
1338 }
b5ff1b31
FB		 1339 goto bad_reg;
1340 case 1: /* System configuration. */
c3d2689d
AZ		 1341 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1342 op2 = 0;
b5ff1b31
FB		 1343 switch (op2) {
1344 case 0:
ce819861 1345 if (!arm_feature(env, ARM_FEATURE_XSCALE) || crm == 0)
c1713132 1346 env->cp15.c1_sys = val;
b5ff1b31
FB		 1347 /* ??? Lots of these bits are not implemented. */
1348 /* This may enable/disable the MMU, so do a TLB flush. */
1349 tlb_flush(env, 1);
1350 break;
9ee6e8bb 1351 case 1: /* Auxiliary cotrol register. */
610c3c8a
AZ		 1352 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
1353 env->cp15.c1_xscaleauxcr = val;
c1713132 1354 break;
610c3c8a 1355 }
9ee6e8bb
PB		 1356 /* Not implemented. */
1357 break;
b5ff1b31 1358 case 2:
610c3c8a
AZ		 1359 if (arm_feature(env, ARM_FEATURE_XSCALE))
1360 goto bad_reg;
4be27dbb
PB		 1361 if (env->cp15.c1_coproc != val) {
1362 env->cp15.c1_coproc = val;
1363 /* ??? Is this safe when called from within a TB? */
1364 tb_flush(env);
1365 }
c1713132 1366 break;
b5ff1b31
FB		 1367 default:
1368 goto bad_reg;
1369 }
1370 break;
ce819861
PB		 1371 case 2: /* MMU Page table control / MPU cache control. */
1372 if (arm_feature(env, ARM_FEATURE_MPU)) {
1373 switch (op2) {
1374 case 0:
1375 env->cp15.c2_data = val;
1376 break;
1377 case 1:
1378 env->cp15.c2_insn = val;
1379 break;
1380 default:
1381 goto bad_reg;
1382 }
1383 } else {
9ee6e8bb
PB		 1384 switch (op2) {
1385 case 0:
1386 env->cp15.c2_base0 = val;
1387 break;
1388 case 1:
1389 env->cp15.c2_base1 = val;
1390 break;
1391 case 2:
b2fa1797
PB		 1392 val &= 7;
1393 env->cp15.c2_control = val;
9ee6e8bb 1394 env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> val);
b2fa1797 1395 env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> val);
9ee6e8bb
PB		 1396 break;
1397 default:
1398 goto bad_reg;
1399 }
ce819861 1400 }
b5ff1b31 1401 break;
ce819861 1402 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31 1403 env->cp15.c3 = val;
405ee3ad 1404 tlb_flush(env, 1); /* Flush TLB as domain not tracked in TLB */
b5ff1b31
FB		 1405 break;
1406 case 4: /* Reserved. */
1407 goto bad_reg;
ce819861 1408 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1409 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1410 op2 = 0;
b5ff1b31
FB		 1411 switch (op2) {
1412 case 0:
ce819861
PB		 1413 if (arm_feature(env, ARM_FEATURE_MPU))
1414 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1415 env->cp15.c5_data = val;
1416 break;
1417 case 1:
ce819861
PB		 1418 if (arm_feature(env, ARM_FEATURE_MPU))
1419 val = extended_mpu_ap_bits(val);
b5ff1b31
FB		 1420 env->cp15.c5_insn = val;
1421 break;
ce819861
PB		 1422 case 2:
1423 if (!arm_feature(env, ARM_FEATURE_MPU))
1424 goto bad_reg;
1425 env->cp15.c5_data = val;
b5ff1b31 1426 break;
ce819861
PB		 1427 case 3:
1428 if (!arm_feature(env, ARM_FEATURE_MPU))
1429 goto bad_reg;
1430 env->cp15.c5_insn = val;
b5ff1b31
FB		 1431 break;
1432 default:
1433 goto bad_reg;
1434 }
1435 break;
ce819861
PB		 1436 case 6: /* MMU Fault address / MPU base/size. */
1437 if (arm_feature(env, ARM_FEATURE_MPU)) {
1438 if (crm >= 8)
1439 goto bad_reg;
1440 env->cp15.c6_region[crm] = val;
1441 } else {
c3d2689d
AZ		 1442 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1443 op2 = 0;
ce819861
PB		 1444 switch (op2) {
1445 case 0:
1446 env->cp15.c6_data = val;
1447 break;
9ee6e8bb
PB		 1448 case 1: /* ??? This is WFAR on armv6 */
1449 case 2:
ce819861
PB		 1450 env->cp15.c6_insn = val;
1451 break;
1452 default:
1453 goto bad_reg;
1454 }
1455 }
1456 break;
b5ff1b31 1457 case 7: /* Cache control. */
c3d2689d
AZ		 1458 env->cp15.c15_i_max = 0x000;
1459 env->cp15.c15_i_min = 0xff0;
b5ff1b31 1460 /* No cache, so nothing to do. */
9ee6e8bb 1461 /* ??? MPCore has VA to PA translation functions. */
b5ff1b31
FB		 1462 break;
1463 case 8: /* MMU TLB control. */
1464 switch (op2) {
1465 case 0: /* Invalidate all. */
1466 tlb_flush(env, 0);
1467 break;
1468 case 1: /* Invalidate single TLB entry. */
1469#if 0
1470 /* ??? This is wrong for large pages and sections. */
1471 /* As an ugly hack to make linux work we always flush a 4K
1472 pages. */
1473 val &= 0xfffff000;
1474 tlb_flush_page(env, val);
1475 tlb_flush_page(env, val + 0x400);
1476 tlb_flush_page(env, val + 0x800);
1477 tlb_flush_page(env, val + 0xc00);
1478#else
1479 tlb_flush(env, 1);
1480#endif
1481 break;
9ee6e8bb
PB		 1482 case 2: /* Invalidate on ASID. */
1483 tlb_flush(env, val == 0);
1484 break;
1485 case 3: /* Invalidate single entry on MVA. */
1486 /* ??? This is like case 1, but ignores ASID. */
1487 tlb_flush(env, 1);
1488 break;
b5ff1b31
FB		 1489 default:
1490 goto bad_reg;
1491 }
1492 break;
ce819861 1493 case 9:
c3d2689d
AZ		 1494 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1495 break;
ce819861
PB		 1496 switch (crm) {
1497 case 0: /* Cache lockdown. */
9ee6e8bb
PB		 1498 switch (op1) {
1499 case 0: /* L1 cache. */
1500 switch (op2) {
1501 case 0:
1502 env->cp15.c9_data = val;
1503 break;
1504 case 1:
1505 env->cp15.c9_insn = val;
1506 break;
1507 default:
1508 goto bad_reg;
1509 }
1510 break;
1511 case 1: /* L2 cache. */
1512 /* Ignore writes to L2 lockdown/auxiliary registers. */
1513 break;
1514 default:
1515 goto bad_reg;
1516 }
1517 break;
ce819861
PB		 1518 case 1: /* TCM memory region registers. */
1519 /* Not implemented. */
1520 goto bad_reg;
b5ff1b31
FB		 1521 default:
1522 goto bad_reg;
1523 }
1524 break;
1525 case 10: /* MMU TLB lockdown. */
1526 /* ??? TLB lockdown not implemented. */
1527 break;
b5ff1b31
FB		 1528 case 12: /* Reserved. */
1529 goto bad_reg;
1530 case 13: /* Process ID. */
1531 switch (op2) {
1532 case 0:
d07edbfa
PB		 1533 /* Unlike real hardware the qemu TLB uses virtual addresses,
1534 not modified virtual addresses, so this causes a TLB flush.
1535 */
1536 if (env->cp15.c13_fcse != val)
1537 tlb_flush(env, 1);
1538 env->cp15.c13_fcse = val;
b5ff1b31
FB		 1539 break;
1540 case 1:
d07edbfa 1541 /* This changes the ASID, so do a TLB flush. */
ce819861
PB		 1542 if (env->cp15.c13_context != val
1543 && !arm_feature(env, ARM_FEATURE_MPU))
d07edbfa
PB		 1544 tlb_flush(env, 0);
1545 env->cp15.c13_context = val;
b5ff1b31 1546 break;
9ee6e8bb
PB		 1547 case 2:
1548 env->cp15.c13_tls1 = val;
1549 break;
1550 case 3:
1551 env->cp15.c13_tls2 = val;
1552 break;
1553 case 4:
1554 env->cp15.c13_tls3 = val;
1555 break;
b5ff1b31
FB		 1556 default:
1557 goto bad_reg;
1558 }
1559 break;
1560 case 14: /* Reserved. */
1561 goto bad_reg;
1562 case 15: /* Implementation specific. */
c1713132 1563 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
ce819861 1564 if (op2 == 0 && crm == 1) {
2e23213f
AZ		 1565 if (env->cp15.c15_cpar != (val & 0x3fff)) {
1566 /* Changes cp0 to cp13 behavior, so needs a TB flush. */
1567 tb_flush(env);
1568 env->cp15.c15_cpar = val & 0x3fff;
1569 }
c1713132
AZ		 1570 break;
1571 }
1572 goto bad_reg;
1573 }
c3d2689d
AZ		 1574 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1575 switch (crm) {
1576 case 0:
1577 break;
1578 case 1: /* Set TI925T configuration. */
1579 env->cp15.c15_ticonfig = val & 0xe7;
1580 env->cp15.c0_cpuid = (val & (1 << 5)) ? /* OS_TYPE bit */
1581 ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1582 break;
1583 case 2: /* Set I_max. */
1584 env->cp15.c15_i_max = val;
1585 break;
1586 case 3: /* Set I_min. */
1587 env->cp15.c15_i_min = val;
1588 break;
1589 case 4: /* Set thread-ID. */
1590 env->cp15.c15_threadid = val & 0xffff;
1591 break;
1592 case 8: /* Wait-for-interrupt (deprecated). */
1593 cpu_interrupt(env, CPU_INTERRUPT_HALT);
1594 break;
1595 default:
1596 goto bad_reg;
1597 }
1598 }
b5ff1b31
FB		 1599 break;
1600 }
1601 return;
1602bad_reg:
1603 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1604 cpu_abort(env, "Unimplemented cp15 register write (c%d, c%d, {%d, %d})\n",
1605 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1606}
1607
8984bd2e 1608uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
b5ff1b31 1609{
9ee6e8bb
PB		 1610 int op1;
1611 int op2;
1612 int crm;
b5ff1b31 1613
9ee6e8bb 1614 op1 = (insn >> 21) & 7;
b5ff1b31 1615 op2 = (insn >> 5) & 7;
c3d2689d 1616 crm = insn & 0xf;
b5ff1b31
FB		 1617 switch ((insn >> 16) & 0xf) {
1618 case 0: /* ID codes. */
9ee6e8bb
PB		 1619 switch (op1) {
1620 case 0:
1621 switch (crm) {
1622 case 0:
1623 switch (op2) {
1624 case 0: /* Device ID. */
1625 return env->cp15.c0_cpuid;
1626 case 1: /* Cache Type. */
1627 return env->cp15.c0_cachetype;
1628 case 2: /* TCM status. */
1629 return 0;
1630 case 3: /* TLB type register. */
1631 return 0; /* No lockable TLB entries. */
1632 case 5: /* CPU ID */
1633 return env->cpu_index;
1634 default:
1635 goto bad_reg;
1636 }
1637 case 1:
1638 if (!arm_feature(env, ARM_FEATURE_V6))
1639 goto bad_reg;
1640 return env->cp15.c0_c1[op2];
1641 case 2:
1642 if (!arm_feature(env, ARM_FEATURE_V6))
1643 goto bad_reg;
1644 return env->cp15.c0_c2[op2];
1645 case 3: case 4: case 5: case 6: case 7:
1646 return 0;
1647 default:
1648 goto bad_reg;
1649 }
1650 case 1:
1651 /* These registers aren't documented on arm11 cores. However
1652 Linux looks at them anyway. */
1653 if (!arm_feature(env, ARM_FEATURE_V6))
1654 goto bad_reg;
1655 if (crm != 0)
1656 goto bad_reg;
a49ea279
PB		 1657 if (!arm_feature(env, ARM_FEATURE_V7))
1658 return 0;
1659
1660 switch (op2) {
1661 case 0:
1662 return env->cp15.c0_ccsid[env->cp15.c0_cssel];
1663 case 1:
1664 return env->cp15.c0_clid;
1665 case 7:
1666 return 0;
1667 }
1668 goto bad_reg;
1669 case 2:
1670 if (op2 != 0 || crm != 0)
610c3c8a 1671 goto bad_reg;
a49ea279 1672 return env->cp15.c0_cssel;
9ee6e8bb
PB		 1673 default:
1674 goto bad_reg;
b5ff1b31
FB		 1675 }
1676 case 1: /* System configuration. */
c3d2689d
AZ		 1677 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1678 op2 = 0;
b5ff1b31
FB		 1679 switch (op2) {
1680 case 0: /* Control register. */
1681 return env->cp15.c1_sys;
1682 case 1: /* Auxiliary control register. */
c1713132 1683 if (arm_feature(env, ARM_FEATURE_XSCALE))
610c3c8a 1684 return env->cp15.c1_xscaleauxcr;
9ee6e8bb
PB		 1685 if (!arm_feature(env, ARM_FEATURE_AUXCR))
1686 goto bad_reg;
1687 switch (ARM_CPUID(env)) {
1688 case ARM_CPUID_ARM1026:
1689 return 1;
1690 case ARM_CPUID_ARM1136:
827df9f3 1691 case ARM_CPUID_ARM1136_R2:
9ee6e8bb
PB		 1692 return 7;
1693 case ARM_CPUID_ARM11MPCORE:
1694 return 1;
1695 case ARM_CPUID_CORTEXA8:
533d177a 1696 return 2;
9ee6e8bb
PB		 1697 default:
1698 goto bad_reg;
1699 }
b5ff1b31 1700 case 2: /* Coprocessor access register. */
610c3c8a
AZ		 1701 if (arm_feature(env, ARM_FEATURE_XSCALE))
1702 goto bad_reg;
b5ff1b31
FB		 1703 return env->cp15.c1_coproc;
1704 default:
1705 goto bad_reg;
1706 }
ce819861
PB		 1707 case 2: /* MMU Page table control / MPU cache control. */
1708 if (arm_feature(env, ARM_FEATURE_MPU)) {
1709 switch (op2) {
1710 case 0:
1711 return env->cp15.c2_data;
1712 break;
1713 case 1:
1714 return env->cp15.c2_insn;
1715 break;
1716 default:
1717 goto bad_reg;
1718 }
1719 } else {
9ee6e8bb
PB		 1720 switch (op2) {
1721 case 0:
1722 return env->cp15.c2_base0;
1723 case 1:
1724 return env->cp15.c2_base1;
1725 case 2:
b2fa1797 1726 return env->cp15.c2_control;
9ee6e8bb
PB		 1727 default:
1728 goto bad_reg;
1729 }
1730 }
ce819861 1731 case 3: /* MMU Domain access control / MPU write buffer control. */
b5ff1b31
FB		 1732 return env->cp15.c3;
1733 case 4: /* Reserved. */
1734 goto bad_reg;
ce819861 1735 case 5: /* MMU Fault status / MPU access permission. */
c3d2689d
AZ		 1736 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1737 op2 = 0;
b5ff1b31
FB		 1738 switch (op2) {
1739 case 0:
ce819861
PB		 1740 if (arm_feature(env, ARM_FEATURE_MPU))
1741 return simple_mpu_ap_bits(env->cp15.c5_data);
b5ff1b31
FB		 1742 return env->cp15.c5_data;
1743 case 1:
ce819861
PB		 1744 if (arm_feature(env, ARM_FEATURE_MPU))
1745 return simple_mpu_ap_bits(env->cp15.c5_data);
1746 return env->cp15.c5_insn;
1747 case 2:
1748 if (!arm_feature(env, ARM_FEATURE_MPU))
1749 goto bad_reg;
1750 return env->cp15.c5_data;
1751 case 3:
1752 if (!arm_feature(env, ARM_FEATURE_MPU))
1753 goto bad_reg;
b5ff1b31
FB		 1754 return env->cp15.c5_insn;
1755 default:
1756 goto bad_reg;
1757 }
9ee6e8bb 1758 case 6: /* MMU Fault address. */
ce819861 1759 if (arm_feature(env, ARM_FEATURE_MPU)) {
9ee6e8bb 1760 if (crm >= 8)
ce819861 1761 goto bad_reg;
9ee6e8bb 1762 return env->cp15.c6_region[crm];
ce819861 1763 } else {
c3d2689d
AZ		 1764 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1765 op2 = 0;
9ee6e8bb
PB		 1766 switch (op2) {
1767 case 0:
1768 return env->cp15.c6_data;
1769 case 1:
1770 if (arm_feature(env, ARM_FEATURE_V6)) {
1771 /* Watchpoint Fault Adrress. */
1772 return 0; /* Not implemented. */
1773 } else {
1774 /* Instruction Fault Adrress. */
1775 /* Arm9 doesn't have an IFAR, but implementing it anyway
1776 shouldn't do any harm. */
1777 return env->cp15.c6_insn;
1778 }
1779 case 2:
1780 if (arm_feature(env, ARM_FEATURE_V6)) {
1781 /* Instruction Fault Adrress. */
1782 return env->cp15.c6_insn;
1783 } else {
1784 goto bad_reg;
1785 }
1786 default:
1787 goto bad_reg;
1788 }
b5ff1b31
FB		 1789 }
1790 case 7: /* Cache control. */
6fbe23d5
PB		 1791 /* FIXME: Should only clear Z flag if destination is r15. */
1792 env->ZF = 0;
b5ff1b31
FB		 1793 return 0;
1794 case 8: /* MMU TLB control. */
1795 goto bad_reg;
1796 case 9: /* Cache lockdown. */
9ee6e8bb
PB		 1797 switch (op1) {
1798 case 0: /* L1 cache. */
1799 if (arm_feature(env, ARM_FEATURE_OMAPCP))
1800 return 0;
1801 switch (op2) {
1802 case 0:
1803 return env->cp15.c9_data;
1804 case 1:
1805 return env->cp15.c9_insn;
1806 default:
1807 goto bad_reg;
1808 }
1809 case 1: /* L2 cache */
1810 if (crm != 0)
1811 goto bad_reg;
1812 /* L2 Lockdown and Auxiliary control. */
c3d2689d 1813 return 0;
b5ff1b31
FB		 1814 default:
1815 goto bad_reg;
1816 }
1817 case 10: /* MMU TLB lockdown. */
1818 /* ??? TLB lockdown not implemented. */
1819 return 0;
1820 case 11: /* TCM DMA control. */
1821 case 12: /* Reserved. */
1822 goto bad_reg;
1823 case 13: /* Process ID. */
1824 switch (op2) {
1825 case 0:
1826 return env->cp15.c13_fcse;
1827 case 1:
1828 return env->cp15.c13_context;
9ee6e8bb
PB		 1829 case 2:
1830 return env->cp15.c13_tls1;
1831 case 3:
1832 return env->cp15.c13_tls2;
1833 case 4:
1834 return env->cp15.c13_tls3;
b5ff1b31
FB		 1835 default:
1836 goto bad_reg;
1837 }
1838 case 14: /* Reserved. */
1839 goto bad_reg;
1840 case 15: /* Implementation specific. */
c1713132 1841 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
c3d2689d 1842 if (op2 == 0 && crm == 1)
c1713132
AZ		 1843 return env->cp15.c15_cpar;
1844
1845 goto bad_reg;
1846 }
c3d2689d
AZ		 1847 if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
1848 switch (crm) {
1849 case 0:
1850 return 0;
1851 case 1: /* Read TI925T configuration. */
1852 return env->cp15.c15_ticonfig;
1853 case 2: /* Read I_max. */
1854 return env->cp15.c15_i_max;
1855 case 3: /* Read I_min. */
1856 return env->cp15.c15_i_min;
1857 case 4: /* Read thread-ID. */
1858 return env->cp15.c15_threadid;
1859 case 8: /* TI925T_status */
1860 return 0;
1861 }
827df9f3
AZ		 1862 /* TODO: Peripheral port remap register:
1863 * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt
1864 * controller base address at $rn & ~0xfff and map size of
1865 * 0x200 << ($rn & 0xfff), when MMU is off. */
c3d2689d
AZ		 1866 goto bad_reg;
1867 }
b5ff1b31
FB		 1868 return 0;
1869 }
1870bad_reg:
1871 /* ??? For debugging only. Should raise illegal instruction exception. */
9ee6e8bb
PB		 1872 cpu_abort(env, "Unimplemented cp15 register read (c%d, c%d, {%d, %d})\n",
1873 (insn >> 16) & 0xf, crm, op1, op2);
b5ff1b31
FB		 1874 return 0;
1875}
1876
b0109805 1877void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
9ee6e8bb
PB		 1878{
1879 env->banked_r13[bank_number(mode)] = val;
1880}
1881
b0109805 1882uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
9ee6e8bb
PB		 1883{
1884 return env->banked_r13[bank_number(mode)];
1885}
1886
8984bd2e 1887uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
9ee6e8bb
PB		 1888{
1889 switch (reg) {
1890 case 0: /* APSR */
1891 return xpsr_read(env) & 0xf8000000;
1892 case 1: /* IAPSR */
1893 return xpsr_read(env) & 0xf80001ff;
1894 case 2: /* EAPSR */
1895 return xpsr_read(env) & 0xff00fc00;
1896 case 3: /* xPSR */
1897 return xpsr_read(env) & 0xff00fdff;
1898 case 5: /* IPSR */
1899 return xpsr_read(env) & 0x000001ff;
1900 case 6: /* EPSR */
1901 return xpsr_read(env) & 0x0700fc00;
1902 case 7: /* IEPSR */
1903 return xpsr_read(env) & 0x0700edff;
1904 case 8: /* MSP */
1905 return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
1906 case 9: /* PSP */
1907 return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
1908 case 16: /* PRIMASK */
1909 return (env->uncached_cpsr & CPSR_I) != 0;
1910 case 17: /* FAULTMASK */
1911 return (env->uncached_cpsr & CPSR_F) != 0;
1912 case 18: /* BASEPRI */
1913 case 19: /* BASEPRI_MAX */
1914 return env->v7m.basepri;
1915 case 20: /* CONTROL */
1916 return env->v7m.control;
1917 default:
1918 /* ??? For debugging only. */
1919 cpu_abort(env, "Unimplemented system register read (%d)\n", reg);
1920 return 0;
1921 }
1922}
1923
8984bd2e 1924void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
9ee6e8bb
PB		 1925{
1926 switch (reg) {
1927 case 0: /* APSR */
1928 xpsr_write(env, val, 0xf8000000);
1929 break;
1930 case 1: /* IAPSR */
1931 xpsr_write(env, val, 0xf8000000);
1932 break;
1933 case 2: /* EAPSR */
1934 xpsr_write(env, val, 0xfe00fc00);
1935 break;
1936 case 3: /* xPSR */
1937 xpsr_write(env, val, 0xfe00fc00);
1938 break;
1939 case 5: /* IPSR */
1940 /* IPSR bits are readonly. */
1941 break;
1942 case 6: /* EPSR */
1943 xpsr_write(env, val, 0x0600fc00);
1944 break;
1945 case 7: /* IEPSR */
1946 xpsr_write(env, val, 0x0600fc00);
1947 break;
1948 case 8: /* MSP */
1949 if (env->v7m.current_sp)
1950 env->v7m.other_sp = val;
1951 else
1952 env->regs[13] = val;
1953 break;
1954 case 9: /* PSP */
1955 if (env->v7m.current_sp)
1956 env->regs[13] = val;
1957 else
1958 env->v7m.other_sp = val;
1959 break;
1960 case 16: /* PRIMASK */
1961 if (val & 1)
1962 env->uncached_cpsr |= CPSR_I;
1963 else
1964 env->uncached_cpsr &= ~CPSR_I;
1965 break;
1966 case 17: /* FAULTMASK */
1967 if (val & 1)
1968 env->uncached_cpsr |= CPSR_F;
1969 else
1970 env->uncached_cpsr &= ~CPSR_F;
1971 break;
1972 case 18: /* BASEPRI */
1973 env->v7m.basepri = val & 0xff;
1974 break;
1975 case 19: /* BASEPRI_MAX */
1976 val &= 0xff;
1977 if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
1978 env->v7m.basepri = val;
1979 break;
1980 case 20: /* CONTROL */
1981 env->v7m.control = val & 3;
1982 switch_v7m_sp(env, (val & 2) != 0);
1983 break;
1984 default:
1985 /* ??? For debugging only. */
1986 cpu_abort(env, "Unimplemented system register write (%d)\n", reg);
1987 return;
1988 }
1989}
1990
c1713132
AZ		 1991void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
1992 ARMReadCPFunc *cp_read, ARMWriteCPFunc *cp_write,
1993 void *opaque)
1994{
1995 if (cpnum < 0 || cpnum > 14) {
1996 cpu_abort(env, "Bad coprocessor number: %i\n", cpnum);
1997 return;
1998 }
1999
2000 env->cp[cpnum].cp_read = cp_read;
2001 env->cp[cpnum].cp_write = cp_write;
2002 env->cp[cpnum].opaque = opaque;
2003}
2004
b5ff1b31 2005#endif
6ddbc6e4
PB		 2006
2007/* Note that signed overflow is undefined in C. The following routines are
2008 careful to use unsigned types where modulo arithmetic is required.
2009 Failure to do so _will_ break on newer gcc. */
2010
2011/* Signed saturating arithmetic. */
2012
1654b2d6 2013/* Perform 16-bit signed saturating addition. */
6ddbc6e4
PB		 2014static inline uint16_t add16_sat(uint16_t a, uint16_t b)
2015{
2016 uint16_t res;
2017
2018 res = a + b;
2019 if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
2020 if (a & 0x8000)
2021 res = 0x8000;
2022 else
2023 res = 0x7fff;
2024 }
2025 return res;
2026}
2027
1654b2d6 2028/* Perform 8-bit signed saturating addition. */
6ddbc6e4
PB		 2029static inline uint8_t add8_sat(uint8_t a, uint8_t b)
2030{
2031 uint8_t res;
2032
2033 res = a + b;
2034 if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
2035 if (a & 0x80)
2036 res = 0x80;
2037 else
2038 res = 0x7f;
2039 }
2040 return res;
2041}
2042
1654b2d6 2043/* Perform 16-bit signed saturating subtraction. */
6ddbc6e4
PB		 2044static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
2045{
2046 uint16_t res;
2047
2048 res = a - b;
2049 if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
2050 if (a & 0x8000)
2051 res = 0x8000;
2052 else
2053 res = 0x7fff;
2054 }
2055 return res;
2056}
2057
1654b2d6 2058/* Perform 8-bit signed saturating subtraction. */
6ddbc6e4
PB		 2059static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
2060{
2061 uint8_t res;
2062
2063 res = a - b;
2064 if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
2065 if (a & 0x80)
2066 res = 0x80;
2067 else
2068 res = 0x7f;
2069 }
2070 return res;
2071}
2072
2073#define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
2074#define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
2075#define ADD8(a, b, n) RESULT(add8_sat(a, b), n, 8);
2076#define SUB8(a, b, n) RESULT(sub8_sat(a, b), n, 8);
2077#define PFX q
2078
2079#include "op_addsub.h"
2080
2081/* Unsigned saturating arithmetic. */
460a09c1 2082static inline uint16_t add16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2083{
2084 uint16_t res;
2085 res = a + b;
2086 if (res < a)
2087 res = 0xffff;
2088 return res;
2089}
2090
460a09c1 2091static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
6ddbc6e4
PB		 2092{
2093 if (a < b)
2094 return a - b;
2095 else
2096 return 0;
2097}
2098
2099static inline uint8_t add8_usat(uint8_t a, uint8_t b)
2100{
2101 uint8_t res;
2102 res = a + b;
2103 if (res < a)
2104 res = 0xff;
2105 return res;
2106}
2107
2108static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
2109{
2110 if (a < b)
2111 return a - b;
2112 else
2113 return 0;
2114}
2115
2116#define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
2117#define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
2118#define ADD8(a, b, n) RESULT(add8_usat(a, b), n, 8);
2119#define SUB8(a, b, n) RESULT(sub8_usat(a, b), n, 8);
2120#define PFX uq
2121
2122#include "op_addsub.h"
2123
2124/* Signed modulo arithmetic. */
2125#define SARITH16(a, b, n, op) do { \
2126 int32_t sum; \
2127 sum = (int16_t)((uint16_t)(a) op (uint16_t)(b)); \
2128 RESULT(sum, n, 16); \
2129 if (sum >= 0) \
2130 ge |= 3 << (n * 2); \
2131 } while(0)
2132
2133#define SARITH8(a, b, n, op) do { \
2134 int32_t sum; \
2135 sum = (int8_t)((uint8_t)(a) op (uint8_t)(b)); \
2136 RESULT(sum, n, 8); \
2137 if (sum >= 0) \
2138 ge |= 1 << n; \
2139 } while(0)
2140
2141
2142#define ADD16(a, b, n) SARITH16(a, b, n, +)
2143#define SUB16(a, b, n) SARITH16(a, b, n, -)
2144#define ADD8(a, b, n) SARITH8(a, b, n, +)
2145#define SUB8(a, b, n) SARITH8(a, b, n, -)
2146#define PFX s
2147#define ARITH_GE
2148
2149#include "op_addsub.h"
2150
2151/* Unsigned modulo arithmetic. */
2152#define ADD16(a, b, n) do { \
2153 uint32_t sum; \
2154 sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
2155 RESULT(sum, n, 16); \
a87aa10b 2156 if ((sum >> 16) == 1) \
6ddbc6e4
PB		 2157 ge |= 3 << (n * 2); \
2158 } while(0)
2159
2160#define ADD8(a, b, n) do { \
2161 uint32_t sum; \
2162 sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
2163 RESULT(sum, n, 8); \
a87aa10b
AZ		 2164 if ((sum >> 8) == 1) \
2165 ge |= 1 << n; \
6ddbc6e4
PB		 2166 } while(0)
2167
2168#define SUB16(a, b, n) do { \
2169 uint32_t sum; \
2170 sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
2171 RESULT(sum, n, 16); \
2172 if ((sum >> 16) == 0) \
2173 ge |= 3 << (n * 2); \
2174 } while(0)
2175
2176#define SUB8(a, b, n) do { \
2177 uint32_t sum; \
2178 sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
2179 RESULT(sum, n, 8); \
2180 if ((sum >> 8) == 0) \
a87aa10b 2181 ge |= 1 << n; \
6ddbc6e4
PB		 2182 } while(0)
2183
2184#define PFX u
2185#define ARITH_GE
2186
2187#include "op_addsub.h"
2188
2189/* Halved signed arithmetic. */
2190#define ADD16(a, b, n) \
2191 RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
2192#define SUB16(a, b, n) \
2193 RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
2194#define ADD8(a, b, n) \
2195 RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
2196#define SUB8(a, b, n) \
2197 RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
2198#define PFX sh
2199
2200#include "op_addsub.h"
2201
2202/* Halved unsigned arithmetic. */
2203#define ADD16(a, b, n) \
2204 RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2205#define SUB16(a, b, n) \
2206 RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
2207#define ADD8(a, b, n) \
2208 RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2209#define SUB8(a, b, n) \
2210 RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
2211#define PFX uh
2212
2213#include "op_addsub.h"
2214
2215static inline uint8_t do_usad(uint8_t a, uint8_t b)
2216{
2217 if (a > b)
2218 return a - b;
2219 else
2220 return b - a;
2221}
2222
2223/* Unsigned sum of absolute byte differences. */
2224uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
2225{
2226 uint32_t sum;
2227 sum = do_usad(a, b);
2228 sum += do_usad(a >> 8, b >> 8);
2229 sum += do_usad(a >> 16, b >>16);
2230 sum += do_usad(a >> 24, b >> 24);
2231 return sum;
2232}
2233
2234/* For ARMv6 SEL instruction. */
2235uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
2236{
2237 uint32_t mask;
2238
2239 mask = 0;
2240 if (flags & 1)
2241 mask |= 0xff;
2242 if (flags & 2)
2243 mask |= 0xff00;
2244 if (flags & 4)
2245 mask |= 0xff0000;
2246 if (flags & 8)
2247 mask |= 0xff000000;
2248 return (a & mask) | (b & ~mask);
2249}
2250
5e3f878a
PB		 2251uint32_t HELPER(logicq_cc)(uint64_t val)
2252{
2253 return (val >> 32) | (val != 0);
2254}
4373f3ce
PB		 2255
2256/* VFP support. We follow the convention used for VFP instrunctions:
2257 Single precition routines have a "s" suffix, double precision a
2258 "d" suffix. */
2259
2260/* Convert host exception flags to vfp form. */
2261static inline int vfp_exceptbits_from_host(int host_bits)
2262{
2263 int target_bits = 0;
2264
2265 if (host_bits & float_flag_invalid)
2266 target_bits |= 1;
2267 if (host_bits & float_flag_divbyzero)
2268 target_bits |= 2;
2269 if (host_bits & float_flag_overflow)
2270 target_bits |= 4;
2271 if (host_bits & float_flag_underflow)
2272 target_bits |= 8;
2273 if (host_bits & float_flag_inexact)
2274 target_bits |= 0x10;
2275 return target_bits;
2276}
2277
2278uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
2279{
2280 int i;
2281 uint32_t fpscr;
2282
2283 fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
2284 | (env->vfp.vec_len << 16)
2285 | (env->vfp.vec_stride << 20);
2286 i = get_float_exception_flags(&env->vfp.fp_status);
2287 fpscr |= vfp_exceptbits_from_host(i);
2288 return fpscr;
2289}
2290
2291/* Convert vfp exception flags to target form. */
2292static inline int vfp_exceptbits_to_host(int target_bits)
2293{
2294 int host_bits = 0;
2295
2296 if (target_bits & 1)
2297 host_bits |= float_flag_invalid;
2298 if (target_bits & 2)
2299 host_bits |= float_flag_divbyzero;
2300 if (target_bits & 4)
2301 host_bits |= float_flag_overflow;
2302 if (target_bits & 8)
2303 host_bits |= float_flag_underflow;
2304 if (target_bits & 0x10)
2305 host_bits |= float_flag_inexact;
2306 return host_bits;
2307}
2308
2309void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
2310{
2311 int i;
2312 uint32_t changed;
2313
2314 changed = env->vfp.xregs[ARM_VFP_FPSCR];
2315 env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
2316 env->vfp.vec_len = (val >> 16) & 7;
2317 env->vfp.vec_stride = (val >> 20) & 3;
2318
2319 changed ^= val;
2320 if (changed & (3 << 22)) {
2321 i = (val >> 22) & 3;
2322 switch (i) {
2323 case 0:
2324 i = float_round_nearest_even;
2325 break;
2326 case 1:
2327 i = float_round_up;
2328 break;
2329 case 2:
2330 i = float_round_down;
2331 break;
2332 case 3:
2333 i = float_round_to_zero;
2334 break;
2335 }
2336 set_float_rounding_mode(i, &env->vfp.fp_status);
2337 }
fe76d976
PB		 2338 if (changed & (1 << 24))
2339 set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
5c7908ed
PB		 2340 if (changed & (1 << 25))
2341 set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4373f3ce
PB		 2342
2343 i = vfp_exceptbits_to_host((val >> 8) & 0x1f);
2344 set_float_exception_flags(i, &env->vfp.fp_status);
4373f3ce
PB		 2345}
2346
2347#define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
2348
2349#define VFP_BINOP(name) \
2350float32 VFP_HELPER(name, s)(float32 a, float32 b, CPUState *env) \
2351{ \
2352 return float32_ ## name (a, b, &env->vfp.fp_status); \
2353} \
2354float64 VFP_HELPER(name, d)(float64 a, float64 b, CPUState *env) \
2355{ \
2356 return float64_ ## name (a, b, &env->vfp.fp_status); \
2357}
2358VFP_BINOP(add)
2359VFP_BINOP(sub)
2360VFP_BINOP(mul)
2361VFP_BINOP(div)
2362#undef VFP_BINOP
2363
2364float32 VFP_HELPER(neg, s)(float32 a)
2365{
2366 return float32_chs(a);
2367}
2368
2369float64 VFP_HELPER(neg, d)(float64 a)
2370{
66230e0d 2371 return float64_chs(a);
4373f3ce
PB		 2372}
2373
2374float32 VFP_HELPER(abs, s)(float32 a)
2375{
2376 return float32_abs(a);
2377}
2378
2379float64 VFP_HELPER(abs, d)(float64 a)
2380{
66230e0d 2381 return float64_abs(a);
4373f3ce
PB		 2382}
2383
2384float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
2385{
2386 return float32_sqrt(a, &env->vfp.fp_status);
2387}
2388
2389float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
2390{
2391 return float64_sqrt(a, &env->vfp.fp_status);
2392}
2393
2394/* XXX: check quiet/signaling case */
2395#define DO_VFP_cmp(p, type) \
2396void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
2397{ \
2398 uint32_t flags; \
2399 switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
2400 case 0: flags = 0x6; break; \
2401 case -1: flags = 0x8; break; \
2402 case 1: flags = 0x2; break; \
2403 default: case 2: flags = 0x3; break; \
2404 } \
2405 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2406 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2407} \
2408void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
2409{ \
2410 uint32_t flags; \
2411 switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
2412 case 0: flags = 0x6; break; \
2413 case -1: flags = 0x8; break; \
2414 case 1: flags = 0x2; break; \
2415 default: case 2: flags = 0x3; break; \
2416 } \
2417 env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
2418 | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
2419}
2420DO_VFP_cmp(s, float32)
2421DO_VFP_cmp(d, float64)
2422#undef DO_VFP_cmp
2423
2424/* Helper routines to perform bitwise copies between float and int. */
2425static inline float32 vfp_itos(uint32_t i)
2426{
2427 union {
2428 uint32_t i;
2429 float32 s;
2430 } v;
2431
2432 v.i = i;
2433 return v.s;
2434}
2435
2436static inline uint32_t vfp_stoi(float32 s)
2437{
2438 union {
2439 uint32_t i;
2440 float32 s;
2441 } v;
2442
2443 v.s = s;
2444 return v.i;
2445}
2446
2447static inline float64 vfp_itod(uint64_t i)
2448{
2449 union {
2450 uint64_t i;
2451 float64 d;
2452 } v;
2453
2454 v.i = i;
2455 return v.d;
2456}
2457
2458static inline uint64_t vfp_dtoi(float64 d)
2459{
2460 union {
2461 uint64_t i;
2462 float64 d;
2463 } v;
2464
2465 v.d = d;
2466 return v.i;
2467}
2468
2469/* Integer to float conversion. */
2470float32 VFP_HELPER(uito, s)(float32 x, CPUState *env)
2471{
2472 return uint32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2473}
2474
2475float64 VFP_HELPER(uito, d)(float32 x, CPUState *env)
2476{
2477 return uint32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2478}
2479
2480float32 VFP_HELPER(sito, s)(float32 x, CPUState *env)
2481{
2482 return int32_to_float32(vfp_stoi(x), &env->vfp.fp_status);
2483}
2484
2485float64 VFP_HELPER(sito, d)(float32 x, CPUState *env)
2486{
2487 return int32_to_float64(vfp_stoi(x), &env->vfp.fp_status);
2488}
2489
2490/* Float to integer conversion. */
2491float32 VFP_HELPER(toui, s)(float32 x, CPUState *env)
2492{
2493 return vfp_itos(float32_to_uint32(x, &env->vfp.fp_status));
2494}
2495
2496float32 VFP_HELPER(toui, d)(float64 x, CPUState *env)
2497{
2498 return vfp_itos(float64_to_uint32(x, &env->vfp.fp_status));
2499}
2500
2501float32 VFP_HELPER(tosi, s)(float32 x, CPUState *env)
2502{
2503 return vfp_itos(float32_to_int32(x, &env->vfp.fp_status));
2504}
2505
2506float32 VFP_HELPER(tosi, d)(float64 x, CPUState *env)
2507{
2508 return vfp_itos(float64_to_int32(x, &env->vfp.fp_status));
2509}
2510
2511float32 VFP_HELPER(touiz, s)(float32 x, CPUState *env)
2512{
2513 return vfp_itos(float32_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2514}
2515
2516float32 VFP_HELPER(touiz, d)(float64 x, CPUState *env)
2517{
2518 return vfp_itos(float64_to_uint32_round_to_zero(x, &env->vfp.fp_status));
2519}
2520
2521float32 VFP_HELPER(tosiz, s)(float32 x, CPUState *env)
2522{
2523 return vfp_itos(float32_to_int32_round_to_zero(x, &env->vfp.fp_status));
2524}
2525
2526float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
2527{
2528 return vfp_itos(float64_to_int32_round_to_zero(x, &env->vfp.fp_status));
2529}
2530
2531/* floating point conversion */
2532float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
2533{
2534 return float32_to_float64(x, &env->vfp.fp_status);
2535}
2536
2537float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
2538{
2539 return float64_to_float32(x, &env->vfp.fp_status);
2540}
2541
2542/* VFP3 fixed point conversion. */
2543#define VFP_CONV_FIX(name, p, ftype, itype, sign) \
2544ftype VFP_HELPER(name##to, p)(ftype x, uint32_t shift, CPUState *env) \
2545{ \
2546 ftype tmp; \
2547 tmp = sign##int32_to_##ftype ((itype)vfp_##p##toi(x), \
2548 &env->vfp.fp_status); \
644ad806 2549 return ftype##_scalbn(tmp, -(int)shift, &env->vfp.fp_status); \
4373f3ce
PB		 2550} \
2551ftype VFP_HELPER(to##name, p)(ftype x, uint32_t shift, CPUState *env) \
2552{ \
2553 ftype tmp; \
2554 tmp = ftype##_scalbn(x, shift, &env->vfp.fp_status); \
2555 return vfp_ito##p((itype)ftype##_to_##sign##int32_round_to_zero(tmp, \
2556 &env->vfp.fp_status)); \
2557}
2558
2559VFP_CONV_FIX(sh, d, float64, int16, )
2560VFP_CONV_FIX(sl, d, float64, int32, )
2561VFP_CONV_FIX(uh, d, float64, uint16, u)
2562VFP_CONV_FIX(ul, d, float64, uint32, u)
2563VFP_CONV_FIX(sh, s, float32, int16, )
2564VFP_CONV_FIX(sl, s, float32, int32, )
2565VFP_CONV_FIX(uh, s, float32, uint16, u)
2566VFP_CONV_FIX(ul, s, float32, uint32, u)
2567#undef VFP_CONV_FIX
2568
2569float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
2570{
2571 float_status *s = &env->vfp.fp_status;
2572 float32 two = int32_to_float32(2, s);
2573 return float32_sub(two, float32_mul(a, b, s), s);
2574}
2575
2576float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
2577{
2578 float_status *s = &env->vfp.fp_status;
2579 float32 three = int32_to_float32(3, s);
2580 return float32_sub(three, float32_mul(a, b, s), s);
2581}
2582
8f8e3aa4
PB		 2583/* NEON helpers. */
2584
4373f3ce
PB		 2585/* TODO: The architecture specifies the value that the estimate functions
2586 should return. We return the exact reciprocal/root instead. */
2587float32 HELPER(recpe_f32)(float32 a, CPUState *env)
2588{
2589 float_status *s = &env->vfp.fp_status;
2590 float32 one = int32_to_float32(1, s);
2591 return float32_div(one, a, s);
2592}
2593
2594float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
2595{
2596 float_status *s = &env->vfp.fp_status;
2597 float32 one = int32_to_float32(1, s);
2598 return float32_div(one, float32_sqrt(a, s), s);
2599}
2600
2601uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
2602{
2603 float_status *s = &env->vfp.fp_status;
2604 float32 tmp;
2605 tmp = int32_to_float32(a, s);
2606 tmp = float32_scalbn(tmp, -32, s);
2607 tmp = helper_recpe_f32(tmp, env);
2608 tmp = float32_scalbn(tmp, 31, s);
2609 return float32_to_int32(tmp, s);
2610}
2611
2612uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
2613{
2614 float_status *s = &env->vfp.fp_status;
2615 float32 tmp;
2616 tmp = int32_to_float32(a, s);
2617 tmp = float32_scalbn(tmp, -32, s);
2618 tmp = helper_rsqrte_f32(tmp, env);
2619 tmp = float32_scalbn(tmp, 31, s);
2620 return float32_to_int32(tmp, s);
2621}
fe1479c3
PB		 2622
2623void HELPER(set_teecr)(CPUState *env, uint32_t val)
2624{
2625 val &= 1;
2626 if (env->teecr != val) {
2627 env->teecr = val;
2628 tb_flush(env);
2629 }
2630}
Qemu copy for testing