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494b00c7 CD |
1 | /* |
2 | * ARM implementation of KVM hooks | |
3 | * | |
4 | * Copyright Christoffer Dall 2009-2010 | |
5 | * | |
6 | * This work is licensed under the terms of the GNU GPL, version 2 or later. | |
7 | * See the COPYING file in the top-level directory. | |
8 | * | |
9 | */ | |
10 | ||
11 | #include <stdio.h> | |
12 | #include <sys/types.h> | |
13 | #include <sys/ioctl.h> | |
14 | #include <sys/mman.h> | |
15 | ||
16 | #include <linux/kvm.h> | |
17 | ||
18 | #include "qemu-common.h" | |
19 | #include "qemu/timer.h" | |
20 | #include "sysemu/sysemu.h" | |
21 | #include "sysemu/kvm.h" | |
eb035b48 | 22 | #include "kvm_arm.h" |
494b00c7 | 23 | #include "cpu.h" |
bd2be150 | 24 | #include "hw/arm/arm.h" |
494b00c7 | 25 | |
721fae12 PM |
26 | /* Check that cpu.h's idea of coprocessor fields matches KVM's */ |
27 | #if (CP_REG_SIZE_SHIFT != KVM_REG_SIZE_SHIFT) || \ | |
28 | (CP_REG_SIZE_MASK != KVM_REG_SIZE_MASK) || \ | |
29 | (CP_REG_SIZE_U32 != KVM_REG_SIZE_U32) || \ | |
30 | (CP_REG_SIZE_U64 != KVM_REG_SIZE_U64) || \ | |
31 | (CP_REG_ARM != KVM_REG_ARM) | |
32 | #error mismatch between cpu.h and KVM header definitions | |
33 | #endif | |
34 | ||
494b00c7 CD |
35 | const KVMCapabilityInfo kvm_arch_required_capabilities[] = { |
36 | KVM_CAP_LAST_INFO | |
37 | }; | |
38 | ||
39 | int kvm_arch_init(KVMState *s) | |
40 | { | |
41 | /* For ARM interrupt delivery is always asynchronous, | |
42 | * whether we are using an in-kernel VGIC or not. | |
43 | */ | |
44 | kvm_async_interrupts_allowed = true; | |
45 | return 0; | |
46 | } | |
47 | ||
48 | unsigned long kvm_arch_vcpu_id(CPUState *cpu) | |
49 | { | |
50 | return cpu->cpu_index; | |
51 | } | |
52 | ||
ff047453 PM |
53 | static bool reg_syncs_via_tuple_list(uint64_t regidx) |
54 | { | |
55 | /* Return true if the regidx is a register we should synchronize | |
56 | * via the cpreg_tuples array (ie is not a core reg we sync by | |
57 | * hand in kvm_arch_get/put_registers()) | |
58 | */ | |
59 | switch (regidx & KVM_REG_ARM_COPROC_MASK) { | |
60 | case KVM_REG_ARM_CORE: | |
61 | case KVM_REG_ARM_VFP: | |
62 | return false; | |
63 | default: | |
64 | return true; | |
65 | } | |
66 | } | |
67 | ||
68 | static int compare_u64(const void *a, const void *b) | |
69 | { | |
0bc2a331 AR |
70 | if (*(uint64_t *)a > *(uint64_t *)b) { |
71 | return 1; | |
72 | } | |
73 | if (*(uint64_t *)a < *(uint64_t *)b) { | |
74 | return -1; | |
75 | } | |
76 | return 0; | |
ff047453 PM |
77 | } |
78 | ||
494b00c7 CD |
79 | int kvm_arch_init_vcpu(CPUState *cs) |
80 | { | |
81 | struct kvm_vcpu_init init; | |
ff047453 | 82 | int i, ret, arraylen; |
81635574 PM |
83 | uint64_t v; |
84 | struct kvm_one_reg r; | |
ff047453 PM |
85 | struct kvm_reg_list rl; |
86 | struct kvm_reg_list *rlp; | |
87 | ARMCPU *cpu = ARM_CPU(cs); | |
494b00c7 CD |
88 | |
89 | init.target = KVM_ARM_TARGET_CORTEX_A15; | |
90 | memset(init.features, 0, sizeof(init.features)); | |
81635574 PM |
91 | ret = kvm_vcpu_ioctl(cs, KVM_ARM_VCPU_INIT, &init); |
92 | if (ret) { | |
93 | return ret; | |
94 | } | |
95 | /* Query the kernel to make sure it supports 32 VFP | |
96 | * registers: QEMU's "cortex-a15" CPU is always a | |
97 | * VFP-D32 core. The simplest way to do this is just | |
98 | * to attempt to read register d31. | |
99 | */ | |
100 | r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP | 31; | |
101 | r.addr = (uintptr_t)(&v); | |
102 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); | |
536f25e4 PM |
103 | if (ret == -ENOENT) { |
104 | return -EINVAL; | |
81635574 | 105 | } |
ff047453 PM |
106 | |
107 | /* Populate the cpreg list based on the kernel's idea | |
108 | * of what registers exist (and throw away the TCG-created list). | |
109 | */ | |
110 | rl.n = 0; | |
111 | ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, &rl); | |
112 | if (ret != -E2BIG) { | |
113 | return ret; | |
114 | } | |
115 | rlp = g_malloc(sizeof(struct kvm_reg_list) + rl.n * sizeof(uint64_t)); | |
116 | rlp->n = rl.n; | |
117 | ret = kvm_vcpu_ioctl(cs, KVM_GET_REG_LIST, rlp); | |
118 | if (ret) { | |
119 | goto out; | |
120 | } | |
121 | /* Sort the list we get back from the kernel, since cpreg_tuples | |
122 | * must be in strictly ascending order. | |
123 | */ | |
124 | qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64); | |
125 | ||
126 | for (i = 0, arraylen = 0; i < rlp->n; i++) { | |
127 | if (!reg_syncs_via_tuple_list(rlp->reg[i])) { | |
128 | continue; | |
129 | } | |
130 | switch (rlp->reg[i] & KVM_REG_SIZE_MASK) { | |
131 | case KVM_REG_SIZE_U32: | |
132 | case KVM_REG_SIZE_U64: | |
133 | break; | |
134 | default: | |
135 | fprintf(stderr, "Can't handle size of register in kernel list\n"); | |
136 | ret = -EINVAL; | |
137 | goto out; | |
138 | } | |
139 | ||
140 | arraylen++; | |
141 | } | |
142 | ||
143 | cpu->cpreg_indexes = g_renew(uint64_t, cpu->cpreg_indexes, arraylen); | |
144 | cpu->cpreg_values = g_renew(uint64_t, cpu->cpreg_values, arraylen); | |
145 | cpu->cpreg_vmstate_indexes = g_renew(uint64_t, cpu->cpreg_vmstate_indexes, | |
146 | arraylen); | |
147 | cpu->cpreg_vmstate_values = g_renew(uint64_t, cpu->cpreg_vmstate_values, | |
148 | arraylen); | |
149 | cpu->cpreg_array_len = arraylen; | |
150 | cpu->cpreg_vmstate_array_len = arraylen; | |
151 | ||
152 | for (i = 0, arraylen = 0; i < rlp->n; i++) { | |
153 | uint64_t regidx = rlp->reg[i]; | |
154 | if (!reg_syncs_via_tuple_list(regidx)) { | |
155 | continue; | |
156 | } | |
157 | cpu->cpreg_indexes[arraylen] = regidx; | |
158 | arraylen++; | |
159 | } | |
160 | assert(cpu->cpreg_array_len == arraylen); | |
161 | ||
162 | if (!write_kvmstate_to_list(cpu)) { | |
163 | /* Shouldn't happen unless kernel is inconsistent about | |
164 | * what registers exist. | |
165 | */ | |
166 | fprintf(stderr, "Initial read of kernel register state failed\n"); | |
167 | ret = -EINVAL; | |
168 | goto out; | |
169 | } | |
170 | ||
2d8e5a0e PM |
171 | /* Save a copy of the initial register values so that we can |
172 | * feed it back to the kernel on VCPU reset. | |
173 | */ | |
174 | cpu->cpreg_reset_values = g_memdup(cpu->cpreg_values, | |
175 | cpu->cpreg_array_len * | |
176 | sizeof(cpu->cpreg_values[0])); | |
177 | ||
ff047453 PM |
178 | out: |
179 | g_free(rlp); | |
81635574 | 180 | return ret; |
494b00c7 CD |
181 | } |
182 | ||
eb035b48 PM |
183 | /* We track all the KVM devices which need their memory addresses |
184 | * passing to the kernel in a list of these structures. | |
185 | * When board init is complete we run through the list and | |
186 | * tell the kernel the base addresses of the memory regions. | |
187 | * We use a MemoryListener to track mapping and unmapping of | |
188 | * the regions during board creation, so the board models don't | |
189 | * need to do anything special for the KVM case. | |
190 | */ | |
191 | typedef struct KVMDevice { | |
192 | struct kvm_arm_device_addr kda; | |
193 | MemoryRegion *mr; | |
194 | QSLIST_ENTRY(KVMDevice) entries; | |
195 | } KVMDevice; | |
196 | ||
197 | static QSLIST_HEAD(kvm_devices_head, KVMDevice) kvm_devices_head; | |
198 | ||
199 | static void kvm_arm_devlistener_add(MemoryListener *listener, | |
200 | MemoryRegionSection *section) | |
201 | { | |
202 | KVMDevice *kd; | |
203 | ||
204 | QSLIST_FOREACH(kd, &kvm_devices_head, entries) { | |
205 | if (section->mr == kd->mr) { | |
206 | kd->kda.addr = section->offset_within_address_space; | |
207 | } | |
208 | } | |
209 | } | |
210 | ||
211 | static void kvm_arm_devlistener_del(MemoryListener *listener, | |
212 | MemoryRegionSection *section) | |
213 | { | |
214 | KVMDevice *kd; | |
215 | ||
216 | QSLIST_FOREACH(kd, &kvm_devices_head, entries) { | |
217 | if (section->mr == kd->mr) { | |
218 | kd->kda.addr = -1; | |
219 | } | |
220 | } | |
221 | } | |
222 | ||
223 | static MemoryListener devlistener = { | |
224 | .region_add = kvm_arm_devlistener_add, | |
225 | .region_del = kvm_arm_devlistener_del, | |
226 | }; | |
227 | ||
228 | static void kvm_arm_machine_init_done(Notifier *notifier, void *data) | |
229 | { | |
230 | KVMDevice *kd, *tkd; | |
231 | ||
232 | memory_listener_unregister(&devlistener); | |
233 | QSLIST_FOREACH_SAFE(kd, &kvm_devices_head, entries, tkd) { | |
234 | if (kd->kda.addr != -1) { | |
235 | if (kvm_vm_ioctl(kvm_state, KVM_ARM_SET_DEVICE_ADDR, | |
236 | &kd->kda) < 0) { | |
237 | fprintf(stderr, "KVM_ARM_SET_DEVICE_ADDRESS failed: %s\n", | |
238 | strerror(errno)); | |
239 | abort(); | |
240 | } | |
241 | } | |
dfde4e6e | 242 | memory_region_unref(kd->mr); |
eb035b48 PM |
243 | g_free(kd); |
244 | } | |
245 | } | |
246 | ||
247 | static Notifier notify = { | |
248 | .notify = kvm_arm_machine_init_done, | |
249 | }; | |
250 | ||
251 | void kvm_arm_register_device(MemoryRegion *mr, uint64_t devid) | |
252 | { | |
253 | KVMDevice *kd; | |
254 | ||
255 | if (!kvm_irqchip_in_kernel()) { | |
256 | return; | |
257 | } | |
258 | ||
259 | if (QSLIST_EMPTY(&kvm_devices_head)) { | |
260 | memory_listener_register(&devlistener, NULL); | |
261 | qemu_add_machine_init_done_notifier(¬ify); | |
262 | } | |
263 | kd = g_new0(KVMDevice, 1); | |
264 | kd->mr = mr; | |
265 | kd->kda.id = devid; | |
266 | kd->kda.addr = -1; | |
267 | QSLIST_INSERT_HEAD(&kvm_devices_head, kd, entries); | |
dfde4e6e | 268 | memory_region_ref(kd->mr); |
eb035b48 PM |
269 | } |
270 | ||
ff047453 PM |
271 | bool write_kvmstate_to_list(ARMCPU *cpu) |
272 | { | |
273 | CPUState *cs = CPU(cpu); | |
274 | int i; | |
275 | bool ok = true; | |
276 | ||
277 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
278 | struct kvm_one_reg r; | |
279 | uint64_t regidx = cpu->cpreg_indexes[i]; | |
280 | uint32_t v32; | |
281 | int ret; | |
282 | ||
283 | r.id = regidx; | |
284 | ||
285 | switch (regidx & KVM_REG_SIZE_MASK) { | |
286 | case KVM_REG_SIZE_U32: | |
287 | r.addr = (uintptr_t)&v32; | |
288 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); | |
289 | if (!ret) { | |
290 | cpu->cpreg_values[i] = v32; | |
291 | } | |
292 | break; | |
293 | case KVM_REG_SIZE_U64: | |
294 | r.addr = (uintptr_t)(cpu->cpreg_values + i); | |
295 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); | |
296 | break; | |
297 | default: | |
298 | abort(); | |
299 | } | |
300 | if (ret) { | |
301 | ok = false; | |
302 | } | |
303 | } | |
304 | return ok; | |
305 | } | |
306 | ||
307 | bool write_list_to_kvmstate(ARMCPU *cpu) | |
308 | { | |
309 | CPUState *cs = CPU(cpu); | |
310 | int i; | |
311 | bool ok = true; | |
312 | ||
313 | for (i = 0; i < cpu->cpreg_array_len; i++) { | |
314 | struct kvm_one_reg r; | |
315 | uint64_t regidx = cpu->cpreg_indexes[i]; | |
316 | uint32_t v32; | |
317 | int ret; | |
318 | ||
319 | r.id = regidx; | |
320 | switch (regidx & KVM_REG_SIZE_MASK) { | |
321 | case KVM_REG_SIZE_U32: | |
322 | v32 = cpu->cpreg_values[i]; | |
323 | r.addr = (uintptr_t)&v32; | |
324 | break; | |
325 | case KVM_REG_SIZE_U64: | |
326 | r.addr = (uintptr_t)(cpu->cpreg_values + i); | |
327 | break; | |
328 | default: | |
329 | abort(); | |
330 | } | |
331 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); | |
332 | if (ret) { | |
333 | /* We might fail for "unknown register" and also for | |
334 | * "you tried to set a register which is constant with | |
335 | * a different value from what it actually contains". | |
336 | */ | |
337 | ok = false; | |
338 | } | |
339 | } | |
340 | return ok; | |
341 | } | |
342 | ||
494b00c7 CD |
343 | typedef struct Reg { |
344 | uint64_t id; | |
345 | int offset; | |
346 | } Reg; | |
347 | ||
348 | #define COREREG(KERNELNAME, QEMUFIELD) \ | |
349 | { \ | |
350 | KVM_REG_ARM | KVM_REG_SIZE_U32 | \ | |
351 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(KERNELNAME), \ | |
352 | offsetof(CPUARMState, QEMUFIELD) \ | |
353 | } | |
354 | ||
81635574 PM |
355 | #define VFPSYSREG(R) \ |
356 | { \ | |
357 | KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | \ | |
358 | KVM_REG_ARM_VFP_##R, \ | |
359 | offsetof(CPUARMState, vfp.xregs[ARM_VFP_##R]) \ | |
360 | } | |
361 | ||
494b00c7 CD |
362 | static const Reg regs[] = { |
363 | /* R0_usr .. R14_usr */ | |
364 | COREREG(usr_regs.uregs[0], regs[0]), | |
365 | COREREG(usr_regs.uregs[1], regs[1]), | |
366 | COREREG(usr_regs.uregs[2], regs[2]), | |
367 | COREREG(usr_regs.uregs[3], regs[3]), | |
368 | COREREG(usr_regs.uregs[4], regs[4]), | |
369 | COREREG(usr_regs.uregs[5], regs[5]), | |
370 | COREREG(usr_regs.uregs[6], regs[6]), | |
371 | COREREG(usr_regs.uregs[7], regs[7]), | |
372 | COREREG(usr_regs.uregs[8], usr_regs[0]), | |
373 | COREREG(usr_regs.uregs[9], usr_regs[1]), | |
374 | COREREG(usr_regs.uregs[10], usr_regs[2]), | |
375 | COREREG(usr_regs.uregs[11], usr_regs[3]), | |
376 | COREREG(usr_regs.uregs[12], usr_regs[4]), | |
377 | COREREG(usr_regs.uregs[13], banked_r13[0]), | |
378 | COREREG(usr_regs.uregs[14], banked_r14[0]), | |
379 | /* R13, R14, SPSR for SVC, ABT, UND, IRQ banks */ | |
380 | COREREG(svc_regs[0], banked_r13[1]), | |
381 | COREREG(svc_regs[1], banked_r14[1]), | |
382 | COREREG(svc_regs[2], banked_spsr[1]), | |
383 | COREREG(abt_regs[0], banked_r13[2]), | |
384 | COREREG(abt_regs[1], banked_r14[2]), | |
385 | COREREG(abt_regs[2], banked_spsr[2]), | |
386 | COREREG(und_regs[0], banked_r13[3]), | |
387 | COREREG(und_regs[1], banked_r14[3]), | |
388 | COREREG(und_regs[2], banked_spsr[3]), | |
389 | COREREG(irq_regs[0], banked_r13[4]), | |
390 | COREREG(irq_regs[1], banked_r14[4]), | |
391 | COREREG(irq_regs[2], banked_spsr[4]), | |
392 | /* R8_fiq .. R14_fiq and SPSR_fiq */ | |
393 | COREREG(fiq_regs[0], fiq_regs[0]), | |
394 | COREREG(fiq_regs[1], fiq_regs[1]), | |
395 | COREREG(fiq_regs[2], fiq_regs[2]), | |
396 | COREREG(fiq_regs[3], fiq_regs[3]), | |
397 | COREREG(fiq_regs[4], fiq_regs[4]), | |
398 | COREREG(fiq_regs[5], banked_r13[5]), | |
399 | COREREG(fiq_regs[6], banked_r14[5]), | |
400 | COREREG(fiq_regs[7], banked_spsr[5]), | |
401 | /* R15 */ | |
402 | COREREG(usr_regs.uregs[15], regs[15]), | |
81635574 PM |
403 | /* VFP system registers */ |
404 | VFPSYSREG(FPSID), | |
405 | VFPSYSREG(MVFR1), | |
406 | VFPSYSREG(MVFR0), | |
407 | VFPSYSREG(FPEXC), | |
408 | VFPSYSREG(FPINST), | |
409 | VFPSYSREG(FPINST2), | |
494b00c7 CD |
410 | }; |
411 | ||
412 | int kvm_arch_put_registers(CPUState *cs, int level) | |
413 | { | |
414 | ARMCPU *cpu = ARM_CPU(cs); | |
415 | CPUARMState *env = &cpu->env; | |
416 | struct kvm_one_reg r; | |
417 | int mode, bn; | |
418 | int ret, i; | |
81635574 | 419 | uint32_t cpsr, fpscr; |
494b00c7 CD |
420 | |
421 | /* Make sure the banked regs are properly set */ | |
422 | mode = env->uncached_cpsr & CPSR_M; | |
423 | bn = bank_number(mode); | |
424 | if (mode == ARM_CPU_MODE_FIQ) { | |
425 | memcpy(env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
426 | } else { | |
427 | memcpy(env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t)); | |
428 | } | |
429 | env->banked_r13[bn] = env->regs[13]; | |
430 | env->banked_r14[bn] = env->regs[14]; | |
431 | env->banked_spsr[bn] = env->spsr; | |
432 | ||
433 | /* Now we can safely copy stuff down to the kernel */ | |
434 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
435 | r.id = regs[i].id; | |
436 | r.addr = (uintptr_t)(env) + regs[i].offset; | |
437 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); | |
438 | if (ret) { | |
439 | return ret; | |
440 | } | |
441 | } | |
442 | ||
443 | /* Special cases which aren't a single CPUARMState field */ | |
444 | cpsr = cpsr_read(env); | |
445 | r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | | |
446 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr); | |
447 | r.addr = (uintptr_t)(&cpsr); | |
448 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); | |
449 | if (ret) { | |
450 | return ret; | |
451 | } | |
452 | ||
81635574 PM |
453 | /* VFP registers */ |
454 | r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; | |
455 | for (i = 0; i < 32; i++) { | |
456 | r.addr = (uintptr_t)(&env->vfp.regs[i]); | |
457 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); | |
458 | if (ret) { | |
459 | return ret; | |
460 | } | |
461 | r.id++; | |
462 | } | |
463 | ||
464 | r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | | |
465 | KVM_REG_ARM_VFP_FPSCR; | |
466 | fpscr = vfp_get_fpscr(env); | |
467 | r.addr = (uintptr_t)&fpscr; | |
468 | ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); | |
f7134d96 PM |
469 | if (ret) { |
470 | return ret; | |
471 | } | |
472 | ||
473 | /* Note that we do not call write_cpustate_to_list() | |
474 | * here, so we are only writing the tuple list back to | |
475 | * KVM. This is safe because nothing can change the | |
476 | * CPUARMState cp15 fields (in particular gdb accesses cannot) | |
477 | * and so there are no changes to sync. In fact syncing would | |
478 | * be wrong at this point: for a constant register where TCG and | |
479 | * KVM disagree about its value, the preceding write_list_to_cpustate() | |
480 | * would not have had any effect on the CPUARMState value (since the | |
481 | * register is read-only), and a write_cpustate_to_list() here would | |
482 | * then try to write the TCG value back into KVM -- this would either | |
483 | * fail or incorrectly change the value the guest sees. | |
484 | * | |
485 | * If we ever want to allow the user to modify cp15 registers via | |
486 | * the gdb stub, we would need to be more clever here (for instance | |
487 | * tracking the set of registers kvm_arch_get_registers() successfully | |
488 | * managed to update the CPUARMState with, and only allowing those | |
489 | * to be written back up into the kernel). | |
490 | */ | |
491 | if (!write_list_to_kvmstate(cpu)) { | |
492 | return EINVAL; | |
493 | } | |
494b00c7 CD |
494 | |
495 | return ret; | |
496 | } | |
497 | ||
498 | int kvm_arch_get_registers(CPUState *cs) | |
499 | { | |
500 | ARMCPU *cpu = ARM_CPU(cs); | |
501 | CPUARMState *env = &cpu->env; | |
502 | struct kvm_one_reg r; | |
503 | int mode, bn; | |
504 | int ret, i; | |
81635574 | 505 | uint32_t cpsr, fpscr; |
494b00c7 CD |
506 | |
507 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
508 | r.id = regs[i].id; | |
509 | r.addr = (uintptr_t)(env) + regs[i].offset; | |
510 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); | |
511 | if (ret) { | |
512 | return ret; | |
513 | } | |
514 | } | |
515 | ||
516 | /* Special cases which aren't a single CPUARMState field */ | |
517 | r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | | |
518 | KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(usr_regs.ARM_cpsr); | |
519 | r.addr = (uintptr_t)(&cpsr); | |
520 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); | |
521 | if (ret) { | |
522 | return ret; | |
523 | } | |
524 | cpsr_write(env, cpsr, 0xffffffff); | |
525 | ||
494b00c7 CD |
526 | /* Make sure the current mode regs are properly set */ |
527 | mode = env->uncached_cpsr & CPSR_M; | |
528 | bn = bank_number(mode); | |
529 | if (mode == ARM_CPU_MODE_FIQ) { | |
530 | memcpy(env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t)); | |
531 | } else { | |
532 | memcpy(env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t)); | |
533 | } | |
534 | env->regs[13] = env->banked_r13[bn]; | |
535 | env->regs[14] = env->banked_r14[bn]; | |
536 | env->spsr = env->banked_spsr[bn]; | |
537 | ||
81635574 PM |
538 | /* VFP registers */ |
539 | r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; | |
540 | for (i = 0; i < 32; i++) { | |
541 | r.addr = (uintptr_t)(&env->vfp.regs[i]); | |
542 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); | |
543 | if (ret) { | |
544 | return ret; | |
545 | } | |
546 | r.id++; | |
547 | } | |
548 | ||
549 | r.id = KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | | |
550 | KVM_REG_ARM_VFP_FPSCR; | |
551 | r.addr = (uintptr_t)&fpscr; | |
552 | ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); | |
553 | if (ret) { | |
554 | return ret; | |
555 | } | |
556 | vfp_set_fpscr(env, fpscr); | |
557 | ||
f7134d96 PM |
558 | if (!write_kvmstate_to_list(cpu)) { |
559 | return EINVAL; | |
560 | } | |
561 | /* Note that it's OK to have registers which aren't in CPUState, | |
562 | * so we can ignore a failure return here. | |
563 | */ | |
564 | write_list_to_cpustate(cpu); | |
565 | ||
494b00c7 CD |
566 | return 0; |
567 | } | |
568 | ||
569 | void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) | |
570 | { | |
571 | } | |
572 | ||
573 | void kvm_arch_post_run(CPUState *cs, struct kvm_run *run) | |
574 | { | |
575 | } | |
576 | ||
577 | int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) | |
578 | { | |
579 | return 0; | |
580 | } | |
581 | ||
582 | void kvm_arch_reset_vcpu(CPUState *cs) | |
583 | { | |
2d8e5a0e PM |
584 | /* Feed the kernel back its initial register state */ |
585 | ARMCPU *cpu = ARM_CPU(cs); | |
586 | ||
587 | memmove(cpu->cpreg_values, cpu->cpreg_reset_values, | |
588 | cpu->cpreg_array_len * sizeof(cpu->cpreg_values[0])); | |
589 | ||
590 | if (!write_list_to_kvmstate(cpu)) { | |
591 | abort(); | |
592 | } | |
494b00c7 CD |
593 | } |
594 | ||
595 | bool kvm_arch_stop_on_emulation_error(CPUState *cs) | |
596 | { | |
597 | return true; | |
598 | } | |
599 | ||
600 | int kvm_arch_process_async_events(CPUState *cs) | |
601 | { | |
602 | return 0; | |
603 | } | |
604 | ||
605 | int kvm_arch_on_sigbus_vcpu(CPUState *cs, int code, void *addr) | |
606 | { | |
607 | return 1; | |
608 | } | |
609 | ||
610 | int kvm_arch_on_sigbus(int code, void *addr) | |
611 | { | |
612 | return 1; | |
613 | } | |
614 | ||
615 | void kvm_arch_update_guest_debug(CPUState *cs, struct kvm_guest_debug *dbg) | |
616 | { | |
617 | qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); | |
618 | } | |
619 | ||
620 | int kvm_arch_insert_sw_breakpoint(CPUState *cs, | |
621 | struct kvm_sw_breakpoint *bp) | |
622 | { | |
623 | qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); | |
624 | return -EINVAL; | |
625 | } | |
626 | ||
627 | int kvm_arch_insert_hw_breakpoint(target_ulong addr, | |
628 | target_ulong len, int type) | |
629 | { | |
630 | qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); | |
631 | return -EINVAL; | |
632 | } | |
633 | ||
634 | int kvm_arch_remove_hw_breakpoint(target_ulong addr, | |
635 | target_ulong len, int type) | |
636 | { | |
637 | qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); | |
638 | return -EINVAL; | |
639 | } | |
640 | ||
641 | int kvm_arch_remove_sw_breakpoint(CPUState *cs, | |
642 | struct kvm_sw_breakpoint *bp) | |
643 | { | |
644 | qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); | |
645 | return -EINVAL; | |
646 | } | |
647 | ||
648 | void kvm_arch_remove_all_hw_breakpoints(void) | |
649 | { | |
650 | qemu_log_mask(LOG_UNIMP, "%s: not implemented\n", __func__); | |
651 | } | |
b3a1c626 AK |
652 | |
653 | void kvm_arch_init_irq_routing(KVMState *s) | |
654 | { | |
655 | } |