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e739a48e AF |
1 | /* |
2 | * QEMU CRIS CPU | |
3 | * | |
1c3b52fb AF |
4 | * Copyright (c) 2008 AXIS Communications AB |
5 | * Written by Edgar E. Iglesias. | |
6 | * | |
e739a48e AF |
7 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
8 | * | |
9 | * This library is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU Lesser General Public | |
11 | * License as published by the Free Software Foundation; either | |
12 | * version 2.1 of the License, or (at your option) any later version. | |
13 | * | |
14 | * This library is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
17 | * Lesser General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU Lesser General Public | |
20 | * License along with this library; if not, see | |
21 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
22 | */ | |
23 | ||
24 | #include "cpu.h" | |
25 | #include "qemu-common.h" | |
1c3b52fb | 26 | #include "mmu.h" |
e739a48e AF |
27 | |
28 | ||
29 | /* CPUClass::reset() */ | |
30 | static void cris_cpu_reset(CPUState *s) | |
31 | { | |
32 | CRISCPU *cpu = CRIS_CPU(s); | |
33 | CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(cpu); | |
34 | CPUCRISState *env = &cpu->env; | |
1c3b52fb AF |
35 | uint32_t vr; |
36 | ||
37 | if (qemu_loglevel_mask(CPU_LOG_RESET)) { | |
55e5c285 | 38 | qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); |
1c3b52fb AF |
39 | log_cpu_state(env, 0); |
40 | } | |
e739a48e AF |
41 | |
42 | ccc->parent_reset(s); | |
43 | ||
1c3b52fb AF |
44 | vr = env->pregs[PR_VR]; |
45 | memset(env, 0, offsetof(CPUCRISState, breakpoints)); | |
46 | env->pregs[PR_VR] = vr; | |
47 | tlb_flush(env, 1); | |
48 | ||
49 | #if defined(CONFIG_USER_ONLY) | |
50 | /* start in user mode with interrupts enabled. */ | |
51 | env->pregs[PR_CCS] |= U_FLAG | I_FLAG | P_FLAG; | |
52 | #else | |
53 | cris_mmu_init(env); | |
54 | env->pregs[PR_CCS] = 0; | |
55 | #endif | |
e739a48e AF |
56 | } |
57 | ||
ca45f8b0 AF |
58 | static void cris_cpu_realizefn(DeviceState *dev, Error **errp) |
59 | { | |
60 | CRISCPU *cpu = CRIS_CPU(dev); | |
61 | CRISCPUClass *ccc = CRIS_CPU_GET_CLASS(dev); | |
62 | ||
63 | cpu_reset(CPU(cpu)); | |
64 | qemu_init_vcpu(&cpu->env); | |
65 | ||
66 | ccc->parent_realize(dev, errp); | |
67 | } | |
68 | ||
aa0d1267 AF |
69 | static void cris_cpu_initfn(Object *obj) |
70 | { | |
71 | CRISCPU *cpu = CRIS_CPU(obj); | |
72 | CPUCRISState *env = &cpu->env; | |
d1a94fec | 73 | static bool tcg_initialized; |
aa0d1267 AF |
74 | |
75 | cpu_exec_init(env); | |
d1a94fec AF |
76 | |
77 | if (tcg_enabled() && !tcg_initialized) { | |
78 | tcg_initialized = true; | |
79 | if (env->pregs[PR_VR] < 32) { | |
80 | cris_initialize_crisv10_tcg(); | |
81 | } else { | |
82 | cris_initialize_tcg(); | |
83 | } | |
84 | } | |
aa0d1267 AF |
85 | } |
86 | ||
e739a48e AF |
87 | static void cris_cpu_class_init(ObjectClass *oc, void *data) |
88 | { | |
ca45f8b0 | 89 | DeviceClass *dc = DEVICE_CLASS(oc); |
e739a48e AF |
90 | CPUClass *cc = CPU_CLASS(oc); |
91 | CRISCPUClass *ccc = CRIS_CPU_CLASS(oc); | |
92 | ||
ca45f8b0 AF |
93 | ccc->parent_realize = dc->realize; |
94 | dc->realize = cris_cpu_realizefn; | |
95 | ||
e739a48e AF |
96 | ccc->parent_reset = cc->reset; |
97 | cc->reset = cris_cpu_reset; | |
98 | } | |
99 | ||
100 | static const TypeInfo cris_cpu_type_info = { | |
101 | .name = TYPE_CRIS_CPU, | |
102 | .parent = TYPE_CPU, | |
103 | .instance_size = sizeof(CRISCPU), | |
aa0d1267 | 104 | .instance_init = cris_cpu_initfn, |
e739a48e AF |
105 | .abstract = false, |
106 | .class_size = sizeof(CRISCPUClass), | |
107 | .class_init = cris_cpu_class_init, | |
108 | }; | |
109 | ||
110 | static void cris_cpu_register_types(void) | |
111 | { | |
112 | type_register_static(&cris_cpu_type_info); | |
113 | } | |
114 | ||
115 | type_init(cris_cpu_register_types) |