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[qemu.git] / target-cris / translate.c
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8170028d
TS		 1/*
2 * CRIS emulation for qemu: main translation routines.
3 *
05ba7d5f 4 * Copyright (c) 2008 AXIS Communications AB
8170028d
TS		 5 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
b41f7df0
EI		 22/*
23 * FIXME:
cf1d97f0 24 * The condition code translation is in need of attention.
b41f7df0
EI		 25 */
26
8170028d
TS		 27#include <stdarg.h>
28#include <stdlib.h>
29#include <stdio.h>
30#include <string.h>
31#include <inttypes.h>
32#include <assert.h>
33
34#include "cpu.h"
35#include "exec-all.h"
36#include "disas.h"
57fec1fe 37#include "tcg-op.h"
05ba7d5f 38#include "helper.h"
8170028d 39#include "crisv32-decode.h"
ca10f867 40#include "qemu-common.h"
8170028d 41
8170028d
TS		 42#define DISAS_CRIS 0
43#if DISAS_CRIS
44#define DIS(x) x
45#else
46#define DIS(x)
47#endif
48
b41f7df0 49#define D(x)
8170028d
TS		 50#define BUG() (gen_BUG(dc, __FILE__, __LINE__))
51#define BUG_ON(x) ({if (x) BUG();})
52
4f400ab5
EI		 53#define DISAS_SWI 5
54
8170028d
TS		 55/* Used by the decoder. */
56#define EXTRACT_FIELD(src, start, end) \
57 (((src) >> start) & ((1 << (end - start + 1)) - 1))
58
59#define CC_MASK_NZ 0xc
60#define CC_MASK_NZV 0xe
61#define CC_MASK_NZVC 0xf
62#define CC_MASK_RNZV 0x10e
63
a825e703
EI		 64TCGv cpu_env;
65TCGv cpu_T[2];
66TCGv cpu_R[16];
67TCGv cpu_PR[16];
68TCGv cc_src;
69TCGv cc_dest;
70TCGv cc_result;
71TCGv cc_op;
72TCGv cc_size;
73TCGv cc_mask;
05ba7d5f 74
b41f7df0
EI		 75TCGv env_btarget;
76TCGv env_pc;
77
8170028d
TS		 78/* This is the state at translation time. */
79typedef struct DisasContext {
80 CPUState *env;
b41f7df0 81 target_ulong pc, ppc;
8170028d
TS		 82
83 /* Decoder. */
84 uint32_t ir;
85 uint32_t opcode;
86 unsigned int op1;
87 unsigned int op2;
88 unsigned int zsize, zzsize;
89 unsigned int mode;
90 unsigned int postinc;
91
8170028d
TS		 92 int update_cc;
93 int cc_op;
94 int cc_size;
95 uint32_t cc_mask;
b41f7df0
EI		 96 int flags_live; /* Wether or not $ccs is uptodate. */
97 int flagx_live; /* Wether or not flags_x has the x flag known at
98 translation time. */
8170028d 99 int flags_x;
b41f7df0 100 int clear_x; /* Clear x after this insn? */
8170028d 101
b41f7df0 102 int user; /* user or kernel mode. */
8170028d 103 int is_jmp;
8170028d 104
8170028d 105 int delayed_branch;
8170028d
TS		 106
107 struct TranslationBlock *tb;
108 int singlestep_enabled;
109} DisasContext;
110
8170028d
TS		 111static void gen_BUG(DisasContext *dc, char *file, int line)
112{
113 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
114 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
cf1d97f0 115 cpu_abort(dc->env, "%s:%d\n", file, line);
8170028d
TS		 116}
117
a825e703
EI		 118const char *regnames[] =
119{
120 "$r0", "$r1", "$r2", "$r3",
121 "$r4", "$r5", "$r6", "$r7",
122 "$r8", "$r9", "$r10", "$r11",
123 "$r12", "$r13", "$sp", "$acr",
124};
125const char *pregnames[] =
126{
127 "$bz", "$vr", "$pid", "$srs",
128 "$wz", "$exs", "$eda", "$mof",
129 "$dz", "$ebp", "$erp", "$srp",
130 "$nrp", "$ccs", "$usp", "$spc",
131};
132
05ba7d5f
EI		 133/* We need this table to handle preg-moves with implicit width. */
134int preg_sizes[] = {
135 1, /* bz. */
136 1, /* vr. */
137 4, /* pid. */
138 1, /* srs. */
139 2, /* wz. */
140 4, 4, 4,
141 4, 4, 4, 4,
142 4, 4, 4, 4,
143};
144
145#define t_gen_mov_TN_env(tn, member) \
3157a0a9 146 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
05ba7d5f 147#define t_gen_mov_env_TN(member, tn) \
3157a0a9 148 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
05ba7d5f 149
b41f7df0
EI		 150static inline void t_gen_mov_TN_reg(TCGv tn, int r)
151{
152 if (r < 0 || r > 15)
153 fprintf(stderr, "wrong register read $r%d\n", r);
154 tcg_gen_mov_tl(tn, cpu_R[r]);
155}
156static inline void t_gen_mov_reg_TN(int r, TCGv tn)
157{
158 if (r < 0 || r > 15)
159 fprintf(stderr, "wrong register write $r%d\n", r);
160 tcg_gen_mov_tl(cpu_R[r], tn);
161}
05ba7d5f
EI		 162
163static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
164{
b41f7df0
EI		 165 if (offset > sizeof (CPUState))
166 fprintf(stderr, "wrong load from env from off=%d\n", offset);
05ba7d5f
EI		 167 tcg_gen_ld_tl(tn, cpu_env, offset);
168}
169static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
170{
b41f7df0
EI		 171 if (offset > sizeof (CPUState))
172 fprintf(stderr, "wrong store to env at off=%d\n", offset);
05ba7d5f
EI		 173 tcg_gen_st_tl(tn, cpu_env, offset);
174}
175
176static inline void t_gen_mov_TN_preg(TCGv tn, int r)
177{
b41f7df0
EI		 178 if (r < 0 || r > 15)
179 fprintf(stderr, "wrong register read $p%d\n", r);
05ba7d5f 180 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
3157a0a9 181 tcg_gen_mov_tl(tn, tcg_const_tl(0));
05ba7d5f 182 else if (r == PR_VR)
3157a0a9 183 tcg_gen_mov_tl(tn, tcg_const_tl(32));
b41f7df0
EI		 184 else if (r == PR_EXS) {
185 printf("read from EXS!\n");
186 tcg_gen_mov_tl(tn, cpu_PR[r]);
187 }
188 else if (r == PR_EDA) {
189 printf("read from EDA!\n");
190 tcg_gen_mov_tl(tn, cpu_PR[r]);
191 }
05ba7d5f 192 else
a825e703 193 tcg_gen_mov_tl(tn, cpu_PR[r]);
05ba7d5f 194}
cf1d97f0 195static inline void t_gen_mov_preg_TN(DisasContext *dc, int r, TCGv tn)
05ba7d5f 196{
b41f7df0
EI		 197 if (r < 0 || r > 15)
198 fprintf(stderr, "wrong register write $p%d\n", r);
05ba7d5f
EI		 199 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
200 return;
b41f7df0
EI		 201 else if (r == PR_SRS)
202 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
203 else {
a825e703 204 tcg_gen_mov_tl(cpu_PR[r], tn);
cf1d97f0
EI		 205 if (r == PR_PID)
206 tcg_gen_helper_0_1(helper_tlb_flush_pid, tn);
b41f7df0 207 }
05ba7d5f
EI		 208}
209
dceaf394 210static inline void t_gen_raise_exception(uint32_t index)
05ba7d5f 211{
dceaf394 212 tcg_gen_helper_0_1(helper_raise_exception, tcg_const_tl(index));
05ba7d5f
EI		 213}
214
215static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
216{
217 int l1;
218
219 l1 = gen_new_label();
220 /* Speculative shift. */
221 tcg_gen_shl_tl(d, a, b);
cb63669a 222 tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
05ba7d5f
EI		 223 /* Clear dst if shift operands were to large. */
224 tcg_gen_movi_tl(d, 0);
225 gen_set_label(l1);
226}
227
228static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
229{
230 int l1;
231
232 l1 = gen_new_label();
233 /* Speculative shift. */
234 tcg_gen_shr_tl(d, a, b);
cb63669a 235 tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
05ba7d5f
EI		 236 /* Clear dst if shift operands were to large. */
237 tcg_gen_movi_tl(d, 0);
238 gen_set_label(l1);
239}
240
241static void t_gen_asr(TCGv d, TCGv a, TCGv b)
242{
243 int l1;
244
245 l1 = gen_new_label();
246 /* Speculative shift. */
247 tcg_gen_sar_tl(d, a, b);
cb63669a 248 tcg_gen_brcondi_tl(TCG_COND_LEU, b, 31, l1);
05ba7d5f 249 /* Clear dst if shift operands were to large. */
b41f7df0 250 tcg_gen_sar_tl(d, a, tcg_const_tl(30));
05ba7d5f
EI		 251 gen_set_label(l1);
252}
253
3157a0a9
EI		 254/* 64-bit signed mul, lower result in d and upper in d2. */
255static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
256{
257 TCGv t0, t1;
258
259 t0 = tcg_temp_new(TCG_TYPE_I64);
260 t1 = tcg_temp_new(TCG_TYPE_I64);
261
262 tcg_gen_ext32s_i64(t0, a);
263 tcg_gen_ext32s_i64(t1, b);
264 tcg_gen_mul_i64(t0, t0, t1);
265
266 tcg_gen_trunc_i64_i32(d, t0);
267 tcg_gen_shri_i64(t0, t0, 32);
268 tcg_gen_trunc_i64_i32(d2, t0);
b41f7df0
EI		 269
270 tcg_gen_discard_i64(t0);
271 tcg_gen_discard_i64(t1);
3157a0a9
EI		 272}
273
274/* 64-bit unsigned muls, lower result in d and upper in d2. */
275static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
276{
277 TCGv t0, t1;
278
279 t0 = tcg_temp_new(TCG_TYPE_I64);
280 t1 = tcg_temp_new(TCG_TYPE_I64);
281
282 tcg_gen_extu_i32_i64(t0, a);
283 tcg_gen_extu_i32_i64(t1, b);
284 tcg_gen_mul_i64(t0, t0, t1);
285
286 tcg_gen_trunc_i64_i32(d, t0);
287 tcg_gen_shri_i64(t0, t0, 32);
288 tcg_gen_trunc_i64_i32(d2, t0);
b41f7df0
EI		 289
290 tcg_gen_discard_i64(t0);
291 tcg_gen_discard_i64(t1);
3157a0a9
EI		 292}
293
d059c172
EI		 294/* 32bit branch-free binary search for counting leading zeros. */
295static void t_gen_lz_i32(TCGv d, TCGv x)
296{
297 TCGv y, m, n;
298
299 y = tcg_temp_new(TCG_TYPE_I32);
300 m = tcg_temp_new(TCG_TYPE_I32);
301 n = tcg_temp_new(TCG_TYPE_I32);
302
303 /* y = -(x >> 16) */
304 tcg_gen_shri_i32(y, x, 16);
390efc54 305 tcg_gen_neg_i32(y, y);
d059c172
EI		 306
307 /* m = (y >> 16) & 16 */
308 tcg_gen_sari_i32(m, y, 16);
309 tcg_gen_andi_i32(m, m, 16);
310
311 /* n = 16 - m */
312 tcg_gen_sub_i32(n, tcg_const_i32(16), m);
313 /* x = x >> m */
314 tcg_gen_shr_i32(x, x, m);
315
316 /* y = x - 0x100 */
317 tcg_gen_subi_i32(y, x, 0x100);
318 /* m = (y >> 16) & 8 */
319 tcg_gen_sari_i32(m, y, 16);
320 tcg_gen_andi_i32(m, m, 8);
321 /* n = n + m */
322 tcg_gen_add_i32(n, n, m);
323 /* x = x << m */
324 tcg_gen_shl_i32(x, x, m);
325
326 /* y = x - 0x1000 */
327 tcg_gen_subi_i32(y, x, 0x1000);
328 /* m = (y >> 16) & 4 */
329 tcg_gen_sari_i32(m, y, 16);
330 tcg_gen_andi_i32(m, m, 4);
331 /* n = n + m */
332 tcg_gen_add_i32(n, n, m);
333 /* x = x << m */
334 tcg_gen_shl_i32(x, x, m);
335
336 /* y = x - 0x4000 */
337 tcg_gen_subi_i32(y, x, 0x4000);
338 /* m = (y >> 16) & 2 */
339 tcg_gen_sari_i32(m, y, 16);
340 tcg_gen_andi_i32(m, m, 2);
341 /* n = n + m */
342 tcg_gen_add_i32(n, n, m);
343 /* x = x << m */
344 tcg_gen_shl_i32(x, x, m);
345
346 /* y = x >> 14 */
347 tcg_gen_shri_i32(y, x, 14);
348 /* m = y & ~(y >> 1) */
349 tcg_gen_sari_i32(m, y, 1);
d1896336 350 tcg_gen_not_i32(m, m);
d059c172
EI		 351 tcg_gen_and_i32(m, m, y);
352
353 /* d = n + 2 - m */
354 tcg_gen_addi_i32(d, n, 2);
355 tcg_gen_sub_i32(d, d, m);
356
357 tcg_gen_discard_i32(y);
358 tcg_gen_discard_i32(m);
359 tcg_gen_discard_i32(n);
360}
361
dceaf394
EI		 362static void t_gen_btst(TCGv d, TCGv s)
363{
364 TCGv sbit;
365 TCGv bset;
366 int l1;
367
368 /* des ref:
369 The N flag is set according to the selected bit in the dest reg.
370 The Z flag is set if the selected bit and all bits to the right are
371 zero.
372 The X flag is cleared.
373 Other flags are left untouched.
374 The destination reg is not affected.
375
376 unsigned int fz, sbit, bset, mask, masked_t0;
377
378 sbit = T1 & 31;
379 bset = !!(T0 & (1 << sbit));
380 mask = sbit == 31 ? -1 : (1 << (sbit + 1)) - 1;
381 masked_t0 = T0 & mask;
382 fz = !(masked_t0 | bset);
383
384 // Clear the X, N and Z flags.
385 T0 = env->pregs[PR_CCS] & ~(X_FLAG | N_FLAG | Z_FLAG);
386 // Set the N and Z flags accordingly.
387 T0 |= (bset << 3) | (fz << 2);
388 */
389
390 l1 = gen_new_label();
391 sbit = tcg_temp_new(TCG_TYPE_TL);
392 bset = tcg_temp_new(TCG_TYPE_TL);
393
394 /* Compute bset and sbit. */
395 tcg_gen_andi_tl(sbit, s, 31);
396 tcg_gen_shl_tl(s, tcg_const_tl(1), sbit);
397 tcg_gen_and_tl(bset, d, s);
398 tcg_gen_shr_tl(bset, bset, sbit);
399 /* Displace to N_FLAG. */
400 tcg_gen_shli_tl(bset, bset, 3);
401
402 tcg_gen_shl_tl(sbit, tcg_const_tl(2), sbit);
403 tcg_gen_subi_tl(sbit, sbit, 1);
404 tcg_gen_and_tl(sbit, d, sbit);
405
406 tcg_gen_andi_tl(d, cpu_PR[PR_CCS], ~(X_FLAG | N_FLAG | Z_FLAG));
407 /* or in the N_FLAG. */
408 tcg_gen_or_tl(d, d, bset);
cb63669a 409 tcg_gen_brcondi_tl(TCG_COND_NE, sbit, 0, l1);
dceaf394
EI		 410 /* or in the Z_FLAG. */
411 tcg_gen_ori_tl(d, d, Z_FLAG);
412 gen_set_label(l1);
413
414 tcg_gen_discard_tl(sbit);
415 tcg_gen_discard_tl(bset);
416}
417
aae6b32a
EI		 418static void t_gen_cris_dstep(TCGv d, TCGv s)
419{
420 int l1;
421
422 l1 = gen_new_label();
423
424 /*
425 * d <<= 1
426 * if (d >= s)
427 * d -= s;
428 */
429 tcg_gen_shli_tl(d, d, 1);
430 tcg_gen_brcond_tl(TCG_COND_LTU, d, s, l1);
431 tcg_gen_sub_tl(d, d, s);
432 gen_set_label(l1);
433}
434
3157a0a9
EI		 435/* Extended arithmetics on CRIS. */
436static inline void t_gen_add_flag(TCGv d, int flag)
437{
438 TCGv c;
439
440 c = tcg_temp_new(TCG_TYPE_TL);
441 t_gen_mov_TN_preg(c, PR_CCS);
442 /* Propagate carry into d. */
443 tcg_gen_andi_tl(c, c, 1 << flag);
444 if (flag)
445 tcg_gen_shri_tl(c, c, flag);
446 tcg_gen_add_tl(d, d, c);
b41f7df0 447 tcg_gen_discard_tl(c);
3157a0a9
EI		 448}
449
450static inline void t_gen_addx_carry(TCGv d)
451{
452 TCGv x, c;
453
454 x = tcg_temp_new(TCG_TYPE_TL);
455 c = tcg_temp_new(TCG_TYPE_TL);
456 t_gen_mov_TN_preg(x, PR_CCS);
457 tcg_gen_mov_tl(c, x);
458
459 /* Propagate carry into d if X is set. Branch free. */
460 tcg_gen_andi_tl(c, c, C_FLAG);
461 tcg_gen_andi_tl(x, x, X_FLAG);
462 tcg_gen_shri_tl(x, x, 4);
463
464 tcg_gen_and_tl(x, x, c);
465 tcg_gen_add_tl(d, d, x);
b41f7df0
EI		 466 tcg_gen_discard_tl(x);
467 tcg_gen_discard_tl(c);
3157a0a9
EI		 468}
469
a39f8f3a 470static inline void t_gen_subx_carry(DisasContext *dc, TCGv d)
3157a0a9 471{
a39f8f3a
EI		 472 if (dc->flagx_live) {
473 TCGv x, c;
474
475 x = tcg_temp_new(TCG_TYPE_TL);
476 c = tcg_temp_new(TCG_TYPE_TL);
477 t_gen_mov_TN_preg(x, PR_CCS);
478 tcg_gen_mov_tl(c, x);
479
480 /* Propagate carry into d if X is set. Branch free. */
481 tcg_gen_andi_tl(c, c, C_FLAG);
482 tcg_gen_andi_tl(x, x, X_FLAG);
483 tcg_gen_shri_tl(x, x, 4);
484
485 tcg_gen_and_tl(x, x, c);
486 tcg_gen_sub_tl(d, d, x);
487 tcg_gen_discard_tl(x);
488 tcg_gen_discard_tl(c);
489 } else {
490 if (dc->flags_x) {
491 TCGv c;
492
493 c = tcg_temp_new(TCG_TYPE_TL);
494 /* C flag is already at bit 0. */
495 tcg_gen_andi_tl(c, c, C_FLAG);
496 tcg_gen_add_tl(d, d, c);
497 tcg_gen_discard_tl(c);
498 }
499 }
3157a0a9
EI		 500}
501
502/* Swap the two bytes within each half word of the s operand.
503 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
504static inline void t_gen_swapb(TCGv d, TCGv s)
505{
506 TCGv t, org_s;
507
508 t = tcg_temp_new(TCG_TYPE_TL);
509 org_s = tcg_temp_new(TCG_TYPE_TL);
510
511 /* d and s may refer to the same object. */
512 tcg_gen_mov_tl(org_s, s);
513 tcg_gen_shli_tl(t, org_s, 8);
514 tcg_gen_andi_tl(d, t, 0xff00ff00);
515 tcg_gen_shri_tl(t, org_s, 8);
516 tcg_gen_andi_tl(t, t, 0x00ff00ff);
517 tcg_gen_or_tl(d, d, t);
b41f7df0
EI		 518 tcg_gen_discard_tl(t);
519 tcg_gen_discard_tl(org_s);
3157a0a9
EI		 520}
521
522/* Swap the halfwords of the s operand. */
523static inline void t_gen_swapw(TCGv d, TCGv s)
524{
525 TCGv t;
526 /* d and s refer the same object. */
527 t = tcg_temp_new(TCG_TYPE_TL);
528 tcg_gen_mov_tl(t, s);
529 tcg_gen_shli_tl(d, t, 16);
530 tcg_gen_shri_tl(t, t, 16);
531 tcg_gen_or_tl(d, d, t);
b41f7df0 532 tcg_gen_discard_tl(t);
3157a0a9
EI		 533}
534
535/* Reverse the within each byte.
536 T0 = (((T0 << 7) & 0x80808080) |
537 ((T0 << 5) & 0x40404040) |
538 ((T0 << 3) & 0x20202020) |
539 ((T0 << 1) & 0x10101010) |
540 ((T0 >> 1) & 0x08080808) |
541 ((T0 >> 3) & 0x04040404) |
542 ((T0 >> 5) & 0x02020202) |
543 ((T0 >> 7) & 0x01010101));
544 */
545static inline void t_gen_swapr(TCGv d, TCGv s)
546{
547 struct {
548 int shift; /* LSL when positive, LSR when negative. */
549 uint32_t mask;
550 } bitrev [] = {
551 {7, 0x80808080},
552 {5, 0x40404040},
553 {3, 0x20202020},
554 {1, 0x10101010},
555 {-1, 0x08080808},
556 {-3, 0x04040404},
557 {-5, 0x02020202},
558 {-7, 0x01010101}
559 };
560 int i;
561 TCGv t, org_s;
562
563 /* d and s refer the same object. */
564 t = tcg_temp_new(TCG_TYPE_TL);
565 org_s = tcg_temp_new(TCG_TYPE_TL);
566 tcg_gen_mov_tl(org_s, s);
567
568 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
569 tcg_gen_andi_tl(d, t, bitrev[0].mask);
570 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
571 if (bitrev[i].shift >= 0) {
572 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
573 } else {
574 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
575 }
576 tcg_gen_andi_tl(t, t, bitrev[i].mask);
577 tcg_gen_or_tl(d, d, t);
578 }
b41f7df0
EI		 579 tcg_gen_discard_tl(t);
580 tcg_gen_discard_tl(org_s);
3157a0a9
EI		 581}
582
cf1d97f0 583static void t_gen_cc_jmp(TCGv pc_true, TCGv pc_false)
17ac9754
EI		 584{
585 TCGv btaken;
586 int l1;
587
588 l1 = gen_new_label();
589 btaken = tcg_temp_new(TCG_TYPE_TL);
590
591 /* Conditional jmp. */
592 t_gen_mov_TN_env(btaken, btaken);
cf1d97f0 593 tcg_gen_mov_tl(env_pc, pc_false);
cb63669a 594 tcg_gen_brcondi_tl(TCG_COND_EQ, btaken, 0, l1);
cf1d97f0 595 tcg_gen_mov_tl(env_pc, pc_true);
17ac9754
EI		 596 gen_set_label(l1);
597
598 tcg_gen_discard_tl(btaken);
599}
600
8170028d
TS		 601static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
602{
603 TranslationBlock *tb;
604 tb = dc->tb;
605 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
05ba7d5f 606 tcg_gen_goto_tb(n);
50cfa95c 607 tcg_gen_movi_tl(env_pc, dest);
05ba7d5f 608 tcg_gen_exit_tb((long)tb + n);
8170028d 609 } else {
50cfa95c 610 tcg_gen_mov_tl(env_pc, cpu_T[0]);
05ba7d5f 611 tcg_gen_exit_tb(0);
8170028d 612 }
8170028d
TS		 613}
614
615/* Sign extend at translation time. */
616static int sign_extend(unsigned int val, unsigned int width)
617{
618 int sval;
619
620 /* LSL. */
621 val <<= 31 - width;
622 sval = val;
623 /* ASR. */
624 sval >>= 31 - width;
625 return sval;
626}
627
05ba7d5f
EI		 628static inline void cris_clear_x_flag(DisasContext *dc)
629{
b41f7df0
EI		 630 if (!dc->flagx_live
631 || (dc->flagx_live && dc->flags_x)
a39f8f3a 632 || dc->cc_op == CC_OP_FLAGS)
b41f7df0
EI		 633 tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
634 dc->flagx_live = 1;
635 dc->flags_x = 0;
05ba7d5f
EI		 636}
637
8170028d
TS		 638static void cris_evaluate_flags(DisasContext *dc)
639{
640 if (!dc->flags_live) {
b41f7df0
EI		 641 tcg_gen_movi_tl(cc_op, dc->cc_op);
642 tcg_gen_movi_tl(cc_size, dc->cc_size);
643 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
644
8170028d
TS		 645 switch (dc->cc_op)
646 {
647 case CC_OP_MCP:
b41f7df0 648 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
8170028d
TS		 649 break;
650 case CC_OP_MULS:
b41f7df0 651 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
8170028d
TS		 652 break;
653 case CC_OP_MULU:
b41f7df0 654 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
8170028d
TS		 655 break;
656 case CC_OP_MOVE:
657 switch (dc->cc_size)
658 {
659 case 4:
b41f7df0 660 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
8170028d
TS		 661 break;
662 case 2:
b41f7df0 663 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
8170028d
TS		 664 break;
665 default:
b41f7df0 666 tcg_gen_helper_0_0(helper_evaluate_flags);
8170028d
TS		 667 break;
668 }
669 break;
b41f7df0
EI		 670 case CC_OP_FLAGS:
671 /* live. */
672 break;
8170028d
TS		 673 default:
674 {
675 switch (dc->cc_size)
676 {
677 case 4:
b41f7df0 678 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
8170028d
TS		 679 break;
680 default:
b41f7df0 681 tcg_gen_helper_0_0(helper_evaluate_flags);
8170028d
TS		 682 break;
683 }
684 }
685 break;
686 }
687 dc->flags_live = 1;
688 }
689}
690
691static void cris_cc_mask(DisasContext *dc, unsigned int mask)
692{
693 uint32_t ovl;
694
fd56059f
AZ		 695 /* Check if we need to evaluate the condition codes due to
696 CC overlaying. */
8170028d
TS		 697 ovl = (dc->cc_mask ^ mask) & ~mask;
698 if (ovl) {
699 /* TODO: optimize this case. It trigs all the time. */
700 cris_evaluate_flags (dc);
701 }
702 dc->cc_mask = mask;
8170028d 703 dc->update_cc = 1;
a825e703 704
8170028d
TS		 705 if (mask == 0)
706 dc->update_cc = 0;
a825e703 707 else
8170028d 708 dc->flags_live = 0;
8170028d
TS		 709}
710
b41f7df0 711static void cris_update_cc_op(DisasContext *dc, int op, int size)
8170028d
TS		 712{
713 dc->cc_op = op;
8170028d 714 dc->cc_size = size;
b41f7df0 715 dc->flags_live = 0;
8170028d
TS		 716}
717
718/* op is the operation.
719 T0, T1 are the operands.
720 dst is the destination reg.
721*/
722static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
723{
724 int writeback = 1;
725 if (dc->update_cc) {
b41f7df0 726 cris_update_cc_op(dc, op, size);
cf1d97f0
EI		 727 if (op != CC_OP_MOVE)
728 tcg_gen_mov_tl(cc_dest, cpu_T[0]);
3157a0a9
EI		 729
730 /* FIXME: This shouldn't be needed. But we don't pass the
cf1d97f0 731 tests without it. Investigate. */
3157a0a9
EI		 732 t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
733 t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
8170028d
TS		 734 }
735
736 /* Emit the ALU insns. */
737 switch (op)
738 {
739 case CC_OP_ADD:
05ba7d5f 740 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d 741 /* Extended arithmetics. */
3157a0a9 742 t_gen_addx_carry(cpu_T[0]);
8170028d
TS		 743 break;
744 case CC_OP_ADDC:
05ba7d5f 745 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3157a0a9 746 t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */
8170028d
TS		 747 break;
748 case CC_OP_MCP:
05ba7d5f 749 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
3157a0a9 750 t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
8170028d
TS		 751 break;
752 case CC_OP_SUB:
390efc54 753 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
05ba7d5f 754 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
390efc54 755 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
8170028d 756 /* CRIS flag evaluation needs ~src. */
d1896336 757 tcg_gen_not_tl(cpu_T[1], cpu_T[1]);
8170028d
TS		 758
759 /* Extended arithmetics. */
a39f8f3a 760 t_gen_subx_carry(dc, cpu_T[0]);
8170028d
TS		 761 break;
762 case CC_OP_MOVE:
05ba7d5f 763 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
8170028d
TS		 764 break;
765 case CC_OP_OR:
05ba7d5f 766 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d
TS		 767 break;
768 case CC_OP_AND:
05ba7d5f 769 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d
TS		 770 break;
771 case CC_OP_XOR:
05ba7d5f 772 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d
TS		 773 break;
774 case CC_OP_LSL:
05ba7d5f 775 t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d
TS		 776 break;
777 case CC_OP_LSR:
05ba7d5f 778 t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d
TS		 779 break;
780 case CC_OP_ASR:
05ba7d5f 781 t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
8170028d
TS		 782 break;
783 case CC_OP_NEG:
390efc54 784 tcg_gen_neg_tl(cpu_T[0], cpu_T[1]);
8170028d 785 /* Extended arithmetics. */
a39f8f3a 786 t_gen_subx_carry(dc, cpu_T[0]);
8170028d
TS		 787 break;
788 case CC_OP_LZ:
d059c172 789 t_gen_lz_i32(cpu_T[0], cpu_T[1]);
8170028d
TS		 790 break;
791 case CC_OP_BTST:
dceaf394 792 t_gen_btst(cpu_T[0], cpu_T[1]);
8170028d
TS		 793 writeback = 0;
794 break;
795 case CC_OP_MULS:
3157a0a9
EI		 796 {
797 TCGv mof;
798 mof = tcg_temp_new(TCG_TYPE_TL);
799 t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
cf1d97f0 800 t_gen_mov_preg_TN(dc, PR_MOF, mof);
b41f7df0 801 tcg_gen_discard_tl(mof);
3157a0a9
EI		 802 }
803 break;
8170028d 804 case CC_OP_MULU:
3157a0a9
EI		 805 {
806 TCGv mof;
807 mof = tcg_temp_new(TCG_TYPE_TL);
808 t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
cf1d97f0 809 t_gen_mov_preg_TN(dc, PR_MOF, mof);
b41f7df0 810 tcg_gen_discard_tl(mof);
3157a0a9
EI		 811 }
812 break;
8170028d 813 case CC_OP_DSTEP:
aae6b32a 814 t_gen_cris_dstep(cpu_T[0], cpu_T[1]);
8170028d
TS		 815 break;
816 case CC_OP_BOUND:
3157a0a9
EI		 817 {
818 int l1;
819 l1 = gen_new_label();
820 tcg_gen_brcond_tl(TCG_COND_LEU,
821 cpu_T[0], cpu_T[1], l1);
822 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
823 gen_set_label(l1);
824 }
825 break;
8170028d 826 case CC_OP_CMP:
a39f8f3a 827 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
05ba7d5f 828 /* CRIS flag evaluation needs ~src. */
d1896336 829 tcg_gen_not_tl(cpu_T[1], cpu_T[1]);
8170028d
TS		 830
831 /* Extended arithmetics. */
a39f8f3a 832 t_gen_subx_carry(dc, cpu_T[0]);
8170028d
TS		 833 writeback = 0;
834 break;
835 default:
836 fprintf (logfile, "illegal ALU op.\n");
837 BUG();
838 break;
839 }
840
841 if (dc->update_cc)
a825e703 842 tcg_gen_mov_tl(cc_src, cpu_T[1]);
8170028d
TS		 843
844 if (size == 1)
05ba7d5f 845 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
8170028d 846 else if (size == 2)
05ba7d5f
EI		 847 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
848
8170028d
TS		 849 /* Writeback. */
850 if (writeback) {
851 if (size == 4)
a39f8f3a 852 tcg_gen_mov_tl(cpu_R[rd], cpu_T[0]);
8170028d 853 else {
8170028d 854 if (size == 1)
a39f8f3a 855 tcg_gen_andi_tl(cpu_R[rd], cpu_R[rd], ~0xff);
8170028d 856 else
a39f8f3a
EI		 857 tcg_gen_andi_tl(cpu_R[rd], cpu_R[rd], ~0xffff);
858 tcg_gen_or_tl(cpu_R[rd], cpu_R[rd], cpu_T[0]);
8170028d
TS		 859 }
860 }
861 if (dc->update_cc)
a825e703 862 tcg_gen_mov_tl(cc_result, cpu_T[0]);
8170028d
TS		 863}
864
865static int arith_cc(DisasContext *dc)
866{
867 if (dc->update_cc) {
868 switch (dc->cc_op) {
869 case CC_OP_ADD: return 1;
870 case CC_OP_SUB: return 1;
871 case CC_OP_LSL: return 1;
872 case CC_OP_LSR: return 1;
873 case CC_OP_ASR: return 1;
874 case CC_OP_CMP: return 1;
875 default:
876 return 0;
877 }
878 }
879 return 0;
880}
881
882static void gen_tst_cc (DisasContext *dc, int cond)
883{
884 int arith_opt;
885
886 /* TODO: optimize more condition codes. */
dceaf394
EI		 887
888 /*
889 * If the flags are live, we've gotta look into the bits of CCS.
890 * Otherwise, if we just did an arithmetic operation we try to
891 * evaluate the condition code faster.
892 *
893 * When this function is done, T0 should be non-zero if the condition
894 * code is true.
895 */
8170028d
TS		 896 arith_opt = arith_cc(dc) && !dc->flags_live;
897 switch (cond) {
898 case CC_EQ:
dceaf394
EI		 899 if (arith_opt) {
900 /* If cc_result is zero, T0 should be
901 non-zero otherwise T0 should be zero. */
902 int l1;
903 l1 = gen_new_label();
904 tcg_gen_movi_tl(cpu_T[0], 0);
cb63669a
PB		 905 tcg_gen_brcondi_tl(TCG_COND_NE, cc_result,
906 0, l1);
dceaf394
EI		 907 tcg_gen_movi_tl(cpu_T[0], 1);
908 gen_set_label(l1);
909 }
8170028d
TS		 910 else {
911 cris_evaluate_flags(dc);
dceaf394
EI		 912 tcg_gen_andi_tl(cpu_T[0],
913 cpu_PR[PR_CCS], Z_FLAG);
8170028d
TS		 914 }
915 break;
916 case CC_NE:
917 if (arith_opt)
dceaf394 918 tcg_gen_mov_tl(cpu_T[0], cc_result);
8170028d
TS		 919 else {
920 cris_evaluate_flags(dc);
dceaf394
EI		 921 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
922 Z_FLAG);
923 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
8170028d
TS		 924 }
925 break;
926 case CC_CS:
927 cris_evaluate_flags(dc);
dceaf394 928 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], C_FLAG);
8170028d
TS		 929 break;
930 case CC_CC:
931 cris_evaluate_flags(dc);
dceaf394
EI		 932 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
933 C_FLAG);
934 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], C_FLAG);
8170028d
TS		 935 break;
936 case CC_VS:
937 cris_evaluate_flags(dc);
dceaf394 938 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], V_FLAG);
8170028d
TS		 939 break;
940 case CC_VC:
941 cris_evaluate_flags(dc);
dceaf394
EI		 942 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
943 V_FLAG);
944 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], V_FLAG);
8170028d
TS		 945 break;
946 case CC_PL:
947 if (arith_opt)
dceaf394 948 tcg_gen_shli_tl(cpu_T[0], cc_result, 31);
8170028d
TS		 949 else {
950 cris_evaluate_flags(dc);
dceaf394
EI		 951 tcg_gen_xori_tl(cpu_T[0], cpu_PR[PR_CCS],
952 N_FLAG);
953 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
8170028d
TS		 954 }
955 break;
956 case CC_MI:
dceaf394
EI		 957 if (arith_opt) {
958 tcg_gen_shli_tl(cpu_T[0], cc_result, 31);
959 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
960 }
8170028d
TS		 961 else {
962 cris_evaluate_flags(dc);
dceaf394
EI		 963 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
964 N_FLAG);
8170028d
TS		 965 }
966 break;
967 case CC_LS:
968 cris_evaluate_flags(dc);
dceaf394
EI		 969 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS],
970 C_FLAG | Z_FLAG);
8170028d
TS		 971 break;
972 case CC_HI:
973 cris_evaluate_flags(dc);
dceaf394
EI		 974 {
975 TCGv tmp;
976
977 tmp = tcg_temp_new(TCG_TYPE_TL);
978 tcg_gen_xori_tl(tmp, cpu_PR[PR_CCS],
979 C_FLAG | Z_FLAG);
980 /* Overlay the C flag on top of the Z. */
981 tcg_gen_shli_tl(cpu_T[0], tmp, 2);
982 tcg_gen_and_tl(cpu_T[0], tmp, cpu_T[0]);
983 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], Z_FLAG);
984
985 tcg_gen_discard_tl(tmp);
986 }
8170028d
TS		 987 break;
988 case CC_GE:
989 cris_evaluate_flags(dc);
dceaf394
EI		 990 /* Overlay the V flag on top of the N. */
991 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
992 tcg_gen_xor_tl(cpu_T[0],
993 cpu_PR[PR_CCS], cpu_T[0]);
994 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
995 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], N_FLAG);
8170028d
TS		 996 break;
997 case CC_LT:
998 cris_evaluate_flags(dc);
dceaf394
EI		 999 /* Overlay the V flag on top of the N. */
1000 tcg_gen_shli_tl(cpu_T[0], cpu_PR[PR_CCS], 2);
1001 tcg_gen_xor_tl(cpu_T[0],
1002 cpu_PR[PR_CCS], cpu_T[0]);
1003 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], N_FLAG);
8170028d
TS		 1004 break;
1005 case CC_GT:
1006 cris_evaluate_flags(dc);
dceaf394
EI		 1007 {
1008 TCGv n, z;
1009
1010 n = tcg_temp_new(TCG_TYPE_TL);
1011 z = tcg_temp_new(TCG_TYPE_TL);
1012
1013 /* To avoid a shift we overlay everything on
1014 the V flag. */
1015 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1016 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1017 /* invert Z. */
1018 tcg_gen_xori_tl(z, z, 2);
1019
1020 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1021 tcg_gen_xori_tl(n, n, 2);
1022 tcg_gen_and_tl(cpu_T[0], z, n);
1023 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1024
1025 tcg_gen_discard_tl(n);
1026 tcg_gen_discard_tl(z);
1027 }
8170028d
TS		 1028 break;
1029 case CC_LE:
1030 cris_evaluate_flags(dc);
dceaf394
EI		 1031 {
1032 TCGv n, z;
1033
1034 n = tcg_temp_new(TCG_TYPE_TL);
1035 z = tcg_temp_new(TCG_TYPE_TL);
1036
1037 /* To avoid a shift we overlay everything on
1038 the V flag. */
1039 tcg_gen_shri_tl(n, cpu_PR[PR_CCS], 2);
1040 tcg_gen_shri_tl(z, cpu_PR[PR_CCS], 1);
1041
1042 tcg_gen_xor_tl(n, n, cpu_PR[PR_CCS]);
1043 tcg_gen_or_tl(cpu_T[0], z, n);
1044 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 2);
1045
1046 tcg_gen_discard_tl(n);
1047 tcg_gen_discard_tl(z);
1048 }
8170028d
TS		 1049 break;
1050 case CC_P:
1051 cris_evaluate_flags(dc);
dceaf394 1052 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], P_FLAG);
8170028d
TS		 1053 break;
1054 case CC_A:
17ac9754 1055 tcg_gen_movi_tl(cpu_T[0], 1);
8170028d
TS		 1056 break;
1057 default:
1058 BUG();
1059 break;
1060 };
1061}
1062
1063static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)
1064{
1065 /* This helps us re-schedule the micro-code to insns in delay-slots
1066 before the actual jump. */
1067 dc->delayed_branch = 2;
8170028d
TS		 1068 if (cond != CC_A)
1069 {
1070 gen_tst_cc (dc, cond);
dceaf394 1071 t_gen_mov_env_TN(btaken, cpu_T[0]);
cf1d97f0
EI		 1072 } else
1073 t_gen_mov_env_TN(btaken, tcg_const_tl(1));
1074 tcg_gen_movi_tl(env_btarget, dc->pc + offset);
8170028d
TS		 1075}
1076
b41f7df0 1077
8170028d
TS		 1078/* Dynamic jumps, when the dest is in a live reg for example. */
1079void cris_prepare_dyn_jmp (DisasContext *dc)
1080{
1081 /* This helps us re-schedule the micro-code to insns in delay-slots
1082 before the actual jump. */
1083 dc->delayed_branch = 2;
cf1d97f0 1084 t_gen_mov_env_TN(btaken, tcg_const_tl(1));
8170028d
TS		 1085}
1086
b41f7df0
EI		 1087void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
1088 unsigned int size, int sign)
8170028d 1089{
b41f7df0
EI		 1090 int mem_index = cpu_mmu_index(dc->env);
1091
cf1d97f0 1092 cris_evaluate_flags(dc);
8170028d
TS		 1093 if (size == 1) {
1094 if (sign)
b41f7df0 1095 tcg_gen_qemu_ld8s(dst, addr, mem_index);
8170028d 1096 else
b41f7df0 1097 tcg_gen_qemu_ld8u(dst, addr, mem_index);
8170028d
TS		 1098 }
1099 else if (size == 2) {
1100 if (sign)
b41f7df0 1101 tcg_gen_qemu_ld16s(dst, addr, mem_index);
8170028d 1102 else
b41f7df0 1103 tcg_gen_qemu_ld16u(dst, addr, mem_index);
8170028d
TS		 1104 }
1105 else {
b41f7df0 1106 tcg_gen_qemu_ld32s(dst, addr, mem_index);
8170028d
TS		 1107 }
1108}
1109
17ac9754
EI		 1110void gen_store (DisasContext *dc, TCGv addr, TCGv val,
1111 unsigned int size)
8170028d 1112{
b41f7df0
EI		 1113 int mem_index = cpu_mmu_index(dc->env);
1114
b41f7df0
EI		 1115 cris_evaluate_flags(dc);
1116
8170028d 1117 /* Remember, operands are flipped. CRIS has reversed order. */
b41f7df0 1118 if (size == 1)
17ac9754 1119 tcg_gen_qemu_st8(val, addr, mem_index);
b41f7df0 1120 else if (size == 2)
17ac9754 1121 tcg_gen_qemu_st16(val, addr, mem_index);
8170028d 1122 else
17ac9754 1123 tcg_gen_qemu_st32(val, addr, mem_index);
8170028d
TS		 1124}
1125
05ba7d5f 1126static inline void t_gen_sext(TCGv d, TCGv s, int size)
8170028d
TS		 1127{
1128 if (size == 1)
05ba7d5f 1129 tcg_gen_ext8s_i32(d, s);
8170028d 1130 else if (size == 2)
05ba7d5f 1131 tcg_gen_ext16s_i32(d, s);
50cfa95c
EI		 1132 else
1133 tcg_gen_mov_tl(d, s);
8170028d
TS		 1134}
1135
05ba7d5f 1136static inline void t_gen_zext(TCGv d, TCGv s, int size)
8170028d
TS		 1137{
1138 if (size == 1)
86831435 1139 tcg_gen_ext8u_i32(d, s);
8170028d 1140 else if (size == 2)
86831435 1141 tcg_gen_ext16u_i32(d, s);
50cfa95c
EI		 1142 else
1143 tcg_gen_mov_tl(d, s);
8170028d
TS		 1144}
1145
1146#if DISAS_CRIS
1147static char memsize_char(int size)
1148{
1149 switch (size)
1150 {
1151 case 1: return 'b'; break;
1152 case 2: return 'w'; break;
1153 case 4: return 'd'; break;
1154 default:
1155 return 'x';
1156 break;
1157 }
1158}
1159#endif
1160
1161static unsigned int memsize_z(DisasContext *dc)
1162{
1163 return dc->zsize + 1;
1164}
1165
1166static unsigned int memsize_zz(DisasContext *dc)
1167{
1168 switch (dc->zzsize)
1169 {
1170 case 0: return 1;
1171 case 1: return 2;
1172 default:
1173 return 4;
1174 }
1175}
1176
c7d05695 1177static inline void do_postinc (DisasContext *dc, int size)
8170028d 1178{
c7d05695
EI		 1179 if (dc->postinc)
1180 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
8170028d
TS		 1181}
1182
8170028d
TS		 1183static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
1184 int size, int s_ext)
1185{
8170028d 1186 if (s_ext)
50cfa95c 1187 t_gen_sext(cpu_T[1], cpu_R[rs], size);
8170028d 1188 else
50cfa95c 1189 t_gen_zext(cpu_T[1], cpu_R[rs], size);
8170028d
TS		 1190}
1191
1192/* Prepare T0 and T1 for a register alu operation.
1193 s_ext decides if the operand1 should be sign-extended or zero-extended when
1194 needed. */
1195static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
1196 int size, int s_ext)
1197{
1198 dec_prep_move_r(dc, rs, rd, size, s_ext);
1199
8170028d 1200 if (s_ext)
50cfa95c 1201 t_gen_sext(cpu_T[0], cpu_R[rd], size);
8170028d 1202 else
50cfa95c 1203 t_gen_zext(cpu_T[0], cpu_R[rd], size);
8170028d
TS		 1204}
1205
cf1d97f0 1206static int dec_prep_move_m(DisasContext *dc, int s_ext, int memsize)
8170028d
TS		 1207{
1208 unsigned int rs, rd;
1209 uint32_t imm;
1210 int is_imm;
1211 int insn_len = 2;
1212
1213 rs = dc->op1;
1214 rd = dc->op2;
1215 is_imm = rs == 15 && dc->postinc;
1216
1217 /* Load [$rs] onto T1. */
1218 if (is_imm) {
1219 insn_len = 2 + memsize;
1220 if (memsize == 1)
1221 insn_len++;
1222
8170028d
TS		 1223 if (memsize != 4) {
1224 if (s_ext) {
17ac9754
EI		 1225 if (memsize == 1)
1226 imm = ldsb_code(dc->pc + 2);
1227 else
1228 imm = ldsw_code(dc->pc + 2);
8170028d
TS		 1229 } else {
1230 if (memsize == 1)
17ac9754 1231 imm = ldub_code(dc->pc + 2);
8170028d 1232 else
17ac9754 1233 imm = lduw_code(dc->pc + 2);
8170028d 1234 }
17ac9754
EI		 1235 } else
1236 imm = ldl_code(dc->pc + 2);
1237
8170028d 1238 DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
cf1d97f0 1239 imm, rd, s_ext, memsize));
05ba7d5f 1240 tcg_gen_movi_tl(cpu_T[1], imm);
8170028d
TS		 1241 dc->postinc = 0;
1242 } else {
b41f7df0 1243 gen_load(dc, cpu_T[1], cpu_R[rs], memsize, 0);
8170028d 1244 if (s_ext)
05ba7d5f 1245 t_gen_sext(cpu_T[1], cpu_T[1], memsize);
8170028d 1246 else
05ba7d5f 1247 t_gen_zext(cpu_T[1], cpu_T[1], memsize);
8170028d 1248 }
cf1d97f0
EI		 1249 return insn_len;
1250}
1251
1252/* Prepare T0 and T1 for a memory + alu operation.
1253 s_ext decides if the operand1 should be sign-extended or zero-extended when
1254 needed. */
1255static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
1256{
1257 int insn_len;
1258
1259 insn_len = dec_prep_move_m(dc, s_ext, memsize);
8170028d
TS		 1260
1261 /* put dest in T0. */
cf1d97f0 1262 tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op2]);
8170028d
TS		 1263 return insn_len;
1264}
1265
1266#if DISAS_CRIS
1267static const char *cc_name(int cc)
1268{
1269 static char *cc_names[16] = {
1270 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1271 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1272 };
1273 assert(cc < 16);
1274 return cc_names[cc];
1275}
1276#endif
1277
b41f7df0
EI		 1278/* Start of insn decoders. */
1279
8170028d
TS		 1280static unsigned int dec_bccq(DisasContext *dc)
1281{
1282 int32_t offset;
1283 int sign;
1284 uint32_t cond = dc->op2;
1285 int tmp;
1286
1287 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1288 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1289
1290 offset *= 2;
1291 offset |= sign << 8;
1292 tmp = offset;
1293 offset = sign_extend(offset, 8);
1294
1295 /* op2 holds the condition-code. */
1296 cris_cc_mask(dc, 0);
1297 cris_prepare_cc_branch (dc, offset, cond);
1298 return 2;
1299}
1300static unsigned int dec_addoq(DisasContext *dc)
1301{
b41f7df0 1302 int32_t imm;
8170028d
TS		 1303
1304 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1305 imm = sign_extend(dc->op1, 7);
1306
1307 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1308 cris_cc_mask(dc, 0);
1309 /* Fetch register operand, */
b41f7df0 1310 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
8170028d
TS		 1311 return 2;
1312}
1313static unsigned int dec_addq(DisasContext *dc)
1314{
1315 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1316
1317 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1318
1319 cris_cc_mask(dc, CC_MASK_NZVC);
1320 /* Fetch register operand, */
05ba7d5f
EI		 1321 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1322 tcg_gen_movi_tl(cpu_T[1], dc->op1);
8170028d
TS		 1323 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1324 return 2;
1325}
1326static unsigned int dec_moveq(DisasContext *dc)
1327{
1328 uint32_t imm;
1329
1330 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1331 imm = sign_extend(dc->op1, 5);
1332 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1333
a39f8f3a 1334 tcg_gen_mov_tl(cpu_R[dc->op2], tcg_const_tl(imm));
8170028d
TS		 1335 return 2;
1336}
1337static unsigned int dec_subq(DisasContext *dc)
1338{
1339 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1340
1341 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1342
1343 cris_cc_mask(dc, CC_MASK_NZVC);
1344 /* Fetch register operand, */
a39f8f3a 1345 tcg_gen_mov_tl(cpu_T[0], cpu_R[dc->op2]);
dceaf394 1346 tcg_gen_movi_tl(cpu_T[1], dc->op1);
8170028d
TS		 1347 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1348 return 2;
1349}
1350static unsigned int dec_cmpq(DisasContext *dc)
1351{
1352 uint32_t imm;
1353 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1354 imm = sign_extend(dc->op1, 5);
1355
1356 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1357 cris_cc_mask(dc, CC_MASK_NZVC);
05ba7d5f 1358 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1359 tcg_gen_movi_tl(cpu_T[1], imm);
8170028d
TS		 1360 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1361 return 2;
1362}
1363static unsigned int dec_andq(DisasContext *dc)
1364{
1365 uint32_t imm;
1366 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1367 imm = sign_extend(dc->op1, 5);
1368
1369 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1370 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1371 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1372 tcg_gen_movi_tl(cpu_T[1], imm);
8170028d
TS		 1373 crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4);
1374 return 2;
1375}
1376static unsigned int dec_orq(DisasContext *dc)
1377{
1378 uint32_t imm;
1379 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1380 imm = sign_extend(dc->op1, 5);
1381 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1382 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1383 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1384 tcg_gen_movi_tl(cpu_T[1], imm);
8170028d
TS		 1385 crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4);
1386 return 2;
1387}
1388static unsigned int dec_btstq(DisasContext *dc)
1389{
1390 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1391 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
17ac9754 1392
8170028d 1393 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1394 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1395 tcg_gen_movi_tl(cpu_T[1], dc->op1);
8170028d
TS		 1396 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1397
b41f7df0 1398 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
cf1d97f0 1399 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
8170028d
TS		 1400 dc->flags_live = 1;
1401 return 2;
1402}
1403static unsigned int dec_asrq(DisasContext *dc)
1404{
1405 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1406 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1407 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1408 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1409 tcg_gen_movi_tl(cpu_T[1], dc->op1);
8170028d
TS		 1410 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4);
1411 return 2;
1412}
1413static unsigned int dec_lslq(DisasContext *dc)
1414{
1415 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1416 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1417
1418 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1419 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1420 tcg_gen_movi_tl(cpu_T[1], dc->op1);
8170028d
TS		 1421 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4);
1422 return 2;
1423}
1424static unsigned int dec_lsrq(DisasContext *dc)
1425{
1426 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1427 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1428
1429 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1430 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
dceaf394 1431 tcg_gen_movi_tl(cpu_T[1], dc->op1);
8170028d
TS		 1432 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4);
1433 return 2;
1434}
1435
1436static unsigned int dec_move_r(DisasContext *dc)
1437{
1438 int size = memsize_zz(dc);
1439
1440 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1441 memsize_char(size), dc->op1, dc->op2));
1442
1443 cris_cc_mask(dc, CC_MASK_NZ);
1444 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1445 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, size);
1446 return 2;
1447}
1448
1449static unsigned int dec_scc_r(DisasContext *dc)
1450{
1451 int cond = dc->op2;
1452
1453 DIS(fprintf (logfile, "s%s $r%u\n",
1454 cc_name(cond), dc->op1));
1455
1456 if (cond != CC_A)
1457 {
dceaf394
EI		 1458 int l1;
1459
8170028d 1460 gen_tst_cc (dc, cond);
dceaf394
EI		 1461
1462 l1 = gen_new_label();
1463 tcg_gen_movi_tl(cpu_R[dc->op1], 0);
cb63669a 1464 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_T[0], 0, l1);
dceaf394
EI		 1465 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
1466 gen_set_label(l1);
8170028d
TS		 1467 }
1468 else
dceaf394 1469 tcg_gen_movi_tl(cpu_R[dc->op1], 1);
8170028d
TS		 1470
1471 cris_cc_mask(dc, 0);
8170028d
TS		 1472 return 2;
1473}
1474
1475static unsigned int dec_and_r(DisasContext *dc)
1476{
1477 int size = memsize_zz(dc);
1478
1479 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1480 memsize_char(size), dc->op1, dc->op2));
1481 cris_cc_mask(dc, CC_MASK_NZ);
1482 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1483 crisv32_alu_op(dc, CC_OP_AND, dc->op2, size);
1484 return 2;
1485}
1486
1487static unsigned int dec_lz_r(DisasContext *dc)
1488{
1489 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1490 dc->op1, dc->op2));
1491 cris_cc_mask(dc, CC_MASK_NZ);
1492 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1493 crisv32_alu_op(dc, CC_OP_LZ, dc->op2, 4);
1494 return 2;
1495}
1496
1497static unsigned int dec_lsl_r(DisasContext *dc)
1498{
1499 int size = memsize_zz(dc);
1500
1501 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1502 memsize_char(size), dc->op1, dc->op2));
1503 cris_cc_mask(dc, CC_MASK_NZ);
1504 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
05ba7d5f 1505 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
8170028d
TS		 1506 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size);
1507 return 2;
1508}
1509
1510static unsigned int dec_lsr_r(DisasContext *dc)
1511{
1512 int size = memsize_zz(dc);
1513
1514 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1515 memsize_char(size), dc->op1, dc->op2));
1516 cris_cc_mask(dc, CC_MASK_NZ);
1517 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
05ba7d5f 1518 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
8170028d
TS		 1519 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size);
1520 return 2;
1521}
1522
1523static unsigned int dec_asr_r(DisasContext *dc)
1524{
1525 int size = memsize_zz(dc);
1526
1527 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1528 memsize_char(size), dc->op1, dc->op2));
1529 cris_cc_mask(dc, CC_MASK_NZ);
1530 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
05ba7d5f 1531 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
8170028d
TS		 1532 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size);
1533 return 2;
1534}
1535
1536static unsigned int dec_muls_r(DisasContext *dc)
1537{
1538 int size = memsize_zz(dc);
1539
1540 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1541 memsize_char(size), dc->op1, dc->op2));
1542 cris_cc_mask(dc, CC_MASK_NZV);
1543 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
05ba7d5f 1544 t_gen_sext(cpu_T[0], cpu_T[0], size);
8170028d
TS		 1545 crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4);
1546 return 2;
1547}
1548
1549static unsigned int dec_mulu_r(DisasContext *dc)
1550{
1551 int size = memsize_zz(dc);
1552
1553 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1554 memsize_char(size), dc->op1, dc->op2));
1555 cris_cc_mask(dc, CC_MASK_NZV);
1556 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
05ba7d5f 1557 t_gen_zext(cpu_T[0], cpu_T[0], size);
8170028d
TS		 1558 crisv32_alu_op(dc, CC_OP_MULU, dc->op2, 4);
1559 return 2;
1560}
1561
1562
1563static unsigned int dec_dstep_r(DisasContext *dc)
1564{
1565 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1566 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f
EI		 1567 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1568 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
8170028d
TS		 1569 crisv32_alu_op(dc, CC_OP_DSTEP, dc->op2, 4);
1570 return 2;
1571}
1572
1573static unsigned int dec_xor_r(DisasContext *dc)
1574{
1575 int size = memsize_zz(dc);
1576 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1577 memsize_char(size), dc->op1, dc->op2));
1578 BUG_ON(size != 4); /* xor is dword. */
1579 cris_cc_mask(dc, CC_MASK_NZ);
1580 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1581 crisv32_alu_op(dc, CC_OP_XOR, dc->op2, 4);
1582 return 2;
1583}
1584
1585static unsigned int dec_bound_r(DisasContext *dc)
1586{
1587 int size = memsize_zz(dc);
1588 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1589 memsize_char(size), dc->op1, dc->op2));
1590 cris_cc_mask(dc, CC_MASK_NZ);
1591 /* TODO: needs optmimization. */
1592 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1593 /* rd should be 4. */
05ba7d5f 1594 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
8170028d
TS		 1595 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
1596 return 2;
1597}
1598
1599static unsigned int dec_cmp_r(DisasContext *dc)
1600{
1601 int size = memsize_zz(dc);
1602 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1603 memsize_char(size), dc->op1, dc->op2));
1604 cris_cc_mask(dc, CC_MASK_NZVC);
1605 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1606 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, size);
1607 return 2;
1608}
1609
1610static unsigned int dec_abs_r(DisasContext *dc)
1611{
3157a0a9
EI		 1612 int l1;
1613
8170028d
TS		 1614 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1615 dc->op1, dc->op2));
1616 cris_cc_mask(dc, CC_MASK_NZ);
1617 dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0);
3157a0a9
EI		 1618
1619 /* TODO: consider a branch free approach. */
1620 l1 = gen_new_label();
cb63669a 1621 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_T[1], 0, l1);
390efc54 1622 tcg_gen_neg_tl(cpu_T[1], cpu_T[1]);
3157a0a9 1623 gen_set_label(l1);
8170028d
TS		 1624 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1625 return 2;
1626}
1627
1628static unsigned int dec_add_r(DisasContext *dc)
1629{
1630 int size = memsize_zz(dc);
1631 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1632 memsize_char(size), dc->op1, dc->op2));
1633 cris_cc_mask(dc, CC_MASK_NZVC);
1634 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1635 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, size);
1636 return 2;
1637}
1638
1639static unsigned int dec_addc_r(DisasContext *dc)
1640{
1641 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1642 dc->op1, dc->op2));
1643 cris_evaluate_flags(dc);
1644 cris_cc_mask(dc, CC_MASK_NZVC);
1645 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1646 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
1647 return 2;
1648}
1649
1650static unsigned int dec_mcp_r(DisasContext *dc)
1651{
1652 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1653 dc->op2, dc->op1));
1654 cris_evaluate_flags(dc);
1655 cris_cc_mask(dc, CC_MASK_RNZV);
05ba7d5f
EI		 1656 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1657 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
8170028d
TS		 1658 crisv32_alu_op(dc, CC_OP_MCP, dc->op1, 4);
1659 return 2;
1660}
1661
1662#if DISAS_CRIS
1663static char * swapmode_name(int mode, char *modename) {
1664 int i = 0;
1665 if (mode & 8)
1666 modename[i++] = 'n';
1667 if (mode & 4)
1668 modename[i++] = 'w';
1669 if (mode & 2)
1670 modename[i++] = 'b';
1671 if (mode & 1)
1672 modename[i++] = 'r';
1673 modename[i++] = 0;
1674 return modename;
1675}
1676#endif
1677
1678static unsigned int dec_swap_r(DisasContext *dc)
1679{
cf1d97f0
EI		 1680#if DISAS_CRIS
1681 char modename[4];
1682#endif
8170028d
TS		 1683 DIS(fprintf (logfile, "swap%s $r%u\n",
1684 swapmode_name(dc->op2, modename), dc->op1));
1685
1686 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1687 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
8170028d 1688 if (dc->op2 & 8)
d1896336 1689 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
8170028d 1690 if (dc->op2 & 4)
3157a0a9 1691 t_gen_swapw(cpu_T[0], cpu_T[0]);
8170028d 1692 if (dc->op2 & 2)
3157a0a9 1693 t_gen_swapb(cpu_T[0], cpu_T[0]);
8170028d 1694 if (dc->op2 & 1)
3157a0a9
EI		 1695 t_gen_swapr(cpu_T[0], cpu_T[0]);
1696 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
8170028d
TS		 1697 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1698 return 2;
1699}
1700
1701static unsigned int dec_or_r(DisasContext *dc)
1702{
1703 int size = memsize_zz(dc);
1704 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1705 memsize_char(size), dc->op1, dc->op2));
1706 cris_cc_mask(dc, CC_MASK_NZ);
1707 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1708 crisv32_alu_op(dc, CC_OP_OR, dc->op2, size);
1709 return 2;
1710}
1711
1712static unsigned int dec_addi_r(DisasContext *dc)
1713{
1714 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1715 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1716 cris_cc_mask(dc, 0);
1717 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
3157a0a9 1718 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
05ba7d5f
EI		 1719 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1720 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
8170028d
TS		 1721 return 2;
1722}
1723
1724static unsigned int dec_addi_acr(DisasContext *dc)
1725{
1726 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
b41f7df0 1727 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
8170028d
TS		 1728 cris_cc_mask(dc, 0);
1729 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
3157a0a9 1730 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
b41f7df0 1731
05ba7d5f
EI		 1732 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1733 t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
8170028d
TS		 1734 return 2;
1735}
1736
1737static unsigned int dec_neg_r(DisasContext *dc)
1738{
1739 int size = memsize_zz(dc);
1740 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1741 memsize_char(size), dc->op1, dc->op2));
1742 cris_cc_mask(dc, CC_MASK_NZVC);
1743 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1744 crisv32_alu_op(dc, CC_OP_NEG, dc->op2, size);
1745 return 2;
1746}
1747
1748static unsigned int dec_btst_r(DisasContext *dc)
1749{
1750 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1751 dc->op1, dc->op2));
8170028d
TS		 1752 cris_cc_mask(dc, CC_MASK_NZ);
1753 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1754 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1755
b41f7df0 1756 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
cf1d97f0 1757 t_gen_mov_preg_TN(dc, PR_CCS, cpu_T[0]);
8170028d
TS		 1758 dc->flags_live = 1;
1759 return 2;
1760}
1761
1762static unsigned int dec_sub_r(DisasContext *dc)
1763{
1764 int size = memsize_zz(dc);
1765 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1766 memsize_char(size), dc->op1, dc->op2));
1767 cris_cc_mask(dc, CC_MASK_NZVC);
1768 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1769 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, size);
1770 return 2;
1771}
1772
1773/* Zero extension. From size to dword. */
1774static unsigned int dec_movu_r(DisasContext *dc)
1775{
1776 int size = memsize_z(dc);
1777 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1778 memsize_char(size),
1779 dc->op1, dc->op2));
1780
1781 cris_cc_mask(dc, CC_MASK_NZ);
1782 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1783 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1784 return 2;
1785}
1786
1787/* Sign extension. From size to dword. */
1788static unsigned int dec_movs_r(DisasContext *dc)
1789{
1790 int size = memsize_z(dc);
1791 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
1792 memsize_char(size),
1793 dc->op1, dc->op2));
1794
1795 cris_cc_mask(dc, CC_MASK_NZ);
05ba7d5f 1796 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
8170028d 1797 /* Size can only be qi or hi. */
05ba7d5f 1798 t_gen_sext(cpu_T[1], cpu_T[0], size);
8170028d
TS		 1799 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1800 return 2;
1801}
1802
1803/* zero extension. From size to dword. */
1804static unsigned int dec_addu_r(DisasContext *dc)
1805{
1806 int size = memsize_z(dc);
1807 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
1808 memsize_char(size),
1809 dc->op1, dc->op2));
1810
1811 cris_cc_mask(dc, CC_MASK_NZVC);
05ba7d5f 1812 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
8170028d 1813 /* Size can only be qi or hi. */
05ba7d5f
EI		 1814 t_gen_zext(cpu_T[1], cpu_T[1], size);
1815 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
8170028d
TS		 1816 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1817 return 2;
1818}
05ba7d5f 1819
8170028d
TS		 1820/* Sign extension. From size to dword. */
1821static unsigned int dec_adds_r(DisasContext *dc)
1822{
1823 int size = memsize_z(dc);
1824 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
1825 memsize_char(size),
1826 dc->op1, dc->op2));
1827
1828 cris_cc_mask(dc, CC_MASK_NZVC);
05ba7d5f 1829 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
8170028d 1830 /* Size can only be qi or hi. */
05ba7d5f
EI		 1831 t_gen_sext(cpu_T[1], cpu_T[1], size);
1832 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1833
8170028d
TS		 1834 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1835 return 2;
1836}
1837
1838/* Zero extension. From size to dword. */
1839static unsigned int dec_subu_r(DisasContext *dc)
1840{
1841 int size = memsize_z(dc);
1842 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
1843 memsize_char(size),
1844 dc->op1, dc->op2));
1845
1846 cris_cc_mask(dc, CC_MASK_NZVC);
05ba7d5f 1847 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
8170028d 1848 /* Size can only be qi or hi. */
05ba7d5f
EI		 1849 t_gen_zext(cpu_T[1], cpu_T[1], size);
1850 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
8170028d
TS		 1851 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1852 return 2;
1853}
1854
1855/* Sign extension. From size to dword. */
1856static unsigned int dec_subs_r(DisasContext *dc)
1857{
1858 int size = memsize_z(dc);
1859 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
1860 memsize_char(size),
1861 dc->op1, dc->op2));
1862
1863 cris_cc_mask(dc, CC_MASK_NZVC);
05ba7d5f 1864 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
8170028d 1865 /* Size can only be qi or hi. */
05ba7d5f
EI		 1866 t_gen_sext(cpu_T[1], cpu_T[1], size);
1867 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
8170028d
TS		 1868 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1869 return 2;
1870}
1871
1872static unsigned int dec_setclrf(DisasContext *dc)
1873{
1874 uint32_t flags;
1875 int set = (~dc->opcode >> 2) & 1;
1876
1877 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1878 | EXTRACT_FIELD(dc->ir, 0, 3);
1879 DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags));
cf1d97f0 1880 if (set && flags == 0) {
8170028d 1881 DIS(fprintf (logfile, "nop\n"));
cf1d97f0 1882 } else if (!set && (flags & 0x20)) {
8170028d 1883 DIS(fprintf (logfile, "di\n"));
cf1d97f0
EI		 1884 }
1885 else {
8170028d 1886 DIS(fprintf (logfile, "%sf %x\n",
cf1d97f0 1887 set ? "set" : "clr",
8170028d 1888 flags));
cf1d97f0 1889 }
8170028d
TS		 1890
1891 if (set && (flags & X_FLAG)) {
1892 dc->flagx_live = 1;
1893 dc->flags_x = 1;
1894 }
1895
1896 /* Simply decode the flags. */
1897 cris_evaluate_flags (dc);
b41f7df0
EI		 1898 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1899 tcg_gen_movi_tl(cc_op, dc->cc_op);
1900
dceaf394
EI		 1901 if (set) {
1902 if (!dc->user && (flags & U_FLAG)) {
1903 /* Enter user mode. */
1904 t_gen_mov_env_TN(ksp, cpu_R[R_SP]);
1905 tcg_gen_mov_tl(cpu_R[R_SP], cpu_PR[PR_USP]);
cf1d97f0 1906 dc->is_jmp = DISAS_NEXT;
dceaf394
EI		 1907 }
1908 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], flags);
1909 }
8170028d 1910 else
dceaf394
EI		 1911 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~flags);
1912
8170028d 1913 dc->flags_live = 1;
b41f7df0 1914 dc->clear_x = 0;
8170028d
TS		 1915 return 2;
1916}
1917
1918static unsigned int dec_move_rs(DisasContext *dc)
1919{
1920 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
1921 cris_cc_mask(dc, 0);
dceaf394
EI		 1922 tcg_gen_helper_0_2(helper_movl_sreg_reg,
1923 tcg_const_tl(dc->op2), tcg_const_tl(dc->op1));
8170028d
TS		 1924 return 2;
1925}
1926static unsigned int dec_move_sr(DisasContext *dc)
1927{
05ba7d5f 1928 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
8170028d 1929 cris_cc_mask(dc, 0);
dceaf394
EI		 1930 tcg_gen_helper_0_2(helper_movl_reg_sreg,
1931 tcg_const_tl(dc->op1), tcg_const_tl(dc->op2));
8170028d
TS		 1932 return 2;
1933}
dceaf394 1934
8170028d
TS		 1935static unsigned int dec_move_rp(DisasContext *dc)
1936{
1937 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
1938 cris_cc_mask(dc, 0);
b41f7df0
EI		 1939
1940 if (dc->op2 == PR_CCS) {
1941 cris_evaluate_flags(dc);
1942 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1943 if (dc->user) {
1944 /* User space is not allowed to touch all flags. */
1945 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
1946 tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
1947 tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1948 }
1949 }
1950 else
1951 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1952
cf1d97f0 1953 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
b41f7df0
EI		 1954 if (dc->op2 == PR_CCS) {
1955 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1956 dc->flags_live = 1;
1957 }
8170028d
TS		 1958 return 2;
1959}
1960static unsigned int dec_move_pr(DisasContext *dc)
1961{
1962 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
1963 cris_cc_mask(dc, 0);
fd56059f
AZ		 1964 /* Support register 0 is hardwired to zero.
1965 Treat it specially. */
1966 if (dc->op2 == 0)
05ba7d5f 1967 tcg_gen_movi_tl(cpu_T[1], 0);
b41f7df0
EI		 1968 else if (dc->op2 == PR_CCS) {
1969 cris_evaluate_flags(dc);
1970 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1971 } else
05ba7d5f 1972 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
8170028d
TS		 1973 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]);
1974 return 2;
1975}
1976
1977static unsigned int dec_move_mr(DisasContext *dc)
1978{
1979 int memsize = memsize_zz(dc);
1980 int insn_len;
1981 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
1982 memsize_char(memsize),
1983 dc->op1, dc->postinc ? "+]" : "]",
1984 dc->op2));
1985
cf1d97f0 1986 insn_len = dec_prep_move_m(dc, 0, memsize);
b41f7df0 1987 cris_cc_mask(dc, CC_MASK_NZ);
8170028d
TS		 1988 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, memsize);
1989 do_postinc(dc, memsize);
1990 return insn_len;
1991}
1992
1993static unsigned int dec_movs_m(DisasContext *dc)
1994{
1995 int memsize = memsize_z(dc);
1996 int insn_len;
1997 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
1998 memsize_char(memsize),
1999 dc->op1, dc->postinc ? "+]" : "]",
2000 dc->op2));
2001
2002 /* sign extend. */
8170028d 2003 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2004 cris_cc_mask(dc, CC_MASK_NZ);
8170028d
TS		 2005 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2006 do_postinc(dc, memsize);
2007 return insn_len;
2008}
2009
2010static unsigned int dec_addu_m(DisasContext *dc)
2011{
2012 int memsize = memsize_z(dc);
2013 int insn_len;
2014 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
2015 memsize_char(memsize),
2016 dc->op1, dc->postinc ? "+]" : "]",
2017 dc->op2));
2018
2019 /* sign extend. */
8170028d 2020 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2021 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2022 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
2023 do_postinc(dc, memsize);
2024 return insn_len;
2025}
2026
2027static unsigned int dec_adds_m(DisasContext *dc)
2028{
2029 int memsize = memsize_z(dc);
2030 int insn_len;
2031 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
2032 memsize_char(memsize),
2033 dc->op1, dc->postinc ? "+]" : "]",
2034 dc->op2));
2035
2036 /* sign extend. */
8170028d 2037 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2038 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2039 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
2040 do_postinc(dc, memsize);
2041 return insn_len;
2042}
2043
2044static unsigned int dec_subu_m(DisasContext *dc)
2045{
2046 int memsize = memsize_z(dc);
2047 int insn_len;
2048 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
2049 memsize_char(memsize),
2050 dc->op1, dc->postinc ? "+]" : "]",
2051 dc->op2));
2052
2053 /* sign extend. */
8170028d 2054 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2055 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2056 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
2057 do_postinc(dc, memsize);
2058 return insn_len;
2059}
2060
2061static unsigned int dec_subs_m(DisasContext *dc)
2062{
2063 int memsize = memsize_z(dc);
2064 int insn_len;
2065 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
2066 memsize_char(memsize),
2067 dc->op1, dc->postinc ? "+]" : "]",
2068 dc->op2));
2069
2070 /* sign extend. */
8170028d 2071 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2072 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2073 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
2074 do_postinc(dc, memsize);
2075 return insn_len;
2076}
2077
2078static unsigned int dec_movu_m(DisasContext *dc)
2079{
2080 int memsize = memsize_z(dc);
2081 int insn_len;
2082
2083 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
2084 memsize_char(memsize),
2085 dc->op1, dc->postinc ? "+]" : "]",
2086 dc->op2));
2087
8170028d 2088 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2089 cris_cc_mask(dc, CC_MASK_NZ);
8170028d
TS		 2090 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2091 do_postinc(dc, memsize);
2092 return insn_len;
2093}
2094
2095static unsigned int dec_cmpu_m(DisasContext *dc)
2096{
2097 int memsize = memsize_z(dc);
2098 int insn_len;
2099 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
2100 memsize_char(memsize),
2101 dc->op1, dc->postinc ? "+]" : "]",
2102 dc->op2));
2103
8170028d 2104 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2105 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2106 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
2107 do_postinc(dc, memsize);
2108 return insn_len;
2109}
2110
2111static unsigned int dec_cmps_m(DisasContext *dc)
2112{
2113 int memsize = memsize_z(dc);
2114 int insn_len;
2115 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
2116 memsize_char(memsize),
2117 dc->op1, dc->postinc ? "+]" : "]",
2118 dc->op2));
2119
8170028d 2120 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2121 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2122 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2123 do_postinc(dc, memsize);
2124 return insn_len;
2125}
2126
2127static unsigned int dec_cmp_m(DisasContext *dc)
2128{
2129 int memsize = memsize_zz(dc);
2130 int insn_len;
2131 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
2132 memsize_char(memsize),
2133 dc->op1, dc->postinc ? "+]" : "]",
2134 dc->op2));
2135
8170028d 2136 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2137 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2138 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2139 do_postinc(dc, memsize);
2140 return insn_len;
2141}
2142
2143static unsigned int dec_test_m(DisasContext *dc)
2144{
2145 int memsize = memsize_zz(dc);
2146 int insn_len;
2147 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
2148 memsize_char(memsize),
2149 dc->op1, dc->postinc ? "+]" : "]",
2150 dc->op2));
2151
dceaf394
EI		 2152 cris_evaluate_flags(dc);
2153
b41f7df0 2154 insn_len = dec_prep_alu_m(dc, 0, memsize);
8170028d 2155 cris_cc_mask(dc, CC_MASK_NZ);
dceaf394 2156 tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3);
b41f7df0 2157
05ba7d5f
EI		 2158 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
2159 tcg_gen_movi_tl(cpu_T[1], 0);
8170028d
TS		 2160 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
2161 do_postinc(dc, memsize);
2162 return insn_len;
2163}
2164
2165static unsigned int dec_and_m(DisasContext *dc)
2166{
2167 int memsize = memsize_zz(dc);
2168 int insn_len;
2169 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
2170 memsize_char(memsize),
2171 dc->op1, dc->postinc ? "+]" : "]",
2172 dc->op2));
2173
8170028d 2174 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2175 cris_cc_mask(dc, CC_MASK_NZ);
8170028d
TS		 2176 crisv32_alu_op(dc, CC_OP_AND, dc->op2, memsize_zz(dc));
2177 do_postinc(dc, memsize);
2178 return insn_len;
2179}
2180
2181static unsigned int dec_add_m(DisasContext *dc)
2182{
2183 int memsize = memsize_zz(dc);
2184 int insn_len;
2185 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2186 memsize_char(memsize),
2187 dc->op1, dc->postinc ? "+]" : "]",
2188 dc->op2));
2189
8170028d 2190 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2191 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2192 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, memsize_zz(dc));
2193 do_postinc(dc, memsize);
2194 return insn_len;
2195}
2196
2197static unsigned int dec_addo_m(DisasContext *dc)
2198{
2199 int memsize = memsize_zz(dc);
2200 int insn_len;
2201 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
2202 memsize_char(memsize),
2203 dc->op1, dc->postinc ? "+]" : "]",
2204 dc->op2));
2205
8170028d 2206 insn_len = dec_prep_alu_m(dc, 1, memsize);
b41f7df0 2207 cris_cc_mask(dc, 0);
9004627f 2208 crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
8170028d
TS		 2209 do_postinc(dc, memsize);
2210 return insn_len;
2211}
2212
2213static unsigned int dec_bound_m(DisasContext *dc)
2214{
2215 int memsize = memsize_zz(dc);
2216 int insn_len;
2217 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
2218 memsize_char(memsize),
2219 dc->op1, dc->postinc ? "+]" : "]",
2220 dc->op2));
2221
8170028d 2222 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2223 cris_cc_mask(dc, CC_MASK_NZ);
8170028d
TS		 2224 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
2225 do_postinc(dc, memsize);
2226 return insn_len;
2227}
2228
2229static unsigned int dec_addc_mr(DisasContext *dc)
2230{
2231 int insn_len = 2;
2232 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
2233 dc->op1, dc->postinc ? "+]" : "]",
2234 dc->op2));
2235
2236 cris_evaluate_flags(dc);
8170028d 2237 insn_len = dec_prep_alu_m(dc, 0, 4);
b41f7df0 2238 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2239 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
2240 do_postinc(dc, 4);
2241 return insn_len;
2242}
2243
2244static unsigned int dec_sub_m(DisasContext *dc)
2245{
2246 int memsize = memsize_zz(dc);
2247 int insn_len;
2248 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2249 memsize_char(memsize),
2250 dc->op1, dc->postinc ? "+]" : "]",
2251 dc->op2, dc->ir, dc->zzsize));
2252
8170028d 2253 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2254 cris_cc_mask(dc, CC_MASK_NZVC);
8170028d
TS		 2255 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, memsize);
2256 do_postinc(dc, memsize);
2257 return insn_len;
2258}
2259
2260static unsigned int dec_or_m(DisasContext *dc)
2261{
2262 int memsize = memsize_zz(dc);
2263 int insn_len;
2264 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2265 memsize_char(memsize),
2266 dc->op1, dc->postinc ? "+]" : "]",
2267 dc->op2, dc->pc));
2268
8170028d 2269 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0 2270 cris_cc_mask(dc, CC_MASK_NZ);
8170028d
TS		 2271 crisv32_alu_op(dc, CC_OP_OR, dc->op2, memsize_zz(dc));
2272 do_postinc(dc, memsize);
2273 return insn_len;
2274}
2275
2276static unsigned int dec_move_mp(DisasContext *dc)
2277{
2278 int memsize = memsize_zz(dc);
2279 int insn_len = 2;
2280
2281 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2282 memsize_char(memsize),
2283 dc->op1,
2284 dc->postinc ? "+]" : "]",
2285 dc->op2));
2286
8170028d 2287 insn_len = dec_prep_alu_m(dc, 0, memsize);
b41f7df0
EI		 2288 cris_cc_mask(dc, 0);
2289 if (dc->op2 == PR_CCS) {
2290 cris_evaluate_flags(dc);
2291 if (dc->user) {
2292 /* User space is not allowed to touch all flags. */
2293 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2294 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2295 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2296 }
2297 }
2298
cf1d97f0 2299 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[1]);
8170028d
TS		 2300
2301 do_postinc(dc, memsize);
2302 return insn_len;
2303}
2304
2305static unsigned int dec_move_pm(DisasContext *dc)
2306{
2307 int memsize;
2308
2309 memsize = preg_sizes[dc->op2];
2310
fd56059f
AZ		 2311 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2312 memsize_char(memsize),
2313 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
8170028d 2314
fd56059f 2315 /* prepare store. Address in T0, value in T1. */
17ac9754
EI		 2316 if (dc->op2 == PR_CCS)
2317 cris_evaluate_flags(dc);
05ba7d5f 2318 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
17ac9754
EI		 2319 gen_store(dc, cpu_R[dc->op1], cpu_T[1], memsize);
2320
b41f7df0 2321 cris_cc_mask(dc, 0);
8170028d 2322 if (dc->postinc)
17ac9754 2323 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
8170028d
TS		 2324 return 2;
2325}
2326
2327static unsigned int dec_movem_mr(DisasContext *dc)
2328{
17ac9754 2329 TCGv tmp[16];
8170028d
TS		 2330 int i;
2331
2332 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2333 dc->postinc ? "+]" : "]", dc->op2));
2334
05ba7d5f 2335 /* fetch the address into T0 and T1. */
8170028d 2336 for (i = 0; i <= dc->op2; i++) {
17ac9754 2337 tmp[i] = tcg_temp_new(TCG_TYPE_TL);
8170028d 2338 /* Perform the load onto regnum i. Always dword wide. */
17ac9754
EI		 2339 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
2340 gen_load(dc, tmp[i], cpu_T[0], 4, 0);
8170028d 2341 }
17ac9754
EI		 2342
2343 for (i = 0; i <= dc->op2; i++) {
2344 tcg_gen_mov_tl(cpu_R[i], tmp[i]);
2345 tcg_gen_discard_tl(tmp[i]);
2346 }
2347
05ba7d5f
EI		 2348 /* writeback the updated pointer value. */
2349 if (dc->postinc)
17ac9754 2350 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
b41f7df0
EI		 2351
2352 /* gen_load might want to evaluate the previous insns flags. */
2353 cris_cc_mask(dc, 0);
8170028d
TS		 2354 return 2;
2355}
2356
2357static unsigned int dec_movem_rm(DisasContext *dc)
2358{
2359 int i;
2360
2361 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2362 dc->postinc ? "+]" : "]"));
2363
8170028d 2364 for (i = 0; i <= dc->op2; i++) {
17ac9754
EI		 2365 /* Displace addr. */
2366 tcg_gen_addi_tl(cpu_T[0], cpu_R[dc->op1], i * 4);
8170028d 2367 /* Perform the store. */
17ac9754 2368 gen_store(dc, cpu_T[0], cpu_R[i], 4);
8170028d 2369 }
17ac9754
EI		 2370 if (dc->postinc)
2371 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], i * 4);
b41f7df0 2372 cris_cc_mask(dc, 0);
8170028d
TS		 2373 return 2;
2374}
2375
2376static unsigned int dec_move_rm(DisasContext *dc)
2377{
2378 int memsize;
2379
2380 memsize = memsize_zz(dc);
2381
2382 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2383 memsize, dc->op2, dc->op1));
2384
8170028d 2385 /* prepare store. */
17ac9754
EI		 2386 gen_store(dc, cpu_R[dc->op1], cpu_R[dc->op2], memsize);
2387
8170028d 2388 if (dc->postinc)
17ac9754 2389 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], memsize);
b41f7df0 2390 cris_cc_mask(dc, 0);
8170028d
TS		 2391 return 2;
2392}
2393
8170028d
TS		 2394static unsigned int dec_lapcq(DisasContext *dc)
2395{
2396 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2397 dc->pc + dc->op1*2, dc->op2));
2398 cris_cc_mask(dc, 0);
05ba7d5f 2399 tcg_gen_movi_tl(cpu_T[1], dc->pc + dc->op1 * 2);
8170028d
TS		 2400 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2401 return 2;
2402}
2403
2404static unsigned int dec_lapc_im(DisasContext *dc)
2405{
2406 unsigned int rd;
2407 int32_t imm;
b41f7df0 2408 int32_t pc;
8170028d
TS		 2409
2410 rd = dc->op2;
2411
2412 cris_cc_mask(dc, 0);
2413 imm = ldl_code(dc->pc + 2);
2414 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
b41f7df0
EI		 2415
2416 pc = dc->pc;
2417 pc += imm;
2418 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
05ba7d5f 2419 return 6;
8170028d
TS		 2420}
2421
2422/* Jump to special reg. */
2423static unsigned int dec_jump_p(DisasContext *dc)
2424{
2425 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
b41f7df0 2426
17ac9754
EI		 2427 if (dc->op2 == PR_CCS)
2428 cris_evaluate_flags(dc);
05ba7d5f 2429 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
b41f7df0
EI		 2430 /* rete will often have low bit set to indicate delayslot. */
2431 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
17ac9754 2432 cris_cc_mask(dc, 0);
8170028d
TS		 2433 cris_prepare_dyn_jmp(dc);
2434 return 2;
2435}
2436
2437/* Jump and save. */
2438static unsigned int dec_jas_r(DisasContext *dc)
2439{
2440 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2441 cris_cc_mask(dc, 0);
b41f7df0
EI		 2442 /* Store the return address in Pd. */
2443 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2444 if (dc->op2 > 15)
2445 abort();
17ac9754
EI		 2446 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4);
2447 tcg_gen_mov_tl(cpu_PR[dc->op2], cpu_T[0]);
b41f7df0 2448
8170028d
TS		 2449 cris_prepare_dyn_jmp(dc);
2450 return 2;
2451}
2452
2453static unsigned int dec_jas_im(DisasContext *dc)
2454{
2455 uint32_t imm;
2456
2457 imm = ldl_code(dc->pc + 2);
2458
2459 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2460 cris_cc_mask(dc, 0);
17ac9754 2461 /* Store the return address in Pd. */
b41f7df0 2462 tcg_gen_movi_tl(env_btarget, imm);
cf1d97f0 2463 t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8));
8170028d
TS		 2464 cris_prepare_dyn_jmp(dc);
2465 return 6;
2466}
2467
2468static unsigned int dec_jasc_im(DisasContext *dc)
2469{
2470 uint32_t imm;
2471
2472 imm = ldl_code(dc->pc + 2);
2473
2474 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2475 cris_cc_mask(dc, 0);
17ac9754 2476 /* Store the return address in Pd. */
05ba7d5f 2477 tcg_gen_movi_tl(cpu_T[0], imm);
73e51723 2478 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
05ba7d5f 2479 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
cf1d97f0 2480 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
8170028d
TS		 2481 cris_prepare_dyn_jmp(dc);
2482 return 6;
2483}
2484
2485static unsigned int dec_jasc_r(DisasContext *dc)
2486{
2487 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2488 cris_cc_mask(dc, 0);
17ac9754 2489 /* Store the return address in Pd. */
05ba7d5f 2490 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
73e51723 2491 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
05ba7d5f 2492 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
cf1d97f0 2493 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
8170028d
TS		 2494 cris_prepare_dyn_jmp(dc);
2495 return 2;
2496}
2497
2498static unsigned int dec_bcc_im(DisasContext *dc)
2499{
2500 int32_t offset;
2501 uint32_t cond = dc->op2;
2502
17ac9754 2503 offset = ldsw_code(dc->pc + 2);
8170028d
TS		 2504
2505 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2506 cc_name(cond), offset,
2507 dc->pc, dc->pc + offset));
2508
2509 cris_cc_mask(dc, 0);
2510 /* op2 holds the condition-code. */
2511 cris_prepare_cc_branch (dc, offset, cond);
2512 return 4;
2513}
2514
2515static unsigned int dec_bas_im(DisasContext *dc)
2516{
2517 int32_t simm;
2518
2519
2520 simm = ldl_code(dc->pc + 2);
2521
2522 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2523 cris_cc_mask(dc, 0);
2524 /* Stor the return address in Pd. */
05ba7d5f 2525 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
73e51723 2526 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
05ba7d5f 2527 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
cf1d97f0 2528 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
8170028d
TS		 2529 cris_prepare_dyn_jmp(dc);
2530 return 6;
2531}
2532
2533static unsigned int dec_basc_im(DisasContext *dc)
2534{
2535 int32_t simm;
2536 simm = ldl_code(dc->pc + 2);
2537
2538 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2539 cris_cc_mask(dc, 0);
2540 /* Stor the return address in Pd. */
05ba7d5f 2541 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
73e51723 2542 tcg_gen_mov_tl(env_btarget, cpu_T[0]);
05ba7d5f 2543 tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
cf1d97f0 2544 t_gen_mov_preg_TN(dc, dc->op2, cpu_T[0]);
8170028d
TS		 2545 cris_prepare_dyn_jmp(dc);
2546 return 6;
2547}
2548
2549static unsigned int dec_rfe_etc(DisasContext *dc)
2550{
2551 DIS(fprintf (logfile, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2552 dc->opcode, dc->pc, dc->op1, dc->op2));
2553
2554 cris_cc_mask(dc, 0);
2555
2556 if (dc->op2 == 15) /* ignore halt. */
05ba7d5f 2557 return 2;
8170028d
TS		 2558
2559 switch (dc->op2 & 7) {
2560 case 2:
2561 /* rfe. */
2562 cris_evaluate_flags(dc);
b41f7df0
EI		 2563 tcg_gen_helper_0_0(helper_rfe);
2564 dc->is_jmp = DISAS_UPDATE;
8170028d
TS		 2565 break;
2566 case 5:
2567 /* rfn. */
2568 BUG();
2569 break;
2570 case 6:
2571 /* break. */
05ba7d5f 2572 tcg_gen_movi_tl(cpu_T[0], dc->pc);
3157a0a9 2573 t_gen_mov_env_TN(pc, cpu_T[0]);
8170028d 2574 /* Breaks start at 16 in the exception vector. */
dceaf394
EI		 2575 t_gen_mov_env_TN(trap_vector,
2576 tcg_const_tl(dc->op1 + 16));
2577 t_gen_raise_exception(EXCP_BREAK);
b41f7df0 2578 dc->is_jmp = DISAS_UPDATE;
8170028d
TS		 2579 break;
2580 default:
2581 printf ("op2=%x\n", dc->op2);
2582 BUG();
2583 break;
2584
2585 }
8170028d
TS		 2586 return 2;
2587}
2588
5d4a534d
EI		 2589static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2590{
2591 /* Ignore D-cache flushes. */
2592 return 2;
2593}
2594
2595static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2596{
2597 /* Ignore I-cache flushes. */
2598 return 2;
2599}
2600
8170028d
TS		 2601static unsigned int dec_null(DisasContext *dc)
2602{
2603 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2604 dc->pc, dc->opcode, dc->op1, dc->op2);
2605 fflush(NULL);
2606 BUG();
2607 return 2;
2608}
2609
2610struct decoder_info {
2611 struct {
2612 uint32_t bits;
2613 uint32_t mask;
2614 };
2615 unsigned int (*dec)(DisasContext *dc);
2616} decinfo[] = {
2617 /* Order matters here. */
2618 {DEC_MOVEQ, dec_moveq},
2619 {DEC_BTSTQ, dec_btstq},
2620 {DEC_CMPQ, dec_cmpq},
2621 {DEC_ADDOQ, dec_addoq},
2622 {DEC_ADDQ, dec_addq},
2623 {DEC_SUBQ, dec_subq},
2624 {DEC_ANDQ, dec_andq},
2625 {DEC_ORQ, dec_orq},
2626 {DEC_ASRQ, dec_asrq},
2627 {DEC_LSLQ, dec_lslq},
2628 {DEC_LSRQ, dec_lsrq},
2629 {DEC_BCCQ, dec_bccq},
2630
2631 {DEC_BCC_IM, dec_bcc_im},
2632 {DEC_JAS_IM, dec_jas_im},
2633 {DEC_JAS_R, dec_jas_r},
2634 {DEC_JASC_IM, dec_jasc_im},
2635 {DEC_JASC_R, dec_jasc_r},
2636 {DEC_BAS_IM, dec_bas_im},
2637 {DEC_BASC_IM, dec_basc_im},
2638 {DEC_JUMP_P, dec_jump_p},
2639 {DEC_LAPC_IM, dec_lapc_im},
2640 {DEC_LAPCQ, dec_lapcq},
2641
2642 {DEC_RFE_ETC, dec_rfe_etc},
2643 {DEC_ADDC_MR, dec_addc_mr},
2644
2645 {DEC_MOVE_MP, dec_move_mp},
2646 {DEC_MOVE_PM, dec_move_pm},
2647 {DEC_MOVEM_MR, dec_movem_mr},
2648 {DEC_MOVEM_RM, dec_movem_rm},
2649 {DEC_MOVE_PR, dec_move_pr},
2650 {DEC_SCC_R, dec_scc_r},
2651 {DEC_SETF, dec_setclrf},
2652 {DEC_CLEARF, dec_setclrf},
2653
2654 {DEC_MOVE_SR, dec_move_sr},
2655 {DEC_MOVE_RP, dec_move_rp},
2656 {DEC_SWAP_R, dec_swap_r},
2657 {DEC_ABS_R, dec_abs_r},
2658 {DEC_LZ_R, dec_lz_r},
2659 {DEC_MOVE_RS, dec_move_rs},
2660 {DEC_BTST_R, dec_btst_r},
2661 {DEC_ADDC_R, dec_addc_r},
2662
2663 {DEC_DSTEP_R, dec_dstep_r},
2664 {DEC_XOR_R, dec_xor_r},
2665 {DEC_MCP_R, dec_mcp_r},
2666 {DEC_CMP_R, dec_cmp_r},
2667
2668 {DEC_ADDI_R, dec_addi_r},
2669 {DEC_ADDI_ACR, dec_addi_acr},
2670
2671 {DEC_ADD_R, dec_add_r},
2672 {DEC_SUB_R, dec_sub_r},
2673
2674 {DEC_ADDU_R, dec_addu_r},
2675 {DEC_ADDS_R, dec_adds_r},
2676 {DEC_SUBU_R, dec_subu_r},
2677 {DEC_SUBS_R, dec_subs_r},
2678 {DEC_LSL_R, dec_lsl_r},
2679
2680 {DEC_AND_R, dec_and_r},
2681 {DEC_OR_R, dec_or_r},
2682 {DEC_BOUND_R, dec_bound_r},
2683 {DEC_ASR_R, dec_asr_r},
2684 {DEC_LSR_R, dec_lsr_r},
2685
2686 {DEC_MOVU_R, dec_movu_r},
2687 {DEC_MOVS_R, dec_movs_r},
2688 {DEC_NEG_R, dec_neg_r},
2689 {DEC_MOVE_R, dec_move_r},
2690
5d4a534d
EI		 2691 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2692 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
8170028d
TS		 2693
2694 {DEC_MULS_R, dec_muls_r},
2695 {DEC_MULU_R, dec_mulu_r},
2696
2697 {DEC_ADDU_M, dec_addu_m},
2698 {DEC_ADDS_M, dec_adds_m},
2699 {DEC_SUBU_M, dec_subu_m},
2700 {DEC_SUBS_M, dec_subs_m},
2701
2702 {DEC_CMPU_M, dec_cmpu_m},
2703 {DEC_CMPS_M, dec_cmps_m},
2704 {DEC_MOVU_M, dec_movu_m},
2705 {DEC_MOVS_M, dec_movs_m},
2706
2707 {DEC_CMP_M, dec_cmp_m},
2708 {DEC_ADDO_M, dec_addo_m},
2709 {DEC_BOUND_M, dec_bound_m},
2710 {DEC_ADD_M, dec_add_m},
2711 {DEC_SUB_M, dec_sub_m},
2712 {DEC_AND_M, dec_and_m},
2713 {DEC_OR_M, dec_or_m},
2714 {DEC_MOVE_RM, dec_move_rm},
2715 {DEC_TEST_M, dec_test_m},
2716 {DEC_MOVE_MR, dec_move_mr},
2717
2718 {{0, 0}, dec_null}
2719};
2720
2721static inline unsigned int
2722cris_decoder(DisasContext *dc)
2723{
2724 unsigned int insn_len = 2;
8170028d
TS		 2725 int i;
2726
2727 /* Load a halfword onto the instruction register. */
17ac9754 2728 dc->ir = lduw_code(dc->pc);
8170028d
TS		 2729
2730 /* Now decode it. */
2731 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2732 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2733 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2734 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2735 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2736 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2737
2738 /* Large switch for all insns. */
2739 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
2740 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
2741 {
2742 insn_len = decinfo[i].dec(dc);
2743 break;
2744 }
2745 }
2746
2747 return insn_len;
2748}
2749
2750static void check_breakpoint(CPUState *env, DisasContext *dc)
2751{
2752 int j;
2753 if (env->nb_breakpoints > 0) {
2754 for(j = 0; j < env->nb_breakpoints; j++) {
2755 if (env->breakpoints[j] == dc->pc) {
2756 cris_evaluate_flags (dc);
05ba7d5f 2757 tcg_gen_movi_tl(cpu_T[0], dc->pc);
3157a0a9 2758 t_gen_mov_env_TN(pc, cpu_T[0]);
dceaf394 2759 t_gen_raise_exception(EXCP_DEBUG);
8170028d
TS		 2760 dc->is_jmp = DISAS_UPDATE;
2761 }
2762 }
2763 }
2764}
2765
cf1d97f0
EI		 2766
2767/*
2768 * Delay slots on QEMU/CRIS.
2769 *
2770 * If an exception hits on a delayslot, the core will let ERP (the Exception
2771 * Return Pointer) point to the branch (the previous) insn and set the lsb to
2772 * to give SW a hint that the exception actually hit on the dslot.
2773 *
2774 * CRIS expects all PC addresses to be 16-bit aligned. The lsb is ignored by
2775 * the core and any jmp to an odd addresses will mask off that lsb. It is
2776 * simply there to let sw know there was an exception on a dslot.
2777 *
2778 * When the software returns from an exception, the branch will re-execute.
2779 * On QEMU care needs to be taken when a branch+delayslot sequence is broken
2780 * and the branch and delayslot dont share pages.
2781 *
2782 * The TB contaning the branch insn will set up env->btarget and evaluate
2783 * env->btaken. When the translation loop exits we will note that the branch
2784 * sequence is broken and let env->dslot be the size of the branch insn (those
2785 * vary in length).
2786 *
2787 * The TB contaning the delayslot will have the PC of its real insn (i.e no lsb
2788 * set). It will also expect to have env->dslot setup with the size of the
2789 * delay slot so that env->pc - env->dslot point to the branch insn. This TB
2790 * will execute the dslot and take the branch, either to btarget or just one
2791 * insn ahead.
2792 *
2793 * When exceptions occur, we check for env->dslot in do_interrupt to detect
2794 * broken branch sequences and setup $erp accordingly (i.e let it point to the
2795 * branch and set lsb). Then env->dslot gets cleared so that the exception
2796 * handler can enter. When returning from exceptions (jump $erp) the lsb gets
2797 * masked off and we will reexecute the branch insn.
2798 *
2799 */
2800
8170028d 2801/* generate intermediate code for basic block 'tb'. */
8170028d
TS		 2802static int
2803gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2804 int search_pc)
2805{
2806 uint16_t *gen_opc_end;
2807 uint32_t pc_start;
2808 unsigned int insn_len;
2809 int j, lj;
cf1d97f0 2810 struct DisasContext ctx;
8170028d
TS		 2811 struct DisasContext *dc = &ctx;
2812 uint32_t next_page_start;
2813
a825e703
EI		 2814 if (!logfile)
2815 logfile = stderr;
2816
73e51723
EI		 2817 /* Odd PC indicates that branch is rexecuting due to exception in the
2818 * delayslot, like in real hw.
73e51723
EI		 2819 */
2820 pc_start = tb->pc & ~1;
8170028d
TS		 2821 dc->env = env;
2822 dc->tb = tb;
2823
8170028d 2824 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
8170028d
TS		 2825
2826 dc->is_jmp = DISAS_NEXT;
b41f7df0 2827 dc->ppc = pc_start;
8170028d
TS		 2828 dc->pc = pc_start;
2829 dc->singlestep_enabled = env->singlestep_enabled;
b41f7df0 2830 dc->flags_live = 1;
8170028d
TS		 2831 dc->flagx_live = 0;
2832 dc->flags_x = 0;
b41f7df0 2833 dc->cc_mask = 0;
cf1d97f0 2834 dc->update_cc = 0;
b41f7df0
EI		 2835 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2836
cf1d97f0
EI		 2837 /* Decode TB flags. */
2838 dc->user = tb->flags & U_FLAG;
2839 dc->delayed_branch = !!(tb->flags & 7);
b41f7df0
EI		 2840
2841 if (loglevel & CPU_LOG_TB_IN_ASM) {
2842 fprintf(logfile,
cf1d97f0
EI		 2843 "srch=%d pc=%x %x bt=%x ds=%lld ccs=%x\n"
2844 "pid=%x usp=%x dbg=%x %x %x\n"
b41f7df0
EI		 2845 "%x.%x.%x.%x\n"
2846 "%x.%x.%x.%x\n"
2847 "%x.%x.%x.%x\n"
2848 "%x.%x.%x.%x\n",
cf1d97f0
EI		 2849 search_pc, dc->pc, dc->ppc,
2850 env->btarget, tb->flags & 7,
2851 env->pregs[PR_CCS],
b41f7df0 2852 env->pregs[PR_PID], env->pregs[PR_USP],
dceaf394 2853 env->debug1, env->debug2, env->debug3,
b41f7df0
EI		 2854 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
2855 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
2856 env->regs[8], env->regs[9],
2857 env->regs[10], env->regs[11],
2858 env->regs[12], env->regs[13],
2859 env->regs[14], env->regs[15]);
2860
2861 }
3157a0a9 2862
8170028d
TS		 2863 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2864 lj = -1;
2865 do
2866 {
2867 check_breakpoint(env, dc);
4f400ab5
EI		 2868 if (dc->is_jmp == DISAS_JUMP
2869 || dc->is_jmp == DISAS_SWI)
8170028d
TS		 2870 goto done;
2871
2872 if (search_pc) {
2873 j = gen_opc_ptr - gen_opc_buf;
2874 if (lj < j) {
2875 lj++;
2876 while (lj < j)
2877 gen_opc_instr_start[lj++] = 0;
2878 }
cf1d97f0 2879 if (dc->delayed_branch == 1)
b41f7df0 2880 gen_opc_pc[lj] = dc->ppc | 1;
cf1d97f0 2881 else
b41f7df0 2882 gen_opc_pc[lj] = dc->pc;
cf1d97f0
EI		 2883 gen_opc_instr_start[lj] = 1;
2884 }
2885
2886 /* Pretty disas. */
2887 DIS(fprintf(logfile, "%x ", dc->pc));
2888 if (search_pc) {
2889 DIS(fprintf(logfile, "%x ", dc->pc));
8170028d
TS		 2890 }
2891
b41f7df0 2892 dc->clear_x = 1;
8170028d 2893 insn_len = cris_decoder(dc);
b41f7df0 2894 dc->ppc = dc->pc;
8170028d 2895 dc->pc += insn_len;
b41f7df0
EI		 2896 if (dc->clear_x)
2897 cris_clear_x_flag(dc);
8170028d
TS		 2898
2899 /* Check for delayed branches here. If we do it before
2900 actually genereating any host code, the simulator will just
2901 loop doing nothing for on this program location. */
2902 if (dc->delayed_branch) {
cf1d97f0 2903 t_gen_mov_env_TN(dslot, tcg_const_tl(0));
8170028d
TS		 2904 dc->delayed_branch--;
2905 if (dc->delayed_branch == 0)
2906 {
cf1d97f0
EI		 2907 t_gen_cc_jmp(env_btarget,
2908 tcg_const_tl(dc->pc));
2909 dc->is_jmp = DISAS_JUMP;
8170028d
TS		 2910 }
2911 }
2912
73e51723
EI		 2913 /* If we are rexecuting a branch due to exceptions on
2914 delay slots dont break. */
2915 if (!(tb->pc & 1) && env->singlestep_enabled)
8170028d
TS		 2916 break;
2917 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
cf1d97f0 2918 && (dc->pc < next_page_start));
b41f7df0 2919
cf1d97f0 2920 /* Broken branch+delayslot sequence. */
b41f7df0 2921 if (dc->delayed_branch == 1) {
cf1d97f0
EI		 2922 /* Set env->dslot to the size of the branch insn. */
2923 t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc));
b41f7df0 2924 }
8170028d
TS		 2925
2926 if (!dc->is_jmp) {
cf1d97f0 2927 D(fprintf(logfile, "!jmp pc=%x jmp=%d db=%d\n", dc->pc,
b41f7df0
EI		 2928 dc->is_jmp, dc->delayed_branch));
2929 /* T0 and env_pc should hold the new pc. */
3157a0a9 2930 tcg_gen_movi_tl(cpu_T[0], dc->pc);
b41f7df0 2931 tcg_gen_mov_tl(env_pc, cpu_T[0]);
8170028d
TS		 2932 }
2933
2934 cris_evaluate_flags (dc);
2935 done:
2936 if (__builtin_expect(env->singlestep_enabled, 0)) {
dceaf394 2937 t_gen_raise_exception(EXCP_DEBUG);
8170028d
TS		 2938 } else {
2939 switch(dc->is_jmp) {
2940 case DISAS_NEXT:
2941 gen_goto_tb(dc, 1, dc->pc);
2942 break;
2943 default:
2944 case DISAS_JUMP:
2945 case DISAS_UPDATE:
2946 /* indicate that the hash table must be used
2947 to find the next TB */
57fec1fe 2948 tcg_gen_exit_tb(0);
8170028d 2949 break;
4f400ab5 2950 case DISAS_SWI:
8170028d
TS		 2951 case DISAS_TB_JUMP:
2952 /* nothing more to generate */
2953 break;
2954 }
2955 }
2956 *gen_opc_ptr = INDEX_op_end;
2957 if (search_pc) {
2958 j = gen_opc_ptr - gen_opc_buf;
2959 lj++;
2960 while (lj <= j)
2961 gen_opc_instr_start[lj++] = 0;
2962 } else {
2963 tb->size = dc->pc - pc_start;
2964 }
2965
2966#ifdef DEBUG_DISAS
2967 if (loglevel & CPU_LOG_TB_IN_ASM) {
2968 fprintf(logfile, "--------------\n");
2969 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
17ac9754 2970 target_disas(logfile, pc_start, dc->pc - pc_start, 0);
b41f7df0
EI		 2971 fprintf(logfile, "\nisize=%d osize=%d\n",
2972 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
8170028d
TS		 2973 }
2974#endif
2975 return 0;
2976}
2977
2978int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2979{
2980 return gen_intermediate_code_internal(env, tb, 0);
2981}
2982
2983int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2984{
2985 return gen_intermediate_code_internal(env, tb, 1);
2986}
2987
2988void cpu_dump_state (CPUState *env, FILE *f,
2989 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2990 int flags)
2991{
2992 int i;
2993 uint32_t srs;
2994
2995 if (!env || !f)
2996 return;
2997
2998 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2999 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
3000 "debug=%x %x %x\n",
9004627f 3001 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
8170028d
TS		 3002 env->cc_op,
3003 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask,
3004 env->debug1, env->debug2, env->debug3);
3005
3006 for (i = 0; i < 16; i++) {
3007 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
3008 if ((i + 1) % 4 == 0)
3009 cpu_fprintf(f, "\n");
3010 }
3011 cpu_fprintf(f, "\nspecial regs:\n");
3012 for (i = 0; i < 16; i++) {
3013 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
3014 if ((i + 1) % 4 == 0)
3015 cpu_fprintf(f, "\n");
3016 }
9004627f 3017 srs = env->pregs[PR_SRS];
b41f7df0 3018 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
8170028d
TS		 3019 if (srs < 256) {
3020 for (i = 0; i < 16; i++) {
3021 cpu_fprintf(f, "s%2.2d=%8.8x ",
3022 i, env->sregs[srs][i]);
3023 if ((i + 1) % 4 == 0)
3024 cpu_fprintf(f, "\n");
3025 }
3026 }
3027 cpu_fprintf(f, "\n\n");
3028
3029}
3030
aaed909a 3031CPUCRISState *cpu_cris_init (const char *cpu_model)
8170028d
TS		 3032{
3033 CPUCRISState *env;
a825e703 3034 int i;
8170028d
TS		 3035
3036 env = qemu_mallocz(sizeof(CPUCRISState));
3037 if (!env)
3038 return NULL;
3039 cpu_exec_init(env);
05ba7d5f 3040
05ba7d5f
EI		 3041 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
3042#if TARGET_LONG_BITS > HOST_LONG_BITS
3043 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
3044 TCG_AREG0, offsetof(CPUState, t0), "T0");
3045 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
3046 TCG_AREG0, offsetof(CPUState, t1), "T1");
3047#else
3048 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
3049 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
3050#endif
3051
a825e703
EI		 3052 cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3053 offsetof(CPUState, cc_src), "cc_src");
3054 cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3055 offsetof(CPUState, cc_dest),
3056 "cc_dest");
3057 cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3058 offsetof(CPUState, cc_result),
3059 "cc_result");
3060 cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3061 offsetof(CPUState, cc_op), "cc_op");
3062 cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3063 offsetof(CPUState, cc_size),
3064 "cc_size");
3065 cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3066 offsetof(CPUState, cc_mask),
3067 "cc_mask");
3068
b41f7df0
EI		 3069 env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3070 offsetof(CPUState, pc),
3071 "pc");
3072 env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3073 offsetof(CPUState, btarget),
3074 "btarget");
3075
a825e703
EI		 3076 for (i = 0; i < 16; i++) {
3077 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3078 offsetof(CPUState, regs[i]),
3079 regnames[i]);
3080 }
3081 for (i = 0; i < 16; i++) {
3082 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
3083 offsetof(CPUState, pregs[i]),
3084 pregnames[i]);
3085 }
3086
dceaf394 3087 TCG_HELPER(helper_raise_exception);
b41f7df0
EI		 3088 TCG_HELPER(helper_store);
3089 TCG_HELPER(helper_dump);
3090 TCG_HELPER(helper_dummy);
3091
dceaf394 3092 TCG_HELPER(helper_tlb_flush);
cf1d97f0 3093 TCG_HELPER(helper_tlb_flush_pid);
dceaf394
EI		 3094 TCG_HELPER(helper_movl_sreg_reg);
3095 TCG_HELPER(helper_movl_reg_sreg);
3096 TCG_HELPER(helper_rfe);
3097
b41f7df0
EI		 3098 TCG_HELPER(helper_evaluate_flags_muls);
3099 TCG_HELPER(helper_evaluate_flags_mulu);
3100 TCG_HELPER(helper_evaluate_flags_mcp);
3101 TCG_HELPER(helper_evaluate_flags_alu_4);
3102 TCG_HELPER(helper_evaluate_flags_move_4);
3103 TCG_HELPER(helper_evaluate_flags_move_2);
3104 TCG_HELPER(helper_evaluate_flags);
3105
8170028d
TS		 3106 cpu_reset(env);
3107 return env;
3108}
3109
3110void cpu_reset (CPUCRISState *env)
3111{
3112 memset(env, 0, offsetof(CPUCRISState, breakpoints));
3113 tlb_flush(env, 1);
b41f7df0
EI		 3114
3115#if defined(CONFIG_USER_ONLY)
3116 /* start in user mode with interrupts enabled. */
3117 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
3118#else
3119 env->pregs[PR_CCS] = 0;
3120#endif
8170028d 3121}
d2856f1a
AJ		 3122
3123void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
3124 unsigned long searched_pc, int pc_pos, void *puc)
3125{
17ac9754 3126 env->pc = gen_opc_pc[pc_pos];
d2856f1a 3127}
Qemu copy for testing