[qemu.git] / target-i386 / cc_helper.c

/*
 *  x86 condition code helpers
 *
 *  Copyright (c) 2003 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "helper.h"

const uint8_t parity_table[256] = {
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
};

#define SHIFT 0
#include "cc_helper_template.h"
#undef SHIFT

#define SHIFT 1
#include "cc_helper_template.h"
#undef SHIFT

#define SHIFT 2
#include "cc_helper_template.h"
#undef SHIFT

#ifdef TARGET_X86_64

#define SHIFT 3
#include "cc_helper_template.h"
#undef SHIFT

#endif

static target_ulong compute_all_adcx(target_ulong dst, target_ulong src1,
                                     target_ulong src2)
{
    return (src1 & ~CC_C) | (dst * CC_C);
}

static target_ulong compute_all_adox(target_ulong dst, target_ulong src1,
                                     target_ulong src2)
{
    return (src1 & ~CC_O) | (src2 * CC_O);
}

static target_ulong compute_all_adcox(target_ulong dst, target_ulong src1,
                                      target_ulong src2)
{
    return (src1 & ~(CC_C | CC_O)) | (dst * CC_C) | (src2 * CC_O);
}

target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1,
                                   target_ulong src2, int op)
{
    switch (op) {
    default: /* should never happen */
        return 0;

    case CC_OP_EFLAGS:
        return src1;
    case CC_OP_CLR:
        return CC_Z;

    case CC_OP_MULB:
        return compute_all_mulb(dst, src1);
    case CC_OP_MULW:
        return compute_all_mulw(dst, src1);
    case CC_OP_MULL:
        return compute_all_mull(dst, src1);

    case CC_OP_ADDB:
        return compute_all_addb(dst, src1);
    case CC_OP_ADDW:
        return compute_all_addw(dst, src1);
    case CC_OP_ADDL:
        return compute_all_addl(dst, src1);

    case CC_OP_ADCB:
        return compute_all_adcb(dst, src1, src2);
    case CC_OP_ADCW:
        return compute_all_adcw(dst, src1, src2);
    case CC_OP_ADCL:
        return compute_all_adcl(dst, src1, src2);

    case CC_OP_SUBB:
        return compute_all_subb(dst, src1);
    case CC_OP_SUBW:
        return compute_all_subw(dst, src1);
    case CC_OP_SUBL:
        return compute_all_subl(dst, src1);

    case CC_OP_SBBB:
        return compute_all_sbbb(dst, src1, src2);
    case CC_OP_SBBW:
        return compute_all_sbbw(dst, src1, src2);
    case CC_OP_SBBL:
        return compute_all_sbbl(dst, src1, src2);

    case CC_OP_LOGICB:
        return compute_all_logicb(dst, src1);
    case CC_OP_LOGICW:
        return compute_all_logicw(dst, src1);
    case CC_OP_LOGICL:
        return compute_all_logicl(dst, src1);

    case CC_OP_INCB:
        return compute_all_incb(dst, src1);
    case CC_OP_INCW:
        return compute_all_incw(dst, src1);
    case CC_OP_INCL:
        return compute_all_incl(dst, src1);

    case CC_OP_DECB:
        return compute_all_decb(dst, src1);
    case CC_OP_DECW:
        return compute_all_decw(dst, src1);
    case CC_OP_DECL:
        return compute_all_decl(dst, src1);

    case CC_OP_SHLB:
        return compute_all_shlb(dst, src1);
    case CC_OP_SHLW:
        return compute_all_shlw(dst, src1);
    case CC_OP_SHLL:
        return compute_all_shll(dst, src1);

    case CC_OP_SARB:
        return compute_all_sarb(dst, src1);
    case CC_OP_SARW:
        return compute_all_sarw(dst, src1);
    case CC_OP_SARL:
        return compute_all_sarl(dst, src1);

    case CC_OP_BMILGB:
        return compute_all_bmilgb(dst, src1);
    case CC_OP_BMILGW:
        return compute_all_bmilgw(dst, src1);
    case CC_OP_BMILGL:
        return compute_all_bmilgl(dst, src1);

    case CC_OP_ADCX:
        return compute_all_adcx(dst, src1, src2);
    case CC_OP_ADOX:
        return compute_all_adox(dst, src1, src2);
    case CC_OP_ADCOX:
        return compute_all_adcox(dst, src1, src2);

#ifdef TARGET_X86_64
    case CC_OP_MULQ:
        return compute_all_mulq(dst, src1);
    case CC_OP_ADDQ:
        return compute_all_addq(dst, src1);
    case CC_OP_ADCQ:
        return compute_all_adcq(dst, src1, src2);
    case CC_OP_SUBQ:
        return compute_all_subq(dst, src1);
    case CC_OP_SBBQ:
        return compute_all_sbbq(dst, src1, src2);
    case CC_OP_LOGICQ:
        return compute_all_logicq(dst, src1);
    case CC_OP_INCQ:
        return compute_all_incq(dst, src1);
    case CC_OP_DECQ:
        return compute_all_decq(dst, src1);
    case CC_OP_SHLQ:
        return compute_all_shlq(dst, src1);
    case CC_OP_SARQ:
        return compute_all_sarq(dst, src1);
    case CC_OP_BMILGQ:
        return compute_all_bmilgq(dst, src1);
#endif
    }
}

uint32_t cpu_cc_compute_all(CPUX86State *env, int op)
{
    return helper_cc_compute_all(CC_DST, CC_SRC, CC_SRC2, op);
}

target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1,
                                 target_ulong src2, int op)
{
    switch (op) {
    default: /* should never happen */
    case CC_OP_LOGICB:
    case CC_OP_LOGICW:
    case CC_OP_LOGICL:
    case CC_OP_LOGICQ:
    case CC_OP_CLR:
        return 0;

    case CC_OP_EFLAGS:
    case CC_OP_SARB:
    case CC_OP_SARW:
    case CC_OP_SARL:
    case CC_OP_SARQ:
    case CC_OP_ADOX:
        return src1 & 1;

    case CC_OP_INCB:
    case CC_OP_INCW:
    case CC_OP_INCL:
    case CC_OP_INCQ:
    case CC_OP_DECB:
    case CC_OP_DECW:
    case CC_OP_DECL:
    case CC_OP_DECQ:
        return src1;

    case CC_OP_MULB:
    case CC_OP_MULW:
    case CC_OP_MULL:
    case CC_OP_MULQ:
        return src1 != 0;

    case CC_OP_ADCX:
    case CC_OP_ADCOX:
        return dst;

    case CC_OP_ADDB:
        return compute_c_addb(dst, src1);
    case CC_OP_ADDW:
        return compute_c_addw(dst, src1);
    case CC_OP_ADDL:
        return compute_c_addl(dst, src1);

    case CC_OP_ADCB:
        return compute_c_adcb(dst, src1, src2);
    case CC_OP_ADCW:
        return compute_c_adcw(dst, src1, src2);
    case CC_OP_ADCL:
        return compute_c_adcl(dst, src1, src2);

    case CC_OP_SUBB:
        return compute_c_subb(dst, src1);
    case CC_OP_SUBW:
        return compute_c_subw(dst, src1);
    case CC_OP_SUBL:
        return compute_c_subl(dst, src1);

    case CC_OP_SBBB:
        return compute_c_sbbb(dst, src1, src2);
    case CC_OP_SBBW:
        return compute_c_sbbw(dst, src1, src2);
    case CC_OP_SBBL:
        return compute_c_sbbl(dst, src1, src2);

    case CC_OP_SHLB:
        return compute_c_shlb(dst, src1);
    case CC_OP_SHLW:
        return compute_c_shlw(dst, src1);
    case CC_OP_SHLL:
        return compute_c_shll(dst, src1);

    case CC_OP_BMILGB:
        return compute_c_bmilgb(dst, src1);
    case CC_OP_BMILGW:
        return compute_c_bmilgw(dst, src1);
    case CC_OP_BMILGL:
        return compute_c_bmilgl(dst, src1);

#ifdef TARGET_X86_64
    case CC_OP_ADDQ:
        return compute_c_addq(dst, src1);
    case CC_OP_ADCQ:
        return compute_c_adcq(dst, src1, src2);
    case CC_OP_SUBQ:
        return compute_c_subq(dst, src1);
    case CC_OP_SBBQ:
        return compute_c_sbbq(dst, src1, src2);
    case CC_OP_SHLQ:
        return compute_c_shlq(dst, src1);
    case CC_OP_BMILGQ:
        return compute_c_bmilgq(dst, src1);
#endif
    }
}

void helper_write_eflags(CPUX86State *env, target_ulong t0,
                         uint32_t update_mask)
{
    cpu_load_eflags(env, t0, update_mask);
}

target_ulong helper_read_eflags(CPUX86State *env)
{
    uint32_t eflags;

    eflags = cpu_cc_compute_all(env, CC_OP);
    eflags |= (env->df & DF_MASK);
    eflags |= env->eflags & ~(VM_MASK | RF_MASK);
    return eflags;
}

void helper_clts(CPUX86State *env)
{
    env->cr[0] &= ~CR0_TS_MASK;
    env->hflags &= ~HF_TS_MASK;
}

void helper_reset_rf(CPUX86State *env)
{
    env->eflags &= ~RF_MASK;
}

void helper_cli(CPUX86State *env)
{
    env->eflags &= ~IF_MASK;
}

void helper_sti(CPUX86State *env)
{
    env->eflags |= IF_MASK;
}

void helper_clac(CPUX86State *env)
{
    env->eflags &= ~AC_MASK;
}

void helper_stac(CPUX86State *env)
{
    env->eflags |= AC_MASK;
}

#if 0
/* vm86plus instructions */
void helper_cli_vm(CPUX86State *env)
{
    env->eflags &= ~VIF_MASK;
}

void helper_sti_vm(CPUX86State *env)
{
    env->eflags |= VIF_MASK;
    if (env->eflags & VIP_MASK) {
        raise_exception(env, EXCP0D_GPF);
    }
}
#endif

void helper_set_inhibit_irq(CPUX86State *env)
{
    env->hflags |= HF_INHIBIT_IRQ_MASK;
}

void helper_reset_inhibit_irq(CPUX86State *env)
{
    env->hflags &= ~HF_INHIBIT_IRQ_MASK;
}
Commit	Line	Data
5918fffb BS	1	/*
	2	* x86 condition code helpers
	3	*
	4	* Copyright (c) 2003 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "cpu.h"
5918fffb BS	21	#include "helper.h"
	22
	23	const uint8_t parity_table[256] = {
	24	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	25	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	26	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	27	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	28	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	29	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	30	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	31	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	32	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	33	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	34	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	35	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	36	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	37	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	38	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	39	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	40	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	41	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	42	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	43	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	44	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	45	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	46	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	47	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	48	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	49	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	50	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	51	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	52	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	53	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	54	CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
	55	0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
	56	};
	57
	58	#define SHIFT 0
	59	#include "cc_helper_template.h"
	60	#undef SHIFT
	61
	62	#define SHIFT 1
	63	#include "cc_helper_template.h"
	64	#undef SHIFT
	65
	66	#define SHIFT 2
	67	#include "cc_helper_template.h"
	68	#undef SHIFT
	69
	70	#ifdef TARGET_X86_64
	71
	72	#define SHIFT 3
	73	#include "cc_helper_template.h"
	74	#undef SHIFT
	75
	76	#endif
	77
cd7f97ca RH	78	static target_ulong compute_all_adcx(target_ulong dst, target_ulong src1,
	79	target_ulong src2)
	80	{
	81	return (src1 & ~CC_C) \| (dst * CC_C);
	82	}
	83
	84	static target_ulong compute_all_adox(target_ulong dst, target_ulong src1,
	85	target_ulong src2)
	86	{
	87	return (src1 & ~CC_O) \| (src2 * CC_O);
	88	}
	89
	90	static target_ulong compute_all_adcox(target_ulong dst, target_ulong src1,
	91	target_ulong src2)
	92	{
	93	return (src1 & ~(CC_C \| CC_O)) \| (dst * CC_C) \| (src2 * CC_O);
	94	}
	95
988c3eb0 RH	96	target_ulong helper_cc_compute_all(target_ulong dst, target_ulong src1,
988c3eb0 RH	97	target_ulong src2, int op)
5918fffb BS	98	{
	99	switch (op) {
	100	default: /* should never happen */
	101	return 0;
	102
	103	case CC_OP_EFLAGS:
8601c0b6	104	return src1;
436ff2d2 RH	105	case CC_OP_CLR:
436ff2d2 RH	106	return CC_Z;
5918fffb BS	107
5918fffb BS	108	case CC_OP_MULB:
8601c0b6	109	return compute_all_mulb(dst, src1);
5918fffb	110	case CC_OP_MULW:
8601c0b6	111	return compute_all_mulw(dst, src1);
5918fffb	112	case CC_OP_MULL:
8601c0b6	113	return compute_all_mull(dst, src1);
5918fffb BS	114
5918fffb BS	115	case CC_OP_ADDB:
8601c0b6	116	return compute_all_addb(dst, src1);
5918fffb	117	case CC_OP_ADDW:
8601c0b6	118	return compute_all_addw(dst, src1);
5918fffb	119	case CC_OP_ADDL:
8601c0b6	120	return compute_all_addl(dst, src1);
5918fffb BS	121
5918fffb BS	122	case CC_OP_ADCB:
988c3eb0	123	return compute_all_adcb(dst, src1, src2);
5918fffb	124	case CC_OP_ADCW:
988c3eb0	125	return compute_all_adcw(dst, src1, src2);
5918fffb	126	case CC_OP_ADCL:
988c3eb0	127	return compute_all_adcl(dst, src1, src2);
5918fffb BS	128
5918fffb BS	129	case CC_OP_SUBB:
8601c0b6	130	return compute_all_subb(dst, src1);
5918fffb	131	case CC_OP_SUBW:
8601c0b6	132	return compute_all_subw(dst, src1);
5918fffb	133	case CC_OP_SUBL:
8601c0b6	134	return compute_all_subl(dst, src1);
5918fffb BS	135
5918fffb BS	136	case CC_OP_SBBB:
988c3eb0	137	return compute_all_sbbb(dst, src1, src2);
5918fffb	138	case CC_OP_SBBW:
988c3eb0	139	return compute_all_sbbw(dst, src1, src2);
5918fffb	140	case CC_OP_SBBL:
988c3eb0	141	return compute_all_sbbl(dst, src1, src2);
5918fffb BS	142
5918fffb BS	143	case CC_OP_LOGICB:
8601c0b6	144	return compute_all_logicb(dst, src1);
5918fffb	145	case CC_OP_LOGICW:
8601c0b6	146	return compute_all_logicw(dst, src1);
5918fffb	147	case CC_OP_LOGICL:
8601c0b6	148	return compute_all_logicl(dst, src1);
5918fffb BS	149
5918fffb BS	150	case CC_OP_INCB:
8601c0b6	151	return compute_all_incb(dst, src1);
5918fffb	152	case CC_OP_INCW:
8601c0b6	153	return compute_all_incw(dst, src1);
5918fffb	154	case CC_OP_INCL:
8601c0b6	155	return compute_all_incl(dst, src1);
5918fffb BS	156
5918fffb BS	157	case CC_OP_DECB:
8601c0b6	158	return compute_all_decb(dst, src1);
5918fffb	159	case CC_OP_DECW:
8601c0b6	160	return compute_all_decw(dst, src1);
5918fffb	161	case CC_OP_DECL:
8601c0b6	162	return compute_all_decl(dst, src1);
5918fffb BS	163
5918fffb BS	164	case CC_OP_SHLB:
8601c0b6	165	return compute_all_shlb(dst, src1);
5918fffb	166	case CC_OP_SHLW:
8601c0b6	167	return compute_all_shlw(dst, src1);
5918fffb	168	case CC_OP_SHLL:
8601c0b6	169	return compute_all_shll(dst, src1);
5918fffb BS	170
5918fffb BS	171	case CC_OP_SARB:
8601c0b6	172	return compute_all_sarb(dst, src1);
5918fffb	173	case CC_OP_SARW:
8601c0b6	174	return compute_all_sarw(dst, src1);
5918fffb	175	case CC_OP_SARL:
8601c0b6	176	return compute_all_sarl(dst, src1);
5918fffb	177
bc4b43dc RH	178	case CC_OP_BMILGB:
	179	return compute_all_bmilgb(dst, src1);
	180	case CC_OP_BMILGW:
	181	return compute_all_bmilgw(dst, src1);
	182	case CC_OP_BMILGL:
	183	return compute_all_bmilgl(dst, src1);
	184
cd7f97ca RH	185	case CC_OP_ADCX:
	186	return compute_all_adcx(dst, src1, src2);
	187	case CC_OP_ADOX:
	188	return compute_all_adox(dst, src1, src2);
	189	case CC_OP_ADCOX:
	190	return compute_all_adcox(dst, src1, src2);
	191
5918fffb BS	192	#ifdef TARGET_X86_64
5918fffb BS	193	case CC_OP_MULQ:
8601c0b6	194	return compute_all_mulq(dst, src1);
5918fffb	195	case CC_OP_ADDQ:
8601c0b6	196	return compute_all_addq(dst, src1);
5918fffb	197	case CC_OP_ADCQ:
988c3eb0	198	return compute_all_adcq(dst, src1, src2);
5918fffb	199	case CC_OP_SUBQ:
8601c0b6	200	return compute_all_subq(dst, src1);
5918fffb	201	case CC_OP_SBBQ:
988c3eb0	202	return compute_all_sbbq(dst, src1, src2);
5918fffb	203	case CC_OP_LOGICQ:
8601c0b6	204	return compute_all_logicq(dst, src1);
5918fffb	205	case CC_OP_INCQ:
8601c0b6	206	return compute_all_incq(dst, src1);
5918fffb	207	case CC_OP_DECQ:
8601c0b6	208	return compute_all_decq(dst, src1);
5918fffb	209	case CC_OP_SHLQ:
8601c0b6	210	return compute_all_shlq(dst, src1);
5918fffb	211	case CC_OP_SARQ:
8601c0b6	212	return compute_all_sarq(dst, src1);
bc4b43dc RH	213	case CC_OP_BMILGQ:
bc4b43dc RH	214	return compute_all_bmilgq(dst, src1);
5918fffb BS	215	#endif
	216	}
	217	}
	218
f0967a1a	219	uint32_t cpu_cc_compute_all(CPUX86State *env, int op)
5918fffb	220	{
988c3eb0	221	return helper_cc_compute_all(CC_DST, CC_SRC, CC_SRC2, op);
5918fffb BS	222	}
5918fffb BS	223
988c3eb0 RH	224	target_ulong helper_cc_compute_c(target_ulong dst, target_ulong src1,
988c3eb0 RH	225	target_ulong src2, int op)
5918fffb BS	226	{
	227	switch (op) {
	228	default: /* should never happen */
8601c0b6 RH	229	case CC_OP_LOGICB:
	230	case CC_OP_LOGICW:
	231	case CC_OP_LOGICL:
	232	case CC_OP_LOGICQ:
436ff2d2	233	case CC_OP_CLR:
5918fffb BS	234	return 0;
	235
	236	case CC_OP_EFLAGS:
8601c0b6 RH	237	case CC_OP_SARB:
	238	case CC_OP_SARW:
	239	case CC_OP_SARL:
	240	case CC_OP_SARQ:
cd7f97ca	241	case CC_OP_ADOX:
8601c0b6 RH	242	return src1 & 1;
	243
	244	case CC_OP_INCB:
	245	case CC_OP_INCW:
	246	case CC_OP_INCL:
	247	case CC_OP_INCQ:
	248	case CC_OP_DECB:
	249	case CC_OP_DECW:
	250	case CC_OP_DECL:
	251	case CC_OP_DECQ:
	252	return src1;
5918fffb BS	253
5918fffb BS	254	case CC_OP_MULB:
5918fffb	255	case CC_OP_MULW:
5918fffb	256	case CC_OP_MULL:
8601c0b6 RH	257	case CC_OP_MULQ:
8601c0b6 RH	258	return src1 != 0;
5918fffb	259
cd7f97ca RH	260	case CC_OP_ADCX:
	261	case CC_OP_ADCOX:
	262	return dst;
	263
5918fffb	264	case CC_OP_ADDB:
8601c0b6	265	return compute_c_addb(dst, src1);
5918fffb	266	case CC_OP_ADDW:
8601c0b6	267	return compute_c_addw(dst, src1);
5918fffb	268	case CC_OP_ADDL:
8601c0b6	269	return compute_c_addl(dst, src1);
5918fffb BS	270
5918fffb BS	271	case CC_OP_ADCB:
988c3eb0	272	return compute_c_adcb(dst, src1, src2);
5918fffb	273	case CC_OP_ADCW:
988c3eb0	274	return compute_c_adcw(dst, src1, src2);
5918fffb	275	case CC_OP_ADCL:
988c3eb0	276	return compute_c_adcl(dst, src1, src2);
5918fffb BS	277
5918fffb BS	278	case CC_OP_SUBB:
8601c0b6	279	return compute_c_subb(dst, src1);
5918fffb	280	case CC_OP_SUBW:
8601c0b6	281	return compute_c_subw(dst, src1);
5918fffb	282	case CC_OP_SUBL:
8601c0b6	283	return compute_c_subl(dst, src1);
5918fffb BS	284
5918fffb BS	285	case CC_OP_SBBB:
988c3eb0	286	return compute_c_sbbb(dst, src1, src2);
5918fffb	287	case CC_OP_SBBW:
988c3eb0	288	return compute_c_sbbw(dst, src1, src2);
5918fffb	289	case CC_OP_SBBL:
988c3eb0	290	return compute_c_sbbl(dst, src1, src2);
5918fffb BS	291
5918fffb BS	292	case CC_OP_SHLB:
8601c0b6	293	return compute_c_shlb(dst, src1);
5918fffb	294	case CC_OP_SHLW:
8601c0b6	295	return compute_c_shlw(dst, src1);
5918fffb	296	case CC_OP_SHLL:
8601c0b6	297	return compute_c_shll(dst, src1);
5918fffb	298
bc4b43dc RH	299	case CC_OP_BMILGB:
	300	return compute_c_bmilgb(dst, src1);
	301	case CC_OP_BMILGW:
	302	return compute_c_bmilgw(dst, src1);
	303	case CC_OP_BMILGL:
	304	return compute_c_bmilgl(dst, src1);
	305
5918fffb	306	#ifdef TARGET_X86_64
5918fffb	307	case CC_OP_ADDQ:
8601c0b6	308	return compute_c_addq(dst, src1);
5918fffb	309	case CC_OP_ADCQ:
988c3eb0	310	return compute_c_adcq(dst, src1, src2);
5918fffb	311	case CC_OP_SUBQ:
8601c0b6	312	return compute_c_subq(dst, src1);
5918fffb	313	case CC_OP_SBBQ:
988c3eb0	314	return compute_c_sbbq(dst, src1, src2);
5918fffb	315	case CC_OP_SHLQ:
8601c0b6	316	return compute_c_shlq(dst, src1);
bc4b43dc RH	317	case CC_OP_BMILGQ:
bc4b43dc RH	318	return compute_c_bmilgq(dst, src1);
5918fffb BS	319	#endif
	320	}
	321	}
	322
f0967a1a BS	323	void helper_write_eflags(CPUX86State *env, target_ulong t0,
f0967a1a BS	324	uint32_t update_mask)
5918fffb BS	325	{
	326	cpu_load_eflags(env, t0, update_mask);
	327	}
	328
f0967a1a	329	target_ulong helper_read_eflags(CPUX86State *env)
5918fffb BS	330	{
	331	uint32_t eflags;
	332
db9f2597	333	eflags = cpu_cc_compute_all(env, CC_OP);
80cf2c81	334	eflags \|= (env->df & DF_MASK);
5918fffb BS	335	eflags \|= env->eflags & ~(VM_MASK \| RF_MASK);
	336	return eflags;
	337	}
	338
f0967a1a	339	void helper_clts(CPUX86State *env)
5918fffb BS	340	{
	341	env->cr[0] &= ~CR0_TS_MASK;
	342	env->hflags &= ~HF_TS_MASK;
	343	}
	344
f0967a1a	345	void helper_reset_rf(CPUX86State *env)
5918fffb BS	346	{
	347	env->eflags &= ~RF_MASK;
	348	}
	349
f0967a1a	350	void helper_cli(CPUX86State *env)
5918fffb BS	351	{
	352	env->eflags &= ~IF_MASK;
	353	}
	354
f0967a1a	355	void helper_sti(CPUX86State *env)
5918fffb BS	356	{
	357	env->eflags \|= IF_MASK;
	358	}
	359
a9321a4d PA	360	void helper_clac(CPUX86State *env)
	361	{
	362	env->eflags &= ~AC_MASK;
	363	}
	364
	365	void helper_stac(CPUX86State *env)
	366	{
	367	env->eflags \|= AC_MASK;
	368	}
	369
5918fffb BS	370	#if 0
5918fffb BS	371	/* vm86plus instructions */
f0967a1a	372	void helper_cli_vm(CPUX86State *env)
5918fffb BS	373	{
	374	env->eflags &= ~VIF_MASK;
	375	}
	376
f0967a1a	377	void helper_sti_vm(CPUX86State *env)
5918fffb BS	378	{
	379	env->eflags \|= VIF_MASK;
	380	if (env->eflags & VIP_MASK) {
	381	raise_exception(env, EXCP0D_GPF);
	382	}
	383	}
	384	#endif
	385
f0967a1a	386	void helper_set_inhibit_irq(CPUX86State *env)
5918fffb BS	387	{
	388	env->hflags \|= HF_INHIBIT_IRQ_MASK;
	389	}
	390
f0967a1a	391	void helper_reset_inhibit_irq(CPUX86State *env)
5918fffb BS	392	{
	393	env->hflags &= ~HF_INHIBIT_IRQ_MASK;
	394	}