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Merge remote-tracking branch 'stefanha/trivial-patches' into staging
[qemu.git] / target-i386 / cpu.c
CommitLineData
c6dc6f63
AP		 1/*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19#include <stdlib.h>
20#include <stdio.h>
21#include <string.h>
22#include <inttypes.h>
23
24#include "cpu.h"
25#include "kvm.h"
26
27#include "qemu-option.h"
28#include "qemu-config.h"
29
71ad61d3 30#include "qapi/qapi-visit-core.h"
e3966126 31#include "qmp-commands.h"
71ad61d3 32
28f52cc0
VR		 33#include "hyperv.h"
34
65dee380
IM		 35#include "hw/hw.h"
36
c6dc6f63
AP		 37/* feature flags taken from "Intel Processor Identification and the CPUID
38 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
39 * between feature naming conventions, aliases may be added.
40 */
41static const char *feature_name[] = {
42 "fpu", "vme", "de", "pse",
43 "tsc", "msr", "pae", "mce",
44 "cx8", "apic", NULL, "sep",
45 "mtrr", "pge", "mca", "cmov",
46 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
47 NULL, "ds" /* Intel dts */, "acpi", "mmx",
48 "fxsr", "sse", "sse2", "ss",
49 "ht" /* Intel htt */, "tm", "ia64", "pbe",
50};
51static const char *ext_feature_name[] = {
f370be3c 52 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
e117f772 53 "ds_cpl", "vmx", "smx", "est",
c6dc6f63 54 "tm2", "ssse3", "cid", NULL,
e117f772 55 "fma", "cx16", "xtpr", "pdcm",
434acb81 56 NULL, "pcid", "dca", "sse4.1|sse4_1",
e117f772 57 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
eaf3f097 58 "tsc-deadline", "aes", "xsave", "osxsave",
e117f772 59 "avx", NULL, NULL, "hypervisor",
c6dc6f63
AP		 60};
61static const char *ext2_feature_name[] = {
62 "fpu", "vme", "de", "pse",
63 "tsc", "msr", "pae", "mce",
64 "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall",
65 "mtrr", "pge", "mca", "cmov",
66 "pat", "pse36", NULL, NULL /* Linux mp */,
3ac8ebfe 67 "nx|xd", NULL, "mmxext", "mmx",
f370be3c 68 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
3ac8ebfe 69 NULL, "lm|i64", "3dnowext", "3dnow",
c6dc6f63
AP		 70};
71static const char *ext3_feature_name[] = {
72 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
73 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
e117f772 74 "3dnowprefetch", "osvw", "ibs", "xop",
c6dc6f63 75 "skinit", "wdt", NULL, NULL,
e117f772 76 "fma4", NULL, "cvt16", "nodeid_msr",
c6dc6f63
AP		 77 NULL, NULL, NULL, NULL,
78 NULL, NULL, NULL, NULL,
79 NULL, NULL, NULL, NULL,
80};
81
82static const char *kvm_feature_name[] = {
bfee7546 83 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, "kvm_pv_eoi", NULL,
c6dc6f63
AP		 84 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
85 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
86 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
87};
88
296acb64
JR		 89static const char *svm_feature_name[] = {
90 "npt", "lbrv", "svm_lock", "nrip_save",
91 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
92 NULL, NULL, "pause_filter", NULL,
93 "pfthreshold", NULL, NULL, NULL,
94 NULL, NULL, NULL, NULL,
95 NULL, NULL, NULL, NULL,
96 NULL, NULL, NULL, NULL,
97 NULL, NULL, NULL, NULL,
98};
99
c6dc6f63
AP		 100/* collects per-function cpuid data
101 */
102typedef struct model_features_t {
103 uint32_t *guest_feat;
104 uint32_t *host_feat;
105 uint32_t check_feat;
106 const char **flag_names;
107 uint32_t cpuid;
108 } model_features_t;
109
110int check_cpuid = 0;
111int enforce_cpuid = 0;
112
bb44e0d1
JK		 113void host_cpuid(uint32_t function, uint32_t count,
114 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
bdde476a
AP		 115{
116#if defined(CONFIG_KVM)
a1fd24af
AL		 117 uint32_t vec[4];
118
119#ifdef __x86_64__
120 asm volatile("cpuid"
121 : "=a"(vec[0]), "=b"(vec[1]),
122 "=c"(vec[2]), "=d"(vec[3])
123 : "0"(function), "c"(count) : "cc");
124#else
125 asm volatile("pusha \n\t"
126 "cpuid \n\t"
127 "mov %%eax, 0(%2) \n\t"
128 "mov %%ebx, 4(%2) \n\t"
129 "mov %%ecx, 8(%2) \n\t"
130 "mov %%edx, 12(%2) \n\t"
131 "popa"
132 : : "a"(function), "c"(count), "S"(vec)
133 : "memory", "cc");
134#endif
135
bdde476a 136 if (eax)
a1fd24af 137 *eax = vec[0];
bdde476a 138 if (ebx)
a1fd24af 139 *ebx = vec[1];
bdde476a 140 if (ecx)
a1fd24af 141 *ecx = vec[2];
bdde476a 142 if (edx)
a1fd24af 143 *edx = vec[3];
bdde476a
AP		 144#endif
145}
c6dc6f63
AP		 146
147#define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
148
149/* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
150 * a substring. ex if !NULL points to the first char after a substring,
151 * otherwise the string is assumed to sized by a terminating nul.
152 * Return lexical ordering of *s1:*s2.
153 */
154static int sstrcmp(const char *s1, const char *e1, const char *s2,
155 const char *e2)
156{
157 for (;;) {
158 if (!*s1 || !*s2 || *s1 != *s2)
159 return (*s1 - *s2);
160 ++s1, ++s2;
161 if (s1 == e1 && s2 == e2)
162 return (0);
163 else if (s1 == e1)
164 return (*s2);
165 else if (s2 == e2)
166 return (*s1);
167 }
168}
169
170/* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
171 * '|' delimited (possibly empty) strings in which case search for a match
172 * within the alternatives proceeds left to right. Return 0 for success,
173 * non-zero otherwise.
174 */
175static int altcmp(const char *s, const char *e, const char *altstr)
176{
177 const char *p, *q;
178
179 for (q = p = altstr; ; ) {
180 while (*p && *p != '|')
181 ++p;
182 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
183 return (0);
184 if (!*p)
185 return (1);
186 else
187 q = ++p;
188 }
189}
190
191/* search featureset for flag *[s..e), if found set corresponding bit in
e41e0fc6 192 * *pval and return true, otherwise return false
c6dc6f63 193 */
e41e0fc6
JK		 194static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
195 const char **featureset)
c6dc6f63
AP		 196{
197 uint32_t mask;
198 const char **ppc;
e41e0fc6 199 bool found = false;
c6dc6f63 200
e41e0fc6 201 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
c6dc6f63
AP		 202 if (*ppc && !altcmp(s, e, *ppc)) {
203 *pval |= mask;
e41e0fc6 204 found = true;
c6dc6f63 205 }
e41e0fc6
JK		 206 }
207 return found;
c6dc6f63
AP		 208}
209
210static void add_flagname_to_bitmaps(const char *flagname, uint32_t *features,
211 uint32_t *ext_features,
212 uint32_t *ext2_features,
213 uint32_t *ext3_features,
296acb64
JR		 214 uint32_t *kvm_features,
215 uint32_t *svm_features)
c6dc6f63
AP		 216{
217 if (!lookup_feature(features, flagname, NULL, feature_name) &&
218 !lookup_feature(ext_features, flagname, NULL, ext_feature_name) &&
219 !lookup_feature(ext2_features, flagname, NULL, ext2_feature_name) &&
220 !lookup_feature(ext3_features, flagname, NULL, ext3_feature_name) &&
296acb64
JR		 221 !lookup_feature(kvm_features, flagname, NULL, kvm_feature_name) &&
222 !lookup_feature(svm_features, flagname, NULL, svm_feature_name))
c6dc6f63
AP		 223 fprintf(stderr, "CPU feature %s not found\n", flagname);
224}
225
226typedef struct x86_def_t {
227 struct x86_def_t *next;
228 const char *name;
229 uint32_t level;
230 uint32_t vendor1, vendor2, vendor3;
231 int family;
232 int model;
233 int stepping;
b862d1fe 234 int tsc_khz;
296acb64
JR		 235 uint32_t features, ext_features, ext2_features, ext3_features;
236 uint32_t kvm_features, svm_features;
c6dc6f63
AP		 237 uint32_t xlevel;
238 char model_id[48];
239 int vendor_override;
240 uint32_t flags;
b3baa152 241 /* Store the results of Centaur's CPUID instructions */
242 uint32_t ext4_features;
243 uint32_t xlevel2;
13526728
EH		 244 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
245 uint32_t cpuid_7_0_ebx_features;
c6dc6f63
AP		 246} x86_def_t;
247
248#define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
249#define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
250 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
251#define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
252 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
253 CPUID_PSE36 | CPUID_FXSR)
254#define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
255#define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
256 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
257 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
258 CPUID_PAE | CPUID_SEP | CPUID_APIC)
42673936 259#define EXT2_FEATURE_MASK 0x0183F3FF
c6dc6f63 260
551a2dec
AP		 261#define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
262 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
263 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
264 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
265 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
8560efed
AJ		 266 /* partly implemented:
267 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
268 CPUID_PSE36 (needed for Solaris) */
269 /* missing:
270 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
551a2dec 271#define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
8713f8ff 272 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
551a2dec 273 CPUID_EXT_HYPERVISOR)
8560efed
AJ		 274 /* missing:
275 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
8713f8ff 276 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
551a2dec
AP		 277#define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
278 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
279 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
8560efed
AJ		 280 /* missing:
281 CPUID_EXT2_PDPE1GB */
551a2dec
AP		 282#define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
283 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
296acb64 284#define TCG_SVM_FEATURES 0
551a2dec 285
c6dc6f63
AP		 286/* maintains list of cpu model definitions
287 */
288static x86_def_t *x86_defs = {NULL};
289
290/* built-in cpu model definitions (deprecated)
291 */
292static x86_def_t builtin_x86_defs[] = {
c6dc6f63
AP		 293 {
294 .name = "qemu64",
295 .level = 4,
296 .vendor1 = CPUID_VENDOR_AMD_1,
297 .vendor2 = CPUID_VENDOR_AMD_2,
298 .vendor3 = CPUID_VENDOR_AMD_3,
299 .family = 6,
300 .model = 2,
301 .stepping = 3,
302 .features = PPRO_FEATURES |
c6dc6f63 303 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
c6dc6f63
AP		 304 CPUID_PSE36,
305 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
42673936 306 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 307 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
308 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
309 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
310 .xlevel = 0x8000000A,
c6dc6f63
AP		 311 },
312 {
313 .name = "phenom",
314 .level = 5,
315 .vendor1 = CPUID_VENDOR_AMD_1,
316 .vendor2 = CPUID_VENDOR_AMD_2,
317 .vendor3 = CPUID_VENDOR_AMD_3,
318 .family = 16,
319 .model = 2,
320 .stepping = 3,
c6dc6f63
AP		 321 .features = PPRO_FEATURES |
322 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed 323 CPUID_PSE36 | CPUID_VME | CPUID_HT,
c6dc6f63
AP		 324 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
325 CPUID_EXT_POPCNT,
42673936 326 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 327 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
328 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
8560efed 329 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
c6dc6f63
AP		 330 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
331 CPUID_EXT3_CR8LEG,
332 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
333 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
334 .ext3_features = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
335 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
296acb64 336 .svm_features = CPUID_SVM_NPT | CPUID_SVM_LBRV,
c6dc6f63
AP		 337 .xlevel = 0x8000001A,
338 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
339 },
340 {
341 .name = "core2duo",
342 .level = 10,
343 .family = 6,
344 .model = 15,
345 .stepping = 11,
c6dc6f63
AP		 346 .features = PPRO_FEATURES |
347 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
8560efed
AJ		 348 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
349 CPUID_HT | CPUID_TM | CPUID_PBE,
350 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
351 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
352 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 353 .ext2_features = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
354 .ext3_features = CPUID_EXT3_LAHF_LM,
355 .xlevel = 0x80000008,
356 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
357 },
358 {
359 .name = "kvm64",
360 .level = 5,
361 .vendor1 = CPUID_VENDOR_INTEL_1,
362 .vendor2 = CPUID_VENDOR_INTEL_2,
363 .vendor3 = CPUID_VENDOR_INTEL_3,
364 .family = 15,
365 .model = 6,
366 .stepping = 1,
367 /* Missing: CPUID_VME, CPUID_HT */
368 .features = PPRO_FEATURES |
369 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
370 CPUID_PSE36,
371 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
372 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_CX16,
373 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
42673936 374 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) |
c6dc6f63
AP		 375 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
376 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
377 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
378 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
379 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
380 .ext3_features = 0,
381 .xlevel = 0x80000008,
382 .model_id = "Common KVM processor"
383 },
c6dc6f63
AP		 384 {
385 .name = "qemu32",
386 .level = 4,
387 .family = 6,
388 .model = 3,
389 .stepping = 3,
390 .features = PPRO_FEATURES,
391 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
58012d66 392 .xlevel = 0x80000004,
c6dc6f63 393 },
eafaf1e5
AP		 394 {
395 .name = "kvm32",
396 .level = 5,
397 .family = 15,
398 .model = 6,
399 .stepping = 1,
400 .features = PPRO_FEATURES |
401 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
402 .ext_features = CPUID_EXT_SSE3,
403 .ext2_features = PPRO_FEATURES & EXT2_FEATURE_MASK,
404 .ext3_features = 0,
405 .xlevel = 0x80000008,
406 .model_id = "Common 32-bit KVM processor"
407 },
c6dc6f63
AP		 408 {
409 .name = "coreduo",
410 .level = 10,
411 .family = 6,
412 .model = 14,
413 .stepping = 8,
c6dc6f63 414 .features = PPRO_FEATURES | CPUID_VME |
8560efed
AJ		 415 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
416 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
417 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
418 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
c6dc6f63
AP		 419 .ext2_features = CPUID_EXT2_NX,
420 .xlevel = 0x80000008,
421 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
422 },
423 {
424 .name = "486",
58012d66 425 .level = 1,
c6dc6f63
AP		 426 .family = 4,
427 .model = 0,
428 .stepping = 0,
429 .features = I486_FEATURES,
430 .xlevel = 0,
431 },
432 {
433 .name = "pentium",
434 .level = 1,
435 .family = 5,
436 .model = 4,
437 .stepping = 3,
438 .features = PENTIUM_FEATURES,
439 .xlevel = 0,
440 },
441 {
442 .name = "pentium2",
443 .level = 2,
444 .family = 6,
445 .model = 5,
446 .stepping = 2,
447 .features = PENTIUM2_FEATURES,
448 .xlevel = 0,
449 },
450 {
451 .name = "pentium3",
452 .level = 2,
453 .family = 6,
454 .model = 7,
455 .stepping = 3,
456 .features = PENTIUM3_FEATURES,
457 .xlevel = 0,
458 },
459 {
460 .name = "athlon",
461 .level = 2,
462 .vendor1 = CPUID_VENDOR_AMD_1,
463 .vendor2 = CPUID_VENDOR_AMD_2,
464 .vendor3 = CPUID_VENDOR_AMD_3,
465 .family = 6,
466 .model = 2,
467 .stepping = 3,
468 .features = PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA,
42673936 469 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
c6dc6f63 470 .xlevel = 0x80000008,
c6dc6f63
AP		 471 },
472 {
473 .name = "n270",
474 /* original is on level 10 */
475 .level = 5,
476 .family = 6,
477 .model = 28,
478 .stepping = 2,
479 .features = PPRO_FEATURES |
8560efed
AJ		 480 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
481 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
c6dc6f63 482 /* Some CPUs got no CPUID_SEP */
8560efed
AJ		 483 .ext_features = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
484 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR,
42673936 485 .ext2_features = (PPRO_FEATURES & EXT2_FEATURE_MASK) | CPUID_EXT2_NX,
8560efed 486 .ext3_features = CPUID_EXT3_LAHF_LM,
c6dc6f63
AP		 487 .xlevel = 0x8000000A,
488 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
489 },
490};
491
492static int cpu_x86_fill_model_id(char *str)
493{
494 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
495 int i;
496
497 for (i = 0; i < 3; i++) {
498 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
499 memcpy(str + i * 16 + 0, &eax, 4);
500 memcpy(str + i * 16 + 4, &ebx, 4);
501 memcpy(str + i * 16 + 8, &ecx, 4);
502 memcpy(str + i * 16 + 12, &edx, 4);
503 }
504 return 0;
505}
506
507static int cpu_x86_fill_host(x86_def_t *x86_cpu_def)
508{
509 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
510
511 x86_cpu_def->name = "host";
512 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
513 x86_cpu_def->level = eax;
514 x86_cpu_def->vendor1 = ebx;
515 x86_cpu_def->vendor2 = edx;
516 x86_cpu_def->vendor3 = ecx;
517
518 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
519 x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
520 x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
521 x86_cpu_def->stepping = eax & 0x0F;
522 x86_cpu_def->ext_features = ecx;
523 x86_cpu_def->features = edx;
524
13526728
EH		 525 if (kvm_enabled() && x86_cpu_def->level >= 7) {
526 x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX);
527 } else {
528 x86_cpu_def->cpuid_7_0_ebx_features = 0;
529 }
530
c6dc6f63
AP		 531 host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx);
532 x86_cpu_def->xlevel = eax;
533
534 host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
535 x86_cpu_def->ext2_features = edx;
536 x86_cpu_def->ext3_features = ecx;
537 cpu_x86_fill_model_id(x86_cpu_def->model_id);
538 x86_cpu_def->vendor_override = 0;
539
b3baa152 540 /* Call Centaur's CPUID instruction. */
541 if (x86_cpu_def->vendor1 == CPUID_VENDOR_VIA_1 &&
542 x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 &&
543 x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) {
544 host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx);
545 if (eax >= 0xC0000001) {
546 /* Support VIA max extended level */
547 x86_cpu_def->xlevel2 = eax;
548 host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx);
549 x86_cpu_def->ext4_features = edx;
550 }
551 }
296acb64
JR		 552
553 /*
554 * Every SVM feature requires emulation support in KVM - so we can't just
555 * read the host features here. KVM might even support SVM features not
556 * available on the host hardware. Just set all bits and mask out the
557 * unsupported ones later.
558 */
559 x86_cpu_def->svm_features = -1;
560
c6dc6f63
AP		 561 return 0;
562}
563
564static int unavailable_host_feature(struct model_features_t *f, uint32_t mask)
565{
566 int i;
567
568 for (i = 0; i < 32; ++i)
569 if (1 << i & mask) {
570 fprintf(stderr, "warning: host cpuid %04x_%04x lacks requested"
571 " flag '%s' [0x%08x]\n",
572 f->cpuid >> 16, f->cpuid & 0xffff,
573 f->flag_names[i] ? f->flag_names[i] : "[reserved]", mask);
574 break;
575 }
576 return 0;
577}
578
579/* best effort attempt to inform user requested cpu flags aren't making
580 * their way to the guest. Note: ft[].check_feat ideally should be
581 * specified via a guest_def field to suppress report of extraneous flags.
582 */
583static int check_features_against_host(x86_def_t *guest_def)
584{
585 x86_def_t host_def;
586 uint32_t mask;
587 int rv, i;
588 struct model_features_t ft[] = {
589 {&guest_def->features, &host_def.features,
590 ~0, feature_name, 0x00000000},
591 {&guest_def->ext_features, &host_def.ext_features,
592 ~CPUID_EXT_HYPERVISOR, ext_feature_name, 0x00000001},
593 {&guest_def->ext2_features, &host_def.ext2_features,
594 ~PPRO_FEATURES, ext2_feature_name, 0x80000000},
595 {&guest_def->ext3_features, &host_def.ext3_features,
596 ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}};
597
598 cpu_x86_fill_host(&host_def);
66fe09ee 599 for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i)
c6dc6f63
AP		 600 for (mask = 1; mask; mask <<= 1)
601 if (ft[i].check_feat & mask && *ft[i].guest_feat & mask &&
602 !(*ft[i].host_feat & mask)) {
603 unavailable_host_feature(&ft[i], mask);
604 rv = 1;
605 }
606 return rv;
607}
608
95b8519d
AF		 609static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
610 const char *name, Error **errp)
611{
612 X86CPU *cpu = X86_CPU(obj);
613 CPUX86State *env = &cpu->env;
614 int64_t value;
615
616 value = (env->cpuid_version >> 8) & 0xf;
617 if (value == 0xf) {
618 value += (env->cpuid_version >> 20) & 0xff;
619 }
620 visit_type_int(v, &value, name, errp);
621}
622
71ad61d3
AF		 623static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
624 const char *name, Error **errp)
ed5e1ec3 625{
71ad61d3
AF		 626 X86CPU *cpu = X86_CPU(obj);
627 CPUX86State *env = &cpu->env;
628 const int64_t min = 0;
629 const int64_t max = 0xff + 0xf;
630 int64_t value;
631
632 visit_type_int(v, &value, name, errp);
633 if (error_is_set(errp)) {
634 return;
635 }
636 if (value < min || value > max) {
637 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
638 name ? name : "null", value, min, max);
639 return;
640 }
641
ed5e1ec3 642 env->cpuid_version &= ~0xff00f00;
71ad61d3
AF		 643 if (value > 0x0f) {
644 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
ed5e1ec3 645 } else {
71ad61d3 646 env->cpuid_version |= value << 8;
ed5e1ec3
AF		 647 }
648}
649
67e30c83
AF		 650static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
651 const char *name, Error **errp)
652{
653 X86CPU *cpu = X86_CPU(obj);
654 CPUX86State *env = &cpu->env;
655 int64_t value;
656
657 value = (env->cpuid_version >> 4) & 0xf;
658 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
659 visit_type_int(v, &value, name, errp);
660}
661
c5291a4f
AF		 662static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
663 const char *name, Error **errp)
b0704cbd 664{
c5291a4f
AF		 665 X86CPU *cpu = X86_CPU(obj);
666 CPUX86State *env = &cpu->env;
667 const int64_t min = 0;
668 const int64_t max = 0xff;
669 int64_t value;
670
671 visit_type_int(v, &value, name, errp);
672 if (error_is_set(errp)) {
673 return;
674 }
675 if (value < min || value > max) {
676 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
677 name ? name : "null", value, min, max);
678 return;
679 }
680
b0704cbd 681 env->cpuid_version &= ~0xf00f0;
c5291a4f 682 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
b0704cbd
AF		 683}
684
35112e41
AF		 685static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
686 void *opaque, const char *name,
687 Error **errp)
688{
689 X86CPU *cpu = X86_CPU(obj);
690 CPUX86State *env = &cpu->env;
691 int64_t value;
692
693 value = env->cpuid_version & 0xf;
694 visit_type_int(v, &value, name, errp);
695}
696
036e2222
AF		 697static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
698 void *opaque, const char *name,
699 Error **errp)
38c3dc46 700{
036e2222
AF		 701 X86CPU *cpu = X86_CPU(obj);
702 CPUX86State *env = &cpu->env;
703 const int64_t min = 0;
704 const int64_t max = 0xf;
705 int64_t value;
706
707 visit_type_int(v, &value, name, errp);
708 if (error_is_set(errp)) {
709 return;
710 }
711 if (value < min || value > max) {
712 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
713 name ? name : "null", value, min, max);
714 return;
715 }
716
38c3dc46 717 env->cpuid_version &= ~0xf;
036e2222 718 env->cpuid_version |= value & 0xf;
38c3dc46
AF		 719}
720
8e1898bf
AF		 721static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
722 const char *name, Error **errp)
723{
724 X86CPU *cpu = X86_CPU(obj);
8e1898bf 725
fa029887 726 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 727}
728
729static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
730 const char *name, Error **errp)
731{
732 X86CPU *cpu = X86_CPU(obj);
8e1898bf 733
fa029887 734 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
8e1898bf
AF		 735}
736
16b93aa8
AF		 737static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
738 const char *name, Error **errp)
739{
740 X86CPU *cpu = X86_CPU(obj);
16b93aa8 741
fa029887 742 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 743}
744
745static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
746 const char *name, Error **errp)
747{
748 X86CPU *cpu = X86_CPU(obj);
16b93aa8 749
fa029887 750 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
16b93aa8
AF		 751}
752
d480e1af
AF		 753static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
754{
755 X86CPU *cpu = X86_CPU(obj);
756 CPUX86State *env = &cpu->env;
757 char *value;
758 int i;
759
760 value = (char *)g_malloc(12 + 1);
761 for (i = 0; i < 4; i++) {
762 value[i ] = env->cpuid_vendor1 >> (8 * i);
763 value[i + 4] = env->cpuid_vendor2 >> (8 * i);
764 value[i + 8] = env->cpuid_vendor3 >> (8 * i);
765 }
766 value[12] = '\0';
767 return value;
768}
769
770static void x86_cpuid_set_vendor(Object *obj, const char *value,
771 Error **errp)
772{
773 X86CPU *cpu = X86_CPU(obj);
774 CPUX86State *env = &cpu->env;
775 int i;
776
777 if (strlen(value) != 12) {
778 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
779 "vendor", value);
780 return;
781 }
782
783 env->cpuid_vendor1 = 0;
784 env->cpuid_vendor2 = 0;
785 env->cpuid_vendor3 = 0;
786 for (i = 0; i < 4; i++) {
787 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
788 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
789 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
790 }
791 env->cpuid_vendor_override = 1;
792}
793
63e886eb
AF		 794static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
795{
796 X86CPU *cpu = X86_CPU(obj);
797 CPUX86State *env = &cpu->env;
798 char *value;
799 int i;
800
801 value = g_malloc(48 + 1);
802 for (i = 0; i < 48; i++) {
803 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
804 }
805 value[48] = '\0';
806 return value;
807}
808
938d4c25
AF		 809static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
810 Error **errp)
dcce6675 811{
938d4c25
AF		 812 X86CPU *cpu = X86_CPU(obj);
813 CPUX86State *env = &cpu->env;
dcce6675
AF		 814 int c, len, i;
815
816 if (model_id == NULL) {
817 model_id = "";
818 }
819 len = strlen(model_id);
d0a6acf4 820 memset(env->cpuid_model, 0, 48);
dcce6675
AF		 821 for (i = 0; i < 48; i++) {
822 if (i >= len) {
823 c = '\0';
824 } else {
825 c = (uint8_t)model_id[i];
826 }
827 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
828 }
829}
830
89e48965
AF		 831static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
832 const char *name, Error **errp)
833{
834 X86CPU *cpu = X86_CPU(obj);
835 int64_t value;
836
837 value = cpu->env.tsc_khz * 1000;
838 visit_type_int(v, &value, name, errp);
839}
840
841static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
842 const char *name, Error **errp)
843{
844 X86CPU *cpu = X86_CPU(obj);
845 const int64_t min = 0;
846 const int64_t max = INT_MAX;
847 int64_t value;
848
849 visit_type_int(v, &value, name, errp);
850 if (error_is_set(errp)) {
851 return;
852 }
853 if (value < min || value > max) {
854 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
855 name ? name : "null", value, min, max);
856 return;
857 }
858
859 cpu->env.tsc_khz = value / 1000;
860}
861
c6dc6f63
AP		 862static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model)
863{
864 unsigned int i;
865 x86_def_t *def;
866
d3c481b3 867 char *s = g_strdup(cpu_model);
c6dc6f63 868 char *featurestr, *name = strtok(s, ",");
296acb64
JR		 869 /* Features to be added*/
870 uint32_t plus_features = 0, plus_ext_features = 0;
871 uint32_t plus_ext2_features = 0, plus_ext3_features = 0;
872 uint32_t plus_kvm_features = 0, plus_svm_features = 0;
873 /* Features to be removed */
874 uint32_t minus_features = 0, minus_ext_features = 0;
875 uint32_t minus_ext2_features = 0, minus_ext3_features = 0;
876 uint32_t minus_kvm_features = 0, minus_svm_features = 0;
c6dc6f63
AP		 877 uint32_t numvalue;
878
879 for (def = x86_defs; def; def = def->next)
04c5b17a 880 if (name && !strcmp(name, def->name))
c6dc6f63 881 break;
04c5b17a 882 if (kvm_enabled() && name && strcmp(name, "host") == 0) {
c6dc6f63
AP		 883 cpu_x86_fill_host(x86_cpu_def);
884 } else if (!def) {
885 goto error;
886 } else {
887 memcpy(x86_cpu_def, def, sizeof(*def));
888 }
889
890 plus_kvm_features = ~0; /* not supported bits will be filtered out later */
891
892 add_flagname_to_bitmaps("hypervisor", &plus_features,
893 &plus_ext_features, &plus_ext2_features, &plus_ext3_features,
296acb64 894 &plus_kvm_features, &plus_svm_features);
c6dc6f63
AP		 895
896 featurestr = strtok(NULL, ",");
897
898 while (featurestr) {
899 char *val;
900 if (featurestr[0] == '+') {
296acb64
JR		 901 add_flagname_to_bitmaps(featurestr + 1, &plus_features,
902 &plus_ext_features, &plus_ext2_features,
903 &plus_ext3_features, &plus_kvm_features,
904 &plus_svm_features);
c6dc6f63 905 } else if (featurestr[0] == '-') {
296acb64
JR		 906 add_flagname_to_bitmaps(featurestr + 1, &minus_features,
907 &minus_ext_features, &minus_ext2_features,
908 &minus_ext3_features, &minus_kvm_features,
909 &minus_svm_features);
c6dc6f63
AP		 910 } else if ((val = strchr(featurestr, '='))) {
911 *val = 0; val++;
912 if (!strcmp(featurestr, "family")) {
913 char *err;
914 numvalue = strtoul(val, &err, 0);
a88a677f 915 if (!*val || *err || numvalue > 0xff + 0xf) {
c6dc6f63
AP		 916 fprintf(stderr, "bad numerical value %s\n", val);
917 goto error;
918 }
919 x86_cpu_def->family = numvalue;
920 } else if (!strcmp(featurestr, "model")) {
921 char *err;
922 numvalue = strtoul(val, &err, 0);
923 if (!*val || *err || numvalue > 0xff) {
924 fprintf(stderr, "bad numerical value %s\n", val);
925 goto error;
926 }
927 x86_cpu_def->model = numvalue;
928 } else if (!strcmp(featurestr, "stepping")) {
929 char *err;
930 numvalue = strtoul(val, &err, 0);
931 if (!*val || *err || numvalue > 0xf) {
932 fprintf(stderr, "bad numerical value %s\n", val);
933 goto error;
934 }
935 x86_cpu_def->stepping = numvalue ;
936 } else if (!strcmp(featurestr, "level")) {
937 char *err;
938 numvalue = strtoul(val, &err, 0);
939 if (!*val || *err) {
940 fprintf(stderr, "bad numerical value %s\n", val);
941 goto error;
942 }
943 x86_cpu_def->level = numvalue;
944 } else if (!strcmp(featurestr, "xlevel")) {
945 char *err;
946 numvalue = strtoul(val, &err, 0);
947 if (!*val || *err) {
948 fprintf(stderr, "bad numerical value %s\n", val);
949 goto error;
950 }
951 if (numvalue < 0x80000000) {
2f7a21c4 952 numvalue += 0x80000000;
c6dc6f63
AP		 953 }
954 x86_cpu_def->xlevel = numvalue;
955 } else if (!strcmp(featurestr, "vendor")) {
956 if (strlen(val) != 12) {
957 fprintf(stderr, "vendor string must be 12 chars long\n");
958 goto error;
959 }
960 x86_cpu_def->vendor1 = 0;
961 x86_cpu_def->vendor2 = 0;
962 x86_cpu_def->vendor3 = 0;
963 for(i = 0; i < 4; i++) {
964 x86_cpu_def->vendor1 |= ((uint8_t)val[i ]) << (8 * i);
965 x86_cpu_def->vendor2 |= ((uint8_t)val[i + 4]) << (8 * i);
966 x86_cpu_def->vendor3 |= ((uint8_t)val[i + 8]) << (8 * i);
967 }
968 x86_cpu_def->vendor_override = 1;
969 } else if (!strcmp(featurestr, "model_id")) {
970 pstrcpy(x86_cpu_def->model_id, sizeof(x86_cpu_def->model_id),
971 val);
b862d1fe
JR		 972 } else if (!strcmp(featurestr, "tsc_freq")) {
973 int64_t tsc_freq;
974 char *err;
975
976 tsc_freq = strtosz_suffix_unit(val, &err,
977 STRTOSZ_DEFSUFFIX_B, 1000);
45009a30 978 if (tsc_freq < 0 || *err) {
b862d1fe
JR		 979 fprintf(stderr, "bad numerical value %s\n", val);
980 goto error;
981 }
982 x86_cpu_def->tsc_khz = tsc_freq / 1000;
28f52cc0
VR		 983 } else if (!strcmp(featurestr, "hv_spinlocks")) {
984 char *err;
985 numvalue = strtoul(val, &err, 0);
986 if (!*val || *err) {
987 fprintf(stderr, "bad numerical value %s\n", val);
988 goto error;
989 }
990 hyperv_set_spinlock_retries(numvalue);
c6dc6f63
AP		 991 } else {
992 fprintf(stderr, "unrecognized feature %s\n", featurestr);
993 goto error;
994 }
995 } else if (!strcmp(featurestr, "check")) {
996 check_cpuid = 1;
997 } else if (!strcmp(featurestr, "enforce")) {
998 check_cpuid = enforce_cpuid = 1;
28f52cc0
VR		 999 } else if (!strcmp(featurestr, "hv_relaxed")) {
1000 hyperv_enable_relaxed_timing(true);
1001 } else if (!strcmp(featurestr, "hv_vapic")) {
1002 hyperv_enable_vapic_recommended(true);
c6dc6f63
AP		 1003 } else {
1004 fprintf(stderr, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr);
1005 goto error;
1006 }
1007 featurestr = strtok(NULL, ",");
1008 }
1009 x86_cpu_def->features |= plus_features;
1010 x86_cpu_def->ext_features |= plus_ext_features;
1011 x86_cpu_def->ext2_features |= plus_ext2_features;
1012 x86_cpu_def->ext3_features |= plus_ext3_features;
1013 x86_cpu_def->kvm_features |= plus_kvm_features;
296acb64 1014 x86_cpu_def->svm_features |= plus_svm_features;
c6dc6f63
AP		 1015 x86_cpu_def->features &= ~minus_features;
1016 x86_cpu_def->ext_features &= ~minus_ext_features;
1017 x86_cpu_def->ext2_features &= ~minus_ext2_features;
1018 x86_cpu_def->ext3_features &= ~minus_ext3_features;
1019 x86_cpu_def->kvm_features &= ~minus_kvm_features;
296acb64 1020 x86_cpu_def->svm_features &= ~minus_svm_features;
c6dc6f63
AP		 1021 if (check_cpuid) {
1022 if (check_features_against_host(x86_cpu_def) && enforce_cpuid)
1023 goto error;
1024 }
d3c481b3 1025 g_free(s);
c6dc6f63
AP		 1026 return 0;
1027
1028error:
d3c481b3 1029 g_free(s);
c6dc6f63
AP		 1030 return -1;
1031}
1032
1033/* generate a composite string into buf of all cpuid names in featureset
1034 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1035 * if flags, suppress names undefined in featureset.
1036 */
1037static void listflags(char *buf, int bufsize, uint32_t fbits,
1038 const char **featureset, uint32_t flags)
1039{
1040 const char **p = &featureset[31];
1041 char *q, *b, bit;
1042 int nc;
1043
1044 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1045 *buf = '\0';
1046 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1047 if (fbits & 1 << bit && (*p || !flags)) {
1048 if (*p)
1049 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1050 else
1051 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1052 if (bufsize <= nc) {
1053 if (b) {
1054 memcpy(b, "...", sizeof("..."));
1055 }
1056 return;
1057 }
1058 q += nc;
1059 bufsize -= nc;
1060 }
1061}
1062
1063/* generate CPU information:
1064 * -? list model names
1065 * -?model list model names/IDs
1066 * -?dump output all model (x86_def_t) data
1067 * -?cpuid list all recognized cpuid flag names
1068 */
9a78eead 1069void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf, const char *optarg)
c6dc6f63
AP		 1070{
1071 unsigned char model = !strcmp("?model", optarg);
1072 unsigned char dump = !strcmp("?dump", optarg);
1073 unsigned char cpuid = !strcmp("?cpuid", optarg);
1074 x86_def_t *def;
1075 char buf[256];
1076
1077 if (cpuid) {
1078 (*cpu_fprintf)(f, "Recognized CPUID flags:\n");
1079 listflags(buf, sizeof (buf), (uint32_t)~0, feature_name, 1);
1080 (*cpu_fprintf)(f, " f_edx: %s\n", buf);
1081 listflags(buf, sizeof (buf), (uint32_t)~0, ext_feature_name, 1);
1082 (*cpu_fprintf)(f, " f_ecx: %s\n", buf);
1083 listflags(buf, sizeof (buf), (uint32_t)~0, ext2_feature_name, 1);
1084 (*cpu_fprintf)(f, " extf_edx: %s\n", buf);
1085 listflags(buf, sizeof (buf), (uint32_t)~0, ext3_feature_name, 1);
1086 (*cpu_fprintf)(f, " extf_ecx: %s\n", buf);
1087 return;
1088 }
1089 for (def = x86_defs; def; def = def->next) {
1090 snprintf(buf, sizeof (buf), def->flags ? "[%s]": "%s", def->name);
1091 if (model || dump) {
1092 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1093 } else {
1094 (*cpu_fprintf)(f, "x86 %16s\n", buf);
1095 }
1096 if (dump) {
1097 memcpy(buf, &def->vendor1, sizeof (def->vendor1));
1098 memcpy(buf + 4, &def->vendor2, sizeof (def->vendor2));
1099 memcpy(buf + 8, &def->vendor3, sizeof (def->vendor3));
1100 buf[12] = '\0';
1101 (*cpu_fprintf)(f,
1102 " family %d model %d stepping %d level %d xlevel 0x%x"
1103 " vendor \"%s\"\n",
1104 def->family, def->model, def->stepping, def->level,
1105 def->xlevel, buf);
1106 listflags(buf, sizeof (buf), def->features, feature_name, 0);
1107 (*cpu_fprintf)(f, " feature_edx %08x (%s)\n", def->features,
1108 buf);
1109 listflags(buf, sizeof (buf), def->ext_features, ext_feature_name,
1110 0);
1111 (*cpu_fprintf)(f, " feature_ecx %08x (%s)\n", def->ext_features,
1112 buf);
1113 listflags(buf, sizeof (buf), def->ext2_features, ext2_feature_name,
1114 0);
1115 (*cpu_fprintf)(f, " extfeature_edx %08x (%s)\n",
1116 def->ext2_features, buf);
1117 listflags(buf, sizeof (buf), def->ext3_features, ext3_feature_name,
1118 0);
1119 (*cpu_fprintf)(f, " extfeature_ecx %08x (%s)\n",
1120 def->ext3_features, buf);
1121 (*cpu_fprintf)(f, "\n");
1122 }
1123 }
ed2c54d4
AP		 1124 if (kvm_enabled()) {
1125 (*cpu_fprintf)(f, "x86 %16s\n", "[host]");
1126 }
c6dc6f63
AP		 1127}
1128
e3966126
AL		 1129CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
1130{
1131 CpuDefinitionInfoList *cpu_list = NULL;
1132 x86_def_t *def;
1133
1134 for (def = x86_defs; def; def = def->next) {
1135 CpuDefinitionInfoList *entry;
1136 CpuDefinitionInfo *info;
1137
1138 info = g_malloc0(sizeof(*info));
1139 info->name = g_strdup(def->name);
1140
1141 entry = g_malloc0(sizeof(*entry));
1142 entry->value = info;
1143 entry->next = cpu_list;
1144 cpu_list = entry;
1145 }
1146
1147 return cpu_list;
1148}
1149
61dcd775 1150int cpu_x86_register(X86CPU *cpu, const char *cpu_model)
c6dc6f63 1151{
61dcd775 1152 CPUX86State *env = &cpu->env;
c6dc6f63 1153 x86_def_t def1, *def = &def1;
71ad61d3 1154 Error *error = NULL;
c6dc6f63 1155
db0ad1ba
JR		 1156 memset(def, 0, sizeof(*def));
1157
c6dc6f63
AP		 1158 if (cpu_x86_find_by_name(def, cpu_model) < 0)
1159 return -1;
1160 if (def->vendor1) {
1161 env->cpuid_vendor1 = def->vendor1;
1162 env->cpuid_vendor2 = def->vendor2;
1163 env->cpuid_vendor3 = def->vendor3;
1164 } else {
1165 env->cpuid_vendor1 = CPUID_VENDOR_INTEL_1;
1166 env->cpuid_vendor2 = CPUID_VENDOR_INTEL_2;
1167 env->cpuid_vendor3 = CPUID_VENDOR_INTEL_3;
1168 }
1169 env->cpuid_vendor_override = def->vendor_override;
8e1898bf 1170 object_property_set_int(OBJECT(cpu), def->level, "level", &error);
71ad61d3 1171 object_property_set_int(OBJECT(cpu), def->family, "family", &error);
c5291a4f 1172 object_property_set_int(OBJECT(cpu), def->model, "model", &error);
036e2222 1173 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", &error);
c6dc6f63 1174 env->cpuid_features = def->features;
c6dc6f63
AP		 1175 env->cpuid_ext_features = def->ext_features;
1176 env->cpuid_ext2_features = def->ext2_features;
4d067ed7 1177 env->cpuid_ext3_features = def->ext3_features;
16b93aa8 1178 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", &error);
c6dc6f63 1179 env->cpuid_kvm_features = def->kvm_features;
296acb64 1180 env->cpuid_svm_features = def->svm_features;
b3baa152 1181 env->cpuid_ext4_features = def->ext4_features;
13526728 1182 env->cpuid_7_0_ebx = def->cpuid_7_0_ebx_features;
b3baa152 1183 env->cpuid_xlevel2 = def->xlevel2;
89e48965
AF		 1184 object_property_set_int(OBJECT(cpu), (int64_t)def->tsc_khz * 1000,
1185 "tsc-frequency", &error);
551a2dec
AP		 1186 if (!kvm_enabled()) {
1187 env->cpuid_features &= TCG_FEATURES;
1188 env->cpuid_ext_features &= TCG_EXT_FEATURES;
1189 env->cpuid_ext2_features &= (TCG_EXT2_FEATURES
1190#ifdef TARGET_X86_64
1191 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
1192#endif
1193 );
1194 env->cpuid_ext3_features &= TCG_EXT3_FEATURES;
296acb64 1195 env->cpuid_svm_features &= TCG_SVM_FEATURES;
551a2dec 1196 }
938d4c25 1197 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error);
71ad61d3
AF		 1198 if (error_is_set(&error)) {
1199 error_free(error);
1200 return -1;
1201 }
c6dc6f63
AP		 1202 return 0;
1203}
1204
1205#if !defined(CONFIG_USER_ONLY)
1206/* copy vendor id string to 32 bit register, nul pad as needed
1207 */
1208static void cpyid(const char *s, uint32_t *id)
1209{
1210 char *d = (char *)id;
1211 char i;
1212
1213 for (i = sizeof (*id); i--; )
1214 *d++ = *s ? *s++ : '\0';
1215}
1216
1217/* interpret radix and convert from string to arbitrary scalar,
1218 * otherwise flag failure
1219 */
1220#define setscalar(pval, str, perr) \
1221{ \
1222 char *pend; \
1223 unsigned long ul; \
1224 \
1225 ul = strtoul(str, &pend, 0); \
1226 *str && !*pend ? (*pval = ul) : (*perr = 1); \
1227}
1228
1229/* map cpuid options to feature bits, otherwise return failure
1230 * (option tags in *str are delimited by whitespace)
1231 */
1232static void setfeatures(uint32_t *pval, const char *str,
1233 const char **featureset, int *perr)
1234{
1235 const char *p, *q;
1236
1237 for (q = p = str; *p || *q; q = p) {
1238 while (iswhite(*p))
1239 q = ++p;
1240 while (*p && !iswhite(*p))
1241 ++p;
1242 if (!*q && !*p)
1243 return;
1244 if (!lookup_feature(pval, q, p, featureset)) {
1245 fprintf(stderr, "error: feature \"%.*s\" not available in set\n",
1246 (int)(p - q), q);
1247 *perr = 1;
1248 return;
1249 }
1250 }
1251}
1252
1253/* map config file options to x86_def_t form
1254 */
1255static int cpudef_setfield(const char *name, const char *str, void *opaque)
1256{
1257 x86_def_t *def = opaque;
1258 int err = 0;
1259
1260 if (!strcmp(name, "name")) {
99e1dec0 1261 g_free((void *)def->name);
d3c481b3 1262 def->name = g_strdup(str);
c6dc6f63
AP		 1263 } else if (!strcmp(name, "model_id")) {
1264 strncpy(def->model_id, str, sizeof (def->model_id));
1265 } else if (!strcmp(name, "level")) {
1266 setscalar(&def->level, str, &err)
1267 } else if (!strcmp(name, "vendor")) {
1268 cpyid(&str[0], &def->vendor1);
1269 cpyid(&str[4], &def->vendor2);
1270 cpyid(&str[8], &def->vendor3);
1271 } else if (!strcmp(name, "family")) {
1272 setscalar(&def->family, str, &err)
1273 } else if (!strcmp(name, "model")) {
1274 setscalar(&def->model, str, &err)
1275 } else if (!strcmp(name, "stepping")) {
1276 setscalar(&def->stepping, str, &err)
1277 } else if (!strcmp(name, "feature_edx")) {
1278 setfeatures(&def->features, str, feature_name, &err);
1279 } else if (!strcmp(name, "feature_ecx")) {
1280 setfeatures(&def->ext_features, str, ext_feature_name, &err);
1281 } else if (!strcmp(name, "extfeature_edx")) {
1282 setfeatures(&def->ext2_features, str, ext2_feature_name, &err);
1283 } else if (!strcmp(name, "extfeature_ecx")) {
1284 setfeatures(&def->ext3_features, str, ext3_feature_name, &err);
1285 } else if (!strcmp(name, "xlevel")) {
1286 setscalar(&def->xlevel, str, &err)
1287 } else {
1288 fprintf(stderr, "error: unknown option [%s = %s]\n", name, str);
1289 return (1);
1290 }
1291 if (err) {
1292 fprintf(stderr, "error: bad option value [%s = %s]\n", name, str);
1293 return (1);
1294 }
1295 return (0);
1296}
1297
1298/* register config file entry as x86_def_t
1299 */
1300static int cpudef_register(QemuOpts *opts, void *opaque)
1301{
7267c094 1302 x86_def_t *def = g_malloc0(sizeof (x86_def_t));
c6dc6f63
AP		 1303
1304 qemu_opt_foreach(opts, cpudef_setfield, def, 1);
1305 def->next = x86_defs;
1306 x86_defs = def;
1307 return (0);
1308}
0e26b7b8
BS		 1309
1310void cpu_clear_apic_feature(CPUX86State *env)
1311{
1312 env->cpuid_features &= ~CPUID_APIC;
1313}
1314
c6dc6f63
AP		 1315#endif /* !CONFIG_USER_ONLY */
1316
1317/* register "cpudef" models defined in configuration file. Here we first
1318 * preload any built-in definitions
1319 */
1320void x86_cpudef_setup(void)
1321{
93bfef4c
CV		 1322 int i, j;
1323 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
c6dc6f63
AP		 1324
1325 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
1326 builtin_x86_defs[i].next = x86_defs;
1327 builtin_x86_defs[i].flags = 1;
93bfef4c
CV		 1328
1329 /* Look for specific "cpudef" models that */
09faecf2 1330 /* have the QEMU version in .model_id */
93bfef4c
CV		 1331 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
1332 if (strcmp(model_with_versions[j], builtin_x86_defs[i].name) == 0) {
1333 pstrcpy(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), "QEMU Virtual CPU version ");
1334 pstrcat(builtin_x86_defs[i].model_id, sizeof(builtin_x86_defs[i].model_id), qemu_get_version());
1335 break;
1336 }
1337 }
1338
c6dc6f63
AP		 1339 x86_defs = &builtin_x86_defs[i];
1340 }
1341#if !defined(CONFIG_USER_ONLY)
3329f07b 1342 qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register, NULL, 0);
c6dc6f63
AP		 1343#endif
1344}
1345
c6dc6f63
AP		 1346static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
1347 uint32_t *ecx, uint32_t *edx)
1348{
1349 *ebx = env->cpuid_vendor1;
1350 *edx = env->cpuid_vendor2;
1351 *ecx = env->cpuid_vendor3;
1352
1353 /* sysenter isn't supported on compatibility mode on AMD, syscall
1354 * isn't supported in compatibility mode on Intel.
1355 * Normally we advertise the actual cpu vendor, but you can override
1356 * this if you want to use KVM's sysenter/syscall emulation
1357 * in compatibility mode and when doing cross vendor migration
1358 */
89354998 1359 if (kvm_enabled() && ! env->cpuid_vendor_override) {
c6dc6f63
AP		 1360 host_cpuid(0, 0, NULL, ebx, ecx, edx);
1361 }
1362}
1363
1364void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1365 uint32_t *eax, uint32_t *ebx,
1366 uint32_t *ecx, uint32_t *edx)
1367{
1368 /* test if maximum index reached */
1369 if (index & 0x80000000) {
b3baa152 1370 if (index > env->cpuid_xlevel) {
1371 if (env->cpuid_xlevel2 > 0) {
1372 /* Handle the Centaur's CPUID instruction. */
1373 if (index > env->cpuid_xlevel2) {
1374 index = env->cpuid_xlevel2;
1375 } else if (index < 0xC0000000) {
1376 index = env->cpuid_xlevel;
1377 }
1378 } else {
1379 index = env->cpuid_xlevel;
1380 }
1381 }
c6dc6f63
AP		 1382 } else {
1383 if (index > env->cpuid_level)
1384 index = env->cpuid_level;
1385 }
1386
1387 switch(index) {
1388 case 0:
1389 *eax = env->cpuid_level;
1390 get_cpuid_vendor(env, ebx, ecx, edx);
1391 break;
1392 case 1:
1393 *eax = env->cpuid_version;
1394 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1395 *ecx = env->cpuid_ext_features;
1396 *edx = env->cpuid_features;
1397 if (env->nr_cores * env->nr_threads > 1) {
1398 *ebx |= (env->nr_cores * env->nr_threads) << 16;
1399 *edx |= 1 << 28; /* HTT bit */
1400 }
1401 break;
1402 case 2:
1403 /* cache info: needed for Pentium Pro compatibility */
1404 *eax = 1;
1405 *ebx = 0;
1406 *ecx = 0;
1407 *edx = 0x2c307d;
1408 break;
1409 case 4:
1410 /* cache info: needed for Core compatibility */
1411 if (env->nr_cores > 1) {
2f7a21c4 1412 *eax = (env->nr_cores - 1) << 26;
c6dc6f63 1413 } else {
2f7a21c4 1414 *eax = 0;
c6dc6f63
AP		 1415 }
1416 switch (count) {
1417 case 0: /* L1 dcache info */
1418 *eax |= 0x0000121;
1419 *ebx = 0x1c0003f;
1420 *ecx = 0x000003f;
1421 *edx = 0x0000001;
1422 break;
1423 case 1: /* L1 icache info */
1424 *eax |= 0x0000122;
1425 *ebx = 0x1c0003f;
1426 *ecx = 0x000003f;
1427 *edx = 0x0000001;
1428 break;
1429 case 2: /* L2 cache info */
1430 *eax |= 0x0000143;
1431 if (env->nr_threads > 1) {
1432 *eax |= (env->nr_threads - 1) << 14;
1433 }
1434 *ebx = 0x3c0003f;
1435 *ecx = 0x0000fff;
1436 *edx = 0x0000001;
1437 break;
1438 default: /* end of info */
1439 *eax = 0;
1440 *ebx = 0;
1441 *ecx = 0;
1442 *edx = 0;
1443 break;
1444 }
1445 break;
1446 case 5:
1447 /* mwait info: needed for Core compatibility */
1448 *eax = 0; /* Smallest monitor-line size in bytes */
1449 *ebx = 0; /* Largest monitor-line size in bytes */
1450 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
1451 *edx = 0;
1452 break;
1453 case 6:
1454 /* Thermal and Power Leaf */
1455 *eax = 0;
1456 *ebx = 0;
1457 *ecx = 0;
1458 *edx = 0;
1459 break;
f7911686 1460 case 7:
13526728
EH		 1461 /* Structured Extended Feature Flags Enumeration Leaf */
1462 if (count == 0) {
1463 *eax = 0; /* Maximum ECX value for sub-leaves */
1464 *ebx = env->cpuid_7_0_ebx; /* Feature flags */
1465 *ecx = 0; /* Reserved */
1466 *edx = 0; /* Reserved */
f7911686
YW		 1467 } else {
1468 *eax = 0;
1469 *ebx = 0;
1470 *ecx = 0;
1471 *edx = 0;
1472 }
1473 break;
c6dc6f63
AP		 1474 case 9:
1475 /* Direct Cache Access Information Leaf */
1476 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
1477 *ebx = 0;
1478 *ecx = 0;
1479 *edx = 0;
1480 break;
1481 case 0xA:
1482 /* Architectural Performance Monitoring Leaf */
a0fa8208
GN		 1483 if (kvm_enabled()) {
1484 KVMState *s = env->kvm_state;
1485
1486 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
1487 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
1488 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
1489 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
1490 } else {
1491 *eax = 0;
1492 *ebx = 0;
1493 *ecx = 0;
1494 *edx = 0;
1495 }
c6dc6f63 1496 break;
51e49430
SY		 1497 case 0xD:
1498 /* Processor Extended State */
1499 if (!(env->cpuid_ext_features & CPUID_EXT_XSAVE)) {
1500 *eax = 0;
1501 *ebx = 0;
1502 *ecx = 0;
1503 *edx = 0;
1504 break;
1505 }
1506 if (kvm_enabled()) {
ba9bc59e
JK		 1507 KVMState *s = env->kvm_state;
1508
1509 *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX);
1510 *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX);
1511 *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX);
1512 *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX);
51e49430
SY		 1513 } else {
1514 *eax = 0;
1515 *ebx = 0;
1516 *ecx = 0;
1517 *edx = 0;
1518 }
1519 break;
c6dc6f63
AP		 1520 case 0x80000000:
1521 *eax = env->cpuid_xlevel;
1522 *ebx = env->cpuid_vendor1;
1523 *edx = env->cpuid_vendor2;
1524 *ecx = env->cpuid_vendor3;
1525 break;
1526 case 0x80000001:
1527 *eax = env->cpuid_version;
1528 *ebx = 0;
1529 *ecx = env->cpuid_ext3_features;
1530 *edx = env->cpuid_ext2_features;
1531
1532 /* The Linux kernel checks for the CMPLegacy bit and
1533 * discards multiple thread information if it is set.
1534 * So dont set it here for Intel to make Linux guests happy.
1535 */
1536 if (env->nr_cores * env->nr_threads > 1) {
1537 uint32_t tebx, tecx, tedx;
1538 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
1539 if (tebx != CPUID_VENDOR_INTEL_1 ||
1540 tedx != CPUID_VENDOR_INTEL_2 ||
1541 tecx != CPUID_VENDOR_INTEL_3) {
1542 *ecx |= 1 << 1; /* CmpLegacy bit */
1543 }
1544 }
c6dc6f63
AP		 1545 break;
1546 case 0x80000002:
1547 case 0x80000003:
1548 case 0x80000004:
1549 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
1550 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
1551 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
1552 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
1553 break;
1554 case 0x80000005:
1555 /* cache info (L1 cache) */
1556 *eax = 0x01ff01ff;
1557 *ebx = 0x01ff01ff;
1558 *ecx = 0x40020140;
1559 *edx = 0x40020140;
1560 break;
1561 case 0x80000006:
1562 /* cache info (L2 cache) */
1563 *eax = 0;
1564 *ebx = 0x42004200;
1565 *ecx = 0x02008140;
1566 *edx = 0;
1567 break;
1568 case 0x80000008:
1569 /* virtual & phys address size in low 2 bytes. */
1570/* XXX: This value must match the one used in the MMU code. */
1571 if (env->cpuid_ext2_features & CPUID_EXT2_LM) {
1572 /* 64 bit processor */
1573/* XXX: The physical address space is limited to 42 bits in exec.c. */
1574 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
1575 } else {
1576 if (env->cpuid_features & CPUID_PSE36)
1577 *eax = 0x00000024; /* 36 bits physical */
1578 else
1579 *eax = 0x00000020; /* 32 bits physical */
1580 }
1581 *ebx = 0;
1582 *ecx = 0;
1583 *edx = 0;
1584 if (env->nr_cores * env->nr_threads > 1) {
1585 *ecx |= (env->nr_cores * env->nr_threads) - 1;
1586 }
1587 break;
1588 case 0x8000000A:
296acb64
JR		 1589 if (env->cpuid_ext3_features & CPUID_EXT3_SVM) {
1590 *eax = 0x00000001; /* SVM Revision */
1591 *ebx = 0x00000010; /* nr of ASIDs */
1592 *ecx = 0;
1593 *edx = env->cpuid_svm_features; /* optional features */
1594 } else {
1595 *eax = 0;
1596 *ebx = 0;
1597 *ecx = 0;
1598 *edx = 0;
1599 }
c6dc6f63 1600 break;
b3baa152 1601 case 0xC0000000:
1602 *eax = env->cpuid_xlevel2;
1603 *ebx = 0;
1604 *ecx = 0;
1605 *edx = 0;
1606 break;
1607 case 0xC0000001:
1608 /* Support for VIA CPU's CPUID instruction */
1609 *eax = env->cpuid_version;
1610 *ebx = 0;
1611 *ecx = 0;
1612 *edx = env->cpuid_ext4_features;
1613 break;
1614 case 0xC0000002:
1615 case 0xC0000003:
1616 case 0xC0000004:
1617 /* Reserved for the future, and now filled with zero */
1618 *eax = 0;
1619 *ebx = 0;
1620 *ecx = 0;
1621 *edx = 0;
1622 break;
c6dc6f63
AP		 1623 default:
1624 /* reserved values: zero */
1625 *eax = 0;
1626 *ebx = 0;
1627 *ecx = 0;
1628 *edx = 0;
1629 break;
1630 }
1631}
5fd2087a
AF		 1632
1633/* CPUClass::reset() */
1634static void x86_cpu_reset(CPUState *s)
1635{
1636 X86CPU *cpu = X86_CPU(s);
1637 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
1638 CPUX86State *env = &cpu->env;
c1958aea
AF		 1639 int i;
1640
1641 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
1642 qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
1643 log_cpu_state(env, X86_DUMP_FPU | X86_DUMP_CCOP);
1644 }
5fd2087a
AF		 1645
1646 xcc->parent_reset(s);
1647
c1958aea
AF		 1648
1649 memset(env, 0, offsetof(CPUX86State, breakpoints));
1650
1651 tlb_flush(env, 1);
1652
1653 env->old_exception = -1;
1654
1655 /* init to reset state */
1656
1657#ifdef CONFIG_SOFTMMU
1658 env->hflags |= HF_SOFTMMU_MASK;
1659#endif
1660 env->hflags2 |= HF2_GIF_MASK;
1661
1662 cpu_x86_update_cr0(env, 0x60000010);
1663 env->a20_mask = ~0x0;
1664 env->smbase = 0x30000;
1665
1666 env->idt.limit = 0xffff;
1667 env->gdt.limit = 0xffff;
1668 env->ldt.limit = 0xffff;
1669 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
1670 env->tr.limit = 0xffff;
1671 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
1672
1673 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
1674 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
1675 DESC_R_MASK | DESC_A_MASK);
1676 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
1677 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1678 DESC_A_MASK);
1679 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
1680 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1681 DESC_A_MASK);
1682 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
1683 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1684 DESC_A_MASK);
1685 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
1686 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1687 DESC_A_MASK);
1688 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
1689 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
1690 DESC_A_MASK);
1691
1692 env->eip = 0xfff0;
1693 env->regs[R_EDX] = env->cpuid_version;
1694
1695 env->eflags = 0x2;
1696
1697 /* FPU init */
1698 for (i = 0; i < 8; i++) {
1699 env->fptags[i] = 1;
1700 }
1701 env->fpuc = 0x37f;
1702
1703 env->mxcsr = 0x1f80;
1704
1705 env->pat = 0x0007040600070406ULL;
1706 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
1707
1708 memset(env->dr, 0, sizeof(env->dr));
1709 env->dr[6] = DR6_FIXED_1;
1710 env->dr[7] = DR7_FIXED_1;
1711 cpu_breakpoint_remove_all(env, BP_CPU);
1712 cpu_watchpoint_remove_all(env, BP_CPU);
dd673288
IM		 1713
1714#if !defined(CONFIG_USER_ONLY)
1715 /* We hard-wire the BSP to the first CPU. */
1716 if (env->cpu_index == 0) {
1717 apic_designate_bsp(env->apic_state);
1718 }
1719
1720 env->halted = !cpu_is_bsp(cpu);
1721#endif
5fd2087a
AF		 1722}
1723
dd673288
IM		 1724#ifndef CONFIG_USER_ONLY
1725bool cpu_is_bsp(X86CPU *cpu)
1726{
1727 return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP;
1728}
65dee380
IM		 1729
1730/* TODO: remove me, when reset over QOM tree is implemented */
1731static void x86_cpu_machine_reset_cb(void *opaque)
1732{
1733 X86CPU *cpu = opaque;
1734 cpu_reset(CPU(cpu));
1735}
dd673288
IM		 1736#endif
1737
de024815
AF		 1738static void mce_init(X86CPU *cpu)
1739{
1740 CPUX86State *cenv = &cpu->env;
1741 unsigned int bank;
1742
1743 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
1744 && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
1745 (CPUID_MCE | CPUID_MCA)) {
1746 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
1747 cenv->mcg_ctl = ~(uint64_t)0;
1748 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
1749 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
1750 }
1751 }
1752}
1753
7a059953
AF		 1754void x86_cpu_realize(Object *obj, Error **errp)
1755{
1756 X86CPU *cpu = X86_CPU(obj);
1757
65dee380
IM		 1758#ifndef CONFIG_USER_ONLY
1759 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
1760#endif
1761
7a059953
AF		 1762 mce_init(cpu);
1763 qemu_init_vcpu(&cpu->env);
65dee380 1764 cpu_reset(CPU(cpu));
7a059953
AF		 1765}
1766
de024815
AF		 1767static void x86_cpu_initfn(Object *obj)
1768{
1769 X86CPU *cpu = X86_CPU(obj);
1770 CPUX86State *env = &cpu->env;
d65e9815 1771 static int inited;
de024815
AF		 1772
1773 cpu_exec_init(env);
71ad61d3
AF		 1774
1775 object_property_add(obj, "family", "int",
95b8519d 1776 x86_cpuid_version_get_family,
71ad61d3 1777 x86_cpuid_version_set_family, NULL, NULL, NULL);
c5291a4f 1778 object_property_add(obj, "model", "int",
67e30c83 1779 x86_cpuid_version_get_model,
c5291a4f 1780 x86_cpuid_version_set_model, NULL, NULL, NULL);
036e2222 1781 object_property_add(obj, "stepping", "int",
35112e41 1782 x86_cpuid_version_get_stepping,
036e2222 1783 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
8e1898bf
AF		 1784 object_property_add(obj, "level", "int",
1785 x86_cpuid_get_level,
1786 x86_cpuid_set_level, NULL, NULL, NULL);
16b93aa8
AF		 1787 object_property_add(obj, "xlevel", "int",
1788 x86_cpuid_get_xlevel,
1789 x86_cpuid_set_xlevel, NULL, NULL, NULL);
d480e1af
AF		 1790 object_property_add_str(obj, "vendor",
1791 x86_cpuid_get_vendor,
1792 x86_cpuid_set_vendor, NULL);
938d4c25 1793 object_property_add_str(obj, "model-id",
63e886eb 1794 x86_cpuid_get_model_id,
938d4c25 1795 x86_cpuid_set_model_id, NULL);
89e48965
AF		 1796 object_property_add(obj, "tsc-frequency", "int",
1797 x86_cpuid_get_tsc_freq,
1798 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
71ad61d3 1799
de024815 1800 env->cpuid_apic_id = env->cpu_index;
d65e9815
IM		 1801
1802 /* init various static tables used in TCG mode */
1803 if (tcg_enabled() && !inited) {
1804 inited = 1;
1805 optimize_flags_init();
1806#ifndef CONFIG_USER_ONLY
1807 cpu_set_debug_excp_handler(breakpoint_handler);
1808#endif
1809 }
de024815
AF		 1810}
1811
5fd2087a
AF		 1812static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
1813{
1814 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1815 CPUClass *cc = CPU_CLASS(oc);
1816
1817 xcc->parent_reset = cc->reset;
1818 cc->reset = x86_cpu_reset;
1819}
1820
1821static const TypeInfo x86_cpu_type_info = {
1822 .name = TYPE_X86_CPU,
1823 .parent = TYPE_CPU,
1824 .instance_size = sizeof(X86CPU),
de024815 1825 .instance_init = x86_cpu_initfn,
5fd2087a
AF		 1826 .abstract = false,
1827 .class_size = sizeof(X86CPUClass),
1828 .class_init = x86_cpu_common_class_init,
1829};
1830
1831static void x86_cpu_register_types(void)
1832{
1833 type_register_static(&x86_cpu_type_info);
1834}
1835
1836type_init(x86_cpu_register_types)
Qemu copy for testing