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b77f98ca AF |
1 | /* |
2 | * QEMU MicroBlaze CPU | |
3 | * | |
61b6208f AF |
4 | * Copyright (c) 2009 Edgar E. Iglesias |
5 | * Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd. | |
b77f98ca AF |
6 | * Copyright (c) 2012 SUSE LINUX Products GmbH |
7 | * | |
8 | * This library is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU Lesser General Public | |
10 | * License as published by the Free Software Foundation; either | |
11 | * version 2.1 of the License, or (at your option) any later version. | |
12 | * | |
13 | * This library is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * Lesser General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU Lesser General Public | |
19 | * License along with this library; if not, see | |
20 | * <http://www.gnu.org/licenses/lgpl-2.1.html> | |
21 | */ | |
22 | ||
23 | #include "cpu.h" | |
24 | #include "qemu-common.h" | |
a1bff71c | 25 | #include "hw/qdev-properties.h" |
3ce8b2bc | 26 | #include "migration/vmstate.h" |
b77f98ca AF |
27 | |
28 | ||
f45748f1 AF |
29 | static void mb_cpu_set_pc(CPUState *cs, vaddr value) |
30 | { | |
31 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); | |
32 | ||
33 | cpu->env.sregs[SR_PC] = value; | |
34 | } | |
35 | ||
b77f98ca AF |
36 | /* CPUClass::reset() */ |
37 | static void mb_cpu_reset(CPUState *s) | |
38 | { | |
39 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); | |
40 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); | |
41 | CPUMBState *env = &cpu->env; | |
42 | ||
43 | mcc->parent_reset(s); | |
44 | ||
61b6208f | 45 | memset(env, 0, offsetof(CPUMBState, breakpoints)); |
8cc9b43f | 46 | env->res_addr = RES_ADDR_NONE; |
61b6208f AF |
47 | tlb_flush(env, 1); |
48 | ||
49 | /* Disable stack protector. */ | |
50 | env->shr = ~0; | |
51 | ||
52 | env->pvr.regs[0] = PVR0_PVR_FULL_MASK \ | |
53 | | PVR0_USE_BARREL_MASK \ | |
54 | | PVR0_USE_DIV_MASK \ | |
55 | | PVR0_USE_HW_MUL_MASK \ | |
56 | | PVR0_USE_EXC_MASK \ | |
57 | | PVR0_USE_ICACHE_MASK \ | |
58 | | PVR0_USE_DCACHE_MASK \ | |
59 | | PVR0_USE_MMU \ | |
60 | | (0xb << 8); | |
61 | env->pvr.regs[2] = PVR2_D_OPB_MASK \ | |
62 | | PVR2_D_LMB_MASK \ | |
63 | | PVR2_I_OPB_MASK \ | |
64 | | PVR2_I_LMB_MASK \ | |
65 | | PVR2_USE_MSR_INSTR \ | |
66 | | PVR2_USE_PCMP_INSTR \ | |
67 | | PVR2_USE_BARREL_MASK \ | |
68 | | PVR2_USE_DIV_MASK \ | |
69 | | PVR2_USE_HW_MUL_MASK \ | |
70 | | PVR2_USE_MUL64_MASK \ | |
71 | | PVR2_USE_FPU_MASK \ | |
72 | | PVR2_USE_FPU2_MASK \ | |
73 | | PVR2_FPU_EXC_MASK \ | |
74 | | 0; | |
75 | env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */ | |
76 | env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17); | |
77 | ||
78 | #if defined(CONFIG_USER_ONLY) | |
79 | /* start in user mode with interrupts enabled. */ | |
80 | env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM; | |
81 | env->pvr.regs[10] = 0x0c000000; /* Spartan 3a dsp. */ | |
82 | #else | |
83 | env->sregs[SR_MSR] = 0; | |
84 | mmu_init(&env->mmu); | |
85 | env->mmu.c_mmu = 3; | |
86 | env->mmu.c_mmu_tlb_access = 3; | |
87 | env->mmu.c_mmu_zones = 16; | |
88 | #endif | |
b77f98ca AF |
89 | } |
90 | ||
746b03b2 AF |
91 | static void mb_cpu_realizefn(DeviceState *dev, Error **errp) |
92 | { | |
14a10fc3 | 93 | CPUState *cs = CPU(dev); |
746b03b2 AF |
94 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev); |
95 | ||
14a10fc3 AF |
96 | cpu_reset(cs); |
97 | qemu_init_vcpu(cs); | |
746b03b2 AF |
98 | |
99 | mcc->parent_realize(dev, errp); | |
100 | } | |
101 | ||
d0e71ef5 AF |
102 | static void mb_cpu_initfn(Object *obj) |
103 | { | |
c05efcb1 | 104 | CPUState *cs = CPU(obj); |
d0e71ef5 AF |
105 | MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj); |
106 | CPUMBState *env = &cpu->env; | |
cd0c24f9 | 107 | static bool tcg_initialized; |
d0e71ef5 | 108 | |
c05efcb1 | 109 | cs->env_ptr = env; |
d0e71ef5 AF |
110 | cpu_exec_init(env); |
111 | ||
112 | set_float_rounding_mode(float_round_nearest_even, &env->fp_status); | |
cd0c24f9 AF |
113 | |
114 | if (tcg_enabled() && !tcg_initialized) { | |
115 | tcg_initialized = true; | |
116 | mb_tcg_init(); | |
117 | } | |
d0e71ef5 AF |
118 | } |
119 | ||
3ce8b2bc AF |
120 | static const VMStateDescription vmstate_mb_cpu = { |
121 | .name = "cpu", | |
122 | .unmigratable = 1, | |
123 | }; | |
124 | ||
a1bff71c EI |
125 | static Property mb_properties[] = { |
126 | DEFINE_PROP_UINT32("xlnx.base-vectors", MicroBlazeCPU, base_vectors, 0), | |
127 | DEFINE_PROP_END_OF_LIST(), | |
128 | }; | |
129 | ||
b77f98ca AF |
130 | static void mb_cpu_class_init(ObjectClass *oc, void *data) |
131 | { | |
3ce8b2bc | 132 | DeviceClass *dc = DEVICE_CLASS(oc); |
b77f98ca AF |
133 | CPUClass *cc = CPU_CLASS(oc); |
134 | MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); | |
135 | ||
746b03b2 AF |
136 | mcc->parent_realize = dc->realize; |
137 | dc->realize = mb_cpu_realizefn; | |
138 | ||
b77f98ca AF |
139 | mcc->parent_reset = cc->reset; |
140 | cc->reset = mb_cpu_reset; | |
3ce8b2bc | 141 | |
97a8ea5a | 142 | cc->do_interrupt = mb_cpu_do_interrupt; |
878096ee | 143 | cc->dump_state = mb_cpu_dump_state; |
f45748f1 | 144 | cc->set_pc = mb_cpu_set_pc; |
5b50e790 AF |
145 | cc->gdb_read_register = mb_cpu_gdb_read_register; |
146 | cc->gdb_write_register = mb_cpu_gdb_write_register; | |
00b941e5 AF |
147 | #ifndef CONFIG_USER_ONLY |
148 | cc->do_unassigned_access = mb_cpu_unassigned_access; | |
149 | cc->get_phys_page_debug = mb_cpu_get_phys_page_debug; | |
150 | #endif | |
3ce8b2bc | 151 | dc->vmsd = &vmstate_mb_cpu; |
a1bff71c | 152 | dc->props = mb_properties; |
a0e372f0 | 153 | cc->gdb_num_core_regs = 32 + 5; |
b77f98ca AF |
154 | } |
155 | ||
156 | static const TypeInfo mb_cpu_type_info = { | |
157 | .name = TYPE_MICROBLAZE_CPU, | |
158 | .parent = TYPE_CPU, | |
159 | .instance_size = sizeof(MicroBlazeCPU), | |
d0e71ef5 | 160 | .instance_init = mb_cpu_initfn, |
b77f98ca AF |
161 | .class_size = sizeof(MicroBlazeCPUClass), |
162 | .class_init = mb_cpu_class_init, | |
163 | }; | |
164 | ||
165 | static void mb_cpu_register_types(void) | |
166 | { | |
167 | type_register_static(&mb_cpu_type_info); | |
168 | } | |
169 | ||
170 | type_init(mb_cpu_register_types) |