[qemu.git] / target-microblaze / op_helper.c

/*
 *  Microblaze helper routines.
 *
 *  Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
 *  Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include <assert.h>
#include "cpu.h"
#include "helper.h"
#include "qemu/host-utils.h"

#define D(x)

#if !defined(CONFIG_USER_ONLY)
#include "exec/softmmu_exec.h"

#define MMUSUFFIX _mmu
#define SHIFT 0
#include "exec/softmmu_template.h"
#define SHIFT 1
#include "exec/softmmu_template.h"
#define SHIFT 2
#include "exec/softmmu_template.h"
#define SHIFT 3
#include "exec/softmmu_template.h"

/* Try to fill the TLB and return an exception if error. If retaddr is
   NULL, it means that the function was called in C code (i.e. not
   from generated code or from helper.c) */
void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx,
              uintptr_t retaddr)
{
    int ret;

    ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
    if (unlikely(ret)) {
        if (retaddr) {
            /* now we have a real cpu fault */
            cpu_restore_state(env, retaddr);
        }
        cpu_loop_exit(env);
    }
}
#endif

void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
             id, data,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
}

uint32_t helper_get(uint32_t id, uint32_t ctrl)
{
    int test = ctrl & STREAM_TEST;
    int atomic = ctrl & STREAM_ATOMIC;
    int control = ctrl & STREAM_CONTROL;
    int nonblock = ctrl & STREAM_NONBLOCK;
    int exception = ctrl & STREAM_EXCEPTION;

    qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
             id,
             test ? "t" : "",
             nonblock ? "n" : "",
             exception ? "e" : "",
             control ? "c" : "",
             atomic ? "a" : "");
    return 0xdead0000 | id;
}

void helper_raise_exception(CPUMBState *env, uint32_t index)
{
    env->exception_index = index;
    cpu_loop_exit(env);
}

void helper_debug(CPUMBState *env)
{
    int i;

    qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
    qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
             env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
             env->debug, env->imm, env->iflags);
    qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
             env->btaken, env->btarget,
             (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
             (env->sregs[SR_MSR] & MSR_EIP),
             (env->sregs[SR_MSR] & MSR_IE));
    for (i = 0; i < 32; i++) {
        qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
        if ((i + 1) % 4 == 0)
            qemu_log("\n");
    }
    qemu_log("\n\n");
}

static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
{
    uint32_t cout = 0;

    if ((b == ~0) && cin)
        cout = 1;
    else if ((~0 - a) < (b + cin))
        cout = 1;
    return cout;
}

uint32_t helper_cmp(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (b & 0x80000000);
    return t;
}

uint32_t helper_cmpu(uint32_t a, uint32_t b)
{
    uint32_t t;

    t = b + ~a + 1;
    if ((b & 0x80000000) ^ (a & 0x80000000))
        t = (t & 0x7fffffff) | (a & 0x80000000);
    return t;
}

uint32_t helper_clz(uint32_t t0)
{
    return clz32(t0);
}

uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
{
    uint32_t ncf;
    ncf = compute_carry(a, b, cf);
    return ncf;
}

static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (b == 0) {
        env->sregs[SR_MSR] |= MSR_DZ;

        if ((env->sregs[SR_MSR] & MSR_EE)
            && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DIVZERO;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
        return 0;
    }
    env->sregs[SR_MSR] &= ~MSR_DZ;
    return 1;
}

uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (!div_prepare(env, a, b)) {
        return 0;
    }
    return (int32_t)a / (int32_t)b;
}

uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
{
    if (!div_prepare(env, a, b)) {
        return 0;
    }
    return a / b;
}

/* raise FPU exception.  */
static void raise_fpu_exception(CPUMBState *env)
{
    env->sregs[SR_ESR] = ESR_EC_FPU;
    helper_raise_exception(env, EXCP_HW_EXCP);
}

static void update_fpu_flags(CPUMBState *env, int flags)
{
    int raise = 0;

    if (flags & float_flag_invalid) {
        env->sregs[SR_FSR] |= FSR_IO;
        raise = 1;
    }
    if (flags & float_flag_divbyzero) {
        env->sregs[SR_FSR] |= FSR_DZ;
        raise = 1;
    }
    if (flags & float_flag_overflow) {
        env->sregs[SR_FSR] |= FSR_OF;
        raise = 1;
    }
    if (flags & float_flag_underflow) {
        env->sregs[SR_FSR] |= FSR_UF;
        raise = 1;
    }
    if (raise
        && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
        && (env->sregs[SR_MSR] & MSR_EE)) {
        raise_fpu_exception(env);
    }
}

uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_add(fa.f, fb.f, &env->fp_status);

    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);
    return fd.l;
}

uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);
    return fd.l;
}

uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fd, fa, fb;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    fd.f = float32_div(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    uint32_t r = 0;

    fa.l = a;
    fb.l = b;

    if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
        update_fpu_flags(env, float_flag_invalid);
        r = 1;
    }

    if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
        r = 1;
    }

    return r;
}

uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_lt(fb.f, fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fb.l = b;
    r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags;
    int r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_le(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);


    return r;
}

uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);
    return r;
}

uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
{
    CPU_FloatU fa, fb;
    int flags, r;

    fa.l = a;
    fb.l = b;
    set_float_exception_flags(0, &env->fp_status);
    r = !float32_lt(fa.f, fb.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags & float_flag_invalid);

    return r;
}

uint32_t helper_flt(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fd, fa;

    fa.l = a;
    fd.f = int32_to_float32(fa.l, &env->fp_status);
    return fd.l;
}

uint32_t helper_fint(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fa;
    uint32_t r;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    r = float32_to_int32(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return r;
}

uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
{
    CPU_FloatU fd, fa;
    int flags;

    set_float_exception_flags(0, &env->fp_status);
    fa.l = a;
    fd.l = float32_sqrt(fa.f, &env->fp_status);
    flags = get_float_exception_flags(&env->fp_status);
    update_fpu_flags(env, flags);

    return fd.l;
}

uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
{
    unsigned int i;
    uint32_t mask = 0xff000000;

    for (i = 0; i < 4; i++) {
        if ((a & mask) == (b & mask))
            return i + 1;
        mask >>= 8;
    }
    return 0;
}

void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
                     uint32_t mask)
{
    if (addr & mask) {
            qemu_log_mask(CPU_LOG_INT,
                          "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
                          addr, mask, wr, dr);
            env->sregs[SR_EAR] = addr;
            env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
                                 | (dr & 31) << 5;
            if (mask == 3) {
                env->sregs[SR_ESR] |= 1 << 11;
            }
            if (!(env->sregs[SR_MSR] & MSR_EE)) {
                return;
            }
            helper_raise_exception(env, EXCP_HW_EXCP);
    }
}

void helper_stackprot(CPUMBState *env, uint32_t addr)
{
    if (addr < env->slr || addr > env->shr) {
            qemu_log("Stack protector violation at %x %x %x\n",
                     addr, env->slr, env->shr);
            env->sregs[SR_EAR] = addr;
            env->sregs[SR_ESR] = ESR_EC_STACKPROT;
            helper_raise_exception(env, EXCP_HW_EXCP);
    }
}

#if !defined(CONFIG_USER_ONLY)
/* Writes/reads to the MMU's special regs end up here.  */
uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
{
    return mmu_read(env, rn);
}

void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
{
    mmu_write(env, rn, v);
}

void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
                              bool is_write, bool is_exec, int is_asi,
                              unsigned size)
{
    MicroBlazeCPU *cpu;
    CPUMBState *env;

    qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
             addr, is_write ? 1 : 0, is_exec ? 1 : 0);
    if (cs == NULL) {
        return;
    }
    cpu = MICROBLAZE_CPU(cs);
    env = &cpu->env;
    if (!(env->sregs[SR_MSR] & MSR_EE)) {
        return;
    }

    env->sregs[SR_EAR] = addr;
    if (is_exec) {
        if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
    } else {
        if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
            env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
            helper_raise_exception(env, EXCP_HW_EXCP);
        }
    }
}
#endif
Commit	Line	Data
4acb54ba EI	1	/*
	2	* Microblaze helper routines.
	3	*
	4	* Copyright (c) 2009 Edgar E. Iglesias <edgar.iglesias@gmail.com>.
dadc1064	5	* Copyright (c) 2009-2012 PetaLogix Qld Pty Ltd.
4acb54ba EI	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
8167ee88	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
4acb54ba EI	19	*/
	20
	21	#include <assert.h>
3e457172	22	#include "cpu.h"
4acb54ba	23	#include "helper.h"
1de7afc9	24	#include "qemu/host-utils.h"
4acb54ba EI	25
	26	#define D(x)
	27
	28	#if !defined(CONFIG_USER_ONLY)
022c62cb	29	#include "exec/softmmu_exec.h"
3e457172	30
4acb54ba EI	31	#define MMUSUFFIX _mmu
4acb54ba EI	32	#define SHIFT 0
022c62cb	33	#include "exec/softmmu_template.h"
4acb54ba	34	#define SHIFT 1
022c62cb	35	#include "exec/softmmu_template.h"
4acb54ba	36	#define SHIFT 2
022c62cb	37	#include "exec/softmmu_template.h"
4acb54ba	38	#define SHIFT 3
022c62cb	39	#include "exec/softmmu_template.h"
4acb54ba EI	40
	41	/* Try to fill the TLB and return an exception if error. If retaddr is
	42	NULL, it means that the function was called in C code (i.e. not
	43	from generated code or from helper.c) */
64254eba	44	void tlb_fill(CPUMBState *env, target_ulong addr, int is_write, int mmu_idx,
20503968	45	uintptr_t retaddr)
4acb54ba	46	{
4acb54ba EI	47	int ret;
4acb54ba EI	48
97b348e7	49	ret = cpu_mb_handle_mmu_fault(env, addr, is_write, mmu_idx);
4acb54ba EI	50	if (unlikely(ret)) {
	51	if (retaddr) {
	52	/* now we have a real cpu fault */
a8a826a3	53	cpu_restore_state(env, retaddr);
4acb54ba	54	}
1162c041	55	cpu_loop_exit(env);
4acb54ba	56	}
4acb54ba EI	57	}
	58	#endif
	59
6d76d23e EI	60	void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
	61	{
	62	int test = ctrl & STREAM_TEST;
	63	int atomic = ctrl & STREAM_ATOMIC;
	64	int control = ctrl & STREAM_CONTROL;
	65	int nonblock = ctrl & STREAM_NONBLOCK;
	66	int exception = ctrl & STREAM_EXCEPTION;
	67
	68	qemu_log("Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
	69	id, data,
	70	test ? "t" : "",
	71	nonblock ? "n" : "",
	72	exception ? "e" : "",
	73	control ? "c" : "",
	74	atomic ? "a" : "");
	75	}
	76
	77	uint32_t helper_get(uint32_t id, uint32_t ctrl)
	78	{
	79	int test = ctrl & STREAM_TEST;
	80	int atomic = ctrl & STREAM_ATOMIC;
	81	int control = ctrl & STREAM_CONTROL;
	82	int nonblock = ctrl & STREAM_NONBLOCK;
	83	int exception = ctrl & STREAM_EXCEPTION;
	84
	85	qemu_log("Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
	86	id,
	87	test ? "t" : "",
	88	nonblock ? "n" : "",
	89	exception ? "e" : "",
	90	control ? "c" : "",
	91	atomic ? "a" : "");
	92	return 0xdead0000 \| id;
	93	}
	94
64254eba	95	void helper_raise_exception(CPUMBState *env, uint32_t index)
4acb54ba EI	96	{
4acb54ba EI	97	env->exception_index = index;
1162c041	98	cpu_loop_exit(env);
4acb54ba EI	99	}
4acb54ba EI	100
64254eba	101	void helper_debug(CPUMBState *env)
4acb54ba EI	102	{
	103	int i;
	104
	105	qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
4c24aa0a MS	106	qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
4c24aa0a MS	107	env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
17c52a43 EI	108	env->debug, env->imm, env->iflags);
	109	qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
	110	env->btaken, env->btarget,
	111	(env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
	112	(env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
	113	(env->sregs[SR_MSR] & MSR_EIP),
	114	(env->sregs[SR_MSR] & MSR_IE));
4acb54ba EI	115	for (i = 0; i < 32; i++) {
	116	qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
	117	if ((i + 1) % 4 == 0)
	118	qemu_log("\n");
	119	}
	120	qemu_log("\n\n");
	121	}
	122
	123	static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
	124	{
	125	uint32_t cout = 0;
	126
	127	if ((b == ~0) && cin)
	128	cout = 1;
	129	else if ((~0 - a) < (b + cin))
	130	cout = 1;
	131	return cout;
	132	}
	133
	134	uint32_t helper_cmp(uint32_t a, uint32_t b)
	135	{
	136	uint32_t t;
	137
	138	t = b + ~a + 1;
	139	if ((b & 0x80000000) ^ (a & 0x80000000))
	140	t = (t & 0x7fffffff) \| (b & 0x80000000);
	141	return t;
	142	}
	143
	144	uint32_t helper_cmpu(uint32_t a, uint32_t b)
	145	{
	146	uint32_t t;
	147
	148	t = b + ~a + 1;
	149	if ((b & 0x80000000) ^ (a & 0x80000000))
	150	t = (t & 0x7fffffff) \| (a & 0x80000000);
	151	return t;
	152	}
	153
48b5e96f EI	154	uint32_t helper_clz(uint32_t t0)
	155	{
	156	return clz32(t0);
	157	}
	158
5d0bb823	159	uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
4acb54ba	160	{
5d0bb823	161	uint32_t ncf;
40cbf5b7 EI	162	ncf = compute_carry(a, b, cf);
40cbf5b7 EI	163	return ncf;
4acb54ba EI	164	}
4acb54ba EI	165
64254eba	166	static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba EI	167	{
	168	if (b == 0) {
	169	env->sregs[SR_MSR] \|= MSR_DZ;
821ebb33 EI	170
	171	if ((env->sregs[SR_MSR] & MSR_EE)
	172	&& !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
	173	env->sregs[SR_ESR] = ESR_EC_DIVZERO;
64254eba	174	helper_raise_exception(env, EXCP_HW_EXCP);
821ebb33	175	}
4acb54ba EI	176	return 0;
	177	}
	178	env->sregs[SR_MSR] &= ~MSR_DZ;
	179	return 1;
	180	}
	181
64254eba	182	uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba	183	{
64254eba	184	if (!div_prepare(env, a, b)) {
4acb54ba	185	return 0;
64254eba	186	}
4acb54ba EI	187	return (int32_t)a / (int32_t)b;
	188	}
	189
64254eba	190	uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
4acb54ba	191	{
64254eba	192	if (!div_prepare(env, a, b)) {
4acb54ba	193	return 0;
64254eba	194	}
4acb54ba EI	195	return a / b;
	196	}
	197
97694c57	198	/* raise FPU exception. */
64254eba	199	static void raise_fpu_exception(CPUMBState *env)
97694c57 EI	200	{
97694c57 EI	201	env->sregs[SR_ESR] = ESR_EC_FPU;
64254eba	202	helper_raise_exception(env, EXCP_HW_EXCP);
97694c57 EI	203	}
97694c57 EI	204
64254eba	205	static void update_fpu_flags(CPUMBState *env, int flags)
97694c57 EI	206	{
	207	int raise = 0;
	208
	209	if (flags & float_flag_invalid) {
	210	env->sregs[SR_FSR] \|= FSR_IO;
	211	raise = 1;
	212	}
	213	if (flags & float_flag_divbyzero) {
	214	env->sregs[SR_FSR] \|= FSR_DZ;
	215	raise = 1;
	216	}
	217	if (flags & float_flag_overflow) {
	218	env->sregs[SR_FSR] \|= FSR_OF;
	219	raise = 1;
	220	}
	221	if (flags & float_flag_underflow) {
	222	env->sregs[SR_FSR] \|= FSR_UF;
	223	raise = 1;
	224	}
	225	if (raise
	226	&& (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
	227	&& (env->sregs[SR_MSR] & MSR_EE)) {
64254eba	228	raise_fpu_exception(env);
97694c57 EI	229	}
	230	}
	231
64254eba	232	uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	233	{
	234	CPU_FloatU fd, fa, fb;
	235	int flags;
	236
	237	set_float_exception_flags(0, &env->fp_status);
	238	fa.l = a;
	239	fb.l = b;
	240	fd.f = float32_add(fa.f, fb.f, &env->fp_status);
	241
	242	flags = get_float_exception_flags(&env->fp_status);
64254eba	243	update_fpu_flags(env, flags);
97694c57 EI	244	return fd.l;
	245	}
	246
64254eba	247	uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	248	{
	249	CPU_FloatU fd, fa, fb;
	250	int flags;
	251
	252	set_float_exception_flags(0, &env->fp_status);
	253	fa.l = a;
	254	fb.l = b;
	255	fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
	256	flags = get_float_exception_flags(&env->fp_status);
64254eba	257	update_fpu_flags(env, flags);
97694c57 EI	258	return fd.l;
	259	}
	260
64254eba	261	uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	262	{
	263	CPU_FloatU fd, fa, fb;
	264	int flags;
	265
	266	set_float_exception_flags(0, &env->fp_status);
	267	fa.l = a;
	268	fb.l = b;
	269	fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
	270	flags = get_float_exception_flags(&env->fp_status);
64254eba	271	update_fpu_flags(env, flags);
97694c57 EI	272
	273	return fd.l;
	274	}
	275
64254eba	276	uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	277	{
	278	CPU_FloatU fd, fa, fb;
	279	int flags;
	280
	281	set_float_exception_flags(0, &env->fp_status);
	282	fa.l = a;
	283	fb.l = b;
	284	fd.f = float32_div(fb.f, fa.f, &env->fp_status);
	285	flags = get_float_exception_flags(&env->fp_status);
64254eba	286	update_fpu_flags(env, flags);
97694c57 EI	287
	288	return fd.l;
	289	}
	290
64254eba	291	uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
97694c57	292	{
ef9d48da EI	293	CPU_FloatU fa, fb;
	294	uint32_t r = 0;
	295
	296	fa.l = a;
	297	fb.l = b;
	298
	299	if (float32_is_signaling_nan(fa.f) \|\| float32_is_signaling_nan(fb.f)) {
64254eba	300	update_fpu_flags(env, float_flag_invalid);
ef9d48da EI	301	r = 1;
	302	}
	303
18569871	304	if (float32_is_quiet_nan(fa.f) \|\| float32_is_quiet_nan(fb.f)) {
ef9d48da EI	305	r = 1;
	306	}
	307
	308	return r;
97694c57 EI	309	}
97694c57 EI	310
64254eba	311	uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	312	{
	313	CPU_FloatU fa, fb;
	314	int r;
	315	int flags;
	316
	317	set_float_exception_flags(0, &env->fp_status);
	318	fa.l = a;
	319	fb.l = b;
	320	r = float32_lt(fb.f, fa.f, &env->fp_status);
	321	flags = get_float_exception_flags(&env->fp_status);
64254eba	322	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	323
	324	return r;
	325	}
	326
64254eba	327	uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	328	{
	329	CPU_FloatU fa, fb;
	330	int flags;
	331	int r;
	332
	333	set_float_exception_flags(0, &env->fp_status);
	334	fa.l = a;
	335	fb.l = b;
211315fb	336	r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57	337	flags = get_float_exception_flags(&env->fp_status);
64254eba	338	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	339
	340	return r;
	341	}
	342
64254eba	343	uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	344	{
	345	CPU_FloatU fa, fb;
	346	int flags;
	347	int r;
	348
	349	fa.l = a;
	350	fb.l = b;
	351	set_float_exception_flags(0, &env->fp_status);
	352	r = float32_le(fa.f, fb.f, &env->fp_status);
	353	flags = get_float_exception_flags(&env->fp_status);
64254eba	354	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	355
	356
	357	return r;
	358	}
	359
64254eba	360	uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	361	{
	362	CPU_FloatU fa, fb;
	363	int flags, r;
	364
	365	fa.l = a;
	366	fb.l = b;
	367	set_float_exception_flags(0, &env->fp_status);
	368	r = float32_lt(fa.f, fb.f, &env->fp_status);
	369	flags = get_float_exception_flags(&env->fp_status);
64254eba	370	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	371	return r;
	372	}
	373
64254eba	374	uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	375	{
	376	CPU_FloatU fa, fb;
	377	int flags, r;
	378
	379	fa.l = a;
	380	fb.l = b;
	381	set_float_exception_flags(0, &env->fp_status);
211315fb	382	r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
97694c57	383	flags = get_float_exception_flags(&env->fp_status);
64254eba	384	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	385
	386	return r;
	387	}
	388
64254eba	389	uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
97694c57 EI	390	{
	391	CPU_FloatU fa, fb;
	392	int flags, r;
	393
	394	fa.l = a;
	395	fb.l = b;
	396	set_float_exception_flags(0, &env->fp_status);
	397	r = !float32_lt(fa.f, fb.f, &env->fp_status);
	398	flags = get_float_exception_flags(&env->fp_status);
64254eba	399	update_fpu_flags(env, flags & float_flag_invalid);
97694c57 EI	400
	401	return r;
	402	}
	403
64254eba	404	uint32_t helper_flt(CPUMBState *env, uint32_t a)
97694c57 EI	405	{
	406	CPU_FloatU fd, fa;
	407
	408	fa.l = a;
	409	fd.f = int32_to_float32(fa.l, &env->fp_status);
	410	return fd.l;
	411	}
	412
64254eba	413	uint32_t helper_fint(CPUMBState *env, uint32_t a)
97694c57 EI	414	{
	415	CPU_FloatU fa;
	416	uint32_t r;
	417	int flags;
	418
	419	set_float_exception_flags(0, &env->fp_status);
	420	fa.l = a;
	421	r = float32_to_int32(fa.f, &env->fp_status);
	422	flags = get_float_exception_flags(&env->fp_status);
64254eba	423	update_fpu_flags(env, flags);
97694c57 EI	424
	425	return r;
	426	}
	427
64254eba	428	uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
97694c57 EI	429	{
	430	CPU_FloatU fd, fa;
	431	int flags;
	432
	433	set_float_exception_flags(0, &env->fp_status);
	434	fa.l = a;
	435	fd.l = float32_sqrt(fa.f, &env->fp_status);
	436	flags = get_float_exception_flags(&env->fp_status);
64254eba	437	update_fpu_flags(env, flags);
97694c57 EI	438
	439	return fd.l;
	440	}
	441
4acb54ba EI	442	uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
	443	{
	444	unsigned int i;
	445	uint32_t mask = 0xff000000;
	446
	447	for (i = 0; i < 4; i++) {
	448	if ((a & mask) == (b & mask))
	449	return i + 1;
	450	mask >>= 8;
	451	}
	452	return 0;
	453	}
	454
64254eba BS	455	void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
64254eba BS	456	uint32_t mask)
968a40f6	457	{
968a40f6	458	if (addr & mask) {
97f90cbf EI	459	qemu_log_mask(CPU_LOG_INT,
	460	"unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
	461	addr, mask, wr, dr);
	462	env->sregs[SR_EAR] = addr;
968a40f6 EI	463	env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA \| (wr << 10) \
968a40f6 EI	464	\| (dr & 31) << 5;
3aa80988	465	if (mask == 3) {
968a40f6 EI	466	env->sregs[SR_ESR] \|= 1 << 11;
968a40f6 EI	467	}
97f90cbf EI	468	if (!(env->sregs[SR_MSR] & MSR_EE)) {
	469	return;
	470	}
64254eba	471	helper_raise_exception(env, EXCP_HW_EXCP);
968a40f6 EI	472	}
	473	}
	474
64254eba	475	void helper_stackprot(CPUMBState *env, uint32_t addr)
5818dee5 EI	476	{
	477	if (addr < env->slr \|\| addr > env->shr) {
	478	qemu_log("Stack protector violation at %x %x %x\n",
	479	addr, env->slr, env->shr);
	480	env->sregs[SR_EAR] = addr;
	481	env->sregs[SR_ESR] = ESR_EC_STACKPROT;
64254eba	482	helper_raise_exception(env, EXCP_HW_EXCP);
5818dee5 EI	483	}
	484	}
	485
4acb54ba EI	486	#if !defined(CONFIG_USER_ONLY)
4acb54ba EI	487	/* Writes/reads to the MMU's special regs end up here. */
64254eba	488	uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
4acb54ba EI	489	{
	490	return mmu_read(env, rn);
	491	}
	492
64254eba	493	void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
4acb54ba EI	494	{
	495	mmu_write(env, rn, v);
	496	}
faed1c2a	497
c658b94f AF	498	void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
	499	bool is_write, bool is_exec, int is_asi,
	500	unsigned size)
faed1c2a	501	{
c658b94f AF	502	MicroBlazeCPU *cpu;
	503	CPUMBState *env;
	504
97f90cbf	505	qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
c658b94f AF	506	addr, is_write ? 1 : 0, is_exec ? 1 : 0);
	507	if (cs == NULL) {
	508	return;
	509	}
	510	cpu = MICROBLAZE_CPU(cs);
	511	env = &cpu->env;
	512	if (!(env->sregs[SR_MSR] & MSR_EE)) {
faed1c2a EI	513	return;
	514	}
	515
97f90cbf	516	env->sregs[SR_EAR] = addr;
faed1c2a	517	if (is_exec) {
97f90cbf	518	if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
faed1c2a	519	env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
64254eba	520	helper_raise_exception(env, EXCP_HW_EXCP);
faed1c2a EI	521	}
faed1c2a EI	522	} else {
97f90cbf	523	if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
faed1c2a	524	env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
64254eba	525	helper_raise_exception(env, EXCP_HW_EXCP);
faed1c2a EI	526	}
	527	}
	528	}
3c7b48b7	529	#endif