projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 2c52c816 TS |
1 | Unsolved issues/bugs in the mips/mipsel backend |
| 2 | ----------------------------------------------- | |
| 3 | ||
| 15dcf5aa TS |
4 | General |
| 5 | ------- | |
| d0f48074 | 6 | - Unimplemented ASEs: |
| d0f48074 TS |
7 | - MDMX |
| 8 | - SmartMIPS | |
| b30706dd | 9 | - microMIPS DSP r1 & r2 encodings |
| d0f48074 TS |
10 | - MT ASE only partially implemented and not functional |
| 11 | - Shadow register support only partially implemented, | |
| 12 | lacks set switching on interrupt/exception. | |
| 13 | - 34K ITC not implemented. | |
| 14 | - A general lack of documentation, especially for technical internals. | |
| 15 | Existing documentation is x86-centric. | |
| 16 | - Reverse endianness bit not implemented | |
| 17 | - The TLB emulation is very inefficient: | |
| 6576b74b | 18 | QEMU's softmmu implements a x86-style MMU, with separate entries |
| d0f48074 TS |
19 | for read/write/execute, a TLB index which is just a modulo of the |
| 20 | virtual address, and a set of TLBs for each user/kernel/supervisor | |
| 21 | MMU mode. | |
| 22 | MIPS has a single entry for read/write/execute and only one MMU mode. | |
| 23 | But it is fully associative with randomized entry indices, and uses | |
| 24 | up to 256 ASID tags as additional matching criterion (which roughly | |
| 25 | equates to 256 MMU modes). It also has a global flag which causes | |
| 26 | entries to match regardless of ASID. | |
| 6576b74b | 27 | To cope with these differences, QEMU currently flushes the TLB at |
| d0f48074 TS |
28 | each ASID change. Using the MMU modes to implement ASIDs hinges on |
| 29 | implementing the global bit efficiently. | |
| bec19c09 | 30 | - save/restore of the CPU state is not implemented (see machine.c). |
| 2c52c816 | 31 | |
| 15dcf5aa TS |
32 | MIPS64 |
| 33 | ------ | |
| 540635ba | 34 | - Userland emulation (both n32 and n64) not functional. |
| 15dcf5aa TS |
35 | |
| 36 | "Generic" 4Kc system emulation | |
| 37 | ------------------------------ | |
| ebbd0ffd TS |
38 | - Doesn't correspond to any real hardware. Should be removed some day, |
| 39 | U-Boot is the last remaining user. | |
| 15dcf5aa | 40 | |
| 509b8ab2 TS |
41 | PICA 61 system emulation |
| 42 | ------------------------ | |
| 43 | - No framebuffer support yet. | |
| 44 | ||
| 15dcf5aa TS |
45 | MALTA system emulation |
| 46 | ---------------------- | |
| 2c52c816 | 47 | - We fake firmware support instead of doing the real thing |
| ebbd0ffd TS |
48 | - Real firmware (YAMON) falls over when trying to init RAM, presumably |
| 49 | due to lacking system controller emulation. | |
| 0300e3fa TS |
50 | - Bonito system controller not implemented |
| 51 | - MSC1 system controller not implemented |