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1/*
2 * QEMU OpenRISC CPU
3 *
4 * Copyright (c) 2012 Jia Liu <proljc@gmail.com>
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19
20#include "cpu.h"
21#include "qemu-common.h"
22
23/* CPUClass::reset() */
24static void openrisc_cpu_reset(CPUState *s)
25{
26 OpenRISCCPU *cpu = OPENRISC_CPU(s);
27 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu);
28
29 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 30 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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31 log_cpu_state(&cpu->env, 0);
32 }
33
34 occ->parent_reset(s);
35
36 memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
37
38 tlb_flush(&cpu->env, 1);
39 /*tb_flush(&cpu->env); FIXME: Do we need it? */
40
41 cpu->env.pc = 0x100;
42 cpu->env.sr = SR_FO | SR_SM;
43 cpu->env.exception_index = -1;
44
45 cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
46 cpu->env.cpucfgr = CPUCFGR_OB32S | CPUCFGR_OF32S;
47 cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
48 cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
49
50#ifndef CONFIG_USER_ONLY
51 cpu->env.picmr = 0x00000000;
52 cpu->env.picsr = 0x00000000;
53
54 cpu->env.ttmr = 0x00000000;
55 cpu->env.ttcr = 0x00000000;
56#endif
57}
58
59static inline void set_feature(OpenRISCCPU *cpu, int feature)
60{
61 cpu->feature |= feature;
62 cpu->env.cpucfgr = cpu->feature;
63}
64
c296262b 65static void openrisc_cpu_realizefn(DeviceState *dev, Error **errp)
e67db06e 66{
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67 OpenRISCCPU *cpu = OPENRISC_CPU(dev);
68 OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(dev);
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69
70 qemu_init_vcpu(&cpu->env);
71 cpu_reset(CPU(cpu));
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72
73 occ->parent_realize(dev, errp);
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74}
75
76static void openrisc_cpu_initfn(Object *obj)
77{
c05efcb1 78 CPUState *cs = CPU(obj);
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79 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
80 static int inited;
81
c05efcb1 82 cs->env_ptr = &cpu->env;
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83 cpu_exec_init(&cpu->env);
84
85#ifndef CONFIG_USER_ONLY
86 cpu_openrisc_mmu_init(cpu);
87#endif
88
89 if (tcg_enabled() && !inited) {
90 inited = 1;
91 openrisc_translate_init();
92 }
93}
94
95/* CPU models */
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96
97static ObjectClass *openrisc_cpu_class_by_name(const char *cpu_model)
98{
99 ObjectClass *oc;
100
101 if (cpu_model == NULL) {
102 return NULL;
103 }
104
105 oc = object_class_by_name(cpu_model);
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106 if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_OPENRISC_CPU) ||
107 object_class_is_abstract(oc))) {
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108 return NULL;
109 }
110 return oc;
111}
112
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113static void or1200_initfn(Object *obj)
114{
115 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
116
117 set_feature(cpu, OPENRISC_FEATURE_OB32S);
118 set_feature(cpu, OPENRISC_FEATURE_OF32S);
119}
120
121static void openrisc_any_initfn(Object *obj)
122{
123 OpenRISCCPU *cpu = OPENRISC_CPU(obj);
124
125 set_feature(cpu, OPENRISC_FEATURE_OB32S);
126}
127
128typedef struct OpenRISCCPUInfo {
129 const char *name;
130 void (*initfn)(Object *obj);
131} OpenRISCCPUInfo;
132
133static const OpenRISCCPUInfo openrisc_cpus[] = {
134 { .name = "or1200", .initfn = or1200_initfn },
135 { .name = "any", .initfn = openrisc_any_initfn },
136};
137
138static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
139{
140 OpenRISCCPUClass *occ = OPENRISC_CPU_CLASS(oc);
141 CPUClass *cc = CPU_CLASS(occ);
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142 DeviceClass *dc = DEVICE_CLASS(oc);
143
144 occ->parent_realize = dc->realize;
145 dc->realize = openrisc_cpu_realizefn;
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146
147 occ->parent_reset = cc->reset;
148 cc->reset = openrisc_cpu_reset;
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149
150 cc->class_by_name = openrisc_cpu_class_by_name;
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151}
152
153static void cpu_register(const OpenRISCCPUInfo *info)
154{
155 TypeInfo type_info = {
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156 .parent = TYPE_OPENRISC_CPU,
157 .instance_size = sizeof(OpenRISCCPU),
158 .instance_init = info->initfn,
159 .class_size = sizeof(OpenRISCCPUClass),
160 };
161
478032a9 162 type_info.name = g_strdup_printf("%s-" TYPE_OPENRISC_CPU, info->name);
a1ebd6ce 163 type_register(&type_info);
478032a9 164 g_free((void *)type_info.name);
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165}
166
167static const TypeInfo openrisc_cpu_type_info = {
168 .name = TYPE_OPENRISC_CPU,
169 .parent = TYPE_CPU,
170 .instance_size = sizeof(OpenRISCCPU),
171 .instance_init = openrisc_cpu_initfn,
bc755a00 172 .abstract = true,
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173 .class_size = sizeof(OpenRISCCPUClass),
174 .class_init = openrisc_cpu_class_init,
175};
176
177static void openrisc_cpu_register_types(void)
178{
179 int i;
180
181 type_register_static(&openrisc_cpu_type_info);
182 for (i = 0; i < ARRAY_SIZE(openrisc_cpus); i++) {
183 cpu_register(&openrisc_cpus[i]);
184 }
185}
186
187OpenRISCCPU *cpu_openrisc_init(const char *cpu_model)
188{
189 OpenRISCCPU *cpu;
bd039ce0 190 ObjectClass *oc;
e67db06e 191
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192 oc = openrisc_cpu_class_by_name(cpu_model);
193 if (oc == NULL) {
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194 return NULL;
195 }
bd039ce0 196 cpu = OPENRISC_CPU(object_new(object_class_get_name(oc)));
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197 cpu->env.cpu_model_str = cpu_model;
198
c296262b 199 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
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200
201 return cpu;
202}
203
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204/* Sort alphabetically by type name, except for "any". */
205static gint openrisc_cpu_list_compare(gconstpointer a, gconstpointer b)
206{
207 ObjectClass *class_a = (ObjectClass *)a;
208 ObjectClass *class_b = (ObjectClass *)b;
209 const char *name_a, *name_b;
210
211 name_a = object_class_get_name(class_a);
212 name_b = object_class_get_name(class_b);
478032a9 213 if (strcmp(name_a, "any-" TYPE_OPENRISC_CPU) == 0) {
e67db06e 214 return 1;
478032a9 215 } else if (strcmp(name_b, "any-" TYPE_OPENRISC_CPU) == 0) {
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216 return -1;
217 } else {
218 return strcmp(name_a, name_b);
219 }
220}
221
222static void openrisc_cpu_list_entry(gpointer data, gpointer user_data)
223{
224 ObjectClass *oc = data;
8486af93 225 CPUListState *s = user_data;
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226 const char *typename;
227 char *name;
e67db06e 228
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229 typename = object_class_get_name(oc);
230 name = g_strndup(typename,
231 strlen(typename) - strlen("-" TYPE_OPENRISC_CPU));
e67db06e 232 (*s->cpu_fprintf)(s->file, " %s\n",
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233 name);
234 g_free(name);
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235}
236
237void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf)
238{
8486af93 239 CPUListState s = {
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240 .file = f,
241 .cpu_fprintf = cpu_fprintf,
242 };
243 GSList *list;
244
245 list = object_class_get_list(TYPE_OPENRISC_CPU, false);
246 list = g_slist_sort(list, openrisc_cpu_list_compare);
247 (*cpu_fprintf)(f, "Available CPUs:\n");
248 g_slist_foreach(list, openrisc_cpu_list_entry, &s);
249 g_slist_free(list);
250}
251
252type_init(openrisc_cpu_register_types)