[qemu.git] / target-openrisc / sys_helper.c

/*
 * OpenRISC system instructions helper routines
 *
 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
 *                         Zhizhou Zhang <etouzh@gmail.com>
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "helper.h"

#define TO_SPR(group, number) (((group) << 11) + (number))

void HELPER(mtspr)(CPUOpenRISCState *env,
                   target_ulong ra, target_ulong rb, target_ulong offset)
{
#ifndef CONFIG_USER_ONLY
    int spr = (ra | offset);
    int idx;

    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);

    switch (spr) {
    case TO_SPR(0, 0): /* VR */
        env->vr = rb;
        break;

    case TO_SPR(0, 16): /* NPC */
        env->npc = rb;
        break;

    case TO_SPR(0, 17): /* SR */
        if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
            (rb & (SR_IME | SR_DME | SR_SM))) {
            tlb_flush(env, 1);
        }
        env->sr = rb;
        env->sr |= SR_FO;      /* FO is const equal to 1 */
        if (env->sr & SR_DME) {
            env->tlb->cpu_openrisc_map_address_data =
                &cpu_openrisc_get_phys_data;
        } else {
            env->tlb->cpu_openrisc_map_address_data =
                &cpu_openrisc_get_phys_nommu;
        }

        if (env->sr & SR_IME) {
            env->tlb->cpu_openrisc_map_address_code =
                &cpu_openrisc_get_phys_code;
        } else {
            env->tlb->cpu_openrisc_map_address_code =
                &cpu_openrisc_get_phys_nommu;
        }
        break;

    case TO_SPR(0, 18): /* PPC */
        env->ppc = rb;
        break;

    case TO_SPR(0, 32): /* EPCR */
        env->epcr = rb;
        break;

    case TO_SPR(0, 48): /* EEAR */
        env->eear = rb;
        break;

    case TO_SPR(0, 64): /* ESR */
        env->esr = rb;
        break;
    case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
        idx = spr - TO_SPR(1, 512);
        if (!(rb & 1)) {
            tlb_flush_page(env, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
        }
        env->tlb->dtlb[0][idx].mr = rb;
        break;

    case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */
        idx = spr - TO_SPR(1, 640);
        env->tlb->dtlb[0][idx].tr = rb;
        break;
    case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
    case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
    case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
    case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
    case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
    case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
        break;
    case TO_SPR(2, 512) ... TO_SPR(2, 639):   /* ITLBW0MR 0-127 */
        idx = spr - TO_SPR(2, 512);
        if (!(rb & 1)) {
            tlb_flush_page(env, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
        }
        env->tlb->itlb[0][idx].mr = rb;
        break;

    case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */
        idx = spr - TO_SPR(2, 640);
        env->tlb->itlb[0][idx].tr = rb;
        break;
    case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
    case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
    case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
    case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
    case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
    case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
        break;
    case TO_SPR(9, 0):  /* PICMR */
        env->picmr |= rb;
        break;
    case TO_SPR(9, 2):  /* PICSR */
        env->picsr &= ~rb;
        break;
    case TO_SPR(10, 0): /* TTMR */
        {
            int ip = env->ttmr & TTMR_IP;

            if (rb & TTMR_IP) {    /* Keep IP bit.  */
                env->ttmr = (rb & ~TTMR_IP) + ip;
            } else {    /* Clear IP bit.  */
                env->ttmr = rb & ~TTMR_IP;
                env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
            }

            cpu_openrisc_count_update(cpu);

            switch (env->ttmr & TTMR_M) {
            case TIMER_NONE:
                cpu_openrisc_count_stop(cpu);
                break;
            case TIMER_INTR:
                cpu_openrisc_count_start(cpu);
                break;
            case TIMER_SHOT:
                cpu_openrisc_count_start(cpu);
                break;
            case TIMER_CONT:
                cpu_openrisc_count_start(cpu);
                break;
            default:
                break;
            }
        }
        break;

    case TO_SPR(10, 1): /* TTCR */
        env->ttcr = rb;
        if (env->ttmr & TIMER_NONE) {
            return;
        }
        cpu_openrisc_count_start(cpu);
        break;
    default:

        break;
    }
#endif
}

target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
                           target_ulong rd, target_ulong ra, uint32_t offset)
{
#ifndef CONFIG_USER_ONLY
    int spr = (ra | offset);
    int idx;

    OpenRISCCPU *cpu = openrisc_env_get_cpu(env);

    switch (spr) {
    case TO_SPR(0, 0): /* VR */
        return env->vr & SPR_VR;

    case TO_SPR(0, 1): /* UPR */
        return env->upr;    /* TT, DM, IM, UP present */

    case TO_SPR(0, 2): /* CPUCFGR */
        return env->cpucfgr;

    case TO_SPR(0, 3): /* DMMUCFGR */
        return env->dmmucfgr;    /* 1Way, 64 entries */

    case TO_SPR(0, 4): /* IMMUCFGR */
        return env->immucfgr;

    case TO_SPR(0, 16): /* NPC */
        return env->npc;

    case TO_SPR(0, 17): /* SR */
        return env->sr;

    case TO_SPR(0, 18): /* PPC */
        return env->ppc;

    case TO_SPR(0, 32): /* EPCR */
        return env->epcr;

    case TO_SPR(0, 48): /* EEAR */
        return env->eear;

    case TO_SPR(0, 64): /* ESR */
        return env->esr;

    case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
        idx = spr - TO_SPR(1, 512);
        return env->tlb->dtlb[0][idx].mr;

    case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */
        idx = spr - TO_SPR(1, 640);
        return env->tlb->dtlb[0][idx].tr;

    case TO_SPR(1, 768) ... TO_SPR(1, 895):   /* DTLBW1MR 0-127 */
    case TO_SPR(1, 896) ... TO_SPR(1, 1023):  /* DTLBW1TR 0-127 */
    case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
    case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
    case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
    case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
        break;

    case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */
        idx = spr - TO_SPR(2, 512);
        return env->tlb->itlb[0][idx].mr;

    case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */
        idx = spr - TO_SPR(2, 640);
        return env->tlb->itlb[0][idx].tr;

    case TO_SPR(2, 768) ... TO_SPR(2, 895):   /* ITLBW1MR 0-127 */
    case TO_SPR(2, 896) ... TO_SPR(2, 1023):  /* ITLBW1TR 0-127 */
    case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
    case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
    case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
    case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
        break;

    case TO_SPR(9, 0):  /* PICMR */
        return env->picmr;

    case TO_SPR(9, 2):  /* PICSR */
        return env->picsr;

    case TO_SPR(10, 0): /* TTMR */
        return env->ttmr;

    case TO_SPR(10, 1): /* TTCR */
        cpu_openrisc_count_update(cpu);
        return env->ttcr;

    default:
        break;
    }
#endif

/*If we later need to add tracepoints (or debug printfs) for the return
value, it may be useful to structure the code like this:

target_ulong ret = 0;

switch() {
case x:
 ret = y;
 break;
case z:
 ret = 42;
 break;
...
}

later something like trace_spr_read(ret);

return ret;*/

    /* for rd is passed in, if rd unchanged, just keep it back.  */
    return rd;
}
Commit	Line	Data
4dd044c6 JL	1	/*
	2	* OpenRISC system instructions helper routines
	3	*
	4	* Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
	5	* Zhizhou Zhang <etouzh@gmail.com>
	6	*
	7	* This library is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU Lesser General Public
	9	* License as published by the Free Software Foundation; either
	10	* version 2 of the License, or (at your option) any later version.
	11	*
	12	* This library is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	15	* Lesser General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU Lesser General Public
	18	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	19	*/
	20
	21	#include "cpu.h"
	22	#include "helper.h"
	23
	24	#define TO_SPR(group, number) (((group) << 11) + (number))
	25
	26	void HELPER(mtspr)(CPUOpenRISCState *env,
	27	target_ulong ra, target_ulong rb, target_ulong offset)
	28	{
	29	#ifndef CONFIG_USER_ONLY
	30	int spr = (ra \| offset);
	31	int idx;
	32
dd51dc52	33	OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
4dd044c6 JL	34
	35	switch (spr) {
	36	case TO_SPR(0, 0): /* VR */
	37	env->vr = rb;
	38	break;
	39
	40	case TO_SPR(0, 16): /* NPC */
	41	env->npc = rb;
	42	break;
	43
	44	case TO_SPR(0, 17): /* SR */
	45	if ((env->sr & (SR_IME \| SR_DME \| SR_SM)) ^
	46	(rb & (SR_IME \| SR_DME \| SR_SM))) {
	47	tlb_flush(env, 1);
	48	}
	49	env->sr = rb;
	50	env->sr \|= SR_FO; /* FO is const equal to 1 */
	51	if (env->sr & SR_DME) {
	52	env->tlb->cpu_openrisc_map_address_data =
	53	&cpu_openrisc_get_phys_data;
	54	} else {
	55	env->tlb->cpu_openrisc_map_address_data =
	56	&cpu_openrisc_get_phys_nommu;
	57	}
	58
	59	if (env->sr & SR_IME) {
	60	env->tlb->cpu_openrisc_map_address_code =
	61	&cpu_openrisc_get_phys_code;
	62	} else {
	63	env->tlb->cpu_openrisc_map_address_code =
	64	&cpu_openrisc_get_phys_nommu;
	65	}
	66	break;
	67
	68	case TO_SPR(0, 18): /* PPC */
	69	env->ppc = rb;
	70	break;
	71
	72	case TO_SPR(0, 32): /* EPCR */
	73	env->epcr = rb;
	74	break;
	75
	76	case TO_SPR(0, 48): /* EEAR */
	77	env->eear = rb;
	78	break;
	79
	80	case TO_SPR(0, 64): /* ESR */
	81	env->esr = rb;
	82	break;
	83	case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
	84	idx = spr - TO_SPR(1, 512);
	85	if (!(rb & 1)) {
	86	tlb_flush_page(env, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
	87	}
	88	env->tlb->dtlb[0][idx].mr = rb;
	89	break;
	90
	91	case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */
	92	idx = spr - TO_SPR(1, 640);
	93	env->tlb->dtlb[0][idx].tr = rb;
	94	break;
	95	case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
	96	case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
	97	case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
98	case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
99	case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
100	case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
101	break;
102	case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */
103	idx = spr - TO_SPR(2, 512);
104	if (!(rb & 1)) {
105	tlb_flush_page(env, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
106	}
107	env->tlb->itlb[0][idx].mr = rb;
108	break;
109
110	case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */
111	idx = spr - TO_SPR(2, 640);
112	env->tlb->itlb[0][idx].tr = rb;
113	break;
114	case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
115	case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
116	case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
117	case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
118	case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
119	case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
120	break;
121	case TO_SPR(9, 0): /* PICMR */
122	env->picmr \|= rb;
123	break;
124	case TO_SPR(9, 2): /* PICSR */
125	env->picsr &= ~rb;
126	break;
127	case TO_SPR(10, 0): /* TTMR */
128	{
129	int ip = env->ttmr & TTMR_IP;
130
131	if (rb & TTMR_IP) { /* Keep IP bit. */
132	env->ttmr = (rb & ~TTMR_IP) + ip;
133	} else { /* Clear IP bit. */
134	env->ttmr = rb & ~TTMR_IP;
135	env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
136	}
137
138	cpu_openrisc_count_update(cpu);
139
140	switch (env->ttmr & TTMR_M) {
141	case TIMER_NONE:
142	cpu_openrisc_count_stop(cpu);
143	break;
144	case TIMER_INTR:
145	cpu_openrisc_count_start(cpu);
146	break;
147	case TIMER_SHOT:
148	cpu_openrisc_count_start(cpu);
149	break;
150	case TIMER_CONT:
151	cpu_openrisc_count_start(cpu);
152	break;
153	default:
154	break;
155	}
156	}
157	break;
158
159	case TO_SPR(10, 1): /* TTCR */
160	env->ttcr = rb;
161	if (env->ttmr & TIMER_NONE) {
162	return;
163	}
164	cpu_openrisc_count_start(cpu);
165	break;
166	default:
167
168	break;
169	}
170	#endif
171	}
172
173	target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
174	target_ulong rd, target_ulong ra, uint32_t offset)
175	{
176	#ifndef CONFIG_USER_ONLY
177	int spr = (ra \| offset);
178	int idx;
179
dd51dc52	180	OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
4dd044c6 JL	181
	182	switch (spr) {
	183	case TO_SPR(0, 0): /* VR */
	184	return env->vr & SPR_VR;
	185
	186	case TO_SPR(0, 1): /* UPR */
	187	return env->upr; /* TT, DM, IM, UP present */
	188
	189	case TO_SPR(0, 2): /* CPUCFGR */
	190	return env->cpucfgr;
	191
	192	case TO_SPR(0, 3): /* DMMUCFGR */
	193	return env->dmmucfgr; /* 1Way, 64 entries */
	194
	195	case TO_SPR(0, 4): /* IMMUCFGR */
	196	return env->immucfgr;
	197
	198	case TO_SPR(0, 16): /* NPC */
	199	return env->npc;
	200
	201	case TO_SPR(0, 17): /* SR */
	202	return env->sr;
	203
	204	case TO_SPR(0, 18): /* PPC */
	205	return env->ppc;
	206
	207	case TO_SPR(0, 32): /* EPCR */
	208	return env->epcr;
	209
	210	case TO_SPR(0, 48): /* EEAR */
	211	return env->eear;
	212
	213	case TO_SPR(0, 64): /* ESR */
	214	return env->esr;
	215
	216	case TO_SPR(1, 512) ... TO_SPR(1, 639): /* DTLBW0MR 0-127 */
	217	idx = spr - TO_SPR(1, 512);
	218	return env->tlb->dtlb[0][idx].mr;
	219
	220	case TO_SPR(1, 640) ... TO_SPR(1, 767): /* DTLBW0TR 0-127 */
	221	idx = spr - TO_SPR(1, 640);
	222	return env->tlb->dtlb[0][idx].tr;
	223
	224	case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
	225	case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
	226	case TO_SPR(1, 1024) ... TO_SPR(1, 1151): /* DTLBW2MR 0-127 */
	227	case TO_SPR(1, 1152) ... TO_SPR(1, 1279): /* DTLBW2TR 0-127 */
	228	case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
	229	case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
	230	break;
	231
	232	case TO_SPR(2, 512) ... TO_SPR(2, 639): /* ITLBW0MR 0-127 */
	233	idx = spr - TO_SPR(2, 512);
	234	return env->tlb->itlb[0][idx].mr;
	235
	236	case TO_SPR(2, 640) ... TO_SPR(2, 767): /* ITLBW0TR 0-127 */
	237	idx = spr - TO_SPR(2, 640);
	238	return env->tlb->itlb[0][idx].tr;
	239
	240	case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
	241	case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
	242	case TO_SPR(2, 1024) ... TO_SPR(2, 1151): /* ITLBW2MR 0-127 */
	243	case TO_SPR(2, 1152) ... TO_SPR(2, 1279): /* ITLBW2TR 0-127 */
	244	case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
245	case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
246	break;
247
248	case TO_SPR(9, 0): /* PICMR */
249	return env->picmr;
250
251	case TO_SPR(9, 2): /* PICSR */
252	return env->picsr;
253
254	case TO_SPR(10, 0): /* TTMR */
255	return env->ttmr;
256
257	case TO_SPR(10, 1): /* TTCR */
258	cpu_openrisc_count_update(cpu);
259	return env->ttcr;
260
261	default:
262	break;
263	}
264	#endif
265
266	/*If we later need to add tracepoints (or debug printfs) for the return
267	value, it may be useful to structure the code like this:
268
269	target_ulong ret = 0;
270
271	switch() {
272	case x:
273	ret = y;
274	break;
275	case z:
276	ret = 42;
277	break;
278	...
279	}
280
281	later something like trace_spr_read(ret);
282
283	return ret;*/
284
285	/* for rd is passed in, if rd unchanged, just keep it back. */
286	return rd;
287	}