projects / qemu.git / blame
| Commit | Line | Data |
|---|---|---|
| 9d7c3f4a DG |
1 | #if !defined (__MMU_HASH32_H__) |
| 2 | #define __MMU_HASH32_H__ | |
| 3 | ||
| 4 | #ifndef CONFIG_USER_ONLY | |
| 5 | ||
| 59191721 | 6 | hwaddr get_pteg_offset32(CPUPPCState *env, hwaddr hash); |
| f2ad6be8 | 7 | hwaddr ppc_hash32_get_phys_page_debug(CPUPPCState *env, target_ulong addr); |
| 25de24ab DG |
8 | int ppc_hash32_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw, |
| 9 | int mmu_idx); | |
| 9d7c3f4a | 10 | |
| d5aea6f3 DG |
11 | /* |
| 12 | * Segment register definitions | |
| 13 | */ | |
| 14 | ||
| 15 | #define SR32_T 0x80000000 | |
| 16 | #define SR32_KS 0x40000000 | |
| 17 | #define SR32_KP 0x20000000 | |
| 18 | #define SR32_NX 0x10000000 | |
| 19 | #define SR32_VSID 0x00ffffff | |
| 20 | ||
| 21 | /* | |
| 22 | * Block Address Translation (BAT) definitions | |
| 23 | */ | |
| 24 | ||
| d5aea6f3 DG |
25 | #define BATU32_BEPI 0xfffe0000 |
| 26 | #define BATU32_BL 0x00001ffc | |
| 27 | #define BATU32_VS 0x00000002 | |
| 28 | #define BATU32_VP 0x00000001 | |
| 29 | ||
| 30 | ||
| d5aea6f3 DG |
31 | #define BATL32_BRPN 0xfffe0000 |
| 32 | #define BATL32_WIMG 0x00000078 | |
| 33 | #define BATL32_PP 0x00000003 | |
| 34 | ||
| 35 | /* PowerPC 601 has slightly different BAT registers */ | |
| 36 | ||
| 37 | #define BATU32_601_KS 0x00000008 | |
| 38 | #define BATU32_601_KP 0x00000004 | |
| 39 | #define BATU32_601_PP 0x00000003 | |
| 40 | ||
| 41 | #define BATL32_601_V 0x00000040 | |
| 42 | #define BATL32_601_BL 0x0000003f | |
| 43 | ||
| 44 | /* | |
| 45 | * Hash page table definitions | |
| 46 | */ | |
| 47 | ||
| 48 | #define HPTES_PER_GROUP 8 | |
| 49 | #define HASH_PTE_SIZE_32 8 | |
| 50 | #define HASH_PTEG_SIZE_32 (HASH_PTE_SIZE_32 * HPTES_PER_GROUP) | |
| 51 | ||
| 52 | #define HPTE32_V_VALID 0x80000000 | |
| 53 | #define HPTE32_V_VSID 0x7fffff80 | |
| 54 | #define HPTE32_V_SECONDARY 0x00000040 | |
| 55 | #define HPTE32_V_API 0x0000003f | |
| 56 | #define HPTE32_V_COMPARE(x, y) (!(((x) ^ (y)) & 0x7fffffbf)) | |
| 57 | ||
| 58 | #define HPTE32_R_RPN 0xfffff000 | |
| 59 | #define HPTE32_R_R 0x00000100 | |
| 60 | #define HPTE32_R_C 0x00000080 | |
| 61 | #define HPTE32_R_W 0x00000040 | |
| 62 | #define HPTE32_R_I 0x00000020 | |
| 63 | #define HPTE32_R_M 0x00000010 | |
| 64 | #define HPTE32_R_G 0x00000008 | |
| 65 | #define HPTE32_R_WIMG 0x00000078 | |
| 66 | #define HPTE32_R_PP 0x00000003 | |
| 67 | ||
| dffdaf61 DG |
68 | static inline target_ulong ppc_hash32_load_hpte0(CPUPPCState *env, |
| 69 | hwaddr pte_offset) | |
| 70 | { | |
| 71 | assert(!env->external_htab); /* Not supported on 32-bit for now */ | |
| 72 | return ldl_phys(env->htab_base + pte_offset); | |
| 73 | } | |
| 74 | ||
| 75 | static inline target_ulong ppc_hash32_load_hpte1(CPUPPCState *env, | |
| 76 | hwaddr pte_offset) | |
| 77 | { | |
| 78 | assert(!env->external_htab); /* Not supported on 32-bit for now */ | |
| 79 | return ldl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2); | |
| 80 | } | |
| 81 | ||
| 82 | static inline void ppc_hash32_store_hpte0(CPUPPCState *env, | |
| 83 | hwaddr pte_offset, target_ulong pte0) | |
| 84 | { | |
| 85 | assert(!env->external_htab); /* Not supported on 32-bit for now */ | |
| 86 | stl_phys(env->htab_base + pte_offset, pte0); | |
| 87 | } | |
| 88 | ||
| 89 | static inline void ppc_hash32_store_hpte1(CPUPPCState *env, | |
| 90 | hwaddr pte_offset, target_ulong pte1) | |
| 91 | { | |
| 92 | assert(!env->external_htab); /* Not supported on 32-bit for now */ | |
| 93 | stl_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_32/2, pte1); | |
| 94 | } | |
| 95 | ||
| aea390e4 DG |
96 | typedef struct { |
| 97 | uint32_t pte0, pte1; | |
| 98 | } ppc_hash_pte32_t; | |
| 99 | ||
| 9d7c3f4a DG |
100 | #endif /* CONFIG_USER_ONLY */ |
| 101 | ||
| 102 | #endif /* __MMU_HASH32_H__ */ |