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cpu: Change qemu_init_vcpu() argument to CPUState
[qemu.git] / target-sh4 / cpu.c
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1/*
2 * QEMU SuperH CPU
3 *
c4bb0f99 4 * Copyright (c) 2005 Samuel Tardieu
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5 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
20 */
21
22#include "cpu.h"
23#include "qemu-common.h"
1e45d31b 24#include "migration/vmstate.h"
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25
26
27/* CPUClass::reset() */
28static void superh_cpu_reset(CPUState *s)
29{
30 SuperHCPU *cpu = SUPERH_CPU(s);
31 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
32 CPUSH4State *env = &cpu->env;
33
c4bb0f99 34 if (qemu_loglevel_mask(CPU_LOG_RESET)) {
55e5c285 35 qemu_log("CPU Reset (CPU %d)\n", s->cpu_index);
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36 log_cpu_state(env, 0);
37 }
38
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39 scc->parent_reset(s);
40
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41 memset(env, 0, offsetof(CPUSH4State, breakpoints));
42 tlb_flush(env, 1);
43
44 env->pc = 0xA0000000;
45#if defined(CONFIG_USER_ONLY)
46 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
47 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
48#else
49 env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;
50 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
51 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
52 set_flush_to_zero(1, &env->fp_status);
53#endif
54 set_default_nan_mode(1, &env->fp_status);
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55}
56
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57typedef struct SuperHCPUListState {
58 fprintf_function cpu_fprintf;
59 FILE *file;
60} SuperHCPUListState;
61
62/* Sort alphabetically by type name. */
63static gint superh_cpu_list_compare(gconstpointer a, gconstpointer b)
64{
65 ObjectClass *class_a = (ObjectClass *)a;
66 ObjectClass *class_b = (ObjectClass *)b;
67 const char *name_a, *name_b;
68
69 name_a = object_class_get_name(class_a);
70 name_b = object_class_get_name(class_b);
71 return strcmp(name_a, name_b);
72}
73
74static void superh_cpu_list_entry(gpointer data, gpointer user_data)
75{
76 ObjectClass *oc = data;
77 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
78 SuperHCPUListState *s = user_data;
79
80 (*s->cpu_fprintf)(s->file, "%s\n",
81 scc->name);
82}
83
84void sh4_cpu_list(FILE *f, fprintf_function cpu_fprintf)
85{
86 SuperHCPUListState s = {
87 .cpu_fprintf = cpu_fprintf,
88 .file = f,
89 };
90 GSList *list;
91
92 list = object_class_get_list(TYPE_SUPERH_CPU, false);
93 list = g_slist_sort(list, superh_cpu_list_compare);
94 g_slist_foreach(list, superh_cpu_list_entry, &s);
95 g_slist_free(list);
96}
97
98static gint superh_cpu_name_compare(gconstpointer a, gconstpointer b)
99{
100 const SuperHCPUClass *scc = SUPERH_CPU_CLASS(a);
101 const char *name = b;
102
103 return strcasecmp(scc->name, name);
104}
105
106static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
107{
108 ObjectClass *oc;
109 GSList *list, *item;
110
111 if (cpu_model == NULL) {
112 return NULL;
113 }
114 if (strcasecmp(cpu_model, "any") == 0) {
115 return object_class_by_name(TYPE_SH7750R_CPU);
116 }
117
118 oc = object_class_by_name(cpu_model);
119 if (oc != NULL && object_class_dynamic_cast(oc, TYPE_SUPERH_CPU) != NULL
120 && !object_class_is_abstract(oc)) {
121 return oc;
122 }
123
124 oc = NULL;
125 list = object_class_get_list(TYPE_SUPERH_CPU, false);
126 item = g_slist_find_custom(list, cpu_model, superh_cpu_name_compare);
127 if (item != NULL) {
128 oc = item->data;
129 }
130 g_slist_free(list);
131 return oc;
132}
133
134SuperHCPU *cpu_sh4_init(const char *cpu_model)
135{
136 SuperHCPU *cpu;
137 CPUSH4State *env;
138 ObjectClass *oc;
139
140 oc = superh_cpu_class_by_name(cpu_model);
141 if (oc == NULL) {
142 return NULL;
143 }
144 cpu = SUPERH_CPU(object_new(object_class_get_name(oc)));
145 env = &cpu->env;
146 env->cpu_model_str = cpu_model;
147
148 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
149
150 return cpu;
151}
152
153static void sh7750r_cpu_initfn(Object *obj)
154{
155 SuperHCPU *cpu = SUPERH_CPU(obj);
156 CPUSH4State *env = &cpu->env;
157
158 env->id = SH_CPU_SH7750R;
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159 env->features = SH_FEATURE_BCR3_AND_BCR4;
160}
161
162static void sh7750r_class_init(ObjectClass *oc, void *data)
163{
164 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
165
166 scc->name = "SH7750R";
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167 scc->pvr = 0x00050000;
168 scc->prr = 0x00000100;
169 scc->cvr = 0x00110000;
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170}
171
172static const TypeInfo sh7750r_type_info = {
173 .name = TYPE_SH7750R_CPU,
174 .parent = TYPE_SUPERH_CPU,
175 .class_init = sh7750r_class_init,
176 .instance_init = sh7750r_cpu_initfn,
177};
178
179static void sh7751r_cpu_initfn(Object *obj)
180{
181 SuperHCPU *cpu = SUPERH_CPU(obj);
182 CPUSH4State *env = &cpu->env;
183
184 env->id = SH_CPU_SH7751R;
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185 env->features = SH_FEATURE_BCR3_AND_BCR4;
186}
187
188static void sh7751r_class_init(ObjectClass *oc, void *data)
189{
190 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
191
192 scc->name = "SH7751R";
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193 scc->pvr = 0x04050005;
194 scc->prr = 0x00000113;
195 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
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196}
197
198static const TypeInfo sh7751r_type_info = {
199 .name = TYPE_SH7751R_CPU,
200 .parent = TYPE_SUPERH_CPU,
201 .class_init = sh7751r_class_init,
202 .instance_init = sh7751r_cpu_initfn,
203};
204
205static void sh7785_cpu_initfn(Object *obj)
206{
207 SuperHCPU *cpu = SUPERH_CPU(obj);
208 CPUSH4State *env = &cpu->env;
209
210 env->id = SH_CPU_SH7785;
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211 env->features = SH_FEATURE_SH4A;
212}
213
214static void sh7785_class_init(ObjectClass *oc, void *data)
215{
216 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
217
218 scc->name = "SH7785";
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219 scc->pvr = 0x10300700;
220 scc->prr = 0x00000200;
221 scc->cvr = 0x71440211;
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222}
223
224static const TypeInfo sh7785_type_info = {
225 .name = TYPE_SH7785_CPU,
226 .parent = TYPE_SUPERH_CPU,
227 .class_init = sh7785_class_init,
228 .instance_init = sh7785_cpu_initfn,
229};
230
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231static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
232{
233 SuperHCPU *cpu = SUPERH_CPU(dev);
234 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
235
236 cpu_reset(CPU(cpu));
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237
238 scc->parent_realize(dev, errp);
239}
240
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241static void superh_cpu_initfn(Object *obj)
242{
c05efcb1 243 CPUState *cs = CPU(obj);
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244 SuperHCPU *cpu = SUPERH_CPU(obj);
245 CPUSH4State *env = &cpu->env;
246
c05efcb1 247 cs->env_ptr = env;
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248 cpu_exec_init(env);
249
250 env->movcal_backup_tail = &(env->movcal_backup);
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251
252 if (tcg_enabled()) {
253 sh4_translate_init();
254 }
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255}
256
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257static const VMStateDescription vmstate_sh_cpu = {
258 .name = "cpu",
259 .unmigratable = 1,
260};
261
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262static void superh_cpu_class_init(ObjectClass *oc, void *data)
263{
1e45d31b 264 DeviceClass *dc = DEVICE_CLASS(oc);
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265 CPUClass *cc = CPU_CLASS(oc);
266 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
267
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268 scc->parent_realize = dc->realize;
269 dc->realize = superh_cpu_realizefn;
270
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271 scc->parent_reset = cc->reset;
272 cc->reset = superh_cpu_reset;
1e45d31b 273
c1b382e7 274 cc->class_by_name = superh_cpu_class_by_name;
97a8ea5a 275 cc->do_interrupt = superh_cpu_do_interrupt;
878096ee 276 cc->dump_state = superh_cpu_dump_state;
1e45d31b 277 dc->vmsd = &vmstate_sh_cpu;
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278}
279
280static const TypeInfo superh_cpu_type_info = {
281 .name = TYPE_SUPERH_CPU,
282 .parent = TYPE_CPU,
283 .instance_size = sizeof(SuperHCPU),
2b4b4906 284 .instance_init = superh_cpu_initfn,
c1b382e7 285 .abstract = true,
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286 .class_size = sizeof(SuperHCPUClass),
287 .class_init = superh_cpu_class_init,
288};
289
290static void superh_cpu_register_types(void)
291{
292 type_register_static(&superh_cpu_type_info);
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293 type_register_static(&sh7750r_type_info);
294 type_register_static(&sh7751r_type_info);
295 type_register_static(&sh7785_type_info);
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296}
297
298type_init(superh_cpu_register_types)