[qemu.git] / target-sparc / win_helper.c

/*
 * Helpers for CWP and PSTATE handling
 *
 *  Copyright (c) 2003-2005 Fabrice Bellard
 *
 * This library is free software; you can redistribute it and/or
 * modify it under the terms of the GNU Lesser General Public
 * License as published by the Free Software Foundation; either
 * version 2 of the License, or (at your option) any later version.
 *
 * This library is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * Lesser General Public License for more details.
 *
 * You should have received a copy of the GNU Lesser General Public
 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
 */

#include "cpu.h"
#include "helper.h"
#include "trace.h"

static inline void memcpy32(target_ulong *dst, const target_ulong *src)
{
    dst[0] = src[0];
    dst[1] = src[1];
    dst[2] = src[2];
    dst[3] = src[3];
    dst[4] = src[4];
    dst[5] = src[5];
    dst[6] = src[6];
    dst[7] = src[7];
}

void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
{
    /* put the modified wrap registers at their proper location */
    if (env->cwp == env->nwindows - 1) {
        memcpy32(env->regbase, env->regbase + env->nwindows * 16);
    }
    env->cwp = new_cwp;

    /* put the wrap registers at their temporary location */
    if (new_cwp == env->nwindows - 1) {
        memcpy32(env->regbase + env->nwindows * 16, env->regbase);
    }
    env->regwptr = env->regbase + (new_cwp * 16);
}

target_ulong cpu_get_psr(CPUSPARCState *env)
{
    helper_compute_psr(env);

#if !defined(TARGET_SPARC64)
    return env->version | (env->psr & PSR_ICC) |
        (env->psref ? PSR_EF : 0) |
        (env->psrpil << 8) |
        (env->psrs ? PSR_S : 0) |
        (env->psrps ? PSR_PS : 0) |
        (env->psret ? PSR_ET : 0) | env->cwp;
#else
    return env->psr & PSR_ICC;
#endif
}

void cpu_put_psr(CPUSPARCState *env, target_ulong val)
{
    env->psr = val & PSR_ICC;
#if !defined(TARGET_SPARC64)
    env->psref = (val & PSR_EF) ? 1 : 0;
    env->psrpil = (val & PSR_PIL) >> 8;
#endif
#if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
    cpu_check_irqs(env);
#endif
#if !defined(TARGET_SPARC64)
    env->psrs = (val & PSR_S) ? 1 : 0;
    env->psrps = (val & PSR_PS) ? 1 : 0;
    env->psret = (val & PSR_ET) ? 1 : 0;
    cpu_set_cwp(env, val & PSR_CWP);
#endif
    env->cc_op = CC_OP_FLAGS;
}

int cpu_cwp_inc(CPUSPARCState *env, int cwp)
{
    if (unlikely(cwp >= env->nwindows)) {
        cwp -= env->nwindows;
    }
    return cwp;
}

int cpu_cwp_dec(CPUSPARCState *env, int cwp)
{
    if (unlikely(cwp < 0)) {
        cwp += env->nwindows;
    }
    return cwp;
}

#ifndef TARGET_SPARC64
void helper_rett(CPUSPARCState *env)
{
    unsigned int cwp;

    if (env->psret == 1) {
        helper_raise_exception(env, TT_ILL_INSN);
    }

    env->psret = 1;
    cwp = cpu_cwp_inc(env, env->cwp + 1) ;
    if (env->wim & (1 << cwp)) {
        helper_raise_exception(env, TT_WIN_UNF);
    }
    cpu_set_cwp(env, cwp);
    env->psrs = env->psrps;
}

/* XXX: use another pointer for %iN registers to avoid slow wrapping
   handling ? */
void helper_save(CPUSPARCState *env)
{
    uint32_t cwp;

    cwp = cpu_cwp_dec(env, env->cwp - 1);
    if (env->wim & (1 << cwp)) {
        helper_raise_exception(env, TT_WIN_OVF);
    }
    cpu_set_cwp(env, cwp);
}

void helper_restore(CPUSPARCState *env)
{
    uint32_t cwp;

    cwp = cpu_cwp_inc(env, env->cwp + 1);
    if (env->wim & (1 << cwp)) {
        helper_raise_exception(env, TT_WIN_UNF);
    }
    cpu_set_cwp(env, cwp);
}

void helper_wrpsr(CPUSPARCState *env, target_ulong new_psr)
{
    if ((new_psr & PSR_CWP) >= env->nwindows) {
        helper_raise_exception(env, TT_ILL_INSN);
    } else {
        cpu_put_psr(env, new_psr);
    }
}

target_ulong helper_rdpsr(CPUSPARCState *env)
{
    return cpu_get_psr(env);
}

#else
/* XXX: use another pointer for %iN registers to avoid slow wrapping
   handling ? */
void helper_save(CPUSPARCState *env)
{
    uint32_t cwp;

    cwp = cpu_cwp_dec(env, env->cwp - 1);
    if (env->cansave == 0) {
        helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ?
                                                (TT_WOTHER |
                                                 ((env->wstate & 0x38) >> 1)) :
                                                ((env->wstate & 0x7) << 2)));
    } else {
        if (env->cleanwin - env->canrestore == 0) {
            /* XXX Clean windows without trap */
            helper_raise_exception(env, TT_CLRWIN);
        } else {
            env->cansave--;
            env->canrestore++;
            cpu_set_cwp(env, cwp);
        }
    }
}

void helper_restore(CPUSPARCState *env)
{
    uint32_t cwp;

    cwp = cpu_cwp_inc(env, env->cwp + 1);
    if (env->canrestore == 0) {
        helper_raise_exception(env, TT_FILL | (env->otherwin != 0 ?
                                               (TT_WOTHER |
                                                ((env->wstate & 0x38) >> 1)) :
                                               ((env->wstate & 0x7) << 2)));
    } else {
        env->cansave++;
        env->canrestore--;
        cpu_set_cwp(env, cwp);
    }
}

void helper_flushw(CPUSPARCState *env)
{
    if (env->cansave != env->nwindows - 2) {
        helper_raise_exception(env, TT_SPILL | (env->otherwin != 0 ?
                                                (TT_WOTHER |
                                                 ((env->wstate & 0x38) >> 1)) :
                                                ((env->wstate & 0x7) << 2)));
    }
}

void helper_saved(CPUSPARCState *env)
{
    env->cansave++;
    if (env->otherwin == 0) {
        env->canrestore--;
    } else {
        env->otherwin--;
    }
}

void helper_restored(CPUSPARCState *env)
{
    env->canrestore++;
    if (env->cleanwin < env->nwindows - 1) {
        env->cleanwin++;
    }
    if (env->otherwin == 0) {
        env->cansave--;
    } else {
        env->otherwin--;
    }
}

target_ulong cpu_get_ccr(CPUSPARCState *env)
{
    target_ulong psr;

    psr = cpu_get_psr(env);

    return ((env->xcc >> 20) << 4) | ((psr & PSR_ICC) >> 20);
}

void cpu_put_ccr(CPUSPARCState *env, target_ulong val)
{
    env->xcc = (val >> 4) << 20;
    env->psr = (val & 0xf) << 20;
    CC_OP = CC_OP_FLAGS;
}

target_ulong cpu_get_cwp64(CPUSPARCState *env)
{
    return env->nwindows - 1 - env->cwp;
}

void cpu_put_cwp64(CPUSPARCState *env, int cwp)
{
    if (unlikely(cwp >= env->nwindows || cwp < 0)) {
        cwp %= env->nwindows;
    }
    cpu_set_cwp(env, env->nwindows - 1 - cwp);
}

target_ulong helper_rdccr(CPUSPARCState *env)
{
    return cpu_get_ccr(env);
}

void helper_wrccr(CPUSPARCState *env, target_ulong new_ccr)
{
    cpu_put_ccr(env, new_ccr);
}

/* CWP handling is reversed in V9, but we still use the V8 register
   order. */
target_ulong helper_rdcwp(CPUSPARCState *env)
{
    return cpu_get_cwp64(env);
}

void helper_wrcwp(CPUSPARCState *env, target_ulong new_cwp)
{
    cpu_put_cwp64(env, new_cwp);
}

static inline uint64_t *get_gregset(CPUSPARCState *env, uint32_t pstate)
{
    switch (pstate) {
    default:
        trace_win_helper_gregset_error(pstate);
        /* pass through to normal set of global registers */
    case 0:
        return env->bgregs;
    case PS_AG:
        return env->agregs;
    case PS_MG:
        return env->mgregs;
    case PS_IG:
        return env->igregs;
    }
}

void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
{
    uint32_t pstate_regs, new_pstate_regs;
    uint64_t *src, *dst;

    if (env->def->features & CPU_FEATURE_GL) {
        /* PS_AG is not implemented in this case */
        new_pstate &= ~PS_AG;
    }

    pstate_regs = env->pstate & 0xc01;
    new_pstate_regs = new_pstate & 0xc01;

    if (new_pstate_regs != pstate_regs) {
        trace_win_helper_switch_pstate(pstate_regs, new_pstate_regs);

        /* Switch global register bank */
        src = get_gregset(env, new_pstate_regs);
        dst = get_gregset(env, pstate_regs);
        memcpy32(dst, env->gregs);
        memcpy32(env->gregs, src);
    } else {
        trace_win_helper_no_switch_pstate(new_pstate_regs);
    }
    env->pstate = new_pstate;
}

void helper_wrpstate(CPUSPARCState *env, target_ulong new_state)
{
    cpu_change_pstate(env, new_state & 0xf3f);

#if !defined(CONFIG_USER_ONLY)
    if (cpu_interrupts_enabled(env)) {
        cpu_check_irqs(env);
    }
#endif
}

void helper_wrpil(CPUSPARCState *env, target_ulong new_pil)
{
#if !defined(CONFIG_USER_ONLY)
    trace_win_helper_wrpil(env->psrpil, (uint32_t)new_pil);

    env->psrpil = new_pil;

    if (cpu_interrupts_enabled(env)) {
        cpu_check_irqs(env);
    }
#endif
}

void helper_done(CPUSPARCState *env)
{
    trap_state *tsptr = cpu_tsptr(env);

    env->pc = tsptr->tnpc;
    env->npc = tsptr->tnpc + 4;
    cpu_put_ccr(env, tsptr->tstate >> 32);
    env->asi = (tsptr->tstate >> 24) & 0xff;
    cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
    cpu_put_cwp64(env, tsptr->tstate & 0xff);
    env->tl--;

    trace_win_helper_done(env->tl);

#if !defined(CONFIG_USER_ONLY)
    if (cpu_interrupts_enabled(env)) {
        cpu_check_irqs(env);
    }
#endif
}

void helper_retry(CPUSPARCState *env)
{
    trap_state *tsptr = cpu_tsptr(env);

    env->pc = tsptr->tpc;
    env->npc = tsptr->tnpc;
    cpu_put_ccr(env, tsptr->tstate >> 32);
    env->asi = (tsptr->tstate >> 24) & 0xff;
    cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
    cpu_put_cwp64(env, tsptr->tstate & 0xff);
    env->tl--;

    trace_win_helper_retry(env->tl);

#if !defined(CONFIG_USER_ONLY)
    if (cpu_interrupts_enabled(env)) {
        cpu_check_irqs(env);
    }
#endif
}
#endif
Commit	Line	Data
070af384 BS	1	/*
	2	* Helpers for CWP and PSTATE handling
	3	*
	4	* Copyright (c) 2003-2005 Fabrice Bellard
	5	*
	6	* This library is free software; you can redistribute it and/or
	7	* modify it under the terms of the GNU Lesser General Public
	8	* License as published by the Free Software Foundation; either
	9	* version 2 of the License, or (at your option) any later version.
	10	*
	11	* This library is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	* Lesser General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU Lesser General Public
	17	* License along with this library; if not, see <http://www.gnu.org/licenses/>.
	18	*/
	19
	20	#include "cpu.h"
070af384	21	#include "helper.h"
870be6ad	22	#include "trace.h"
070af384 BS	23
	24	static inline void memcpy32(target_ulong dst, const target_ulong src)
	25	{
	26	dst[0] = src[0];
	27	dst[1] = src[1];
	28	dst[2] = src[2];
	29	dst[3] = src[3];
	30	dst[4] = src[4];
	31	dst[5] = src[5];
	32	dst[6] = src[6];
	33	dst[7] = src[7];
	34	}
	35
c5f9864e	36	void cpu_set_cwp(CPUSPARCState *env, int new_cwp)
070af384 BS	37	{
	38	/* put the modified wrap registers at their proper location */
	39	if (env->cwp == env->nwindows - 1) {
	40	memcpy32(env->regbase, env->regbase + env->nwindows * 16);
	41	}
	42	env->cwp = new_cwp;
	43
	44	/* put the wrap registers at their temporary location */
	45	if (new_cwp == env->nwindows - 1) {
	46	memcpy32(env->regbase + env->nwindows * 16, env->regbase);
	47	}
	48	env->regwptr = env->regbase + (new_cwp * 16);
	49	}
	50
c5f9864e	51	target_ulong cpu_get_psr(CPUSPARCState *env)
070af384 BS	52	{
	53	helper_compute_psr(env);
	54
	55	#if !defined(TARGET_SPARC64)
	56	return env->version \| (env->psr & PSR_ICC) \|
	57	(env->psref ? PSR_EF : 0) \|
	58	(env->psrpil << 8) \|
	59	(env->psrs ? PSR_S : 0) \|
	60	(env->psrps ? PSR_PS : 0) \|
	61	(env->psret ? PSR_ET : 0) \| env->cwp;
	62	#else
	63	return env->psr & PSR_ICC;
	64	#endif
	65	}
	66
c5f9864e	67	void cpu_put_psr(CPUSPARCState *env, target_ulong val)
070af384 BS	68	{
	69	env->psr = val & PSR_ICC;
	70	#if !defined(TARGET_SPARC64)
	71	env->psref = (val & PSR_EF) ? 1 : 0;
	72	env->psrpil = (val & PSR_PIL) >> 8;
	73	#endif
	74	#if ((!defined(TARGET_SPARC64)) && !defined(CONFIG_USER_ONLY))
	75	cpu_check_irqs(env);
	76	#endif
	77	#if !defined(TARGET_SPARC64)
	78	env->psrs = (val & PSR_S) ? 1 : 0;
	79	env->psrps = (val & PSR_PS) ? 1 : 0;
	80	env->psret = (val & PSR_ET) ? 1 : 0;
063c3675	81	cpu_set_cwp(env, val & PSR_CWP);
070af384 BS	82	#endif
	83	env->cc_op = CC_OP_FLAGS;
	84	}
	85
c5f9864e	86	int cpu_cwp_inc(CPUSPARCState *env, int cwp)
070af384 BS	87	{
	88	if (unlikely(cwp >= env->nwindows)) {
	89	cwp -= env->nwindows;
	90	}
	91	return cwp;
	92	}
	93
c5f9864e	94	int cpu_cwp_dec(CPUSPARCState *env, int cwp)
070af384 BS	95	{
	96	if (unlikely(cwp < 0)) {
	97	cwp += env->nwindows;
	98	}
	99	return cwp;
	100	}
	101
070af384	102	#ifndef TARGET_SPARC64
c5f9864e	103	void helper_rett(CPUSPARCState *env)
070af384 BS	104	{
	105	unsigned int cwp;
	106
	107	if (env->psret == 1) {
	108	helper_raise_exception(env, TT_ILL_INSN);
	109	}
	110
	111	env->psret = 1;
063c3675	112	cwp = cpu_cwp_inc(env, env->cwp + 1) ;
070af384 BS	113	if (env->wim & (1 << cwp)) {
	114	helper_raise_exception(env, TT_WIN_UNF);
	115	}
063c3675	116	cpu_set_cwp(env, cwp);
070af384 BS	117	env->psrs = env->psrps;
	118	}
	119
	120	/* XXX: use another pointer for %iN registers to avoid slow wrapping
	121	handling ? */
c5f9864e	122	void helper_save(CPUSPARCState *env)
070af384 BS	123	{
	124	uint32_t cwp;
	125
063c3675	126	cwp = cpu_cwp_dec(env, env->cwp - 1);
070af384 BS	127	if (env->wim & (1 << cwp)) {
	128	helper_raise_exception(env, TT_WIN_OVF);
	129	}
063c3675	130	cpu_set_cwp(env, cwp);
070af384 BS	131	}
070af384 BS	132
c5f9864e	133	void helper_restore(CPUSPARCState *env)
070af384 BS	134	{
	135	uint32_t cwp;
	136
063c3675	137	cwp = cpu_cwp_inc(env, env->cwp + 1);
070af384 BS	138	if (env->wim & (1 << cwp)) {
	139	helper_raise_exception(env, TT_WIN_UNF);
	140	}
063c3675	141	cpu_set_cwp(env, cwp);
070af384 BS	142	}
070af384 BS	143
c5f9864e	144	void helper_wrpsr(CPUSPARCState *env, target_ulong new_psr)
070af384 BS	145	{
	146	if ((new_psr & PSR_CWP) >= env->nwindows) {
	147	helper_raise_exception(env, TT_ILL_INSN);
	148	} else {
	149	cpu_put_psr(env, new_psr);
	150	}
	151	}
	152
c5f9864e	153	target_ulong helper_rdpsr(CPUSPARCState *env)
070af384	154	{
063c3675	155	return cpu_get_psr(env);
070af384 BS	156	}
	157
	158	#else
	159	/* XXX: use another pointer for %iN registers to avoid slow wrapping
	160	handling ? */
c5f9864e	161	void helper_save(CPUSPARCState *env)
070af384 BS	162	{
	163	uint32_t cwp;
	164
063c3675	165	cwp = cpu_cwp_dec(env, env->cwp - 1);
070af384 BS	166	if (env->cansave == 0) {
	167	helper_raise_exception(env, TT_SPILL \| (env->otherwin != 0 ?
	168	(TT_WOTHER \|
	169	((env->wstate & 0x38) >> 1)) :
	170	((env->wstate & 0x7) << 2)));
	171	} else {
	172	if (env->cleanwin - env->canrestore == 0) {
	173	/* XXX Clean windows without trap */
	174	helper_raise_exception(env, TT_CLRWIN);
	175	} else {
	176	env->cansave--;
	177	env->canrestore++;
063c3675	178	cpu_set_cwp(env, cwp);
070af384 BS	179	}
	180	}
	181	}
	182
c5f9864e	183	void helper_restore(CPUSPARCState *env)
070af384 BS	184	{
	185	uint32_t cwp;
	186
063c3675	187	cwp = cpu_cwp_inc(env, env->cwp + 1);
070af384 BS	188	if (env->canrestore == 0) {
	189	helper_raise_exception(env, TT_FILL \| (env->otherwin != 0 ?
	190	(TT_WOTHER \|
	191	((env->wstate & 0x38) >> 1)) :
	192	((env->wstate & 0x7) << 2)));
	193	} else {
	194	env->cansave++;
	195	env->canrestore--;
063c3675	196	cpu_set_cwp(env, cwp);
070af384 BS	197	}
	198	}
	199
c5f9864e	200	void helper_flushw(CPUSPARCState *env)
070af384 BS	201	{
	202	if (env->cansave != env->nwindows - 2) {
	203	helper_raise_exception(env, TT_SPILL \| (env->otherwin != 0 ?
	204	(TT_WOTHER \|
	205	((env->wstate & 0x38) >> 1)) :
	206	((env->wstate & 0x7) << 2)));
	207	}
	208	}
	209
c5f9864e	210	void helper_saved(CPUSPARCState *env)
070af384 BS	211	{
	212	env->cansave++;
	213	if (env->otherwin == 0) {
	214	env->canrestore--;
	215	} else {
	216	env->otherwin--;
	217	}
	218	}
	219
c5f9864e	220	void helper_restored(CPUSPARCState *env)
070af384 BS	221	{
	222	env->canrestore++;
	223	if (env->cleanwin < env->nwindows - 1) {
	224	env->cleanwin++;
	225	}
	226	if (env->otherwin == 0) {
	227	env->cansave--;
	228	} else {
	229	env->otherwin--;
	230	}
	231	}
	232
c5f9864e	233	target_ulong cpu_get_ccr(CPUSPARCState *env)
070af384 BS	234	{
	235	target_ulong psr;
	236
063c3675	237	psr = cpu_get_psr(env);
070af384 BS	238
	239	return ((env->xcc >> 20) << 4) \| ((psr & PSR_ICC) >> 20);
	240	}
	241
c5f9864e	242	void cpu_put_ccr(CPUSPARCState *env, target_ulong val)
070af384 BS	243	{
	244	env->xcc = (val >> 4) << 20;
	245	env->psr = (val & 0xf) << 20;
	246	CC_OP = CC_OP_FLAGS;
	247	}
	248
c5f9864e	249	target_ulong cpu_get_cwp64(CPUSPARCState *env)
070af384 BS	250	{
	251	return env->nwindows - 1 - env->cwp;
	252	}
	253
c5f9864e	254	void cpu_put_cwp64(CPUSPARCState *env, int cwp)
070af384 BS	255	{
	256	if (unlikely(cwp >= env->nwindows \|\| cwp < 0)) {
	257	cwp %= env->nwindows;
	258	}
063c3675	259	cpu_set_cwp(env, env->nwindows - 1 - cwp);
070af384 BS	260	}
070af384 BS	261
c5f9864e	262	target_ulong helper_rdccr(CPUSPARCState *env)
070af384	263	{
063c3675	264	return cpu_get_ccr(env);
070af384 BS	265	}
070af384 BS	266
c5f9864e	267	void helper_wrccr(CPUSPARCState *env, target_ulong new_ccr)
070af384	268	{
063c3675	269	cpu_put_ccr(env, new_ccr);
070af384 BS	270	}
	271
	272	/* CWP handling is reversed in V9, but we still use the V8 register
	273	order. */
c5f9864e	274	target_ulong helper_rdcwp(CPUSPARCState *env)
070af384	275	{
063c3675	276	return cpu_get_cwp64(env);
070af384 BS	277	}
070af384 BS	278
c5f9864e	279	void helper_wrcwp(CPUSPARCState *env, target_ulong new_cwp)
070af384	280	{
063c3675	281	cpu_put_cwp64(env, new_cwp);
070af384 BS	282	}
070af384 BS	283
c5f9864e	284	static inline uint64_t get_gregset(CPUSPARCState env, uint32_t pstate)
070af384 BS	285	{
	286	switch (pstate) {
	287	default:
870be6ad	288	trace_win_helper_gregset_error(pstate);
070af384 BS	289	/* pass through to normal set of global registers */
	290	case 0:
	291	return env->bgregs;
	292	case PS_AG:
	293	return env->agregs;
	294	case PS_MG:
	295	return env->mgregs;
	296	case PS_IG:
	297	return env->igregs;
	298	}
	299	}
	300
c5f9864e	301	void cpu_change_pstate(CPUSPARCState *env, uint32_t new_pstate)
070af384 BS	302	{
	303	uint32_t pstate_regs, new_pstate_regs;
	304	uint64_t src, dst;
	305
	306	if (env->def->features & CPU_FEATURE_GL) {
	307	/* PS_AG is not implemented in this case */
	308	new_pstate &= ~PS_AG;
	309	}
	310
	311	pstate_regs = env->pstate & 0xc01;
	312	new_pstate_regs = new_pstate & 0xc01;
	313
	314	if (new_pstate_regs != pstate_regs) {
870be6ad BS	315	trace_win_helper_switch_pstate(pstate_regs, new_pstate_regs);
870be6ad BS	316
070af384	317	/* Switch global register bank */
063c3675 BS	318	src = get_gregset(env, new_pstate_regs);
063c3675 BS	319	dst = get_gregset(env, pstate_regs);
070af384 BS	320	memcpy32(dst, env->gregs);
	321	memcpy32(env->gregs, src);
	322	} else {
870be6ad	323	trace_win_helper_no_switch_pstate(new_pstate_regs);
070af384 BS	324	}
	325	env->pstate = new_pstate;
	326	}
	327
c5f9864e	328	void helper_wrpstate(CPUSPARCState *env, target_ulong new_state)
070af384	329	{
063c3675	330	cpu_change_pstate(env, new_state & 0xf3f);
070af384 BS	331
	332	#if !defined(CONFIG_USER_ONLY)
	333	if (cpu_interrupts_enabled(env)) {
	334	cpu_check_irqs(env);
	335	}
	336	#endif
	337	}
	338
c5f9864e	339	void helper_wrpil(CPUSPARCState *env, target_ulong new_pil)
070af384 BS	340	{
070af384 BS	341	#if !defined(CONFIG_USER_ONLY)
870be6ad	342	trace_win_helper_wrpil(env->psrpil, (uint32_t)new_pil);
070af384 BS	343
	344	env->psrpil = new_pil;
	345
	346	if (cpu_interrupts_enabled(env)) {
	347	cpu_check_irqs(env);
	348	}
	349	#endif
	350	}
	351
c5f9864e	352	void helper_done(CPUSPARCState *env)
070af384 BS	353	{
	354	trap_state *tsptr = cpu_tsptr(env);
	355
	356	env->pc = tsptr->tnpc;
	357	env->npc = tsptr->tnpc + 4;
063c3675	358	cpu_put_ccr(env, tsptr->tstate >> 32);
070af384	359	env->asi = (tsptr->tstate >> 24) & 0xff;
063c3675 BS	360	cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
063c3675 BS	361	cpu_put_cwp64(env, tsptr->tstate & 0xff);
070af384 BS	362	env->tl--;
070af384 BS	363
870be6ad	364	trace_win_helper_done(env->tl);
070af384 BS	365
	366	#if !defined(CONFIG_USER_ONLY)
	367	if (cpu_interrupts_enabled(env)) {
	368	cpu_check_irqs(env);
	369	}
	370	#endif
	371	}
	372
c5f9864e	373	void helper_retry(CPUSPARCState *env)
070af384 BS	374	{
	375	trap_state *tsptr = cpu_tsptr(env);
	376
	377	env->pc = tsptr->tpc;
	378	env->npc = tsptr->tnpc;
063c3675	379	cpu_put_ccr(env, tsptr->tstate >> 32);
070af384	380	env->asi = (tsptr->tstate >> 24) & 0xff;
063c3675 BS	381	cpu_change_pstate(env, (tsptr->tstate >> 8) & 0xf3f);
063c3675 BS	382	cpu_put_cwp64(env, tsptr->tstate & 0xff);
070af384 BS	383	env->tl--;
070af384 BS	384
870be6ad	385	trace_win_helper_retry(env->tl);
070af384 BS	386
	387	#if !defined(CONFIG_USER_ONLY)
	388	if (cpu_interrupts_enabled(env)) {
	389	cpu_check_irqs(env);
	390	}
	391	#endif
	392	}
	393	#endif